1 #ifndef LINUX_BCMA_DRIVER_CC_H_
2 #define LINUX_BCMA_DRIVER_CC_H_
4 /** ChipCommon core registers. **/
5 #define BCMA_CC_ID 0x0000
6 #define BCMA_CC_ID_ID 0x0000FFFF
7 #define BCMA_CC_ID_ID_SHIFT 0
8 #define BCMA_CC_ID_REV 0x000F0000
9 #define BCMA_CC_ID_REV_SHIFT 16
10 #define BCMA_CC_ID_PKG 0x00F00000
11 #define BCMA_CC_ID_PKG_SHIFT 20
12 #define BCMA_CC_ID_NRCORES 0x0F000000
13 #define BCMA_CC_ID_NRCORES_SHIFT 24
14 #define BCMA_CC_ID_TYPE 0xF0000000
15 #define BCMA_CC_ID_TYPE_SHIFT 28
16 #define BCMA_CC_CAP 0x0004 /* Capabilities */
17 #define BCMA_CC_CAP_NRUART 0x00000003 /* # of UARTs */
18 #define BCMA_CC_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */
19 #define BCMA_CC_CAP_UARTCLK 0x00000018 /* UART clock select */
20 #define BCMA_CC_CAP_UARTCLK_INT 0x00000008 /* UARTs are driven by internal divided clock */
21 #define BCMA_CC_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
22 #define BCMA_CC_CAP_EXTBUS 0x000000C0 /* External buses present */
23 #define BCMA_CC_CAP_FLASHT 0x00000700 /* Flash Type */
24 #define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */
25 #define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */
26 #define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */
27 #define BCMA_CC_FLASHT_NFLASH 0x00000200 /* NAND flash */
28 #define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */
29 #define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */
30 #define BCMA_PLLTYPE_NONE 0x00000000
31 #define BCMA_PLLTYPE_1 0x00010000 /* 48Mhz base, 3 dividers */
32 #define BCMA_PLLTYPE_2 0x00020000 /* 48Mhz, 4 dividers */
33 #define BCMA_PLLTYPE_3 0x00030000 /* 25Mhz, 2 dividers */
34 #define BCMA_PLLTYPE_4 0x00008000 /* 48Mhz, 4 dividers */
35 #define BCMA_PLLTYPE_5 0x00018000 /* 25Mhz, 4 dividers */
36 #define BCMA_PLLTYPE_6 0x00028000 /* 100/200 or 120/240 only */
37 #define BCMA_PLLTYPE_7 0x00038000 /* 25Mhz, 4 dividers */
38 #define BCMA_CC_CAP_PCTL 0x00040000 /* Power Control */
39 #define BCMA_CC_CAP_OTPS 0x00380000 /* OTP size */
40 #define BCMA_CC_CAP_OTPS_SHIFT 19
41 #define BCMA_CC_CAP_OTPS_BASE 5
42 #define BCMA_CC_CAP_JTAGM 0x00400000 /* JTAG master present */
43 #define BCMA_CC_CAP_BROM 0x00800000 /* Internal boot ROM active */
44 #define BCMA_CC_CAP_64BIT 0x08000000 /* 64-bit Backplane */
45 #define BCMA_CC_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
46 #define BCMA_CC_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
47 #define BCMA_CC_CAP_SPROM 0x40000000 /* SPROM present */
48 #define BCMA_CC_CAP_NFLASH 0x80000000 /* NAND flash present (rev >= 35 or BCM4706?) */
49 #define BCMA_CC_CORECTL 0x0008
50 #define BCMA_CC_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
51 #define BCMA_CC_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
52 #define BCMA_CC_CORECTL_UARTCLKEN 0x00000008 /* UART clock enable (rev >= 21) */
53 #define BCMA_CC_BIST 0x000C
54 #define BCMA_CC_OTPS 0x0010 /* OTP status */
55 #define BCMA_CC_OTPS_PROGFAIL 0x80000000
56 #define BCMA_CC_OTPS_PROTECT 0x00000007
57 #define BCMA_CC_OTPS_HW_PROTECT 0x00000001
58 #define BCMA_CC_OTPS_SW_PROTECT 0x00000002
59 #define BCMA_CC_OTPS_CID_PROTECT 0x00000004
60 #define BCMA_CC_OTPS_GU_PROG_IND 0x00000F00 /* General Use programmed indication */
61 #define BCMA_CC_OTPS_GU_PROG_IND_SHIFT 8
62 #define BCMA_CC_OTPS_GU_PROG_HW 0x00000100 /* HW region programmed */
63 #define BCMA_CC_OTPC 0x0014 /* OTP control */
64 #define BCMA_CC_OTPC_RECWAIT 0xFF000000
65 #define BCMA_CC_OTPC_PROGWAIT 0x00FFFF00
66 #define BCMA_CC_OTPC_PRW_SHIFT 8
67 #define BCMA_CC_OTPC_MAXFAIL 0x00000038
68 #define BCMA_CC_OTPC_VSEL 0x00000006
69 #define BCMA_CC_OTPC_SELVL 0x00000001
70 #define BCMA_CC_OTPP 0x0018 /* OTP prog */
71 #define BCMA_CC_OTPP_COL 0x000000FF
72 #define BCMA_CC_OTPP_ROW 0x0000FF00
73 #define BCMA_CC_OTPP_ROW_SHIFT 8
74 #define BCMA_CC_OTPP_READERR 0x10000000
75 #define BCMA_CC_OTPP_VALUE 0x20000000
76 #define BCMA_CC_OTPP_READ 0x40000000
77 #define BCMA_CC_OTPP_START 0x80000000
78 #define BCMA_CC_OTPP_BUSY 0x80000000
79 #define BCMA_CC_OTPL 0x001C /* OTP layout */
80 #define BCMA_CC_OTPL_GURGN_OFFSET 0x00000FFF /* offset of general use region */
81 #define BCMA_CC_IRQSTAT 0x0020
82 #define BCMA_CC_IRQMASK 0x0024
83 #define BCMA_CC_IRQ_GPIO 0x00000001 /* gpio intr */
84 #define BCMA_CC_IRQ_EXT 0x00000002 /* ro: ext intr pin (corerev >= 3) */
85 #define BCMA_CC_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */
86 #define BCMA_CC_CHIPCTL 0x0028 /* Rev >= 11 only */
87 #define BCMA_CC_CHIPSTAT 0x002C /* Rev >= 11 only */
88 #define BCMA_CC_CHIPST_4313_SPROM_PRESENT 1
89 #define BCMA_CC_CHIPST_4313_OTP_PRESENT 2
90 #define BCMA_CC_CHIPST_4331_SPROM_PRESENT 2
91 #define BCMA_CC_CHIPST_4331_OTP_PRESENT 4
92 #define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */
93 #define BCMA_CC_CHIPST_4706_SFLASH_PRESENT BIT(1) /* 0: parallel, 1: serial flash is present */
94 #define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
95 #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
96 #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
97 #define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
98 #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
99 #define BCMA_CC_JCMD_START 0x80000000
100 #define BCMA_CC_JCMD_BUSY 0x80000000
101 #define BCMA_CC_JCMD_PAUSE 0x40000000
102 #define BCMA_CC_JCMD0_ACC_MASK 0x0000F000
103 #define BCMA_CC_JCMD0_ACC_IRDR 0x00000000
104 #define BCMA_CC_JCMD0_ACC_DR 0x00001000
105 #define BCMA_CC_JCMD0_ACC_IR 0x00002000
106 #define BCMA_CC_JCMD0_ACC_RESET 0x00003000
107 #define BCMA_CC_JCMD0_ACC_IRPDR 0x00004000
108 #define BCMA_CC_JCMD0_ACC_PDR 0x00005000
109 #define BCMA_CC_JCMD0_IRW_MASK 0x00000F00
110 #define BCMA_CC_JCMD_ACC_MASK 0x000F0000 /* Changes for corerev 11 */
111 #define BCMA_CC_JCMD_ACC_IRDR 0x00000000
112 #define BCMA_CC_JCMD_ACC_DR 0x00010000
113 #define BCMA_CC_JCMD_ACC_IR 0x00020000
114 #define BCMA_CC_JCMD_ACC_RESET 0x00030000
115 #define BCMA_CC_JCMD_ACC_IRPDR 0x00040000
116 #define BCMA_CC_JCMD_ACC_PDR 0x00050000
117 #define BCMA_CC_JCMD_IRW_MASK 0x00001F00
118 #define BCMA_CC_JCMD_IRW_SHIFT 8
119 #define BCMA_CC_JCMD_DRW_MASK 0x0000003F
120 #define BCMA_CC_JIR 0x0034 /* Rev >= 10 only */
121 #define BCMA_CC_JDR 0x0038 /* Rev >= 10 only */
122 #define BCMA_CC_JCTL 0x003C /* Rev >= 10 only */
123 #define BCMA_CC_JCTL_FORCE_CLK 4 /* Force clock */
124 #define BCMA_CC_JCTL_EXT_EN 2 /* Enable external targets */
125 #define BCMA_CC_JCTL_EN 1 /* Enable Jtag master */
126 #define BCMA_CC_FLASHCTL 0x0040
127 /* Start/busy bit in flashcontrol */
128 #define BCMA_CC_FLASHCTL_OPCODE 0x000000ff
129 #define BCMA_CC_FLASHCTL_ACTION 0x00000700
130 #define BCMA_CC_FLASHCTL_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */
131 #define BCMA_CC_FLASHCTL_START 0x80000000
132 #define BCMA_CC_FLASHCTL_BUSY BCMA_CC_FLASHCTL_START
133 /* Flashcontrol action + opcodes for ST flashes */
134 #define BCMA_CC_FLASHCTL_ST_WREN 0x0006 /* Write Enable */
135 #define BCMA_CC_FLASHCTL_ST_WRDIS 0x0004 /* Write Disable */
136 #define BCMA_CC_FLASHCTL_ST_RDSR 0x0105 /* Read Status Register */
137 #define BCMA_CC_FLASHCTL_ST_WRSR 0x0101 /* Write Status Register */
138 #define BCMA_CC_FLASHCTL_ST_READ 0x0303 /* Read Data Bytes */
139 #define BCMA_CC_FLASHCTL_ST_PP 0x0302 /* Page Program */
140 #define BCMA_CC_FLASHCTL_ST_SE 0x02d8 /* Sector Erase */
141 #define BCMA_CC_FLASHCTL_ST_BE 0x00c7 /* Bulk Erase */
142 #define BCMA_CC_FLASHCTL_ST_DP 0x00b9 /* Deep Power-down */
143 #define BCMA_CC_FLASHCTL_ST_RES 0x03ab /* Read Electronic Signature */
144 #define BCMA_CC_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */
145 #define BCMA_CC_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
146 /* Flashcontrol action + opcodes for Atmel flashes */
147 #define BCMA_CC_FLASHCTL_AT_READ 0x07e8
148 #define BCMA_CC_FLASHCTL_AT_PAGE_READ 0x07d2
149 #define BCMA_CC_FLASHCTL_AT_STATUS 0x01d7
150 #define BCMA_CC_FLASHCTL_AT_BUF1_WRITE 0x0384
151 #define BCMA_CC_FLASHCTL_AT_BUF2_WRITE 0x0387
152 #define BCMA_CC_FLASHCTL_AT_BUF1_ERASE_PROGRAM 0x0283
153 #define BCMA_CC_FLASHCTL_AT_BUF2_ERASE_PROGRAM 0x0286
154 #define BCMA_CC_FLASHCTL_AT_BUF1_PROGRAM 0x0288
155 #define BCMA_CC_FLASHCTL_AT_BUF2_PROGRAM 0x0289
156 #define BCMA_CC_FLASHCTL_AT_PAGE_ERASE 0x0281
157 #define BCMA_CC_FLASHCTL_AT_BLOCK_ERASE 0x0250
158 #define BCMA_CC_FLASHCTL_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
159 #define BCMA_CC_FLASHCTL_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
160 #define BCMA_CC_FLASHCTL_AT_BUF1_LOAD 0x0253
161 #define BCMA_CC_FLASHCTL_AT_BUF2_LOAD 0x0255
162 #define BCMA_CC_FLASHCTL_AT_BUF1_COMPARE 0x0260
163 #define BCMA_CC_FLASHCTL_AT_BUF2_COMPARE 0x0261
164 #define BCMA_CC_FLASHCTL_AT_BUF1_REPROGRAM 0x0258
165 #define BCMA_CC_FLASHCTL_AT_BUF2_REPROGRAM 0x0259
166 #define BCMA_CC_FLASHADDR 0x0044
167 #define BCMA_CC_FLASHDATA 0x0048
168 /* Status register bits for ST flashes */
169 #define BCMA_CC_FLASHDATA_ST_WIP 0x01 /* Write In Progress */
170 #define BCMA_CC_FLASHDATA_ST_WEL 0x02 /* Write Enable Latch */
171 #define BCMA_CC_FLASHDATA_ST_BP_MASK 0x1c /* Block Protect */
172 #define BCMA_CC_FLASHDATA_ST_BP_SHIFT 2
173 #define BCMA_CC_FLASHDATA_ST_SRWD 0x80 /* Status Register Write Disable */
174 /* Status register bits for Atmel flashes */
175 #define BCMA_CC_FLASHDATA_AT_READY 0x80
176 #define BCMA_CC_FLASHDATA_AT_MISMATCH 0x40
177 #define BCMA_CC_FLASHDATA_AT_ID_MASK 0x38
178 #define BCMA_CC_FLASHDATA_AT_ID_SHIFT 3
179 #define BCMA_CC_BCAST_ADDR 0x0050
180 #define BCMA_CC_BCAST_DATA 0x0054
181 #define BCMA_CC_GPIOPULLUP 0x0058 /* Rev >= 20 only */
182 #define BCMA_CC_GPIOPULLDOWN 0x005C /* Rev >= 20 only */
183 #define BCMA_CC_GPIOIN 0x0060
184 #define BCMA_CC_GPIOOUT 0x0064
185 #define BCMA_CC_GPIOOUTEN 0x0068
186 #define BCMA_CC_GPIOCTL 0x006C
187 #define BCMA_CC_GPIOPOL 0x0070
188 #define BCMA_CC_GPIOIRQ 0x0074
189 #define BCMA_CC_WATCHDOG 0x0080
190 #define BCMA_CC_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
191 #define BCMA_CC_GPIOTIMER_OFFTIME 0x0000FFFF
192 #define BCMA_CC_GPIOTIMER_OFFTIME_SHIFT 0
193 #define BCMA_CC_GPIOTIMER_ONTIME 0xFFFF0000
194 #define BCMA_CC_GPIOTIMER_ONTIME_SHIFT 16
195 #define BCMA_CC_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
196 #define BCMA_CC_CLOCK_N 0x0090
197 #define BCMA_CC_CLOCK_SB 0x0094
198 #define BCMA_CC_CLOCK_PCI 0x0098
199 #define BCMA_CC_CLOCK_M2 0x009C
200 #define BCMA_CC_CLOCK_MIPS 0x00A0
201 #define BCMA_CC_CLKDIV 0x00A4 /* Rev >= 3 only */
202 #define BCMA_CC_CLKDIV_SFLASH 0x0F000000
203 #define BCMA_CC_CLKDIV_SFLASH_SHIFT 24
204 #define BCMA_CC_CLKDIV_OTP 0x000F0000
205 #define BCMA_CC_CLKDIV_OTP_SHIFT 16
206 #define BCMA_CC_CLKDIV_JTAG 0x00000F00
207 #define BCMA_CC_CLKDIV_JTAG_SHIFT 8
208 #define BCMA_CC_CLKDIV_UART 0x000000FF
209 #define BCMA_CC_CAP_EXT 0x00AC /* Capabilities */
210 #define BCMA_CC_PLLONDELAY 0x00B0 /* Rev >= 4 only */
211 #define BCMA_CC_FREFSELDELAY 0x00B4 /* Rev >= 4 only */
212 #define BCMA_CC_SLOWCLKCTL 0x00B8 /* 6 <= Rev <= 9 only */
213 #define BCMA_CC_SLOWCLKCTL_SRC 0x00000007 /* slow clock source mask */
214 #define BCMA_CC_SLOWCLKCTL_SRC_LPO 0x00000000 /* source of slow clock is LPO */
215 #define BCMA_CC_SLOWCLKCTL_SRC_XTAL 0x00000001 /* source of slow clock is crystal */
216 #define BCMA_CC_SLOECLKCTL_SRC_PCI 0x00000002 /* source of slow clock is PCI */
217 #define BCMA_CC_SLOWCLKCTL_LPOFREQ 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
218 #define BCMA_CC_SLOWCLKCTL_LPOPD 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
219 #define BCMA_CC_SLOWCLKCTL_FSLOW 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
220 #define BCMA_CC_SLOWCLKCTL_IPLL 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
221 #define BCMA_CC_SLOWCLKCTL_ENXTAL 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
222 #define BCMA_CC_SLOWCLKCTL_XTALPU 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
223 #define BCMA_CC_SLOWCLKCTL_CLKDIV 0xFFFF0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
224 #define BCMA_CC_SLOWCLKCTL_CLKDIV_SHIFT 16
225 #define BCMA_CC_SYSCLKCTL 0x00C0 /* Rev >= 3 only */
226 #define BCMA_CC_SYSCLKCTL_IDLPEN 0x00000001 /* ILPen: Enable Idle Low Power */
227 #define BCMA_CC_SYSCLKCTL_ALPEN 0x00000002 /* ALPen: Enable Active Low Power */
228 #define BCMA_CC_SYSCLKCTL_PLLEN 0x00000004 /* ForcePLLOn */
229 #define BCMA_CC_SYSCLKCTL_FORCEALP 0x00000008 /* Force ALP (or HT if ALPen is not set */
230 #define BCMA_CC_SYSCLKCTL_FORCEHT 0x00000010 /* Force HT */
231 #define BCMA_CC_SYSCLKCTL_CLKDIV 0xFFFF0000 /* ClkDiv (ILP = 1/(4+divisor)) */
232 #define BCMA_CC_SYSCLKCTL_CLKDIV_SHIFT 16
233 #define BCMA_CC_CLKSTSTR 0x00C4 /* Rev >= 3 only */
234 #define BCMA_CC_EROM 0x00FC
235 #define BCMA_CC_PCMCIA_CFG 0x0100
236 #define BCMA_CC_PCMCIA_MEMWAIT 0x0104
237 #define BCMA_CC_PCMCIA_ATTRWAIT 0x0108
238 #define BCMA_CC_PCMCIA_IOWAIT 0x010C
239 #define BCMA_CC_IDE_CFG 0x0110
240 #define BCMA_CC_IDE_MEMWAIT 0x0114
241 #define BCMA_CC_IDE_ATTRWAIT 0x0118
242 #define BCMA_CC_IDE_IOWAIT 0x011C
243 #define BCMA_CC_PROG_CFG 0x0120
244 #define BCMA_CC_PROG_WAITCNT 0x0124
245 #define BCMA_CC_FLASH_CFG 0x0128
246 #define BCMA_CC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
247 #define BCMA_CC_FLASH_WAITCNT 0x012C
248 #define BCMA_CC_SROM_CONTROL 0x0190
249 #define BCMA_CC_SROM_CONTROL_START 0x80000000
250 #define BCMA_CC_SROM_CONTROL_BUSY 0x80000000
251 #define BCMA_CC_SROM_CONTROL_OPCODE 0x60000000
252 #define BCMA_CC_SROM_CONTROL_OP_READ 0x00000000
253 #define BCMA_CC_SROM_CONTROL_OP_WRITE 0x20000000
254 #define BCMA_CC_SROM_CONTROL_OP_WRDIS 0x40000000
255 #define BCMA_CC_SROM_CONTROL_OP_WREN 0x60000000
256 #define BCMA_CC_SROM_CONTROL_OTPSEL 0x00000010
257 #define BCMA_CC_SROM_CONTROL_LOCK 0x00000008
258 #define BCMA_CC_SROM_CONTROL_SIZE_MASK 0x00000006
259 #define BCMA_CC_SROM_CONTROL_SIZE_1K 0x00000000
260 #define BCMA_CC_SROM_CONTROL_SIZE_4K 0x00000002
261 #define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004
262 #define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1
263 #define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001
264 /* Block 0x140 - 0x190 registers are chipset specific */
265 #define BCMA_CC_4706_FLASHSCFG 0x18C /* Flash struct configuration */
266 #define BCMA_CC_4706_FLASHSCFG_MASK 0x000000ff
267 #define BCMA_CC_4706_FLASHSCFG_SF1 0x00000001 /* 2nd serial flash present */
268 #define BCMA_CC_4706_FLASHSCFG_PF1 0x00000002 /* 2nd parallel flash present */
269 #define BCMA_CC_4706_FLASHSCFG_SF1_TYPE 0x00000004 /* 2nd serial flash type : 0 : ST, 1 : Atmel */
270 #define BCMA_CC_4706_FLASHSCFG_NF1 0x00000008 /* 2nd NAND flash present */
271 #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_MASK 0x000000f0
272 #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_4MB 0x00000010 /* 4MB */
273 #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_8MB 0x00000020 /* 8MB */
274 #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_16MB 0x00000030 /* 16MB */
275 #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_32MB 0x00000040 /* 32MB */
276 #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_64MB 0x00000050 /* 64MB */
277 #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_128MB 0x00000060 /* 128MB */
278 #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_256MB 0x00000070 /* 256MB */
279 /* NAND flash registers for BCM4706 (corerev = 31) */
280 #define BCMA_CC_NFLASH_CTL 0x01A0
281 #define BCMA_CC_NFLASH_CTL_ERR 0x08000000
282 #define BCMA_CC_NFLASH_CONF 0x01A4
283 #define BCMA_CC_NFLASH_COL_ADDR 0x01A8
284 #define BCMA_CC_NFLASH_ROW_ADDR 0x01AC
285 #define BCMA_CC_NFLASH_DATA 0x01B0
286 #define BCMA_CC_NFLASH_WAITCNT0 0x01B4
287 /* 0x1E0 is defined as shared BCMA_CLKCTLST */
288 #define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
289 #define BCMA_CC_UART0_DATA 0x0300
290 #define BCMA_CC_UART0_IMR 0x0304
291 #define BCMA_CC_UART0_FCR 0x0308
292 #define BCMA_CC_UART0_LCR 0x030C
293 #define BCMA_CC_UART0_MCR 0x0310
294 #define BCMA_CC_UART0_LSR 0x0314
295 #define BCMA_CC_UART0_MSR 0x0318
296 #define BCMA_CC_UART0_SCRATCH 0x031C
297 #define BCMA_CC_UART1_DATA 0x0400
298 #define BCMA_CC_UART1_IMR 0x0404
299 #define BCMA_CC_UART1_FCR 0x0408
300 #define BCMA_CC_UART1_LCR 0x040C
301 #define BCMA_CC_UART1_MCR 0x0410
302 #define BCMA_CC_UART1_LSR 0x0414
303 #define BCMA_CC_UART1_MSR 0x0418
304 #define BCMA_CC_UART1_SCRATCH 0x041C
305 /* PMU registers (rev >= 20) */
306 #define BCMA_CC_PMU_CTL 0x0600 /* PMU control */
307 #define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
308 #define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
309 #define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400
310 #define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
311 #define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
312 #define BCMA_CC_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */
313 #define BCMA_CC_PMU_CTL_XTALFREQ 0x0000007C /* Crystal freq */
314 #define BCMA_CC_PMU_CTL_XTALFREQ_SHIFT 2
315 #define BCMA_CC_PMU_CTL_ILPDIVEN 0x00000002 /* ILP div enable */
316 #define BCMA_CC_PMU_CTL_LPOSEL 0x00000001 /* LPO sel */
317 #define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */
318 #define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */
319 #define BCMA_CC_PMU_STAT 0x0608 /* PMU status */
320 #define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
321 #define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
322 #define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
323 #define BCMA_CC_PMU_STAT_HAVEHT 0x00000004 /* HT available */
324 #define BCMA_CC_PMU_STAT_RESINIT 0x00000003 /* Res init */
325 #define BCMA_CC_PMU_RES_STAT 0x060C /* PMU res status */
326 #define BCMA_CC_PMU_RES_PEND 0x0610 /* PMU res pending */
327 #define BCMA_CC_PMU_TIMER 0x0614 /* PMU timer */
328 #define BCMA_CC_PMU_MINRES_MSK 0x0618 /* PMU min res mask */
329 #define BCMA_CC_PMU_MAXRES_MSK 0x061C /* PMU max res mask */
330 #define BCMA_CC_PMU_RES_TABSEL 0x0620 /* PMU res table sel */
331 #define BCMA_CC_PMU_RES_DEPMSK 0x0624 /* PMU res dep mask */
332 #define BCMA_CC_PMU_RES_UPDNTM 0x0628 /* PMU res updown timer */
333 #define BCMA_CC_PMU_RES_TIMER 0x062C /* PMU res timer */
334 #define BCMA_CC_PMU_CLKSTRETCH 0x0630 /* PMU clockstretch */
335 #define BCMA_CC_PMU_WATCHDOG 0x0634 /* PMU watchdog */
336 #define BCMA_CC_PMU_RES_REQTS 0x0640 /* PMU res req timer sel */
337 #define BCMA_CC_PMU_RES_REQT 0x0644 /* PMU res req timer */
338 #define BCMA_CC_PMU_RES_REQM 0x0648 /* PMU res req mask */
339 #define BCMA_CC_CHIPCTL_ADDR 0x0650
340 #define BCMA_CC_CHIPCTL_DATA 0x0654
341 #define BCMA_CC_REGCTL_ADDR 0x0658
342 #define BCMA_CC_REGCTL_DATA 0x065C
343 #define BCMA_CC_PLLCTL_ADDR 0x0660
344 #define BCMA_CC_PLLCTL_DATA 0x0664
345 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
346 /* NAND flash MLC controller registers (corerev >= 38) */
347 #define BCMA_CC_NAND_REVISION 0x0C00
348 #define BCMA_CC_NAND_CMD_START 0x0C04
349 #define BCMA_CC_NAND_CMD_ADDR_X 0x0C08
350 #define BCMA_CC_NAND_CMD_ADDR 0x0C0C
351 #define BCMA_CC_NAND_CMD_END_ADDR 0x0C10
352 #define BCMA_CC_NAND_CS_NAND_SELECT 0x0C14
353 #define BCMA_CC_NAND_CS_NAND_XOR 0x0C18
354 #define BCMA_CC_NAND_SPARE_RD0 0x0C20
355 #define BCMA_CC_NAND_SPARE_RD4 0x0C24
356 #define BCMA_CC_NAND_SPARE_RD8 0x0C28
357 #define BCMA_CC_NAND_SPARE_RD12 0x0C2C
358 #define BCMA_CC_NAND_SPARE_WR0 0x0C30
359 #define BCMA_CC_NAND_SPARE_WR4 0x0C34
360 #define BCMA_CC_NAND_SPARE_WR8 0x0C38
361 #define BCMA_CC_NAND_SPARE_WR12 0x0C3C
362 #define BCMA_CC_NAND_ACC_CONTROL 0x0C40
363 #define BCMA_CC_NAND_CONFIG 0x0C48
364 #define BCMA_CC_NAND_TIMING_1 0x0C50
365 #define BCMA_CC_NAND_TIMING_2 0x0C54
366 #define BCMA_CC_NAND_SEMAPHORE 0x0C58
367 #define BCMA_CC_NAND_DEVID 0x0C60
368 #define BCMA_CC_NAND_DEVID_X 0x0C64
369 #define BCMA_CC_NAND_BLOCK_LOCK_STATUS 0x0C68
370 #define BCMA_CC_NAND_INTFC_STATUS 0x0C6C
371 #define BCMA_CC_NAND_ECC_CORR_ADDR_X 0x0C70
372 #define BCMA_CC_NAND_ECC_CORR_ADDR 0x0C74
373 #define BCMA_CC_NAND_ECC_UNC_ADDR_X 0x0C78
374 #define BCMA_CC_NAND_ECC_UNC_ADDR 0x0C7C
375 #define BCMA_CC_NAND_READ_ERROR_COUNT 0x0C80
376 #define BCMA_CC_NAND_CORR_STAT_THRESHOLD 0x0C84
377 #define BCMA_CC_NAND_READ_ADDR_X 0x0C90
378 #define BCMA_CC_NAND_READ_ADDR 0x0C94
379 #define BCMA_CC_NAND_PAGE_PROGRAM_ADDR_X 0x0C98
380 #define BCMA_CC_NAND_PAGE_PROGRAM_ADDR 0x0C9C
381 #define BCMA_CC_NAND_COPY_BACK_ADDR_X 0x0CA0
382 #define BCMA_CC_NAND_COPY_BACK_ADDR 0x0CA4
383 #define BCMA_CC_NAND_BLOCK_ERASE_ADDR_X 0x0CA8
384 #define BCMA_CC_NAND_BLOCK_ERASE_ADDR 0x0CAC
385 #define BCMA_CC_NAND_INV_READ_ADDR_X 0x0CB0
386 #define BCMA_CC_NAND_INV_READ_ADDR 0x0CB4
387 #define BCMA_CC_NAND_BLK_WR_PROTECT 0x0CC0
388 #define BCMA_CC_NAND_ACC_CONTROL_CS1 0x0CD0
389 #define BCMA_CC_NAND_CONFIG_CS1 0x0CD4
390 #define BCMA_CC_NAND_TIMING_1_CS1 0x0CD8
391 #define BCMA_CC_NAND_TIMING_2_CS1 0x0CDC
392 #define BCMA_CC_NAND_SPARE_RD16 0x0D30
393 #define BCMA_CC_NAND_SPARE_RD20 0x0D34
394 #define BCMA_CC_NAND_SPARE_RD24 0x0D38
395 #define BCMA_CC_NAND_SPARE_RD28 0x0D3C
396 #define BCMA_CC_NAND_CACHE_ADDR 0x0D40
397 #define BCMA_CC_NAND_CACHE_DATA 0x0D44
398 #define BCMA_CC_NAND_CTRL_CONFIG 0x0D48
399 #define BCMA_CC_NAND_CTRL_STATUS 0x0D4C
401 /* Divider allocation in 4716/47162/5356 */
402 #define BCMA_CC_PMU5_MAINPLL_CPU 1
403 #define BCMA_CC_PMU5_MAINPLL_MEM 2
404 #define BCMA_CC_PMU5_MAINPLL_SSB 3
406 /* PLL usage in 4716/47162 */
407 #define BCMA_CC_PMU4716_MAINPLL_PLL0 12
409 /* PLL usage in 5356/5357 */
410 #define BCMA_CC_PMU5356_MAINPLL_PLL0 0
411 #define BCMA_CC_PMU5357_MAINPLL_PLL0 0
414 #define BCMA_CC_PMU4706_MAINPLL_PLL0 0
415 #define BCMA_CC_PMU6_4706_PROCPLL_OFF 4 /* The CPU PLL */
416 #define BCMA_CC_PMU6_4706_PROC_P2DIV_MASK 0x000f0000
417 #define BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT 16
418 #define BCMA_CC_PMU6_4706_PROC_P1DIV_MASK 0x0000f000
419 #define BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT 12
420 #define BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK 0x00000ff8
421 #define BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT 3
422 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007
423 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0
425 /* ALP clock on pre-PMU chips */
426 #define BCMA_CC_PMU_ALP_CLOCK 20000000
427 /* HT clock for systems with PMU-enabled chipcommon */
428 #define BCMA_CC_PMU_HT_CLOCK 80000000
430 /* PMU rev 5 (& 6) */
431 #define BCMA_CC_PPL_P1P2_OFF 0
432 #define BCMA_CC_PPL_P1_MASK 0x0f000000
433 #define BCMA_CC_PPL_P1_SHIFT 24
434 #define BCMA_CC_PPL_P2_MASK 0x00f00000
435 #define BCMA_CC_PPL_P2_SHIFT 20
436 #define BCMA_CC_PPL_M14_OFF 1
437 #define BCMA_CC_PPL_MDIV_MASK 0x000000ff
438 #define BCMA_CC_PPL_MDIV_WIDTH 8
439 #define BCMA_CC_PPL_NM5_OFF 2
440 #define BCMA_CC_PPL_NDIV_MASK 0xfff00000
441 #define BCMA_CC_PPL_NDIV_SHIFT 20
442 #define BCMA_CC_PPL_FMAB_OFF 3
443 #define BCMA_CC_PPL_MRAT_MASK 0xf0000000
444 #define BCMA_CC_PPL_MRAT_SHIFT 28
445 #define BCMA_CC_PPL_ABRAT_MASK 0x08000000
446 #define BCMA_CC_PPL_ABRAT_SHIFT 27
447 #define BCMA_CC_PPL_FDIV_MASK 0x07ffffff
448 #define BCMA_CC_PPL_PLLCTL_OFF 4
449 #define BCMA_CC_PPL_PCHI_OFF 5
450 #define BCMA_CC_PPL_PCHI_MASK 0x0000003f
452 #define BCMA_CC_PMU_PLL_CTL0 0
453 #define BCMA_CC_PMU_PLL_CTL1 1
454 #define BCMA_CC_PMU_PLL_CTL2 2
455 #define BCMA_CC_PMU_PLL_CTL3 3
456 #define BCMA_CC_PMU_PLL_CTL4 4
457 #define BCMA_CC_PMU_PLL_CTL5 5
459 #define BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000
460 #define BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT 20
462 #define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000
463 #define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT 20
465 /* BCM4331 ChipControl numbers. */
466 #define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */
467 #define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */
468 #define BCMA_CHIPCTL_4331_EXT_LNA BIT(2) /* 0 disable */
469 #define BCMA_CHIPCTL_4331_SPROM_GPIO13_15 BIT(3) /* sprom/gpio13-15 mux */
470 #define BCMA_CHIPCTL_4331_EXTPA_EN BIT(4) /* 0 ext pa disable, 1 ext pa enabled */
471 #define BCMA_CHIPCTL_4331_GPIOCLK_ON_SPROMCS BIT(5) /* set drive out GPIO_CLK on sprom_cs pin */
472 #define BCMA_CHIPCTL_4331_PCIE_MDIO_ON_SPROMCS BIT(6) /* use sprom_cs pin as PCIE mdio interface */
473 #define BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5 BIT(7) /* aband extpa will be at gpio2/5 and sprom_dout */
474 #define BCMA_CHIPCTL_4331_OVR_PIPEAUXCLKEN BIT(8) /* override core control on pipe_AuxClkEnable */
475 #define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN BIT(9) /* override core control on pipe_AuxPowerDown */
476 #define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN BIT(10) /* pcie_auxclkenable */
477 #define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN BIT(11) /* pcie_pipe_pllpowerdown */
478 #define BCMA_CHIPCTL_4331_EXTPA_EN2 BIT(12) /* 0 ext pa disable, 1 ext pa enabled */
479 #define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4 BIT(16) /* enable bt_shd0 at gpio4 */
480 #define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5 BIT(17) /* enable bt_shd1 at gpio5 */
482 /* 43224 chip-specific ChipControl register bits */
483 #define BCMA_CCTRL_43224_GPIO_TOGGLE 0x8000 /* gpio[3:0] pins as btcoex or s/w gpio */
484 #define BCMA_CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */
485 #define BCMA_CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */
487 /* 4313 Chip specific ChipControl register bits */
488 #define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */
490 /* BCM5357 ChipControl register bits */
491 #define BCMA_CHIPCTL_5357_EXTPA BIT(14)
492 #define BCMA_CHIPCTL_5357_ANT_MUX_2O3 BIT(15)
493 #define BCMA_CHIPCTL_5357_NFLASH BIT(16)
494 #define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
495 #define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
497 /* Data for the PMU, if available.
498 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
500 struct bcma_chipcommon_pmu {
501 u8 rev; /* PMU revision */
502 u32 crystalfreq; /* The active crystal frequency (in kHz) */
505 #ifdef CONFIG_BCMA_DRIVER_MIPS
512 struct bcma_serial_port {
514 unsigned long clockspeed;
516 unsigned int baud_base;
517 unsigned int reg_shift;
519 #endif /* CONFIG_BCMA_DRIVER_MIPS */
522 struct bcma_device *core;
525 u32 capabilities_ext;
527 /* Fast Powerup Delay constant */
528 u16 fast_pwrup_delay;
529 struct bcma_chipcommon_pmu pmu;
530 #ifdef CONFIG_BCMA_DRIVER_MIPS
531 struct bcma_pflash pflash;
534 struct bcma_serial_port serial_ports[4];
535 #endif /* CONFIG_BCMA_DRIVER_MIPS */
538 /* Register access */
539 #define bcma_cc_read32(cc, offset) \
540 bcma_read32((cc)->core, offset)
541 #define bcma_cc_write32(cc, offset, val) \
542 bcma_write32((cc)->core, offset, val)
544 #define bcma_cc_mask32(cc, offset, mask) \
545 bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) & (mask))
546 #define bcma_cc_set32(cc, offset, set) \
547 bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) | (set))
548 #define bcma_cc_maskset32(cc, offset, mask, set) \
549 bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
551 extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
553 extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
554 extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
556 void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
558 extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
561 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
563 u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask);
565 /* Chipcommon GPIO pin access. */
566 u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask);
567 u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value);
568 u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value);
569 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value);
570 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value);
571 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value);
574 extern void bcma_pmu_init(struct bcma_drv_cc *cc);
576 extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
578 extern void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset,
580 extern void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
581 u32 offset, u32 mask, u32 set);
582 extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc,
583 u32 offset, u32 mask, u32 set);
584 extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid);
586 #endif /* LINUX_BCMA_DRIVER_CC_H_ */
projects / karo-tx-linux.git / blob