1 #ifndef _DMA_REMAPPING_H
2 #define _DMA_REMAPPING_H
5 * VT-d hardware uses 4KiB page size regardless of host page size.
7 #define VTD_PAGE_SHIFT (12)
8 #define VTD_PAGE_SIZE (1UL << VTD_PAGE_SHIFT)
9 #define VTD_PAGE_MASK (((u64)-1) << VTD_PAGE_SHIFT)
10 #define VTD_PAGE_ALIGN(addr) (((addr) + VTD_PAGE_SIZE - 1) & VTD_PAGE_MASK)
15 * 12-63: Context Ptr (12 - (haw-1))
22 #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
23 static inline bool root_present(struct root_entry *root)
25 return (root->val & 1);
27 static inline void set_root_present(struct root_entry *root)
31 static inline void set_root_value(struct root_entry *root, unsigned long value)
33 root->val |= value & VTD_PAGE_MASK;
37 static inline struct context_entry *
38 get_context_addr_from_root(struct root_entry *root)
40 return (struct context_entry *)
41 (root_present(root)?phys_to_virt(
42 root->val & VTD_PAGE_MASK) :
49 * 1: fault processing disable
50 * 2-3: translation type
51 * 12-63: address space root
57 struct context_entry {
61 #define context_present(c) ((c).lo & 1)
62 #define context_fault_disable(c) (((c).lo >> 1) & 1)
63 #define context_translation_type(c) (((c).lo >> 2) & 3)
64 #define context_address_root(c) ((c).lo & VTD_PAGE_MASK)
65 #define context_address_width(c) ((c).hi & 7)
66 #define context_domain_id(c) (((c).hi >> 8) & ((1 << 16) - 1))
68 #define context_set_present(c) do {(c).lo |= 1;} while (0)
69 #define context_set_fault_enable(c) \
70 do {(c).lo &= (((u64)-1) << 2) | 1;} while (0)
71 #define context_set_translation_type(c, val) \
73 (c).lo &= (((u64)-1) << 4) | 3; \
74 (c).lo |= ((val) & 3) << 2; \
76 #define CONTEXT_TT_MULTI_LEVEL 0
77 #define context_set_address_root(c, val) \
78 do {(c).lo |= (val) & VTD_PAGE_MASK; } while (0)
79 #define context_set_address_width(c, val) do {(c).hi |= (val) & 7;} while (0)
80 #define context_set_domain_id(c, val) \
81 do {(c).hi |= ((val) & ((1 << 16) - 1)) << 8;} while (0)
82 #define context_clear_entry(c) do {(c).lo = 0; (c).hi = 0;} while (0)
90 * 12-63: Host physcial address
95 #define dma_clear_pte(p) do {(p).val = 0;} while (0)
97 #define DMA_PTE_READ (1)
98 #define DMA_PTE_WRITE (2)
100 #define dma_set_pte_readable(p) do {(p).val |= DMA_PTE_READ;} while (0)
101 #define dma_set_pte_writable(p) do {(p).val |= DMA_PTE_WRITE;} while (0)
102 #define dma_set_pte_prot(p, prot) \
103 do {(p).val = ((p).val & ~3) | ((prot) & 3); } while (0)
104 #define dma_pte_addr(p) ((p).val & VTD_PAGE_MASK)
105 #define dma_set_pte_addr(p, addr) do {\
106 (p).val |= ((addr) & VTD_PAGE_MASK); } while (0)
107 #define dma_pte_present(p) (((p).val & 3) != 0)
112 int id; /* domain id */
113 struct intel_iommu *iommu; /* back pointer to owning iommu */
115 struct list_head devices; /* all devices' list */
116 struct iova_domain iovad; /* iova's that belong to this domain */
118 struct dma_pte *pgd; /* virtual address */
119 spinlock_t mapping_lock; /* page table lock */
120 int gaw; /* max guest address width */
122 /* adjusted guest address width, 0 is level 2 30-bit */
125 #define DOMAIN_FLAG_MULTIPLE_DEVICES 1
129 /* PCI domain-device relationship */
130 struct device_domain_info {
131 struct list_head link; /* link to domain siblings */
132 struct list_head global; /* link to global list */
133 u8 bus; /* PCI bus numer */
134 u8 devfn; /* PCI devfn number */
135 struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
136 struct dmar_domain *domain; /* pointer to domain */
139 extern void free_dmar_iommu(struct intel_iommu *iommu);
141 extern int dmar_disabled;
143 #ifndef CONFIG_DMAR_GFX_WA
144 static inline void iommu_prepare_gfx_mapping(void)
148 #endif /* !CONFIG_DMAR_GFX_WA */