2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/if_ether.h>
37 #include <linux/pci.h>
38 #include <linux/completion.h>
39 #include <linux/radix-tree.h>
40 #include <linux/cpu_rmap.h>
42 #include <linux/atomic.h>
44 #include <linux/clocksource.h>
46 #define MAX_MSIX_P_PORT 17
48 #define MSIX_LEGACY_SZ 4
49 #define MIN_MSIX_P_PORT 5
52 MLX4_FLAG_MSI_X = 1 << 0,
53 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
54 MLX4_FLAG_MASTER = 1 << 2,
55 MLX4_FLAG_SLAVE = 1 << 3,
56 MLX4_FLAG_SRIOV = 1 << 4,
57 MLX4_FLAG_OLD_REG_MAC = 1 << 6,
61 MLX4_PORT_CAP_IS_SM = 1 << 1,
62 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
67 MLX4_MAX_PORT_PKEYS = 128
70 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
71 * These qkeys must not be allowed for general use. This is a 64k range,
72 * and to test for violation, we use the mask (protect against future chg).
74 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
75 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
78 MLX4_BOARD_ID_LEN = 64
85 MLX4_MAX_EQ_NUM = 1024,
86 MLX4_MFUNC_EQ_NUM = 4,
87 MLX4_MFUNC_MAX_EQES = 8,
88 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
91 /* Driver supports 3 diffrent device methods to manage traffic steering:
92 * -device managed - High level API for ib and eth flow steering. FW is
93 * managing flow steering tables.
94 * - B0 steering mode - Common low level API for ib and (if supported) eth.
95 * - A0 steering mode - Limited low level API for eth. In case of IB,
99 MLX4_STEERING_MODE_A0,
100 MLX4_STEERING_MODE_B0,
101 MLX4_STEERING_MODE_DEVICE_MANAGED
104 static inline const char *mlx4_steering_mode_str(int steering_mode)
106 switch (steering_mode) {
107 case MLX4_STEERING_MODE_A0:
108 return "A0 steering";
110 case MLX4_STEERING_MODE_B0:
111 return "B0 steering";
113 case MLX4_STEERING_MODE_DEVICE_MANAGED:
114 return "Device managed flow steering";
117 return "Unrecognize steering mode";
122 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
123 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
124 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
125 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
126 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
127 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
128 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
129 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
130 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
131 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
132 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
133 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
134 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
135 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
136 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
137 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
138 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
139 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
140 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
141 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
142 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
143 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
144 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
145 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
146 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
147 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
148 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
149 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
150 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
151 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
155 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
156 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
157 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
158 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
159 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4,
160 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
161 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
162 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7,
163 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8,
164 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9
168 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
169 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1
173 MLX4_USER_DEV_CAP_64B_CQE = 1L << 0
177 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0
181 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
184 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1,
185 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
186 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
187 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
188 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
189 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
193 MLX4_EVENT_TYPE_COMP = 0x00,
194 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
195 MLX4_EVENT_TYPE_COMM_EST = 0x02,
196 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
197 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
198 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
199 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
200 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
201 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
202 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
203 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
204 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
205 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
206 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
207 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
208 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
209 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
210 MLX4_EVENT_TYPE_CMD = 0x0a,
211 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
212 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
213 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a,
214 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
215 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
216 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
217 MLX4_EVENT_TYPE_NONE = 0xff,
221 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
222 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
226 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
229 enum slave_port_state {
235 enum slave_port_gen_event {
236 SLAVE_PORT_GEN_EVENT_DOWN = 0,
237 SLAVE_PORT_GEN_EVENT_UP,
238 SLAVE_PORT_GEN_EVENT_NONE,
241 enum slave_port_state_event {
242 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
243 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
244 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
245 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
249 MLX4_PERM_LOCAL_READ = 1 << 10,
250 MLX4_PERM_LOCAL_WRITE = 1 << 11,
251 MLX4_PERM_REMOTE_READ = 1 << 12,
252 MLX4_PERM_REMOTE_WRITE = 1 << 13,
253 MLX4_PERM_ATOMIC = 1 << 14,
254 MLX4_PERM_BIND_MW = 1 << 15,
258 MLX4_OPCODE_NOP = 0x00,
259 MLX4_OPCODE_SEND_INVAL = 0x01,
260 MLX4_OPCODE_RDMA_WRITE = 0x08,
261 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
262 MLX4_OPCODE_SEND = 0x0a,
263 MLX4_OPCODE_SEND_IMM = 0x0b,
264 MLX4_OPCODE_LSO = 0x0e,
265 MLX4_OPCODE_RDMA_READ = 0x10,
266 MLX4_OPCODE_ATOMIC_CS = 0x11,
267 MLX4_OPCODE_ATOMIC_FA = 0x12,
268 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
269 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
270 MLX4_OPCODE_BIND_MW = 0x18,
271 MLX4_OPCODE_FMR = 0x19,
272 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
273 MLX4_OPCODE_CONFIG_CMD = 0x1f,
275 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
276 MLX4_RECV_OPCODE_SEND = 0x01,
277 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
278 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
280 MLX4_CQE_OPCODE_ERROR = 0x1e,
281 MLX4_CQE_OPCODE_RESIZE = 0x16,
285 MLX4_STAT_RATE_OFFSET = 5
289 MLX4_PROT_IB_IPV6 = 0,
296 MLX4_MTT_FLAG_PRESENT = 1
299 enum mlx4_qp_region {
300 MLX4_QP_REGION_FW = 0,
301 MLX4_QP_REGION_ETH_ADDR,
302 MLX4_QP_REGION_FC_ADDR,
303 MLX4_QP_REGION_FC_EXCH,
307 enum mlx4_port_type {
308 MLX4_PORT_TYPE_NONE = 0,
309 MLX4_PORT_TYPE_IB = 1,
310 MLX4_PORT_TYPE_ETH = 2,
311 MLX4_PORT_TYPE_AUTO = 3
314 enum mlx4_special_vlan_idx {
315 MLX4_NO_VLAN_IDX = 0,
320 enum mlx4_steer_type {
327 MLX4_NUM_FEXCH = 64 * 1024,
331 MLX4_MAX_FAST_REG_PAGES = 511,
335 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
336 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
337 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
340 /* Port mgmt change event handling */
342 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
343 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
344 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
345 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
346 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
349 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
350 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
352 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
354 return (major << 32) | (minor << 16) | subminor;
357 struct mlx4_phys_caps {
358 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
359 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
363 u32 base_tunnel_sqpn;
370 int vl_cap[MLX4_MAX_PORTS + 1];
371 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
372 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
373 u64 def_mac[MLX4_MAX_PORTS + 1];
374 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
375 int gid_table_len[MLX4_MAX_PORTS + 1];
376 int pkey_table_len[MLX4_MAX_PORTS + 1];
377 int trans_type[MLX4_MAX_PORTS + 1];
378 int vendor_oui[MLX4_MAX_PORTS + 1];
379 int wavelength[MLX4_MAX_PORTS + 1];
380 u64 trans_code[MLX4_MAX_PORTS + 1];
381 int local_ca_ack_delay;
385 int bf_regs_per_page;
392 int max_qp_init_rdma;
393 int max_qp_dest_rdma;
407 int num_comp_vectors;
412 int fmr_reserved_mtts;
421 int fs_log_max_ucast_qp_range_size;
433 u16 stat_rate_support;
434 u8 port_width_cap[MLX4_MAX_PORTS + 1];
437 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
439 int reserved_qps_base[MLX4_NUM_QP_REGION];
443 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
444 u8 supported_type[MLX4_MAX_PORTS + 1];
445 u8 suggested_type[MLX4_MAX_PORTS + 1];
446 u8 default_sense[MLX4_MAX_PORTS + 1];
447 u32 port_mask[MLX4_MAX_PORTS + 1];
448 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
450 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
455 u32 userspace_caps; /* userspace must be aware of these */
456 u32 function_caps; /* VFs must be aware of these */
460 struct mlx4_buf_list {
466 struct mlx4_buf_list direct;
467 struct mlx4_buf_list *page_list;
480 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
483 struct mlx4_db_pgdir {
484 struct list_head list;
485 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
486 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
487 unsigned long *bits[2];
492 struct mlx4_ib_user_db_page;
497 struct mlx4_db_pgdir *pgdir;
498 struct mlx4_ib_user_db_page *user_page;
505 struct mlx4_hwq_resources {
529 enum mlx4_mw_type type;
535 struct mlx4_mpt_entry *mpt;
537 dma_addr_t dma_handle;
547 struct list_head bf_list;
548 unsigned free_bf_bmap;
550 void __iomem *bf_map;
554 unsigned long offset;
556 struct mlx4_uar *uar;
561 void (*comp) (struct mlx4_cq *);
562 void (*event) (struct mlx4_cq *, enum mlx4_event);
564 struct mlx4_uar *uar;
576 struct completion free;
580 void (*event) (struct mlx4_qp *, enum mlx4_event);
585 struct completion free;
589 void (*event) (struct mlx4_srq *, enum mlx4_event);
597 struct completion free;
609 __be32 sl_tclass_flowlabel;
622 __be32 sl_tclass_flowlabel;
631 struct mlx4_eth_av eth;
634 struct mlx4_counter {
656 struct pci_dev *pdev;
658 unsigned long num_slaves;
659 struct mlx4_caps caps;
660 struct mlx4_phys_caps phys_caps;
661 struct mlx4_quotas quotas;
662 struct radix_tree_root qp_table_tree;
664 char board_id[MLX4_BOARD_ID_LEN];
667 int oper_log_mgm_entry_size;
668 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
669 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
705 } __packed port_change;
707 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
709 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
710 } __packed comm_channel_arm;
715 } __packed mac_update;
718 } __packed flr_event;
720 __be16 current_temperature;
721 __be16 warning_threshold;
734 } __packed port_info;
737 __be32 tbl_entries_mask;
738 } __packed tbl_change_info;
740 } __packed port_mgmt_change;
747 struct mlx4_init_port_param {
761 #define mlx4_foreach_port(port, dev, type) \
762 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
763 if ((type) == (dev)->caps.port_mask[(port)])
765 #define mlx4_foreach_non_ib_transport_port(port, dev) \
766 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
767 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB))
769 #define mlx4_foreach_ib_transport_port(port, dev) \
770 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
771 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
772 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
774 #define MLX4_INVALID_SLAVE_ID 0xFF
776 void handle_port_mgmt_change_event(struct work_struct *work);
778 static inline int mlx4_master_func_num(struct mlx4_dev *dev)
780 return dev->caps.function;
783 static inline int mlx4_is_master(struct mlx4_dev *dev)
785 return dev->flags & MLX4_FLAG_MASTER;
788 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev)
790 return dev->phys_caps.base_sqpn + 8 +
791 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev);
794 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
796 return (qpn < dev->phys_caps.base_sqpn + 8 +
797 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev));
800 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
802 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
804 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
810 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
812 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
815 static inline int mlx4_is_slave(struct mlx4_dev *dev)
817 return dev->flags & MLX4_FLAG_SLAVE;
820 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
821 struct mlx4_buf *buf);
822 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
823 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
825 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
826 return buf->direct.buf + offset;
828 return buf->page_list[offset >> PAGE_SHIFT].buf +
829 (offset & (PAGE_SIZE - 1));
832 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
833 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
834 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
835 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
837 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
838 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
839 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node);
840 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
842 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
843 struct mlx4_mtt *mtt);
844 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
845 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
847 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
848 int npages, int page_shift, struct mlx4_mr *mr);
849 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
850 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
851 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
853 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
854 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
855 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
856 int start_index, int npages, u64 *page_list);
857 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
858 struct mlx4_buf *buf);
860 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
861 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
863 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
864 int size, int max_direct);
865 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
868 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
869 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
870 unsigned vector, int collapsed, int timestamp_en);
871 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
873 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
874 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
876 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
877 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
879 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
880 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
881 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
882 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
883 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
885 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
886 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
888 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
889 int block_mcast_loopback, enum mlx4_protocol prot);
890 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
891 enum mlx4_protocol prot);
892 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
893 u8 port, int block_mcast_loopback,
894 enum mlx4_protocol protocol, u64 *reg_id);
895 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
896 enum mlx4_protocol protocol, u64 reg_id);
899 MLX4_DOMAIN_UVERBS = 0x1000,
900 MLX4_DOMAIN_ETHTOOL = 0x2000,
901 MLX4_DOMAIN_RFS = 0x3000,
902 MLX4_DOMAIN_NIC = 0x5000,
905 enum mlx4_net_trans_rule_id {
906 MLX4_NET_TRANS_RULE_ID_ETH = 0,
907 MLX4_NET_TRANS_RULE_ID_IB,
908 MLX4_NET_TRANS_RULE_ID_IPV6,
909 MLX4_NET_TRANS_RULE_ID_IPV4,
910 MLX4_NET_TRANS_RULE_ID_TCP,
911 MLX4_NET_TRANS_RULE_ID_UDP,
912 MLX4_NET_TRANS_RULE_NUM, /* should be last */
915 extern const u16 __sw_id_hw[];
917 static inline int map_hw_to_sw_id(u16 header_id)
921 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
922 if (header_id == __sw_id_hw[i])
928 enum mlx4_net_trans_promisc_mode {
934 MLX4_FS_MODE_NUM, /* should be last */
937 struct mlx4_spec_eth {
938 u8 dst_mac[ETH_ALEN];
939 u8 dst_mac_msk[ETH_ALEN];
940 u8 src_mac[ETH_ALEN];
941 u8 src_mac_msk[ETH_ALEN];
942 u8 ether_type_enable;
948 struct mlx4_spec_tcp_udp {
955 struct mlx4_spec_ipv4 {
962 struct mlx4_spec_ib {
969 struct mlx4_spec_list {
970 struct list_head list;
971 enum mlx4_net_trans_rule_id id;
973 struct mlx4_spec_eth eth;
974 struct mlx4_spec_ib ib;
975 struct mlx4_spec_ipv4 ipv4;
976 struct mlx4_spec_tcp_udp tcp_udp;
980 enum mlx4_net_trans_hw_rule_queue {
981 MLX4_NET_TRANS_Q_FIFO,
982 MLX4_NET_TRANS_Q_LIFO,
985 struct mlx4_net_trans_rule {
986 struct list_head list;
987 enum mlx4_net_trans_hw_rule_queue queue_mode;
990 enum mlx4_net_trans_promisc_mode promisc_mode;
996 struct mlx4_net_trans_rule_hw_ctrl {
1008 struct mlx4_net_trans_rule_hw_ib {
1019 struct mlx4_net_trans_rule_hw_eth {
1032 u8 ether_type_enable;
1034 __be16 vlan_tag_msk;
1038 struct mlx4_net_trans_rule_hw_tcp_udp {
1045 __be16 dst_port_msk;
1049 __be16 src_port_msk;
1052 struct mlx4_net_trans_rule_hw_ipv4 {
1070 struct mlx4_net_trans_rule_hw_eth eth;
1071 struct mlx4_net_trans_rule_hw_ib ib;
1072 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
1073 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
1077 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
1078 enum mlx4_net_trans_promisc_mode mode);
1079 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1080 enum mlx4_net_trans_promisc_mode mode);
1081 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1082 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1083 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1084 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1085 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
1087 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1088 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1089 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
1090 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
1091 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap);
1092 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
1093 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
1094 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
1096 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc);
1097 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
1098 u8 *pg, u16 *ratelimit);
1099 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
1100 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1101 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1103 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
1104 int npages, u64 iova, u32 *lkey, u32 *rkey);
1105 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
1106 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
1107 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1108 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
1109 u32 *lkey, u32 *rkey);
1110 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1111 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1112 int mlx4_test_interrupts(struct mlx4_dev *dev);
1113 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
1115 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1117 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1118 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1120 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
1121 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1123 int mlx4_flow_attach(struct mlx4_dev *dev,
1124 struct mlx4_net_trans_rule *rule, u64 *reg_id);
1125 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1126 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
1127 enum mlx4_net_trans_promisc_mode flow_type);
1128 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
1129 enum mlx4_net_trans_rule_id id);
1130 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
1132 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1135 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1137 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1138 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1139 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1140 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
1141 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1142 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1143 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1145 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1146 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1148 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
1151 cycle_t mlx4_read_clock(struct mlx4_dev *dev);
1153 #endif /* MLX4_DEVICE_H */