2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
77 MLX5_CMD_OP_INIT_HCA = 0x102,
78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
79 MLX5_CMD_OP_ENABLE_HCA = 0x104,
80 MLX5_CMD_OP_DISABLE_HCA = 0x105,
81 MLX5_CMD_OP_QUERY_PAGES = 0x107,
82 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
83 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
84 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
85 MLX5_CMD_OP_SET_ISSI = 0x10b,
86 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
87 MLX5_CMD_OP_CREATE_MKEY = 0x200,
88 MLX5_CMD_OP_QUERY_MKEY = 0x201,
89 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
90 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
91 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
92 MLX5_CMD_OP_CREATE_EQ = 0x301,
93 MLX5_CMD_OP_DESTROY_EQ = 0x302,
94 MLX5_CMD_OP_QUERY_EQ = 0x303,
95 MLX5_CMD_OP_GEN_EQE = 0x304,
96 MLX5_CMD_OP_CREATE_CQ = 0x400,
97 MLX5_CMD_OP_DESTROY_CQ = 0x401,
98 MLX5_CMD_OP_QUERY_CQ = 0x402,
99 MLX5_CMD_OP_MODIFY_CQ = 0x403,
100 MLX5_CMD_OP_CREATE_QP = 0x500,
101 MLX5_CMD_OP_DESTROY_QP = 0x501,
102 MLX5_CMD_OP_RST2INIT_QP = 0x502,
103 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
104 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
105 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
106 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
107 MLX5_CMD_OP_2ERR_QP = 0x507,
108 MLX5_CMD_OP_2RST_QP = 0x50a,
109 MLX5_CMD_OP_QUERY_QP = 0x50b,
110 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
111 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
112 MLX5_CMD_OP_CREATE_PSV = 0x600,
113 MLX5_CMD_OP_DESTROY_PSV = 0x601,
114 MLX5_CMD_OP_CREATE_SRQ = 0x700,
115 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
116 MLX5_CMD_OP_QUERY_SRQ = 0x702,
117 MLX5_CMD_OP_ARM_RQ = 0x703,
118 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
119 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
120 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
121 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
122 MLX5_CMD_OP_CREATE_DCT = 0x710,
123 MLX5_CMD_OP_DESTROY_DCT = 0x711,
124 MLX5_CMD_OP_DRAIN_DCT = 0x712,
125 MLX5_CMD_OP_QUERY_DCT = 0x713,
126 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
127 MLX5_CMD_OP_CREATE_XRQ = 0x717,
128 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
129 MLX5_CMD_OP_QUERY_XRQ = 0x719,
130 MLX5_CMD_OP_ARM_XRQ = 0x71a,
131 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
132 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
133 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
134 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
135 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
136 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
137 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
138 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
139 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
140 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
141 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
142 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
143 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
144 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
145 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
146 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
147 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780,
148 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
149 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
150 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
151 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
152 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
153 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
154 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
155 MLX5_CMD_OP_ALLOC_PD = 0x800,
156 MLX5_CMD_OP_DEALLOC_PD = 0x801,
157 MLX5_CMD_OP_ALLOC_UAR = 0x802,
158 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
159 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
160 MLX5_CMD_OP_ACCESS_REG = 0x805,
161 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
162 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
163 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
164 MLX5_CMD_OP_MAD_IFC = 0x50d,
165 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
166 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
167 MLX5_CMD_OP_NOP = 0x80d,
168 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
169 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
170 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
171 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
172 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
173 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
174 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
175 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
176 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
177 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
178 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
179 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
180 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
181 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
182 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
183 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
184 MLX5_CMD_OP_CREATE_LAG = 0x840,
185 MLX5_CMD_OP_MODIFY_LAG = 0x841,
186 MLX5_CMD_OP_QUERY_LAG = 0x842,
187 MLX5_CMD_OP_DESTROY_LAG = 0x843,
188 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
189 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
190 MLX5_CMD_OP_CREATE_TIR = 0x900,
191 MLX5_CMD_OP_MODIFY_TIR = 0x901,
192 MLX5_CMD_OP_DESTROY_TIR = 0x902,
193 MLX5_CMD_OP_QUERY_TIR = 0x903,
194 MLX5_CMD_OP_CREATE_SQ = 0x904,
195 MLX5_CMD_OP_MODIFY_SQ = 0x905,
196 MLX5_CMD_OP_DESTROY_SQ = 0x906,
197 MLX5_CMD_OP_QUERY_SQ = 0x907,
198 MLX5_CMD_OP_CREATE_RQ = 0x908,
199 MLX5_CMD_OP_MODIFY_RQ = 0x909,
200 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
201 MLX5_CMD_OP_QUERY_RQ = 0x90b,
202 MLX5_CMD_OP_CREATE_RMP = 0x90c,
203 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
204 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
205 MLX5_CMD_OP_QUERY_RMP = 0x90f,
206 MLX5_CMD_OP_CREATE_TIS = 0x912,
207 MLX5_CMD_OP_MODIFY_TIS = 0x913,
208 MLX5_CMD_OP_DESTROY_TIS = 0x914,
209 MLX5_CMD_OP_QUERY_TIS = 0x915,
210 MLX5_CMD_OP_CREATE_RQT = 0x916,
211 MLX5_CMD_OP_MODIFY_RQT = 0x917,
212 MLX5_CMD_OP_DESTROY_RQT = 0x918,
213 MLX5_CMD_OP_QUERY_RQT = 0x919,
214 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
215 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
216 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
217 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
218 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
219 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
220 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
221 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
222 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
223 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
224 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
225 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
226 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
227 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
228 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
229 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
230 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
231 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
235 struct mlx5_ifc_flow_table_fields_supported_bits {
238 u8 outer_ether_type[0x1];
239 u8 outer_ip_version[0x1];
240 u8 outer_first_prio[0x1];
241 u8 outer_first_cfi[0x1];
242 u8 outer_first_vid[0x1];
243 u8 reserved_at_7[0x1];
244 u8 outer_second_prio[0x1];
245 u8 outer_second_cfi[0x1];
246 u8 outer_second_vid[0x1];
247 u8 reserved_at_b[0x1];
251 u8 outer_ip_protocol[0x1];
252 u8 outer_ip_ecn[0x1];
253 u8 outer_ip_dscp[0x1];
254 u8 outer_udp_sport[0x1];
255 u8 outer_udp_dport[0x1];
256 u8 outer_tcp_sport[0x1];
257 u8 outer_tcp_dport[0x1];
258 u8 outer_tcp_flags[0x1];
259 u8 outer_gre_protocol[0x1];
260 u8 outer_gre_key[0x1];
261 u8 outer_vxlan_vni[0x1];
262 u8 reserved_at_1a[0x5];
263 u8 source_eswitch_port[0x1];
267 u8 inner_ether_type[0x1];
268 u8 inner_ip_version[0x1];
269 u8 inner_first_prio[0x1];
270 u8 inner_first_cfi[0x1];
271 u8 inner_first_vid[0x1];
272 u8 reserved_at_27[0x1];
273 u8 inner_second_prio[0x1];
274 u8 inner_second_cfi[0x1];
275 u8 inner_second_vid[0x1];
276 u8 reserved_at_2b[0x1];
280 u8 inner_ip_protocol[0x1];
281 u8 inner_ip_ecn[0x1];
282 u8 inner_ip_dscp[0x1];
283 u8 inner_udp_sport[0x1];
284 u8 inner_udp_dport[0x1];
285 u8 inner_tcp_sport[0x1];
286 u8 inner_tcp_dport[0x1];
287 u8 inner_tcp_flags[0x1];
288 u8 reserved_at_37[0x9];
290 u8 reserved_at_40[0x40];
293 struct mlx5_ifc_flow_table_prop_layout_bits {
295 u8 reserved_at_1[0x1];
296 u8 flow_counter[0x1];
297 u8 flow_modify_en[0x1];
299 u8 identified_miss_table_mode[0x1];
300 u8 flow_table_modify[0x1];
303 u8 reserved_at_9[0x17];
305 u8 reserved_at_20[0x2];
306 u8 log_max_ft_size[0x6];
307 u8 log_max_modify_header_context[0x8];
308 u8 max_modify_header_actions[0x8];
309 u8 max_ft_level[0x8];
311 u8 reserved_at_40[0x20];
313 u8 reserved_at_60[0x18];
314 u8 log_max_ft_num[0x8];
316 u8 reserved_at_80[0x18];
317 u8 log_max_destination[0x8];
319 u8 reserved_at_a0[0x18];
320 u8 log_max_flow[0x8];
322 u8 reserved_at_c0[0x40];
324 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
326 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
329 struct mlx5_ifc_odp_per_transport_service_cap_bits {
336 u8 reserved_at_6[0x1a];
339 struct mlx5_ifc_ipv4_layout_bits {
340 u8 reserved_at_0[0x60];
345 struct mlx5_ifc_ipv6_layout_bits {
349 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
350 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
351 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
352 u8 reserved_at_0[0x80];
355 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
380 u8 reserved_at_c0[0x20];
385 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
387 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
390 struct mlx5_ifc_fte_match_set_misc_bits {
391 u8 reserved_at_0[0x8];
394 u8 reserved_at_20[0x10];
395 u8 source_port[0x10];
397 u8 outer_second_prio[0x3];
398 u8 outer_second_cfi[0x1];
399 u8 outer_second_vid[0xc];
400 u8 inner_second_prio[0x3];
401 u8 inner_second_cfi[0x1];
402 u8 inner_second_vid[0xc];
404 u8 outer_second_cvlan_tag[0x1];
405 u8 inner_second_cvlan_tag[0x1];
406 u8 outer_second_svlan_tag[0x1];
407 u8 inner_second_svlan_tag[0x1];
408 u8 reserved_at_64[0xc];
409 u8 gre_protocol[0x10];
415 u8 reserved_at_b8[0x8];
417 u8 reserved_at_c0[0x20];
419 u8 reserved_at_e0[0xc];
420 u8 outer_ipv6_flow_label[0x14];
422 u8 reserved_at_100[0xc];
423 u8 inner_ipv6_flow_label[0x14];
425 u8 reserved_at_120[0xe0];
428 struct mlx5_ifc_cmd_pas_bits {
432 u8 reserved_at_34[0xc];
435 struct mlx5_ifc_uint64_bits {
442 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
443 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
444 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
445 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
446 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
447 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
448 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
449 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
450 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
451 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
454 struct mlx5_ifc_ads_bits {
457 u8 reserved_at_2[0xe];
460 u8 reserved_at_20[0x8];
466 u8 reserved_at_45[0x3];
467 u8 src_addr_index[0x8];
468 u8 reserved_at_50[0x4];
472 u8 reserved_at_60[0x4];
476 u8 rgid_rip[16][0x8];
478 u8 reserved_at_100[0x4];
481 u8 reserved_at_106[0x1];
496 struct mlx5_ifc_flow_table_nic_cap_bits {
497 u8 nic_rx_multi_path_tirs[0x1];
498 u8 nic_rx_multi_path_tirs_fts[0x1];
499 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
500 u8 reserved_at_3[0x1fd];
502 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
504 u8 reserved_at_400[0x200];
506 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
508 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
510 u8 reserved_at_a00[0x200];
512 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
514 u8 reserved_at_e00[0x7200];
517 struct mlx5_ifc_flow_table_eswitch_cap_bits {
518 u8 reserved_at_0[0x200];
520 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
522 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
524 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
526 u8 reserved_at_800[0x7800];
529 struct mlx5_ifc_e_switch_cap_bits {
530 u8 vport_svlan_strip[0x1];
531 u8 vport_cvlan_strip[0x1];
532 u8 vport_svlan_insert[0x1];
533 u8 vport_cvlan_insert_if_not_exist[0x1];
534 u8 vport_cvlan_insert_overwrite[0x1];
535 u8 reserved_at_5[0x19];
536 u8 nic_vport_node_guid_modify[0x1];
537 u8 nic_vport_port_guid_modify[0x1];
539 u8 vxlan_encap_decap[0x1];
540 u8 nvgre_encap_decap[0x1];
541 u8 reserved_at_22[0x9];
542 u8 log_max_encap_headers[0x5];
544 u8 max_encap_header_size[0xa];
546 u8 reserved_40[0x7c0];
550 struct mlx5_ifc_qos_cap_bits {
551 u8 packet_pacing[0x1];
552 u8 esw_scheduling[0x1];
553 u8 esw_bw_share[0x1];
554 u8 esw_rate_limit[0x1];
555 u8 reserved_at_4[0x1c];
557 u8 reserved_at_20[0x20];
559 u8 packet_pacing_max_rate[0x20];
561 u8 packet_pacing_min_rate[0x20];
563 u8 reserved_at_80[0x10];
564 u8 packet_pacing_rate_table_size[0x10];
566 u8 esw_element_type[0x10];
567 u8 esw_tsar_type[0x10];
569 u8 reserved_at_c0[0x10];
570 u8 max_qos_para_vport[0x10];
572 u8 max_tsar_bw_share[0x20];
574 u8 reserved_at_100[0x700];
577 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
581 u8 lro_psh_flag[0x1];
582 u8 lro_time_stamp[0x1];
583 u8 reserved_at_5[0x2];
584 u8 wqe_vlan_insert[0x1];
585 u8 self_lb_en_modifiable[0x1];
586 u8 reserved_at_9[0x2];
588 u8 multi_pkt_send_wqe[0x2];
589 u8 wqe_inline_mode[0x2];
590 u8 rss_ind_tbl_cap[0x4];
593 u8 reserved_at_1a[0x1];
594 u8 tunnel_lso_const_out_ip_id[0x1];
595 u8 reserved_at_1c[0x2];
596 u8 tunnel_statless_gre[0x1];
597 u8 tunnel_stateless_vxlan[0x1];
599 u8 reserved_at_20[0x20];
601 u8 reserved_at_40[0x10];
602 u8 lro_min_mss_size[0x10];
604 u8 reserved_at_60[0x120];
606 u8 lro_timer_supported_periods[4][0x20];
608 u8 reserved_at_200[0x600];
611 struct mlx5_ifc_roce_cap_bits {
613 u8 reserved_at_1[0x1f];
615 u8 reserved_at_20[0x60];
617 u8 reserved_at_80[0xc];
619 u8 reserved_at_90[0x8];
620 u8 roce_version[0x8];
622 u8 reserved_at_a0[0x10];
623 u8 r_roce_dest_udp_port[0x10];
625 u8 r_roce_max_src_udp_port[0x10];
626 u8 r_roce_min_src_udp_port[0x10];
628 u8 reserved_at_e0[0x10];
629 u8 roce_address_table_size[0x10];
631 u8 reserved_at_100[0x700];
635 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
636 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
637 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
638 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
639 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
640 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
641 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
642 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
643 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
647 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
648 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
649 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
650 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
651 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
652 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
653 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
654 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
655 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
658 struct mlx5_ifc_atomic_caps_bits {
659 u8 reserved_at_0[0x40];
661 u8 atomic_req_8B_endianess_mode[0x2];
662 u8 reserved_at_42[0x4];
663 u8 supported_atomic_req_8B_endianess_mode_1[0x1];
665 u8 reserved_at_47[0x19];
667 u8 reserved_at_60[0x20];
669 u8 reserved_at_80[0x10];
670 u8 atomic_operations[0x10];
672 u8 reserved_at_a0[0x10];
673 u8 atomic_size_qp[0x10];
675 u8 reserved_at_c0[0x10];
676 u8 atomic_size_dc[0x10];
678 u8 reserved_at_e0[0x720];
681 struct mlx5_ifc_odp_cap_bits {
682 u8 reserved_at_0[0x40];
685 u8 reserved_at_41[0x1f];
687 u8 reserved_at_60[0x20];
689 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
691 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
693 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
695 u8 reserved_at_e0[0x720];
698 struct mlx5_ifc_calc_op {
699 u8 reserved_at_0[0x10];
700 u8 reserved_at_10[0x9];
701 u8 op_swap_endianness[0x1];
710 struct mlx5_ifc_vector_calc_cap_bits {
712 u8 reserved_at_1[0x1f];
713 u8 reserved_at_20[0x8];
714 u8 max_vec_count[0x8];
715 u8 reserved_at_30[0xd];
716 u8 max_chunk_size[0x3];
717 struct mlx5_ifc_calc_op calc0;
718 struct mlx5_ifc_calc_op calc1;
719 struct mlx5_ifc_calc_op calc2;
720 struct mlx5_ifc_calc_op calc3;
722 u8 reserved_at_e0[0x720];
726 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
727 MLX5_WQ_TYPE_CYCLIC = 0x1,
728 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
732 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
733 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
737 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
738 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
739 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
740 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
741 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
745 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
746 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
747 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
748 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
749 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
750 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
754 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
755 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
759 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
760 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
761 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
765 MLX5_CAP_PORT_TYPE_IB = 0x0,
766 MLX5_CAP_PORT_TYPE_ETH = 0x1,
769 struct mlx5_ifc_cmd_hca_cap_bits {
770 u8 reserved_at_0[0x80];
772 u8 log_max_srq_sz[0x8];
773 u8 log_max_qp_sz[0x8];
774 u8 reserved_at_90[0xb];
777 u8 reserved_at_a0[0xb];
779 u8 reserved_at_b0[0x10];
781 u8 reserved_at_c0[0x8];
782 u8 log_max_cq_sz[0x8];
783 u8 reserved_at_d0[0xb];
786 u8 log_max_eq_sz[0x8];
787 u8 reserved_at_e8[0x2];
788 u8 log_max_mkey[0x6];
789 u8 reserved_at_f0[0xc];
792 u8 max_indirection[0x8];
793 u8 fixed_buffer_size[0x1];
794 u8 log_max_mrw_sz[0x7];
795 u8 reserved_at_110[0x2];
796 u8 log_max_bsf_list_size[0x6];
797 u8 umr_extended_translation_offset[0x1];
799 u8 log_max_klm_list_size[0x6];
801 u8 reserved_at_120[0xa];
802 u8 log_max_ra_req_dc[0x6];
803 u8 reserved_at_130[0xa];
804 u8 log_max_ra_res_dc[0x6];
806 u8 reserved_at_140[0xa];
807 u8 log_max_ra_req_qp[0x6];
808 u8 reserved_at_150[0xa];
809 u8 log_max_ra_res_qp[0x6];
812 u8 cc_query_allowed[0x1];
813 u8 cc_modify_allowed[0x1];
815 u8 cache_line_128byte[0x1];
816 u8 reserved_at_163[0xb];
817 u8 gid_table_size[0x10];
819 u8 out_of_seq_cnt[0x1];
820 u8 vport_counters[0x1];
821 u8 retransmission_q_counters[0x1];
822 u8 reserved_at_183[0x1];
823 u8 modify_rq_counter_set_id[0x1];
824 u8 reserved_at_185[0x1];
826 u8 pkey_table_size[0x10];
828 u8 vport_group_manager[0x1];
829 u8 vhca_group_manager[0x1];
832 u8 reserved_at_1a4[0x1];
834 u8 nic_flow_table[0x1];
835 u8 eswitch_flow_table[0x1];
836 u8 early_vf_enable[0x1];
839 u8 local_ca_ack_delay[0x5];
840 u8 port_module_event[0x1];
841 u8 reserved_at_1b1[0x1];
843 u8 reserved_at_1b3[0x1];
844 u8 disable_link_up[0x1];
849 u8 reserved_at_1c0[0x1];
853 u8 reserved_at_1c8[0x4];
855 u8 reserved_at_1d0[0x1];
857 u8 reserved_at_1d2[0x4];
860 u8 reserved_at_1d8[0x1];
869 u8 stat_rate_support[0x10];
870 u8 reserved_at_1f0[0xc];
873 u8 compact_address_vector[0x1];
875 u8 reserved_at_202[0x1];
876 u8 ipoib_enhanced_offloads[0x1];
877 u8 ipoib_basic_offloads[0x1];
878 u8 reserved_at_205[0xa];
879 u8 drain_sigerr[0x1];
880 u8 cmdif_checksum[0x2];
882 u8 reserved_at_213[0x1];
883 u8 wq_signature[0x1];
884 u8 sctr_data_cqe[0x1];
885 u8 reserved_at_216[0x1];
891 u8 eth_net_offloads[0x1];
894 u8 reserved_at_21f[0x1];
898 u8 cq_moderation[0x1];
899 u8 reserved_at_223[0x3];
903 u8 reserved_at_229[0x1];
904 u8 scqe_break_moderation[0x1];
905 u8 cq_period_start_from_cqe[0x1];
907 u8 reserved_at_22d[0x1];
910 u8 umr_ptr_rlky[0x1];
912 u8 reserved_at_232[0x4];
915 u8 set_deth_sqpn[0x1];
916 u8 reserved_at_239[0x3];
923 u8 reserved_at_241[0x9];
925 u8 reserved_at_250[0x8];
929 u8 driver_version[0x1];
930 u8 pad_tx_eth_packet[0x1];
931 u8 reserved_at_263[0x8];
932 u8 log_bf_reg_size[0x5];
934 u8 reserved_at_270[0xb];
936 u8 num_lag_ports[0x4];
938 u8 reserved_at_280[0x10];
939 u8 max_wqe_sz_sq[0x10];
941 u8 reserved_at_2a0[0x10];
942 u8 max_wqe_sz_rq[0x10];
944 u8 reserved_at_2c0[0x10];
945 u8 max_wqe_sz_sq_dc[0x10];
947 u8 reserved_at_2e0[0x7];
950 u8 reserved_at_300[0x18];
953 u8 reserved_at_320[0x3];
954 u8 log_max_transport_domain[0x5];
955 u8 reserved_at_328[0x3];
957 u8 reserved_at_330[0xb];
958 u8 log_max_xrcd[0x5];
960 u8 reserved_at_340[0x8];
961 u8 log_max_flow_counter_bulk[0x8];
962 u8 max_flow_counter[0x10];
965 u8 reserved_at_360[0x3];
967 u8 reserved_at_368[0x3];
969 u8 reserved_at_370[0x3];
971 u8 reserved_at_378[0x3];
974 u8 basic_cyclic_rcv_wqe[0x1];
975 u8 reserved_at_381[0x2];
977 u8 reserved_at_388[0x3];
979 u8 reserved_at_390[0x3];
980 u8 log_max_rqt_size[0x5];
981 u8 reserved_at_398[0x3];
982 u8 log_max_tis_per_sq[0x5];
984 u8 reserved_at_3a0[0x3];
985 u8 log_max_stride_sz_rq[0x5];
986 u8 reserved_at_3a8[0x3];
987 u8 log_min_stride_sz_rq[0x5];
988 u8 reserved_at_3b0[0x3];
989 u8 log_max_stride_sz_sq[0x5];
990 u8 reserved_at_3b8[0x3];
991 u8 log_min_stride_sz_sq[0x5];
993 u8 reserved_at_3c0[0x1b];
994 u8 log_max_wq_sz[0x5];
996 u8 nic_vport_change_event[0x1];
997 u8 reserved_at_3e1[0xa];
998 u8 log_max_vlan_list[0x5];
999 u8 reserved_at_3f0[0x3];
1000 u8 log_max_current_mc_list[0x5];
1001 u8 reserved_at_3f8[0x3];
1002 u8 log_max_current_uc_list[0x5];
1004 u8 reserved_at_400[0x80];
1006 u8 reserved_at_480[0x3];
1007 u8 log_max_l2_table[0x5];
1008 u8 reserved_at_488[0x8];
1009 u8 log_uar_page_sz[0x10];
1011 u8 reserved_at_4a0[0x20];
1012 u8 device_frequency_mhz[0x20];
1013 u8 device_frequency_khz[0x20];
1015 u8 reserved_at_500[0x20];
1016 u8 num_of_uars_per_page[0x20];
1017 u8 reserved_at_540[0x40];
1019 u8 reserved_at_580[0x3f];
1020 u8 cqe_compression[0x1];
1022 u8 cqe_compression_timeout[0x10];
1023 u8 cqe_compression_max_num[0x10];
1025 u8 reserved_at_5e0[0x10];
1026 u8 tag_matching[0x1];
1027 u8 rndv_offload_rc[0x1];
1028 u8 rndv_offload_dc[0x1];
1029 u8 log_tag_matching_list_sz[0x5];
1030 u8 reserved_at_5f8[0x3];
1031 u8 log_max_xrq[0x5];
1033 u8 reserved_at_600[0x200];
1036 enum mlx5_flow_destination_type {
1037 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1038 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1039 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1041 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
1044 struct mlx5_ifc_dest_format_struct_bits {
1045 u8 destination_type[0x8];
1046 u8 destination_id[0x18];
1048 u8 reserved_at_20[0x20];
1051 struct mlx5_ifc_flow_counter_list_bits {
1053 u8 num_of_counters[0xf];
1054 u8 flow_counter_id[0x10];
1056 u8 reserved_at_20[0x20];
1059 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1060 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1061 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1062 u8 reserved_at_0[0x40];
1065 struct mlx5_ifc_fte_match_param_bits {
1066 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1068 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1070 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1072 u8 reserved_at_600[0xa00];
1076 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1077 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1078 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1079 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1080 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1083 struct mlx5_ifc_rx_hash_field_select_bits {
1084 u8 l3_prot_type[0x1];
1085 u8 l4_prot_type[0x1];
1086 u8 selected_fields[0x1e];
1090 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1091 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1095 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1096 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1099 struct mlx5_ifc_wq_bits {
1101 u8 wq_signature[0x1];
1102 u8 end_padding_mode[0x2];
1104 u8 reserved_at_8[0x18];
1106 u8 hds_skip_first_sge[0x1];
1107 u8 log2_hds_buf_size[0x3];
1108 u8 reserved_at_24[0x7];
1109 u8 page_offset[0x5];
1112 u8 reserved_at_40[0x8];
1115 u8 reserved_at_60[0x8];
1120 u8 hw_counter[0x20];
1122 u8 sw_counter[0x20];
1124 u8 reserved_at_100[0xc];
1125 u8 log_wq_stride[0x4];
1126 u8 reserved_at_110[0x3];
1127 u8 log_wq_pg_sz[0x5];
1128 u8 reserved_at_118[0x3];
1131 u8 reserved_at_120[0x15];
1132 u8 log_wqe_num_of_strides[0x3];
1133 u8 two_byte_shift_en[0x1];
1134 u8 reserved_at_139[0x4];
1135 u8 log_wqe_stride_size[0x3];
1137 u8 reserved_at_140[0x4c0];
1139 struct mlx5_ifc_cmd_pas_bits pas[0];
1142 struct mlx5_ifc_rq_num_bits {
1143 u8 reserved_at_0[0x8];
1147 struct mlx5_ifc_mac_address_layout_bits {
1148 u8 reserved_at_0[0x10];
1149 u8 mac_addr_47_32[0x10];
1151 u8 mac_addr_31_0[0x20];
1154 struct mlx5_ifc_vlan_layout_bits {
1155 u8 reserved_at_0[0x14];
1158 u8 reserved_at_20[0x20];
1161 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1162 u8 reserved_at_0[0xa0];
1164 u8 min_time_between_cnps[0x20];
1166 u8 reserved_at_c0[0x12];
1168 u8 reserved_at_d8[0x5];
1169 u8 cnp_802p_prio[0x3];
1171 u8 reserved_at_e0[0x720];
1174 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1175 u8 reserved_at_0[0x60];
1177 u8 reserved_at_60[0x4];
1178 u8 clamp_tgt_rate[0x1];
1179 u8 reserved_at_65[0x3];
1180 u8 clamp_tgt_rate_after_time_inc[0x1];
1181 u8 reserved_at_69[0x17];
1183 u8 reserved_at_80[0x20];
1185 u8 rpg_time_reset[0x20];
1187 u8 rpg_byte_reset[0x20];
1189 u8 rpg_threshold[0x20];
1191 u8 rpg_max_rate[0x20];
1193 u8 rpg_ai_rate[0x20];
1195 u8 rpg_hai_rate[0x20];
1199 u8 rpg_min_dec_fac[0x20];
1201 u8 rpg_min_rate[0x20];
1203 u8 reserved_at_1c0[0xe0];
1205 u8 rate_to_set_on_first_cnp[0x20];
1209 u8 dce_tcp_rtt[0x20];
1211 u8 rate_reduce_monitor_period[0x20];
1213 u8 reserved_at_320[0x20];
1215 u8 initial_alpha_value[0x20];
1217 u8 reserved_at_360[0x4a0];
1220 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1221 u8 reserved_at_0[0x80];
1223 u8 rppp_max_rps[0x20];
1225 u8 rpg_time_reset[0x20];
1227 u8 rpg_byte_reset[0x20];
1229 u8 rpg_threshold[0x20];
1231 u8 rpg_max_rate[0x20];
1233 u8 rpg_ai_rate[0x20];
1235 u8 rpg_hai_rate[0x20];
1239 u8 rpg_min_dec_fac[0x20];
1241 u8 rpg_min_rate[0x20];
1243 u8 reserved_at_1c0[0x640];
1247 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1248 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1249 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1252 struct mlx5_ifc_resize_field_select_bits {
1253 u8 resize_field_select[0x20];
1257 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1258 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1259 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1260 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1263 struct mlx5_ifc_modify_field_select_bits {
1264 u8 modify_field_select[0x20];
1267 struct mlx5_ifc_field_select_r_roce_np_bits {
1268 u8 field_select_r_roce_np[0x20];
1271 struct mlx5_ifc_field_select_r_roce_rp_bits {
1272 u8 field_select_r_roce_rp[0x20];
1276 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1277 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1278 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1279 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1280 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1281 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1282 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1283 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1284 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1285 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1288 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1289 u8 field_select_8021qaurp[0x20];
1292 struct mlx5_ifc_phys_layer_cntrs_bits {
1293 u8 time_since_last_clear_high[0x20];
1295 u8 time_since_last_clear_low[0x20];
1297 u8 symbol_errors_high[0x20];
1299 u8 symbol_errors_low[0x20];
1301 u8 sync_headers_errors_high[0x20];
1303 u8 sync_headers_errors_low[0x20];
1305 u8 edpl_bip_errors_lane0_high[0x20];
1307 u8 edpl_bip_errors_lane0_low[0x20];
1309 u8 edpl_bip_errors_lane1_high[0x20];
1311 u8 edpl_bip_errors_lane1_low[0x20];
1313 u8 edpl_bip_errors_lane2_high[0x20];
1315 u8 edpl_bip_errors_lane2_low[0x20];
1317 u8 edpl_bip_errors_lane3_high[0x20];
1319 u8 edpl_bip_errors_lane3_low[0x20];
1321 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1323 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1325 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1327 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1329 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1331 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1333 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1335 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1337 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1339 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1341 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1343 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1345 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1347 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1349 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1351 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1353 u8 rs_fec_corrected_blocks_high[0x20];
1355 u8 rs_fec_corrected_blocks_low[0x20];
1357 u8 rs_fec_uncorrectable_blocks_high[0x20];
1359 u8 rs_fec_uncorrectable_blocks_low[0x20];
1361 u8 rs_fec_no_errors_blocks_high[0x20];
1363 u8 rs_fec_no_errors_blocks_low[0x20];
1365 u8 rs_fec_single_error_blocks_high[0x20];
1367 u8 rs_fec_single_error_blocks_low[0x20];
1369 u8 rs_fec_corrected_symbols_total_high[0x20];
1371 u8 rs_fec_corrected_symbols_total_low[0x20];
1373 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1375 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1377 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1379 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1381 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1383 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1385 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1387 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1389 u8 link_down_events[0x20];
1391 u8 successful_recovery_events[0x20];
1393 u8 reserved_at_640[0x180];
1396 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1397 u8 time_since_last_clear_high[0x20];
1399 u8 time_since_last_clear_low[0x20];
1401 u8 phy_received_bits_high[0x20];
1403 u8 phy_received_bits_low[0x20];
1405 u8 phy_symbol_errors_high[0x20];
1407 u8 phy_symbol_errors_low[0x20];
1409 u8 phy_corrected_bits_high[0x20];
1411 u8 phy_corrected_bits_low[0x20];
1413 u8 phy_corrected_bits_lane0_high[0x20];
1415 u8 phy_corrected_bits_lane0_low[0x20];
1417 u8 phy_corrected_bits_lane1_high[0x20];
1419 u8 phy_corrected_bits_lane1_low[0x20];
1421 u8 phy_corrected_bits_lane2_high[0x20];
1423 u8 phy_corrected_bits_lane2_low[0x20];
1425 u8 phy_corrected_bits_lane3_high[0x20];
1427 u8 phy_corrected_bits_lane3_low[0x20];
1429 u8 reserved_at_200[0x5c0];
1432 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1433 u8 symbol_error_counter[0x10];
1435 u8 link_error_recovery_counter[0x8];
1437 u8 link_downed_counter[0x8];
1439 u8 port_rcv_errors[0x10];
1441 u8 port_rcv_remote_physical_errors[0x10];
1443 u8 port_rcv_switch_relay_errors[0x10];
1445 u8 port_xmit_discards[0x10];
1447 u8 port_xmit_constraint_errors[0x8];
1449 u8 port_rcv_constraint_errors[0x8];
1451 u8 reserved_at_70[0x8];
1453 u8 link_overrun_errors[0x8];
1455 u8 reserved_at_80[0x10];
1457 u8 vl_15_dropped[0x10];
1459 u8 reserved_at_a0[0x80];
1461 u8 port_xmit_wait[0x20];
1464 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1465 u8 transmit_queue_high[0x20];
1467 u8 transmit_queue_low[0x20];
1469 u8 reserved_at_40[0x780];
1472 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1473 u8 rx_octets_high[0x20];
1475 u8 rx_octets_low[0x20];
1477 u8 reserved_at_40[0xc0];
1479 u8 rx_frames_high[0x20];
1481 u8 rx_frames_low[0x20];
1483 u8 tx_octets_high[0x20];
1485 u8 tx_octets_low[0x20];
1487 u8 reserved_at_180[0xc0];
1489 u8 tx_frames_high[0x20];
1491 u8 tx_frames_low[0x20];
1493 u8 rx_pause_high[0x20];
1495 u8 rx_pause_low[0x20];
1497 u8 rx_pause_duration_high[0x20];
1499 u8 rx_pause_duration_low[0x20];
1501 u8 tx_pause_high[0x20];
1503 u8 tx_pause_low[0x20];
1505 u8 tx_pause_duration_high[0x20];
1507 u8 tx_pause_duration_low[0x20];
1509 u8 rx_pause_transition_high[0x20];
1511 u8 rx_pause_transition_low[0x20];
1513 u8 reserved_at_3c0[0x400];
1516 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1517 u8 port_transmit_wait_high[0x20];
1519 u8 port_transmit_wait_low[0x20];
1521 u8 reserved_at_40[0x780];
1524 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1525 u8 dot3stats_alignment_errors_high[0x20];
1527 u8 dot3stats_alignment_errors_low[0x20];
1529 u8 dot3stats_fcs_errors_high[0x20];
1531 u8 dot3stats_fcs_errors_low[0x20];
1533 u8 dot3stats_single_collision_frames_high[0x20];
1535 u8 dot3stats_single_collision_frames_low[0x20];
1537 u8 dot3stats_multiple_collision_frames_high[0x20];
1539 u8 dot3stats_multiple_collision_frames_low[0x20];
1541 u8 dot3stats_sqe_test_errors_high[0x20];
1543 u8 dot3stats_sqe_test_errors_low[0x20];
1545 u8 dot3stats_deferred_transmissions_high[0x20];
1547 u8 dot3stats_deferred_transmissions_low[0x20];
1549 u8 dot3stats_late_collisions_high[0x20];
1551 u8 dot3stats_late_collisions_low[0x20];
1553 u8 dot3stats_excessive_collisions_high[0x20];
1555 u8 dot3stats_excessive_collisions_low[0x20];
1557 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1559 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1561 u8 dot3stats_carrier_sense_errors_high[0x20];
1563 u8 dot3stats_carrier_sense_errors_low[0x20];
1565 u8 dot3stats_frame_too_longs_high[0x20];
1567 u8 dot3stats_frame_too_longs_low[0x20];
1569 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1571 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1573 u8 dot3stats_symbol_errors_high[0x20];
1575 u8 dot3stats_symbol_errors_low[0x20];
1577 u8 dot3control_in_unknown_opcodes_high[0x20];
1579 u8 dot3control_in_unknown_opcodes_low[0x20];
1581 u8 dot3in_pause_frames_high[0x20];
1583 u8 dot3in_pause_frames_low[0x20];
1585 u8 dot3out_pause_frames_high[0x20];
1587 u8 dot3out_pause_frames_low[0x20];
1589 u8 reserved_at_400[0x3c0];
1592 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1593 u8 ether_stats_drop_events_high[0x20];
1595 u8 ether_stats_drop_events_low[0x20];
1597 u8 ether_stats_octets_high[0x20];
1599 u8 ether_stats_octets_low[0x20];
1601 u8 ether_stats_pkts_high[0x20];
1603 u8 ether_stats_pkts_low[0x20];
1605 u8 ether_stats_broadcast_pkts_high[0x20];
1607 u8 ether_stats_broadcast_pkts_low[0x20];
1609 u8 ether_stats_multicast_pkts_high[0x20];
1611 u8 ether_stats_multicast_pkts_low[0x20];
1613 u8 ether_stats_crc_align_errors_high[0x20];
1615 u8 ether_stats_crc_align_errors_low[0x20];
1617 u8 ether_stats_undersize_pkts_high[0x20];
1619 u8 ether_stats_undersize_pkts_low[0x20];
1621 u8 ether_stats_oversize_pkts_high[0x20];
1623 u8 ether_stats_oversize_pkts_low[0x20];
1625 u8 ether_stats_fragments_high[0x20];
1627 u8 ether_stats_fragments_low[0x20];
1629 u8 ether_stats_jabbers_high[0x20];
1631 u8 ether_stats_jabbers_low[0x20];
1633 u8 ether_stats_collisions_high[0x20];
1635 u8 ether_stats_collisions_low[0x20];
1637 u8 ether_stats_pkts64octets_high[0x20];
1639 u8 ether_stats_pkts64octets_low[0x20];
1641 u8 ether_stats_pkts65to127octets_high[0x20];
1643 u8 ether_stats_pkts65to127octets_low[0x20];
1645 u8 ether_stats_pkts128to255octets_high[0x20];
1647 u8 ether_stats_pkts128to255octets_low[0x20];
1649 u8 ether_stats_pkts256to511octets_high[0x20];
1651 u8 ether_stats_pkts256to511octets_low[0x20];
1653 u8 ether_stats_pkts512to1023octets_high[0x20];
1655 u8 ether_stats_pkts512to1023octets_low[0x20];
1657 u8 ether_stats_pkts1024to1518octets_high[0x20];
1659 u8 ether_stats_pkts1024to1518octets_low[0x20];
1661 u8 ether_stats_pkts1519to2047octets_high[0x20];
1663 u8 ether_stats_pkts1519to2047octets_low[0x20];
1665 u8 ether_stats_pkts2048to4095octets_high[0x20];
1667 u8 ether_stats_pkts2048to4095octets_low[0x20];
1669 u8 ether_stats_pkts4096to8191octets_high[0x20];
1671 u8 ether_stats_pkts4096to8191octets_low[0x20];
1673 u8 ether_stats_pkts8192to10239octets_high[0x20];
1675 u8 ether_stats_pkts8192to10239octets_low[0x20];
1677 u8 reserved_at_540[0x280];
1680 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1681 u8 if_in_octets_high[0x20];
1683 u8 if_in_octets_low[0x20];
1685 u8 if_in_ucast_pkts_high[0x20];
1687 u8 if_in_ucast_pkts_low[0x20];
1689 u8 if_in_discards_high[0x20];
1691 u8 if_in_discards_low[0x20];
1693 u8 if_in_errors_high[0x20];
1695 u8 if_in_errors_low[0x20];
1697 u8 if_in_unknown_protos_high[0x20];
1699 u8 if_in_unknown_protos_low[0x20];
1701 u8 if_out_octets_high[0x20];
1703 u8 if_out_octets_low[0x20];
1705 u8 if_out_ucast_pkts_high[0x20];
1707 u8 if_out_ucast_pkts_low[0x20];
1709 u8 if_out_discards_high[0x20];
1711 u8 if_out_discards_low[0x20];
1713 u8 if_out_errors_high[0x20];
1715 u8 if_out_errors_low[0x20];
1717 u8 if_in_multicast_pkts_high[0x20];
1719 u8 if_in_multicast_pkts_low[0x20];
1721 u8 if_in_broadcast_pkts_high[0x20];
1723 u8 if_in_broadcast_pkts_low[0x20];
1725 u8 if_out_multicast_pkts_high[0x20];
1727 u8 if_out_multicast_pkts_low[0x20];
1729 u8 if_out_broadcast_pkts_high[0x20];
1731 u8 if_out_broadcast_pkts_low[0x20];
1733 u8 reserved_at_340[0x480];
1736 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1737 u8 a_frames_transmitted_ok_high[0x20];
1739 u8 a_frames_transmitted_ok_low[0x20];
1741 u8 a_frames_received_ok_high[0x20];
1743 u8 a_frames_received_ok_low[0x20];
1745 u8 a_frame_check_sequence_errors_high[0x20];
1747 u8 a_frame_check_sequence_errors_low[0x20];
1749 u8 a_alignment_errors_high[0x20];
1751 u8 a_alignment_errors_low[0x20];
1753 u8 a_octets_transmitted_ok_high[0x20];
1755 u8 a_octets_transmitted_ok_low[0x20];
1757 u8 a_octets_received_ok_high[0x20];
1759 u8 a_octets_received_ok_low[0x20];
1761 u8 a_multicast_frames_xmitted_ok_high[0x20];
1763 u8 a_multicast_frames_xmitted_ok_low[0x20];
1765 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1767 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1769 u8 a_multicast_frames_received_ok_high[0x20];
1771 u8 a_multicast_frames_received_ok_low[0x20];
1773 u8 a_broadcast_frames_received_ok_high[0x20];
1775 u8 a_broadcast_frames_received_ok_low[0x20];
1777 u8 a_in_range_length_errors_high[0x20];
1779 u8 a_in_range_length_errors_low[0x20];
1781 u8 a_out_of_range_length_field_high[0x20];
1783 u8 a_out_of_range_length_field_low[0x20];
1785 u8 a_frame_too_long_errors_high[0x20];
1787 u8 a_frame_too_long_errors_low[0x20];
1789 u8 a_symbol_error_during_carrier_high[0x20];
1791 u8 a_symbol_error_during_carrier_low[0x20];
1793 u8 a_mac_control_frames_transmitted_high[0x20];
1795 u8 a_mac_control_frames_transmitted_low[0x20];
1797 u8 a_mac_control_frames_received_high[0x20];
1799 u8 a_mac_control_frames_received_low[0x20];
1801 u8 a_unsupported_opcodes_received_high[0x20];
1803 u8 a_unsupported_opcodes_received_low[0x20];
1805 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1807 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1809 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1811 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1813 u8 reserved_at_4c0[0x300];
1816 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1817 u8 life_time_counter_high[0x20];
1819 u8 life_time_counter_low[0x20];
1825 u8 l0_to_recovery_eieos[0x20];
1827 u8 l0_to_recovery_ts[0x20];
1829 u8 l0_to_recovery_framing[0x20];
1831 u8 l0_to_recovery_retrain[0x20];
1833 u8 crc_error_dllp[0x20];
1835 u8 crc_error_tlp[0x20];
1837 u8 reserved_at_140[0x680];
1840 struct mlx5_ifc_cmd_inter_comp_event_bits {
1841 u8 command_completion_vector[0x20];
1843 u8 reserved_at_20[0xc0];
1846 struct mlx5_ifc_stall_vl_event_bits {
1847 u8 reserved_at_0[0x18];
1849 u8 reserved_at_19[0x3];
1852 u8 reserved_at_20[0xa0];
1855 struct mlx5_ifc_db_bf_congestion_event_bits {
1856 u8 event_subtype[0x8];
1857 u8 reserved_at_8[0x8];
1858 u8 congestion_level[0x8];
1859 u8 reserved_at_18[0x8];
1861 u8 reserved_at_20[0xa0];
1864 struct mlx5_ifc_gpio_event_bits {
1865 u8 reserved_at_0[0x60];
1867 u8 gpio_event_hi[0x20];
1869 u8 gpio_event_lo[0x20];
1871 u8 reserved_at_a0[0x40];
1874 struct mlx5_ifc_port_state_change_event_bits {
1875 u8 reserved_at_0[0x40];
1878 u8 reserved_at_44[0x1c];
1880 u8 reserved_at_60[0x80];
1883 struct mlx5_ifc_dropped_packet_logged_bits {
1884 u8 reserved_at_0[0xe0];
1888 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1889 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1892 struct mlx5_ifc_cq_error_bits {
1893 u8 reserved_at_0[0x8];
1896 u8 reserved_at_20[0x20];
1898 u8 reserved_at_40[0x18];
1901 u8 reserved_at_60[0x80];
1904 struct mlx5_ifc_rdma_page_fault_event_bits {
1905 u8 bytes_committed[0x20];
1909 u8 reserved_at_40[0x10];
1910 u8 packet_len[0x10];
1912 u8 rdma_op_len[0x20];
1916 u8 reserved_at_c0[0x5];
1923 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1924 u8 bytes_committed[0x20];
1926 u8 reserved_at_20[0x10];
1929 u8 reserved_at_40[0x10];
1932 u8 reserved_at_60[0x60];
1934 u8 reserved_at_c0[0x5];
1941 struct mlx5_ifc_qp_events_bits {
1942 u8 reserved_at_0[0xa0];
1945 u8 reserved_at_a8[0x18];
1947 u8 reserved_at_c0[0x8];
1948 u8 qpn_rqn_sqn[0x18];
1951 struct mlx5_ifc_dct_events_bits {
1952 u8 reserved_at_0[0xc0];
1954 u8 reserved_at_c0[0x8];
1955 u8 dct_number[0x18];
1958 struct mlx5_ifc_comp_event_bits {
1959 u8 reserved_at_0[0xc0];
1961 u8 reserved_at_c0[0x8];
1966 MLX5_QPC_STATE_RST = 0x0,
1967 MLX5_QPC_STATE_INIT = 0x1,
1968 MLX5_QPC_STATE_RTR = 0x2,
1969 MLX5_QPC_STATE_RTS = 0x3,
1970 MLX5_QPC_STATE_SQER = 0x4,
1971 MLX5_QPC_STATE_ERR = 0x6,
1972 MLX5_QPC_STATE_SQD = 0x7,
1973 MLX5_QPC_STATE_SUSPENDED = 0x9,
1977 MLX5_QPC_ST_RC = 0x0,
1978 MLX5_QPC_ST_UC = 0x1,
1979 MLX5_QPC_ST_UD = 0x2,
1980 MLX5_QPC_ST_XRC = 0x3,
1981 MLX5_QPC_ST_DCI = 0x5,
1982 MLX5_QPC_ST_QP0 = 0x7,
1983 MLX5_QPC_ST_QP1 = 0x8,
1984 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1985 MLX5_QPC_ST_REG_UMR = 0xc,
1989 MLX5_QPC_PM_STATE_ARMED = 0x0,
1990 MLX5_QPC_PM_STATE_REARM = 0x1,
1991 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1992 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1996 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1997 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2001 MLX5_QPC_MTU_256_BYTES = 0x1,
2002 MLX5_QPC_MTU_512_BYTES = 0x2,
2003 MLX5_QPC_MTU_1K_BYTES = 0x3,
2004 MLX5_QPC_MTU_2K_BYTES = 0x4,
2005 MLX5_QPC_MTU_4K_BYTES = 0x5,
2006 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2010 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2011 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2012 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2013 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2014 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2015 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2016 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2017 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2021 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2022 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2023 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2027 MLX5_QPC_CS_RES_DISABLE = 0x0,
2028 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2029 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2032 struct mlx5_ifc_qpc_bits {
2034 u8 lag_tx_port_affinity[0x4];
2036 u8 reserved_at_10[0x3];
2038 u8 reserved_at_15[0x7];
2039 u8 end_padding_mode[0x2];
2040 u8 reserved_at_1e[0x2];
2042 u8 wq_signature[0x1];
2043 u8 block_lb_mc[0x1];
2044 u8 atomic_like_write_en[0x1];
2045 u8 latency_sensitive[0x1];
2046 u8 reserved_at_24[0x1];
2047 u8 drain_sigerr[0x1];
2048 u8 reserved_at_26[0x2];
2052 u8 log_msg_max[0x5];
2053 u8 reserved_at_48[0x1];
2054 u8 log_rq_size[0x4];
2055 u8 log_rq_stride[0x3];
2057 u8 log_sq_size[0x4];
2058 u8 reserved_at_55[0x6];
2060 u8 ulp_stateless_offload_mode[0x4];
2062 u8 counter_set_id[0x8];
2065 u8 reserved_at_80[0x8];
2066 u8 user_index[0x18];
2068 u8 reserved_at_a0[0x3];
2069 u8 log_page_size[0x5];
2070 u8 remote_qpn[0x18];
2072 struct mlx5_ifc_ads_bits primary_address_path;
2074 struct mlx5_ifc_ads_bits secondary_address_path;
2076 u8 log_ack_req_freq[0x4];
2077 u8 reserved_at_384[0x4];
2078 u8 log_sra_max[0x3];
2079 u8 reserved_at_38b[0x2];
2080 u8 retry_count[0x3];
2082 u8 reserved_at_393[0x1];
2084 u8 cur_rnr_retry[0x3];
2085 u8 cur_retry_count[0x3];
2086 u8 reserved_at_39b[0x5];
2088 u8 reserved_at_3a0[0x20];
2090 u8 reserved_at_3c0[0x8];
2091 u8 next_send_psn[0x18];
2093 u8 reserved_at_3e0[0x8];
2096 u8 reserved_at_400[0x8];
2099 u8 reserved_at_420[0x20];
2101 u8 reserved_at_440[0x8];
2102 u8 last_acked_psn[0x18];
2104 u8 reserved_at_460[0x8];
2107 u8 reserved_at_480[0x8];
2108 u8 log_rra_max[0x3];
2109 u8 reserved_at_48b[0x1];
2110 u8 atomic_mode[0x4];
2114 u8 reserved_at_493[0x1];
2115 u8 page_offset[0x6];
2116 u8 reserved_at_49a[0x3];
2117 u8 cd_slave_receive[0x1];
2118 u8 cd_slave_send[0x1];
2121 u8 reserved_at_4a0[0x3];
2122 u8 min_rnr_nak[0x5];
2123 u8 next_rcv_psn[0x18];
2125 u8 reserved_at_4c0[0x8];
2128 u8 reserved_at_4e0[0x8];
2135 u8 reserved_at_560[0x5];
2137 u8 srqn_rmpn_xrqn[0x18];
2139 u8 reserved_at_580[0x8];
2142 u8 hw_sq_wqebb_counter[0x10];
2143 u8 sw_sq_wqebb_counter[0x10];
2145 u8 hw_rq_counter[0x20];
2147 u8 sw_rq_counter[0x20];
2149 u8 reserved_at_600[0x20];
2151 u8 reserved_at_620[0xf];
2156 u8 dc_access_key[0x40];
2158 u8 reserved_at_680[0xc0];
2161 struct mlx5_ifc_roce_addr_layout_bits {
2162 u8 source_l3_address[16][0x8];
2164 u8 reserved_at_80[0x3];
2167 u8 source_mac_47_32[0x10];
2169 u8 source_mac_31_0[0x20];
2171 u8 reserved_at_c0[0x14];
2172 u8 roce_l3_type[0x4];
2173 u8 roce_version[0x8];
2175 u8 reserved_at_e0[0x20];
2178 union mlx5_ifc_hca_cap_union_bits {
2179 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2180 struct mlx5_ifc_odp_cap_bits odp_cap;
2181 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2182 struct mlx5_ifc_roce_cap_bits roce_cap;
2183 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2184 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2185 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2186 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2187 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2188 struct mlx5_ifc_qos_cap_bits qos_cap;
2189 u8 reserved_at_0[0x8000];
2193 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2194 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2195 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2196 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2197 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2198 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2199 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
2202 struct mlx5_ifc_flow_context_bits {
2203 u8 reserved_at_0[0x20];
2207 u8 reserved_at_40[0x8];
2210 u8 reserved_at_60[0x10];
2213 u8 reserved_at_80[0x8];
2214 u8 destination_list_size[0x18];
2216 u8 reserved_at_a0[0x8];
2217 u8 flow_counter_list_size[0x18];
2221 u8 modify_header_id[0x20];
2223 u8 reserved_at_100[0x100];
2225 struct mlx5_ifc_fte_match_param_bits match_value;
2227 u8 reserved_at_1200[0x600];
2229 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2233 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2234 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2237 struct mlx5_ifc_xrc_srqc_bits {
2239 u8 log_xrc_srq_size[0x4];
2240 u8 reserved_at_8[0x18];
2242 u8 wq_signature[0x1];
2244 u8 reserved_at_22[0x1];
2246 u8 basic_cyclic_rcv_wqe[0x1];
2247 u8 log_rq_stride[0x3];
2250 u8 page_offset[0x6];
2251 u8 reserved_at_46[0x2];
2254 u8 reserved_at_60[0x20];
2256 u8 user_index_equal_xrc_srqn[0x1];
2257 u8 reserved_at_81[0x1];
2258 u8 log_page_size[0x6];
2259 u8 user_index[0x18];
2261 u8 reserved_at_a0[0x20];
2263 u8 reserved_at_c0[0x8];
2269 u8 reserved_at_100[0x40];
2271 u8 db_record_addr_h[0x20];
2273 u8 db_record_addr_l[0x1e];
2274 u8 reserved_at_17e[0x2];
2276 u8 reserved_at_180[0x80];
2279 struct mlx5_ifc_traffic_counter_bits {
2285 struct mlx5_ifc_tisc_bits {
2286 u8 strict_lag_tx_port_affinity[0x1];
2287 u8 reserved_at_1[0x3];
2288 u8 lag_tx_port_affinity[0x04];
2290 u8 reserved_at_8[0x4];
2292 u8 reserved_at_10[0x10];
2294 u8 reserved_at_20[0x100];
2296 u8 reserved_at_120[0x8];
2297 u8 transport_domain[0x18];
2299 u8 reserved_at_140[0x8];
2300 u8 underlay_qpn[0x18];
2301 u8 reserved_at_160[0x3a0];
2305 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2306 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2310 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2311 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2315 MLX5_RX_HASH_FN_NONE = 0x0,
2316 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2317 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2321 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2322 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2325 struct mlx5_ifc_tirc_bits {
2326 u8 reserved_at_0[0x20];
2329 u8 reserved_at_24[0x1c];
2331 u8 reserved_at_40[0x40];
2333 u8 reserved_at_80[0x4];
2334 u8 lro_timeout_period_usecs[0x10];
2335 u8 lro_enable_mask[0x4];
2336 u8 lro_max_ip_payload_size[0x8];
2338 u8 reserved_at_a0[0x40];
2340 u8 reserved_at_e0[0x8];
2341 u8 inline_rqn[0x18];
2343 u8 rx_hash_symmetric[0x1];
2344 u8 reserved_at_101[0x1];
2345 u8 tunneled_offload_en[0x1];
2346 u8 reserved_at_103[0x5];
2347 u8 indirect_table[0x18];
2350 u8 reserved_at_124[0x2];
2351 u8 self_lb_block[0x2];
2352 u8 transport_domain[0x18];
2354 u8 rx_hash_toeplitz_key[10][0x20];
2356 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2358 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2360 u8 reserved_at_2c0[0x4c0];
2364 MLX5_SRQC_STATE_GOOD = 0x0,
2365 MLX5_SRQC_STATE_ERROR = 0x1,
2368 struct mlx5_ifc_srqc_bits {
2370 u8 log_srq_size[0x4];
2371 u8 reserved_at_8[0x18];
2373 u8 wq_signature[0x1];
2375 u8 reserved_at_22[0x1];
2377 u8 reserved_at_24[0x1];
2378 u8 log_rq_stride[0x3];
2381 u8 page_offset[0x6];
2382 u8 reserved_at_46[0x2];
2385 u8 reserved_at_60[0x20];
2387 u8 reserved_at_80[0x2];
2388 u8 log_page_size[0x6];
2389 u8 reserved_at_88[0x18];
2391 u8 reserved_at_a0[0x20];
2393 u8 reserved_at_c0[0x8];
2399 u8 reserved_at_100[0x40];
2403 u8 reserved_at_180[0x80];
2407 MLX5_SQC_STATE_RST = 0x0,
2408 MLX5_SQC_STATE_RDY = 0x1,
2409 MLX5_SQC_STATE_ERR = 0x3,
2412 struct mlx5_ifc_sqc_bits {
2416 u8 flush_in_error_en[0x1];
2417 u8 reserved_at_4[0x1];
2418 u8 min_wqe_inline_mode[0x3];
2421 u8 reserved_at_d[0x13];
2423 u8 reserved_at_20[0x8];
2424 u8 user_index[0x18];
2426 u8 reserved_at_40[0x8];
2429 u8 reserved_at_60[0x90];
2431 u8 packet_pacing_rate_limit_index[0x10];
2432 u8 tis_lst_sz[0x10];
2433 u8 reserved_at_110[0x10];
2435 u8 reserved_at_120[0x40];
2437 u8 reserved_at_160[0x8];
2440 struct mlx5_ifc_wq_bits wq;
2444 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2445 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2446 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2447 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2450 struct mlx5_ifc_scheduling_context_bits {
2451 u8 element_type[0x8];
2452 u8 reserved_at_8[0x18];
2454 u8 element_attributes[0x20];
2456 u8 parent_element_id[0x20];
2458 u8 reserved_at_60[0x40];
2462 u8 max_average_bw[0x20];
2464 u8 reserved_at_e0[0x120];
2467 struct mlx5_ifc_rqtc_bits {
2468 u8 reserved_at_0[0xa0];
2470 u8 reserved_at_a0[0x10];
2471 u8 rqt_max_size[0x10];
2473 u8 reserved_at_c0[0x10];
2474 u8 rqt_actual_size[0x10];
2476 u8 reserved_at_e0[0x6a0];
2478 struct mlx5_ifc_rq_num_bits rq_num[0];
2482 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2483 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2487 MLX5_RQC_STATE_RST = 0x0,
2488 MLX5_RQC_STATE_RDY = 0x1,
2489 MLX5_RQC_STATE_ERR = 0x3,
2492 struct mlx5_ifc_rqc_bits {
2494 u8 reserved_at_1[0x1];
2495 u8 scatter_fcs[0x1];
2497 u8 mem_rq_type[0x4];
2499 u8 reserved_at_c[0x1];
2500 u8 flush_in_error_en[0x1];
2501 u8 reserved_at_e[0x12];
2503 u8 reserved_at_20[0x8];
2504 u8 user_index[0x18];
2506 u8 reserved_at_40[0x8];
2509 u8 counter_set_id[0x8];
2510 u8 reserved_at_68[0x18];
2512 u8 reserved_at_80[0x8];
2515 u8 reserved_at_a0[0xe0];
2517 struct mlx5_ifc_wq_bits wq;
2521 MLX5_RMPC_STATE_RDY = 0x1,
2522 MLX5_RMPC_STATE_ERR = 0x3,
2525 struct mlx5_ifc_rmpc_bits {
2526 u8 reserved_at_0[0x8];
2528 u8 reserved_at_c[0x14];
2530 u8 basic_cyclic_rcv_wqe[0x1];
2531 u8 reserved_at_21[0x1f];
2533 u8 reserved_at_40[0x140];
2535 struct mlx5_ifc_wq_bits wq;
2538 struct mlx5_ifc_nic_vport_context_bits {
2539 u8 reserved_at_0[0x5];
2540 u8 min_wqe_inline_mode[0x3];
2541 u8 reserved_at_8[0x17];
2544 u8 arm_change_event[0x1];
2545 u8 reserved_at_21[0x1a];
2546 u8 event_on_mtu[0x1];
2547 u8 event_on_promisc_change[0x1];
2548 u8 event_on_vlan_change[0x1];
2549 u8 event_on_mc_address_change[0x1];
2550 u8 event_on_uc_address_change[0x1];
2552 u8 reserved_at_40[0xf0];
2556 u8 system_image_guid[0x40];
2560 u8 reserved_at_200[0x140];
2561 u8 qkey_violation_counter[0x10];
2562 u8 reserved_at_350[0x430];
2566 u8 promisc_all[0x1];
2567 u8 reserved_at_783[0x2];
2568 u8 allowed_list_type[0x3];
2569 u8 reserved_at_788[0xc];
2570 u8 allowed_list_size[0xc];
2572 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2574 u8 reserved_at_7e0[0x20];
2576 u8 current_uc_mac_address[0][0x40];
2580 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2581 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2582 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2583 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
2586 struct mlx5_ifc_mkc_bits {
2587 u8 reserved_at_0[0x1];
2589 u8 reserved_at_2[0xd];
2590 u8 small_fence_on_rdma_read_response[0x1];
2597 u8 access_mode[0x2];
2598 u8 reserved_at_18[0x8];
2603 u8 reserved_at_40[0x20];
2608 u8 reserved_at_63[0x2];
2609 u8 expected_sigerr_count[0x1];
2610 u8 reserved_at_66[0x1];
2614 u8 start_addr[0x40];
2618 u8 bsf_octword_size[0x20];
2620 u8 reserved_at_120[0x80];
2622 u8 translations_octword_size[0x20];
2624 u8 reserved_at_1c0[0x1b];
2625 u8 log_page_size[0x5];
2627 u8 reserved_at_1e0[0x20];
2630 struct mlx5_ifc_pkey_bits {
2631 u8 reserved_at_0[0x10];
2635 struct mlx5_ifc_array128_auto_bits {
2636 u8 array128_auto[16][0x8];
2639 struct mlx5_ifc_hca_vport_context_bits {
2640 u8 field_select[0x20];
2642 u8 reserved_at_20[0xe0];
2644 u8 sm_virt_aware[0x1];
2647 u8 grh_required[0x1];
2648 u8 reserved_at_104[0xc];
2649 u8 port_physical_state[0x4];
2650 u8 vport_state_policy[0x4];
2652 u8 vport_state[0x4];
2654 u8 reserved_at_120[0x20];
2656 u8 system_image_guid[0x40];
2664 u8 cap_mask1_field_select[0x20];
2668 u8 cap_mask2_field_select[0x20];
2670 u8 reserved_at_280[0x80];
2673 u8 reserved_at_310[0x4];
2674 u8 init_type_reply[0x4];
2676 u8 subnet_timeout[0x5];
2680 u8 reserved_at_334[0xc];
2682 u8 qkey_violation_counter[0x10];
2683 u8 pkey_violation_counter[0x10];
2685 u8 reserved_at_360[0xca0];
2688 struct mlx5_ifc_esw_vport_context_bits {
2689 u8 reserved_at_0[0x3];
2690 u8 vport_svlan_strip[0x1];
2691 u8 vport_cvlan_strip[0x1];
2692 u8 vport_svlan_insert[0x1];
2693 u8 vport_cvlan_insert[0x2];
2694 u8 reserved_at_8[0x18];
2696 u8 reserved_at_20[0x20];
2705 u8 reserved_at_60[0x7a0];
2709 MLX5_EQC_STATUS_OK = 0x0,
2710 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2714 MLX5_EQC_ST_ARMED = 0x9,
2715 MLX5_EQC_ST_FIRED = 0xa,
2718 struct mlx5_ifc_eqc_bits {
2720 u8 reserved_at_4[0x9];
2723 u8 reserved_at_f[0x5];
2725 u8 reserved_at_18[0x8];
2727 u8 reserved_at_20[0x20];
2729 u8 reserved_at_40[0x14];
2730 u8 page_offset[0x6];
2731 u8 reserved_at_5a[0x6];
2733 u8 reserved_at_60[0x3];
2734 u8 log_eq_size[0x5];
2737 u8 reserved_at_80[0x20];
2739 u8 reserved_at_a0[0x18];
2742 u8 reserved_at_c0[0x3];
2743 u8 log_page_size[0x5];
2744 u8 reserved_at_c8[0x18];
2746 u8 reserved_at_e0[0x60];
2748 u8 reserved_at_140[0x8];
2749 u8 consumer_counter[0x18];
2751 u8 reserved_at_160[0x8];
2752 u8 producer_counter[0x18];
2754 u8 reserved_at_180[0x80];
2758 MLX5_DCTC_STATE_ACTIVE = 0x0,
2759 MLX5_DCTC_STATE_DRAINING = 0x1,
2760 MLX5_DCTC_STATE_DRAINED = 0x2,
2764 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2765 MLX5_DCTC_CS_RES_NA = 0x1,
2766 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2770 MLX5_DCTC_MTU_256_BYTES = 0x1,
2771 MLX5_DCTC_MTU_512_BYTES = 0x2,
2772 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2773 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2774 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2777 struct mlx5_ifc_dctc_bits {
2778 u8 reserved_at_0[0x4];
2780 u8 reserved_at_8[0x18];
2782 u8 reserved_at_20[0x8];
2783 u8 user_index[0x18];
2785 u8 reserved_at_40[0x8];
2788 u8 counter_set_id[0x8];
2789 u8 atomic_mode[0x4];
2793 u8 atomic_like_write_en[0x1];
2794 u8 latency_sensitive[0x1];
2797 u8 reserved_at_73[0xd];
2799 u8 reserved_at_80[0x8];
2801 u8 reserved_at_90[0x3];
2802 u8 min_rnr_nak[0x5];
2803 u8 reserved_at_98[0x8];
2805 u8 reserved_at_a0[0x8];
2808 u8 reserved_at_c0[0x8];
2812 u8 reserved_at_e8[0x4];
2813 u8 flow_label[0x14];
2815 u8 dc_access_key[0x40];
2817 u8 reserved_at_140[0x5];
2820 u8 pkey_index[0x10];
2822 u8 reserved_at_160[0x8];
2823 u8 my_addr_index[0x8];
2824 u8 reserved_at_170[0x8];
2827 u8 dc_access_key_violation_count[0x20];
2829 u8 reserved_at_1a0[0x14];
2835 u8 reserved_at_1c0[0x40];
2839 MLX5_CQC_STATUS_OK = 0x0,
2840 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2841 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2845 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2846 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2850 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2851 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2852 MLX5_CQC_ST_FIRED = 0xa,
2856 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2857 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2858 MLX5_CQ_PERIOD_NUM_MODES
2861 struct mlx5_ifc_cqc_bits {
2863 u8 reserved_at_4[0x4];
2866 u8 reserved_at_c[0x1];
2867 u8 scqe_break_moderation_en[0x1];
2869 u8 cq_period_mode[0x2];
2870 u8 cqe_comp_en[0x1];
2871 u8 mini_cqe_res_format[0x2];
2873 u8 reserved_at_18[0x8];
2875 u8 reserved_at_20[0x20];
2877 u8 reserved_at_40[0x14];
2878 u8 page_offset[0x6];
2879 u8 reserved_at_5a[0x6];
2881 u8 reserved_at_60[0x3];
2882 u8 log_cq_size[0x5];
2885 u8 reserved_at_80[0x4];
2887 u8 cq_max_count[0x10];
2889 u8 reserved_at_a0[0x18];
2892 u8 reserved_at_c0[0x3];
2893 u8 log_page_size[0x5];
2894 u8 reserved_at_c8[0x18];
2896 u8 reserved_at_e0[0x20];
2898 u8 reserved_at_100[0x8];
2899 u8 last_notified_index[0x18];
2901 u8 reserved_at_120[0x8];
2902 u8 last_solicit_index[0x18];
2904 u8 reserved_at_140[0x8];
2905 u8 consumer_counter[0x18];
2907 u8 reserved_at_160[0x8];
2908 u8 producer_counter[0x18];
2910 u8 reserved_at_180[0x40];
2915 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2916 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2917 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2918 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2919 u8 reserved_at_0[0x800];
2922 struct mlx5_ifc_query_adapter_param_block_bits {
2923 u8 reserved_at_0[0xc0];
2925 u8 reserved_at_c0[0x8];
2926 u8 ieee_vendor_id[0x18];
2928 u8 reserved_at_e0[0x10];
2929 u8 vsd_vendor_id[0x10];
2933 u8 vsd_contd_psid[16][0x8];
2937 MLX5_XRQC_STATE_GOOD = 0x0,
2938 MLX5_XRQC_STATE_ERROR = 0x1,
2942 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2943 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
2947 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2950 struct mlx5_ifc_tag_matching_topology_context_bits {
2951 u8 log_matching_list_sz[0x4];
2952 u8 reserved_at_4[0xc];
2953 u8 append_next_index[0x10];
2955 u8 sw_phase_cnt[0x10];
2956 u8 hw_phase_cnt[0x10];
2958 u8 reserved_at_40[0x40];
2961 struct mlx5_ifc_xrqc_bits {
2964 u8 reserved_at_5[0xf];
2966 u8 reserved_at_18[0x4];
2969 u8 reserved_at_20[0x8];
2970 u8 user_index[0x18];
2972 u8 reserved_at_40[0x8];
2975 u8 reserved_at_60[0xa0];
2977 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
2979 u8 reserved_at_180[0x880];
2981 struct mlx5_ifc_wq_bits wq;
2984 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2985 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2986 struct mlx5_ifc_resize_field_select_bits resize_field_select;
2987 u8 reserved_at_0[0x20];
2990 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2991 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2992 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2993 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2994 u8 reserved_at_0[0x20];
2997 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2998 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2999 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3000 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3001 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3002 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3003 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3004 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3005 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3006 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3007 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3008 u8 reserved_at_0[0x7c0];
3011 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3012 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3013 u8 reserved_at_0[0x7c0];
3016 union mlx5_ifc_event_auto_bits {
3017 struct mlx5_ifc_comp_event_bits comp_event;
3018 struct mlx5_ifc_dct_events_bits dct_events;
3019 struct mlx5_ifc_qp_events_bits qp_events;
3020 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3021 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3022 struct mlx5_ifc_cq_error_bits cq_error;
3023 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3024 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3025 struct mlx5_ifc_gpio_event_bits gpio_event;
3026 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3027 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3028 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3029 u8 reserved_at_0[0xe0];
3032 struct mlx5_ifc_health_buffer_bits {
3033 u8 reserved_at_0[0x100];
3035 u8 assert_existptr[0x20];
3037 u8 assert_callra[0x20];
3039 u8 reserved_at_140[0x40];
3041 u8 fw_version[0x20];
3045 u8 reserved_at_1c0[0x20];
3047 u8 irisc_index[0x8];
3052 struct mlx5_ifc_register_loopback_control_bits {
3054 u8 reserved_at_1[0x7];
3056 u8 reserved_at_10[0x10];
3058 u8 reserved_at_20[0x60];
3061 struct mlx5_ifc_vport_tc_element_bits {
3062 u8 traffic_class[0x4];
3063 u8 reserved_at_4[0xc];
3064 u8 vport_number[0x10];
3067 struct mlx5_ifc_vport_element_bits {
3068 u8 reserved_at_0[0x10];
3069 u8 vport_number[0x10];
3073 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3074 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3075 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3078 struct mlx5_ifc_tsar_element_bits {
3079 u8 reserved_at_0[0x8];
3081 u8 reserved_at_10[0x10];
3084 struct mlx5_ifc_teardown_hca_out_bits {
3086 u8 reserved_at_8[0x18];
3090 u8 reserved_at_40[0x40];
3094 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3095 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
3098 struct mlx5_ifc_teardown_hca_in_bits {
3100 u8 reserved_at_10[0x10];
3102 u8 reserved_at_20[0x10];
3105 u8 reserved_at_40[0x10];
3108 u8 reserved_at_60[0x20];
3111 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3113 u8 reserved_at_8[0x18];
3117 u8 reserved_at_40[0x40];
3120 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3122 u8 reserved_at_10[0x10];
3124 u8 reserved_at_20[0x10];
3127 u8 reserved_at_40[0x8];
3130 u8 reserved_at_60[0x20];
3132 u8 opt_param_mask[0x20];
3134 u8 reserved_at_a0[0x20];
3136 struct mlx5_ifc_qpc_bits qpc;
3138 u8 reserved_at_800[0x80];
3141 struct mlx5_ifc_sqd2rts_qp_out_bits {
3143 u8 reserved_at_8[0x18];
3147 u8 reserved_at_40[0x40];
3150 struct mlx5_ifc_sqd2rts_qp_in_bits {
3152 u8 reserved_at_10[0x10];
3154 u8 reserved_at_20[0x10];
3157 u8 reserved_at_40[0x8];
3160 u8 reserved_at_60[0x20];
3162 u8 opt_param_mask[0x20];
3164 u8 reserved_at_a0[0x20];
3166 struct mlx5_ifc_qpc_bits qpc;
3168 u8 reserved_at_800[0x80];
3171 struct mlx5_ifc_set_roce_address_out_bits {
3173 u8 reserved_at_8[0x18];
3177 u8 reserved_at_40[0x40];
3180 struct mlx5_ifc_set_roce_address_in_bits {
3182 u8 reserved_at_10[0x10];
3184 u8 reserved_at_20[0x10];
3187 u8 roce_address_index[0x10];
3188 u8 reserved_at_50[0x10];
3190 u8 reserved_at_60[0x20];
3192 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3195 struct mlx5_ifc_set_mad_demux_out_bits {
3197 u8 reserved_at_8[0x18];
3201 u8 reserved_at_40[0x40];
3205 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3206 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3209 struct mlx5_ifc_set_mad_demux_in_bits {
3211 u8 reserved_at_10[0x10];
3213 u8 reserved_at_20[0x10];
3216 u8 reserved_at_40[0x20];
3218 u8 reserved_at_60[0x6];
3220 u8 reserved_at_68[0x18];
3223 struct mlx5_ifc_set_l2_table_entry_out_bits {
3225 u8 reserved_at_8[0x18];
3229 u8 reserved_at_40[0x40];
3232 struct mlx5_ifc_set_l2_table_entry_in_bits {
3234 u8 reserved_at_10[0x10];
3236 u8 reserved_at_20[0x10];
3239 u8 reserved_at_40[0x60];
3241 u8 reserved_at_a0[0x8];
3242 u8 table_index[0x18];
3244 u8 reserved_at_c0[0x20];
3246 u8 reserved_at_e0[0x13];
3250 struct mlx5_ifc_mac_address_layout_bits mac_address;
3252 u8 reserved_at_140[0xc0];
3255 struct mlx5_ifc_set_issi_out_bits {
3257 u8 reserved_at_8[0x18];
3261 u8 reserved_at_40[0x40];
3264 struct mlx5_ifc_set_issi_in_bits {
3266 u8 reserved_at_10[0x10];
3268 u8 reserved_at_20[0x10];
3271 u8 reserved_at_40[0x10];
3272 u8 current_issi[0x10];
3274 u8 reserved_at_60[0x20];
3277 struct mlx5_ifc_set_hca_cap_out_bits {
3279 u8 reserved_at_8[0x18];
3283 u8 reserved_at_40[0x40];
3286 struct mlx5_ifc_set_hca_cap_in_bits {
3288 u8 reserved_at_10[0x10];
3290 u8 reserved_at_20[0x10];
3293 u8 reserved_at_40[0x40];
3295 union mlx5_ifc_hca_cap_union_bits capability;
3299 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3300 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3301 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3302 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3305 struct mlx5_ifc_set_fte_out_bits {
3307 u8 reserved_at_8[0x18];
3311 u8 reserved_at_40[0x40];
3314 struct mlx5_ifc_set_fte_in_bits {
3316 u8 reserved_at_10[0x10];
3318 u8 reserved_at_20[0x10];
3321 u8 other_vport[0x1];
3322 u8 reserved_at_41[0xf];
3323 u8 vport_number[0x10];
3325 u8 reserved_at_60[0x20];
3328 u8 reserved_at_88[0x18];
3330 u8 reserved_at_a0[0x8];
3333 u8 reserved_at_c0[0x18];
3334 u8 modify_enable_mask[0x8];
3336 u8 reserved_at_e0[0x20];
3338 u8 flow_index[0x20];
3340 u8 reserved_at_120[0xe0];
3342 struct mlx5_ifc_flow_context_bits flow_context;
3345 struct mlx5_ifc_rts2rts_qp_out_bits {
3347 u8 reserved_at_8[0x18];
3351 u8 reserved_at_40[0x40];
3354 struct mlx5_ifc_rts2rts_qp_in_bits {
3356 u8 reserved_at_10[0x10];
3358 u8 reserved_at_20[0x10];
3361 u8 reserved_at_40[0x8];
3364 u8 reserved_at_60[0x20];
3366 u8 opt_param_mask[0x20];
3368 u8 reserved_at_a0[0x20];
3370 struct mlx5_ifc_qpc_bits qpc;
3372 u8 reserved_at_800[0x80];
3375 struct mlx5_ifc_rtr2rts_qp_out_bits {
3377 u8 reserved_at_8[0x18];
3381 u8 reserved_at_40[0x40];
3384 struct mlx5_ifc_rtr2rts_qp_in_bits {
3386 u8 reserved_at_10[0x10];
3388 u8 reserved_at_20[0x10];
3391 u8 reserved_at_40[0x8];
3394 u8 reserved_at_60[0x20];
3396 u8 opt_param_mask[0x20];
3398 u8 reserved_at_a0[0x20];
3400 struct mlx5_ifc_qpc_bits qpc;
3402 u8 reserved_at_800[0x80];
3405 struct mlx5_ifc_rst2init_qp_out_bits {
3407 u8 reserved_at_8[0x18];
3411 u8 reserved_at_40[0x40];
3414 struct mlx5_ifc_rst2init_qp_in_bits {
3416 u8 reserved_at_10[0x10];
3418 u8 reserved_at_20[0x10];
3421 u8 reserved_at_40[0x8];
3424 u8 reserved_at_60[0x20];
3426 u8 opt_param_mask[0x20];
3428 u8 reserved_at_a0[0x20];
3430 struct mlx5_ifc_qpc_bits qpc;
3432 u8 reserved_at_800[0x80];
3435 struct mlx5_ifc_query_xrq_out_bits {
3437 u8 reserved_at_8[0x18];
3441 u8 reserved_at_40[0x40];
3443 struct mlx5_ifc_xrqc_bits xrq_context;
3446 struct mlx5_ifc_query_xrq_in_bits {
3448 u8 reserved_at_10[0x10];
3450 u8 reserved_at_20[0x10];
3453 u8 reserved_at_40[0x8];
3456 u8 reserved_at_60[0x20];
3459 struct mlx5_ifc_query_xrc_srq_out_bits {
3461 u8 reserved_at_8[0x18];
3465 u8 reserved_at_40[0x40];
3467 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3469 u8 reserved_at_280[0x600];
3474 struct mlx5_ifc_query_xrc_srq_in_bits {
3476 u8 reserved_at_10[0x10];
3478 u8 reserved_at_20[0x10];
3481 u8 reserved_at_40[0x8];
3484 u8 reserved_at_60[0x20];
3488 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3489 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3492 struct mlx5_ifc_query_vport_state_out_bits {
3494 u8 reserved_at_8[0x18];
3498 u8 reserved_at_40[0x20];
3500 u8 reserved_at_60[0x18];
3501 u8 admin_state[0x4];
3506 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
3507 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
3510 struct mlx5_ifc_query_vport_state_in_bits {
3512 u8 reserved_at_10[0x10];
3514 u8 reserved_at_20[0x10];
3517 u8 other_vport[0x1];
3518 u8 reserved_at_41[0xf];
3519 u8 vport_number[0x10];
3521 u8 reserved_at_60[0x20];
3524 struct mlx5_ifc_query_vport_counter_out_bits {
3526 u8 reserved_at_8[0x18];
3530 u8 reserved_at_40[0x40];
3532 struct mlx5_ifc_traffic_counter_bits received_errors;
3534 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3536 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3538 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3540 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3542 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3544 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3546 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3548 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3550 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3552 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3554 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3556 u8 reserved_at_680[0xa00];
3560 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3563 struct mlx5_ifc_query_vport_counter_in_bits {
3565 u8 reserved_at_10[0x10];
3567 u8 reserved_at_20[0x10];
3570 u8 other_vport[0x1];
3571 u8 reserved_at_41[0xb];
3573 u8 vport_number[0x10];
3575 u8 reserved_at_60[0x60];
3578 u8 reserved_at_c1[0x1f];
3580 u8 reserved_at_e0[0x20];
3583 struct mlx5_ifc_query_tis_out_bits {
3585 u8 reserved_at_8[0x18];
3589 u8 reserved_at_40[0x40];
3591 struct mlx5_ifc_tisc_bits tis_context;
3594 struct mlx5_ifc_query_tis_in_bits {
3596 u8 reserved_at_10[0x10];
3598 u8 reserved_at_20[0x10];
3601 u8 reserved_at_40[0x8];
3604 u8 reserved_at_60[0x20];
3607 struct mlx5_ifc_query_tir_out_bits {
3609 u8 reserved_at_8[0x18];
3613 u8 reserved_at_40[0xc0];
3615 struct mlx5_ifc_tirc_bits tir_context;
3618 struct mlx5_ifc_query_tir_in_bits {
3620 u8 reserved_at_10[0x10];
3622 u8 reserved_at_20[0x10];
3625 u8 reserved_at_40[0x8];
3628 u8 reserved_at_60[0x20];
3631 struct mlx5_ifc_query_srq_out_bits {
3633 u8 reserved_at_8[0x18];
3637 u8 reserved_at_40[0x40];
3639 struct mlx5_ifc_srqc_bits srq_context_entry;
3641 u8 reserved_at_280[0x600];
3646 struct mlx5_ifc_query_srq_in_bits {
3648 u8 reserved_at_10[0x10];
3650 u8 reserved_at_20[0x10];
3653 u8 reserved_at_40[0x8];
3656 u8 reserved_at_60[0x20];
3659 struct mlx5_ifc_query_sq_out_bits {
3661 u8 reserved_at_8[0x18];
3665 u8 reserved_at_40[0xc0];
3667 struct mlx5_ifc_sqc_bits sq_context;
3670 struct mlx5_ifc_query_sq_in_bits {
3672 u8 reserved_at_10[0x10];
3674 u8 reserved_at_20[0x10];
3677 u8 reserved_at_40[0x8];
3680 u8 reserved_at_60[0x20];
3683 struct mlx5_ifc_query_special_contexts_out_bits {
3685 u8 reserved_at_8[0x18];
3689 u8 dump_fill_mkey[0x20];
3695 u8 reserved_at_a0[0x60];
3698 struct mlx5_ifc_query_special_contexts_in_bits {
3700 u8 reserved_at_10[0x10];
3702 u8 reserved_at_20[0x10];
3705 u8 reserved_at_40[0x40];
3708 struct mlx5_ifc_query_scheduling_element_out_bits {
3710 u8 reserved_at_10[0x10];
3712 u8 reserved_at_20[0x10];
3715 u8 reserved_at_40[0xc0];
3717 struct mlx5_ifc_scheduling_context_bits scheduling_context;
3719 u8 reserved_at_300[0x100];
3723 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3726 struct mlx5_ifc_query_scheduling_element_in_bits {
3728 u8 reserved_at_10[0x10];
3730 u8 reserved_at_20[0x10];
3733 u8 scheduling_hierarchy[0x8];
3734 u8 reserved_at_48[0x18];
3736 u8 scheduling_element_id[0x20];
3738 u8 reserved_at_80[0x180];
3741 struct mlx5_ifc_query_rqt_out_bits {
3743 u8 reserved_at_8[0x18];
3747 u8 reserved_at_40[0xc0];
3749 struct mlx5_ifc_rqtc_bits rqt_context;
3752 struct mlx5_ifc_query_rqt_in_bits {
3754 u8 reserved_at_10[0x10];
3756 u8 reserved_at_20[0x10];
3759 u8 reserved_at_40[0x8];
3762 u8 reserved_at_60[0x20];
3765 struct mlx5_ifc_query_rq_out_bits {
3767 u8 reserved_at_8[0x18];
3771 u8 reserved_at_40[0xc0];
3773 struct mlx5_ifc_rqc_bits rq_context;
3776 struct mlx5_ifc_query_rq_in_bits {
3778 u8 reserved_at_10[0x10];
3780 u8 reserved_at_20[0x10];
3783 u8 reserved_at_40[0x8];
3786 u8 reserved_at_60[0x20];
3789 struct mlx5_ifc_query_roce_address_out_bits {
3791 u8 reserved_at_8[0x18];
3795 u8 reserved_at_40[0x40];
3797 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3800 struct mlx5_ifc_query_roce_address_in_bits {
3802 u8 reserved_at_10[0x10];
3804 u8 reserved_at_20[0x10];
3807 u8 roce_address_index[0x10];
3808 u8 reserved_at_50[0x10];
3810 u8 reserved_at_60[0x20];
3813 struct mlx5_ifc_query_rmp_out_bits {
3815 u8 reserved_at_8[0x18];
3819 u8 reserved_at_40[0xc0];
3821 struct mlx5_ifc_rmpc_bits rmp_context;
3824 struct mlx5_ifc_query_rmp_in_bits {
3826 u8 reserved_at_10[0x10];
3828 u8 reserved_at_20[0x10];
3831 u8 reserved_at_40[0x8];
3834 u8 reserved_at_60[0x20];
3837 struct mlx5_ifc_query_qp_out_bits {
3839 u8 reserved_at_8[0x18];
3843 u8 reserved_at_40[0x40];
3845 u8 opt_param_mask[0x20];
3847 u8 reserved_at_a0[0x20];
3849 struct mlx5_ifc_qpc_bits qpc;
3851 u8 reserved_at_800[0x80];
3856 struct mlx5_ifc_query_qp_in_bits {
3858 u8 reserved_at_10[0x10];
3860 u8 reserved_at_20[0x10];
3863 u8 reserved_at_40[0x8];
3866 u8 reserved_at_60[0x20];
3869 struct mlx5_ifc_query_q_counter_out_bits {
3871 u8 reserved_at_8[0x18];
3875 u8 reserved_at_40[0x40];
3877 u8 rx_write_requests[0x20];
3879 u8 reserved_at_a0[0x20];
3881 u8 rx_read_requests[0x20];
3883 u8 reserved_at_e0[0x20];
3885 u8 rx_atomic_requests[0x20];
3887 u8 reserved_at_120[0x20];
3889 u8 rx_dct_connect[0x20];
3891 u8 reserved_at_160[0x20];
3893 u8 out_of_buffer[0x20];
3895 u8 reserved_at_1a0[0x20];
3897 u8 out_of_sequence[0x20];
3899 u8 reserved_at_1e0[0x20];
3901 u8 duplicate_request[0x20];
3903 u8 reserved_at_220[0x20];
3905 u8 rnr_nak_retry_err[0x20];
3907 u8 reserved_at_260[0x20];
3909 u8 packet_seq_err[0x20];
3911 u8 reserved_at_2a0[0x20];
3913 u8 implied_nak_seq_err[0x20];
3915 u8 reserved_at_2e0[0x20];
3917 u8 local_ack_timeout_err[0x20];
3919 u8 reserved_at_320[0x4e0];
3922 struct mlx5_ifc_query_q_counter_in_bits {
3924 u8 reserved_at_10[0x10];
3926 u8 reserved_at_20[0x10];
3929 u8 reserved_at_40[0x80];
3932 u8 reserved_at_c1[0x1f];
3934 u8 reserved_at_e0[0x18];
3935 u8 counter_set_id[0x8];
3938 struct mlx5_ifc_query_pages_out_bits {
3940 u8 reserved_at_8[0x18];
3944 u8 reserved_at_40[0x10];
3945 u8 function_id[0x10];
3951 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3952 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3953 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3956 struct mlx5_ifc_query_pages_in_bits {
3958 u8 reserved_at_10[0x10];
3960 u8 reserved_at_20[0x10];
3963 u8 reserved_at_40[0x10];
3964 u8 function_id[0x10];
3966 u8 reserved_at_60[0x20];
3969 struct mlx5_ifc_query_nic_vport_context_out_bits {
3971 u8 reserved_at_8[0x18];
3975 u8 reserved_at_40[0x40];
3977 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3980 struct mlx5_ifc_query_nic_vport_context_in_bits {
3982 u8 reserved_at_10[0x10];
3984 u8 reserved_at_20[0x10];
3987 u8 other_vport[0x1];
3988 u8 reserved_at_41[0xf];
3989 u8 vport_number[0x10];
3991 u8 reserved_at_60[0x5];
3992 u8 allowed_list_type[0x3];
3993 u8 reserved_at_68[0x18];
3996 struct mlx5_ifc_query_mkey_out_bits {
3998 u8 reserved_at_8[0x18];
4002 u8 reserved_at_40[0x40];
4004 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4006 u8 reserved_at_280[0x600];
4008 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4010 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4013 struct mlx5_ifc_query_mkey_in_bits {
4015 u8 reserved_at_10[0x10];
4017 u8 reserved_at_20[0x10];
4020 u8 reserved_at_40[0x8];
4021 u8 mkey_index[0x18];
4024 u8 reserved_at_61[0x1f];
4027 struct mlx5_ifc_query_mad_demux_out_bits {
4029 u8 reserved_at_8[0x18];
4033 u8 reserved_at_40[0x40];
4035 u8 mad_dumux_parameters_block[0x20];
4038 struct mlx5_ifc_query_mad_demux_in_bits {
4040 u8 reserved_at_10[0x10];
4042 u8 reserved_at_20[0x10];
4045 u8 reserved_at_40[0x40];
4048 struct mlx5_ifc_query_l2_table_entry_out_bits {
4050 u8 reserved_at_8[0x18];
4054 u8 reserved_at_40[0xa0];
4056 u8 reserved_at_e0[0x13];
4060 struct mlx5_ifc_mac_address_layout_bits mac_address;
4062 u8 reserved_at_140[0xc0];
4065 struct mlx5_ifc_query_l2_table_entry_in_bits {
4067 u8 reserved_at_10[0x10];
4069 u8 reserved_at_20[0x10];
4072 u8 reserved_at_40[0x60];
4074 u8 reserved_at_a0[0x8];
4075 u8 table_index[0x18];
4077 u8 reserved_at_c0[0x140];
4080 struct mlx5_ifc_query_issi_out_bits {
4082 u8 reserved_at_8[0x18];
4086 u8 reserved_at_40[0x10];
4087 u8 current_issi[0x10];
4089 u8 reserved_at_60[0xa0];
4091 u8 reserved_at_100[76][0x8];
4092 u8 supported_issi_dw0[0x20];
4095 struct mlx5_ifc_query_issi_in_bits {
4097 u8 reserved_at_10[0x10];
4099 u8 reserved_at_20[0x10];
4102 u8 reserved_at_40[0x40];
4105 struct mlx5_ifc_set_driver_version_out_bits {
4107 u8 reserved_0[0x18];
4110 u8 reserved_1[0x40];
4113 struct mlx5_ifc_set_driver_version_in_bits {
4115 u8 reserved_0[0x10];
4117 u8 reserved_1[0x10];
4120 u8 reserved_2[0x40];
4121 u8 driver_version[64][0x8];
4124 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4126 u8 reserved_at_8[0x18];
4130 u8 reserved_at_40[0x40];
4132 struct mlx5_ifc_pkey_bits pkey[0];
4135 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4137 u8 reserved_at_10[0x10];
4139 u8 reserved_at_20[0x10];
4142 u8 other_vport[0x1];
4143 u8 reserved_at_41[0xb];
4145 u8 vport_number[0x10];
4147 u8 reserved_at_60[0x10];
4148 u8 pkey_index[0x10];
4152 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4153 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4154 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4157 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4159 u8 reserved_at_8[0x18];
4163 u8 reserved_at_40[0x20];
4166 u8 reserved_at_70[0x10];
4168 struct mlx5_ifc_array128_auto_bits gid[0];
4171 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4173 u8 reserved_at_10[0x10];
4175 u8 reserved_at_20[0x10];
4178 u8 other_vport[0x1];
4179 u8 reserved_at_41[0xb];
4181 u8 vport_number[0x10];
4183 u8 reserved_at_60[0x10];
4187 struct mlx5_ifc_query_hca_vport_context_out_bits {
4189 u8 reserved_at_8[0x18];
4193 u8 reserved_at_40[0x40];
4195 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4198 struct mlx5_ifc_query_hca_vport_context_in_bits {
4200 u8 reserved_at_10[0x10];
4202 u8 reserved_at_20[0x10];
4205 u8 other_vport[0x1];
4206 u8 reserved_at_41[0xb];
4208 u8 vport_number[0x10];
4210 u8 reserved_at_60[0x20];
4213 struct mlx5_ifc_query_hca_cap_out_bits {
4215 u8 reserved_at_8[0x18];
4219 u8 reserved_at_40[0x40];
4221 union mlx5_ifc_hca_cap_union_bits capability;
4224 struct mlx5_ifc_query_hca_cap_in_bits {
4226 u8 reserved_at_10[0x10];
4228 u8 reserved_at_20[0x10];
4231 u8 reserved_at_40[0x40];
4234 struct mlx5_ifc_query_flow_table_out_bits {
4236 u8 reserved_at_8[0x18];
4240 u8 reserved_at_40[0x80];
4242 u8 reserved_at_c0[0x8];
4244 u8 reserved_at_d0[0x8];
4247 u8 reserved_at_e0[0x120];
4250 struct mlx5_ifc_query_flow_table_in_bits {
4252 u8 reserved_at_10[0x10];
4254 u8 reserved_at_20[0x10];
4257 u8 reserved_at_40[0x40];
4260 u8 reserved_at_88[0x18];
4262 u8 reserved_at_a0[0x8];
4265 u8 reserved_at_c0[0x140];
4268 struct mlx5_ifc_query_fte_out_bits {
4270 u8 reserved_at_8[0x18];
4274 u8 reserved_at_40[0x1c0];
4276 struct mlx5_ifc_flow_context_bits flow_context;
4279 struct mlx5_ifc_query_fte_in_bits {
4281 u8 reserved_at_10[0x10];
4283 u8 reserved_at_20[0x10];
4286 u8 reserved_at_40[0x40];
4289 u8 reserved_at_88[0x18];
4291 u8 reserved_at_a0[0x8];
4294 u8 reserved_at_c0[0x40];
4296 u8 flow_index[0x20];
4298 u8 reserved_at_120[0xe0];
4302 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4303 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4304 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4307 struct mlx5_ifc_query_flow_group_out_bits {
4309 u8 reserved_at_8[0x18];
4313 u8 reserved_at_40[0xa0];
4315 u8 start_flow_index[0x20];
4317 u8 reserved_at_100[0x20];
4319 u8 end_flow_index[0x20];
4321 u8 reserved_at_140[0xa0];
4323 u8 reserved_at_1e0[0x18];
4324 u8 match_criteria_enable[0x8];
4326 struct mlx5_ifc_fte_match_param_bits match_criteria;
4328 u8 reserved_at_1200[0xe00];
4331 struct mlx5_ifc_query_flow_group_in_bits {
4333 u8 reserved_at_10[0x10];
4335 u8 reserved_at_20[0x10];
4338 u8 reserved_at_40[0x40];
4341 u8 reserved_at_88[0x18];
4343 u8 reserved_at_a0[0x8];
4348 u8 reserved_at_e0[0x120];
4351 struct mlx5_ifc_query_flow_counter_out_bits {
4353 u8 reserved_at_8[0x18];
4357 u8 reserved_at_40[0x40];
4359 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4362 struct mlx5_ifc_query_flow_counter_in_bits {
4364 u8 reserved_at_10[0x10];
4366 u8 reserved_at_20[0x10];
4369 u8 reserved_at_40[0x80];
4372 u8 reserved_at_c1[0xf];
4373 u8 num_of_counters[0x10];
4375 u8 reserved_at_e0[0x10];
4376 u8 flow_counter_id[0x10];
4379 struct mlx5_ifc_query_esw_vport_context_out_bits {
4381 u8 reserved_at_8[0x18];
4385 u8 reserved_at_40[0x40];
4387 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4390 struct mlx5_ifc_query_esw_vport_context_in_bits {
4392 u8 reserved_at_10[0x10];
4394 u8 reserved_at_20[0x10];
4397 u8 other_vport[0x1];
4398 u8 reserved_at_41[0xf];
4399 u8 vport_number[0x10];
4401 u8 reserved_at_60[0x20];
4404 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4406 u8 reserved_at_8[0x18];
4410 u8 reserved_at_40[0x40];
4413 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4414 u8 reserved_at_0[0x1c];
4415 u8 vport_cvlan_insert[0x1];
4416 u8 vport_svlan_insert[0x1];
4417 u8 vport_cvlan_strip[0x1];
4418 u8 vport_svlan_strip[0x1];
4421 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4423 u8 reserved_at_10[0x10];
4425 u8 reserved_at_20[0x10];
4428 u8 other_vport[0x1];
4429 u8 reserved_at_41[0xf];
4430 u8 vport_number[0x10];
4432 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4434 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4437 struct mlx5_ifc_query_eq_out_bits {
4439 u8 reserved_at_8[0x18];
4443 u8 reserved_at_40[0x40];
4445 struct mlx5_ifc_eqc_bits eq_context_entry;
4447 u8 reserved_at_280[0x40];
4449 u8 event_bitmask[0x40];
4451 u8 reserved_at_300[0x580];
4456 struct mlx5_ifc_query_eq_in_bits {
4458 u8 reserved_at_10[0x10];
4460 u8 reserved_at_20[0x10];
4463 u8 reserved_at_40[0x18];
4466 u8 reserved_at_60[0x20];
4469 struct mlx5_ifc_encap_header_in_bits {
4470 u8 reserved_at_0[0x5];
4471 u8 header_type[0x3];
4472 u8 reserved_at_8[0xe];
4473 u8 encap_header_size[0xa];
4475 u8 reserved_at_20[0x10];
4476 u8 encap_header[2][0x8];
4478 u8 more_encap_header[0][0x8];
4481 struct mlx5_ifc_query_encap_header_out_bits {
4483 u8 reserved_at_8[0x18];
4487 u8 reserved_at_40[0xa0];
4489 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4492 struct mlx5_ifc_query_encap_header_in_bits {
4494 u8 reserved_at_10[0x10];
4496 u8 reserved_at_20[0x10];
4501 u8 reserved_at_60[0xa0];
4504 struct mlx5_ifc_alloc_encap_header_out_bits {
4506 u8 reserved_at_8[0x18];
4512 u8 reserved_at_60[0x20];
4515 struct mlx5_ifc_alloc_encap_header_in_bits {
4517 u8 reserved_at_10[0x10];
4519 u8 reserved_at_20[0x10];
4522 u8 reserved_at_40[0xa0];
4524 struct mlx5_ifc_encap_header_in_bits encap_header;
4527 struct mlx5_ifc_dealloc_encap_header_out_bits {
4529 u8 reserved_at_8[0x18];
4533 u8 reserved_at_40[0x40];
4536 struct mlx5_ifc_dealloc_encap_header_in_bits {
4538 u8 reserved_at_10[0x10];
4540 u8 reserved_20[0x10];
4545 u8 reserved_60[0x20];
4548 struct mlx5_ifc_set_action_in_bits {
4549 u8 action_type[0x4];
4551 u8 reserved_at_10[0x3];
4553 u8 reserved_at_18[0x3];
4559 struct mlx5_ifc_add_action_in_bits {
4560 u8 action_type[0x4];
4562 u8 reserved_at_10[0x10];
4567 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4568 struct mlx5_ifc_set_action_in_bits set_action_in;
4569 struct mlx5_ifc_add_action_in_bits add_action_in;
4570 u8 reserved_at_0[0x40];
4574 MLX5_ACTION_TYPE_SET = 0x1,
4575 MLX5_ACTION_TYPE_ADD = 0x2,
4579 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
4580 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
4581 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
4582 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
4583 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
4584 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
4585 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
4586 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
4587 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
4588 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
4589 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
4590 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
4591 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
4592 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
4593 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
4594 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
4595 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
4596 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
4597 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
4598 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
4599 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
4600 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
4603 struct mlx5_ifc_alloc_modify_header_context_out_bits {
4605 u8 reserved_at_8[0x18];
4609 u8 modify_header_id[0x20];
4611 u8 reserved_at_60[0x20];
4614 struct mlx5_ifc_alloc_modify_header_context_in_bits {
4616 u8 reserved_at_10[0x10];
4618 u8 reserved_at_20[0x10];
4621 u8 reserved_at_40[0x20];
4624 u8 reserved_at_68[0x10];
4625 u8 num_of_actions[0x8];
4627 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4630 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4632 u8 reserved_at_8[0x18];
4636 u8 reserved_at_40[0x40];
4639 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4641 u8 reserved_at_10[0x10];
4643 u8 reserved_at_20[0x10];
4646 u8 modify_header_id[0x20];
4648 u8 reserved_at_60[0x20];
4651 struct mlx5_ifc_query_dct_out_bits {
4653 u8 reserved_at_8[0x18];
4657 u8 reserved_at_40[0x40];
4659 struct mlx5_ifc_dctc_bits dct_context_entry;
4661 u8 reserved_at_280[0x180];
4664 struct mlx5_ifc_query_dct_in_bits {
4666 u8 reserved_at_10[0x10];
4668 u8 reserved_at_20[0x10];
4671 u8 reserved_at_40[0x8];
4674 u8 reserved_at_60[0x20];
4677 struct mlx5_ifc_query_cq_out_bits {
4679 u8 reserved_at_8[0x18];
4683 u8 reserved_at_40[0x40];
4685 struct mlx5_ifc_cqc_bits cq_context;
4687 u8 reserved_at_280[0x600];
4692 struct mlx5_ifc_query_cq_in_bits {
4694 u8 reserved_at_10[0x10];
4696 u8 reserved_at_20[0x10];
4699 u8 reserved_at_40[0x8];
4702 u8 reserved_at_60[0x20];
4705 struct mlx5_ifc_query_cong_status_out_bits {
4707 u8 reserved_at_8[0x18];
4711 u8 reserved_at_40[0x20];
4715 u8 reserved_at_62[0x1e];
4718 struct mlx5_ifc_query_cong_status_in_bits {
4720 u8 reserved_at_10[0x10];
4722 u8 reserved_at_20[0x10];
4725 u8 reserved_at_40[0x18];
4727 u8 cong_protocol[0x4];
4729 u8 reserved_at_60[0x20];
4732 struct mlx5_ifc_query_cong_statistics_out_bits {
4734 u8 reserved_at_8[0x18];
4738 u8 reserved_at_40[0x40];
4740 u8 rp_cur_flows[0x20];
4744 u8 rp_cnp_ignored_high[0x20];
4746 u8 rp_cnp_ignored_low[0x20];
4748 u8 rp_cnp_handled_high[0x20];
4750 u8 rp_cnp_handled_low[0x20];
4752 u8 reserved_at_140[0x100];
4754 u8 time_stamp_high[0x20];
4756 u8 time_stamp_low[0x20];
4758 u8 accumulators_period[0x20];
4760 u8 np_ecn_marked_roce_packets_high[0x20];
4762 u8 np_ecn_marked_roce_packets_low[0x20];
4764 u8 np_cnp_sent_high[0x20];
4766 u8 np_cnp_sent_low[0x20];
4768 u8 reserved_at_320[0x560];
4771 struct mlx5_ifc_query_cong_statistics_in_bits {
4773 u8 reserved_at_10[0x10];
4775 u8 reserved_at_20[0x10];
4779 u8 reserved_at_41[0x1f];
4781 u8 reserved_at_60[0x20];
4784 struct mlx5_ifc_query_cong_params_out_bits {
4786 u8 reserved_at_8[0x18];
4790 u8 reserved_at_40[0x40];
4792 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4795 struct mlx5_ifc_query_cong_params_in_bits {
4797 u8 reserved_at_10[0x10];
4799 u8 reserved_at_20[0x10];
4802 u8 reserved_at_40[0x1c];
4803 u8 cong_protocol[0x4];
4805 u8 reserved_at_60[0x20];
4808 struct mlx5_ifc_query_adapter_out_bits {
4810 u8 reserved_at_8[0x18];
4814 u8 reserved_at_40[0x40];
4816 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4819 struct mlx5_ifc_query_adapter_in_bits {
4821 u8 reserved_at_10[0x10];
4823 u8 reserved_at_20[0x10];
4826 u8 reserved_at_40[0x40];
4829 struct mlx5_ifc_qp_2rst_out_bits {
4831 u8 reserved_at_8[0x18];
4835 u8 reserved_at_40[0x40];
4838 struct mlx5_ifc_qp_2rst_in_bits {
4840 u8 reserved_at_10[0x10];
4842 u8 reserved_at_20[0x10];
4845 u8 reserved_at_40[0x8];
4848 u8 reserved_at_60[0x20];
4851 struct mlx5_ifc_qp_2err_out_bits {
4853 u8 reserved_at_8[0x18];
4857 u8 reserved_at_40[0x40];
4860 struct mlx5_ifc_qp_2err_in_bits {
4862 u8 reserved_at_10[0x10];
4864 u8 reserved_at_20[0x10];
4867 u8 reserved_at_40[0x8];
4870 u8 reserved_at_60[0x20];
4873 struct mlx5_ifc_page_fault_resume_out_bits {
4875 u8 reserved_at_8[0x18];
4879 u8 reserved_at_40[0x40];
4882 struct mlx5_ifc_page_fault_resume_in_bits {
4884 u8 reserved_at_10[0x10];
4886 u8 reserved_at_20[0x10];
4890 u8 reserved_at_41[0x4];
4891 u8 page_fault_type[0x3];
4894 u8 reserved_at_60[0x8];
4898 struct mlx5_ifc_nop_out_bits {
4900 u8 reserved_at_8[0x18];
4904 u8 reserved_at_40[0x40];
4907 struct mlx5_ifc_nop_in_bits {
4909 u8 reserved_at_10[0x10];
4911 u8 reserved_at_20[0x10];
4914 u8 reserved_at_40[0x40];
4917 struct mlx5_ifc_modify_vport_state_out_bits {
4919 u8 reserved_at_8[0x18];
4923 u8 reserved_at_40[0x40];
4926 struct mlx5_ifc_modify_vport_state_in_bits {
4928 u8 reserved_at_10[0x10];
4930 u8 reserved_at_20[0x10];
4933 u8 other_vport[0x1];
4934 u8 reserved_at_41[0xf];
4935 u8 vport_number[0x10];
4937 u8 reserved_at_60[0x18];
4938 u8 admin_state[0x4];
4939 u8 reserved_at_7c[0x4];
4942 struct mlx5_ifc_modify_tis_out_bits {
4944 u8 reserved_at_8[0x18];
4948 u8 reserved_at_40[0x40];
4951 struct mlx5_ifc_modify_tis_bitmask_bits {
4952 u8 reserved_at_0[0x20];
4954 u8 reserved_at_20[0x1d];
4955 u8 lag_tx_port_affinity[0x1];
4956 u8 strict_lag_tx_port_affinity[0x1];
4960 struct mlx5_ifc_modify_tis_in_bits {
4962 u8 reserved_at_10[0x10];
4964 u8 reserved_at_20[0x10];
4967 u8 reserved_at_40[0x8];
4970 u8 reserved_at_60[0x20];
4972 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
4974 u8 reserved_at_c0[0x40];
4976 struct mlx5_ifc_tisc_bits ctx;
4979 struct mlx5_ifc_modify_tir_bitmask_bits {
4980 u8 reserved_at_0[0x20];
4982 u8 reserved_at_20[0x1b];
4984 u8 reserved_at_3c[0x1];
4986 u8 reserved_at_3e[0x1];
4990 struct mlx5_ifc_modify_tir_out_bits {
4992 u8 reserved_at_8[0x18];
4996 u8 reserved_at_40[0x40];
4999 struct mlx5_ifc_modify_tir_in_bits {
5001 u8 reserved_at_10[0x10];
5003 u8 reserved_at_20[0x10];
5006 u8 reserved_at_40[0x8];
5009 u8 reserved_at_60[0x20];
5011 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5013 u8 reserved_at_c0[0x40];
5015 struct mlx5_ifc_tirc_bits ctx;
5018 struct mlx5_ifc_modify_sq_out_bits {
5020 u8 reserved_at_8[0x18];
5024 u8 reserved_at_40[0x40];
5027 struct mlx5_ifc_modify_sq_in_bits {
5029 u8 reserved_at_10[0x10];
5031 u8 reserved_at_20[0x10];
5035 u8 reserved_at_44[0x4];
5038 u8 reserved_at_60[0x20];
5040 u8 modify_bitmask[0x40];
5042 u8 reserved_at_c0[0x40];
5044 struct mlx5_ifc_sqc_bits ctx;
5047 struct mlx5_ifc_modify_scheduling_element_out_bits {
5049 u8 reserved_at_8[0x18];
5053 u8 reserved_at_40[0x1c0];
5057 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5058 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5061 struct mlx5_ifc_modify_scheduling_element_in_bits {
5063 u8 reserved_at_10[0x10];
5065 u8 reserved_at_20[0x10];
5068 u8 scheduling_hierarchy[0x8];
5069 u8 reserved_at_48[0x18];
5071 u8 scheduling_element_id[0x20];
5073 u8 reserved_at_80[0x20];
5075 u8 modify_bitmask[0x20];
5077 u8 reserved_at_c0[0x40];
5079 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5081 u8 reserved_at_300[0x100];
5084 struct mlx5_ifc_modify_rqt_out_bits {
5086 u8 reserved_at_8[0x18];
5090 u8 reserved_at_40[0x40];
5093 struct mlx5_ifc_rqt_bitmask_bits {
5094 u8 reserved_at_0[0x20];
5096 u8 reserved_at_20[0x1f];
5100 struct mlx5_ifc_modify_rqt_in_bits {
5102 u8 reserved_at_10[0x10];
5104 u8 reserved_at_20[0x10];
5107 u8 reserved_at_40[0x8];
5110 u8 reserved_at_60[0x20];
5112 struct mlx5_ifc_rqt_bitmask_bits bitmask;
5114 u8 reserved_at_c0[0x40];
5116 struct mlx5_ifc_rqtc_bits ctx;
5119 struct mlx5_ifc_modify_rq_out_bits {
5121 u8 reserved_at_8[0x18];
5125 u8 reserved_at_40[0x40];
5129 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5130 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5131 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5134 struct mlx5_ifc_modify_rq_in_bits {
5136 u8 reserved_at_10[0x10];
5138 u8 reserved_at_20[0x10];
5142 u8 reserved_at_44[0x4];
5145 u8 reserved_at_60[0x20];
5147 u8 modify_bitmask[0x40];
5149 u8 reserved_at_c0[0x40];
5151 struct mlx5_ifc_rqc_bits ctx;
5154 struct mlx5_ifc_modify_rmp_out_bits {
5156 u8 reserved_at_8[0x18];
5160 u8 reserved_at_40[0x40];
5163 struct mlx5_ifc_rmp_bitmask_bits {
5164 u8 reserved_at_0[0x20];
5166 u8 reserved_at_20[0x1f];
5170 struct mlx5_ifc_modify_rmp_in_bits {
5172 u8 reserved_at_10[0x10];
5174 u8 reserved_at_20[0x10];
5178 u8 reserved_at_44[0x4];
5181 u8 reserved_at_60[0x20];
5183 struct mlx5_ifc_rmp_bitmask_bits bitmask;
5185 u8 reserved_at_c0[0x40];
5187 struct mlx5_ifc_rmpc_bits ctx;
5190 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5192 u8 reserved_at_8[0x18];
5196 u8 reserved_at_40[0x40];
5199 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5200 u8 reserved_at_0[0x16];
5205 u8 change_event[0x1];
5207 u8 permanent_address[0x1];
5208 u8 addresses_list[0x1];
5210 u8 reserved_at_1f[0x1];
5213 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5215 u8 reserved_at_10[0x10];
5217 u8 reserved_at_20[0x10];
5220 u8 other_vport[0x1];
5221 u8 reserved_at_41[0xf];
5222 u8 vport_number[0x10];
5224 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5226 u8 reserved_at_80[0x780];
5228 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5231 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5233 u8 reserved_at_8[0x18];
5237 u8 reserved_at_40[0x40];
5240 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5242 u8 reserved_at_10[0x10];
5244 u8 reserved_at_20[0x10];
5247 u8 other_vport[0x1];
5248 u8 reserved_at_41[0xb];
5250 u8 vport_number[0x10];
5252 u8 reserved_at_60[0x20];
5254 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5257 struct mlx5_ifc_modify_cq_out_bits {
5259 u8 reserved_at_8[0x18];
5263 u8 reserved_at_40[0x40];
5267 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5268 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5271 struct mlx5_ifc_modify_cq_in_bits {
5273 u8 reserved_at_10[0x10];
5275 u8 reserved_at_20[0x10];
5278 u8 reserved_at_40[0x8];
5281 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5283 struct mlx5_ifc_cqc_bits cq_context;
5285 u8 reserved_at_280[0x600];
5290 struct mlx5_ifc_modify_cong_status_out_bits {
5292 u8 reserved_at_8[0x18];
5296 u8 reserved_at_40[0x40];
5299 struct mlx5_ifc_modify_cong_status_in_bits {
5301 u8 reserved_at_10[0x10];
5303 u8 reserved_at_20[0x10];
5306 u8 reserved_at_40[0x18];
5308 u8 cong_protocol[0x4];
5312 u8 reserved_at_62[0x1e];
5315 struct mlx5_ifc_modify_cong_params_out_bits {
5317 u8 reserved_at_8[0x18];
5321 u8 reserved_at_40[0x40];
5324 struct mlx5_ifc_modify_cong_params_in_bits {
5326 u8 reserved_at_10[0x10];
5328 u8 reserved_at_20[0x10];
5331 u8 reserved_at_40[0x1c];
5332 u8 cong_protocol[0x4];
5334 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5336 u8 reserved_at_80[0x80];
5338 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5341 struct mlx5_ifc_manage_pages_out_bits {
5343 u8 reserved_at_8[0x18];
5347 u8 output_num_entries[0x20];
5349 u8 reserved_at_60[0x20];
5355 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5356 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5357 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5360 struct mlx5_ifc_manage_pages_in_bits {
5362 u8 reserved_at_10[0x10];
5364 u8 reserved_at_20[0x10];
5367 u8 reserved_at_40[0x10];
5368 u8 function_id[0x10];
5370 u8 input_num_entries[0x20];
5375 struct mlx5_ifc_mad_ifc_out_bits {
5377 u8 reserved_at_8[0x18];
5381 u8 reserved_at_40[0x40];
5383 u8 response_mad_packet[256][0x8];
5386 struct mlx5_ifc_mad_ifc_in_bits {
5388 u8 reserved_at_10[0x10];
5390 u8 reserved_at_20[0x10];
5393 u8 remote_lid[0x10];
5394 u8 reserved_at_50[0x8];
5397 u8 reserved_at_60[0x20];
5402 struct mlx5_ifc_init_hca_out_bits {
5404 u8 reserved_at_8[0x18];
5408 u8 reserved_at_40[0x40];
5411 struct mlx5_ifc_init_hca_in_bits {
5413 u8 reserved_at_10[0x10];
5415 u8 reserved_at_20[0x10];
5418 u8 reserved_at_40[0x40];
5421 struct mlx5_ifc_init2rtr_qp_out_bits {
5423 u8 reserved_at_8[0x18];
5427 u8 reserved_at_40[0x40];
5430 struct mlx5_ifc_init2rtr_qp_in_bits {
5432 u8 reserved_at_10[0x10];
5434 u8 reserved_at_20[0x10];
5437 u8 reserved_at_40[0x8];
5440 u8 reserved_at_60[0x20];
5442 u8 opt_param_mask[0x20];
5444 u8 reserved_at_a0[0x20];
5446 struct mlx5_ifc_qpc_bits qpc;
5448 u8 reserved_at_800[0x80];
5451 struct mlx5_ifc_init2init_qp_out_bits {
5453 u8 reserved_at_8[0x18];
5457 u8 reserved_at_40[0x40];
5460 struct mlx5_ifc_init2init_qp_in_bits {
5462 u8 reserved_at_10[0x10];
5464 u8 reserved_at_20[0x10];
5467 u8 reserved_at_40[0x8];
5470 u8 reserved_at_60[0x20];
5472 u8 opt_param_mask[0x20];
5474 u8 reserved_at_a0[0x20];
5476 struct mlx5_ifc_qpc_bits qpc;
5478 u8 reserved_at_800[0x80];
5481 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5483 u8 reserved_at_8[0x18];
5487 u8 reserved_at_40[0x40];
5489 u8 packet_headers_log[128][0x8];
5491 u8 packet_syndrome[64][0x8];
5494 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5496 u8 reserved_at_10[0x10];
5498 u8 reserved_at_20[0x10];
5501 u8 reserved_at_40[0x40];
5504 struct mlx5_ifc_gen_eqe_in_bits {
5506 u8 reserved_at_10[0x10];
5508 u8 reserved_at_20[0x10];
5511 u8 reserved_at_40[0x18];
5514 u8 reserved_at_60[0x20];
5519 struct mlx5_ifc_gen_eq_out_bits {
5521 u8 reserved_at_8[0x18];
5525 u8 reserved_at_40[0x40];
5528 struct mlx5_ifc_enable_hca_out_bits {
5530 u8 reserved_at_8[0x18];
5534 u8 reserved_at_40[0x20];
5537 struct mlx5_ifc_enable_hca_in_bits {
5539 u8 reserved_at_10[0x10];
5541 u8 reserved_at_20[0x10];
5544 u8 reserved_at_40[0x10];
5545 u8 function_id[0x10];
5547 u8 reserved_at_60[0x20];
5550 struct mlx5_ifc_drain_dct_out_bits {
5552 u8 reserved_at_8[0x18];
5556 u8 reserved_at_40[0x40];
5559 struct mlx5_ifc_drain_dct_in_bits {
5561 u8 reserved_at_10[0x10];
5563 u8 reserved_at_20[0x10];
5566 u8 reserved_at_40[0x8];
5569 u8 reserved_at_60[0x20];
5572 struct mlx5_ifc_disable_hca_out_bits {
5574 u8 reserved_at_8[0x18];
5578 u8 reserved_at_40[0x20];
5581 struct mlx5_ifc_disable_hca_in_bits {
5583 u8 reserved_at_10[0x10];
5585 u8 reserved_at_20[0x10];
5588 u8 reserved_at_40[0x10];
5589 u8 function_id[0x10];
5591 u8 reserved_at_60[0x20];
5594 struct mlx5_ifc_detach_from_mcg_out_bits {
5596 u8 reserved_at_8[0x18];
5600 u8 reserved_at_40[0x40];
5603 struct mlx5_ifc_detach_from_mcg_in_bits {
5605 u8 reserved_at_10[0x10];
5607 u8 reserved_at_20[0x10];
5610 u8 reserved_at_40[0x8];
5613 u8 reserved_at_60[0x20];
5615 u8 multicast_gid[16][0x8];
5618 struct mlx5_ifc_destroy_xrq_out_bits {
5620 u8 reserved_at_8[0x18];
5624 u8 reserved_at_40[0x40];
5627 struct mlx5_ifc_destroy_xrq_in_bits {
5629 u8 reserved_at_10[0x10];
5631 u8 reserved_at_20[0x10];
5634 u8 reserved_at_40[0x8];
5637 u8 reserved_at_60[0x20];
5640 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5642 u8 reserved_at_8[0x18];
5646 u8 reserved_at_40[0x40];
5649 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5651 u8 reserved_at_10[0x10];
5653 u8 reserved_at_20[0x10];
5656 u8 reserved_at_40[0x8];
5659 u8 reserved_at_60[0x20];
5662 struct mlx5_ifc_destroy_tis_out_bits {
5664 u8 reserved_at_8[0x18];
5668 u8 reserved_at_40[0x40];
5671 struct mlx5_ifc_destroy_tis_in_bits {
5673 u8 reserved_at_10[0x10];
5675 u8 reserved_at_20[0x10];
5678 u8 reserved_at_40[0x8];
5681 u8 reserved_at_60[0x20];
5684 struct mlx5_ifc_destroy_tir_out_bits {
5686 u8 reserved_at_8[0x18];
5690 u8 reserved_at_40[0x40];
5693 struct mlx5_ifc_destroy_tir_in_bits {
5695 u8 reserved_at_10[0x10];
5697 u8 reserved_at_20[0x10];
5700 u8 reserved_at_40[0x8];
5703 u8 reserved_at_60[0x20];
5706 struct mlx5_ifc_destroy_srq_out_bits {
5708 u8 reserved_at_8[0x18];
5712 u8 reserved_at_40[0x40];
5715 struct mlx5_ifc_destroy_srq_in_bits {
5717 u8 reserved_at_10[0x10];
5719 u8 reserved_at_20[0x10];
5722 u8 reserved_at_40[0x8];
5725 u8 reserved_at_60[0x20];
5728 struct mlx5_ifc_destroy_sq_out_bits {
5730 u8 reserved_at_8[0x18];
5734 u8 reserved_at_40[0x40];
5737 struct mlx5_ifc_destroy_sq_in_bits {
5739 u8 reserved_at_10[0x10];
5741 u8 reserved_at_20[0x10];
5744 u8 reserved_at_40[0x8];
5747 u8 reserved_at_60[0x20];
5750 struct mlx5_ifc_destroy_scheduling_element_out_bits {
5752 u8 reserved_at_8[0x18];
5756 u8 reserved_at_40[0x1c0];
5759 struct mlx5_ifc_destroy_scheduling_element_in_bits {
5761 u8 reserved_at_10[0x10];
5763 u8 reserved_at_20[0x10];
5766 u8 scheduling_hierarchy[0x8];
5767 u8 reserved_at_48[0x18];
5769 u8 scheduling_element_id[0x20];
5771 u8 reserved_at_80[0x180];
5774 struct mlx5_ifc_destroy_rqt_out_bits {
5776 u8 reserved_at_8[0x18];
5780 u8 reserved_at_40[0x40];
5783 struct mlx5_ifc_destroy_rqt_in_bits {
5785 u8 reserved_at_10[0x10];
5787 u8 reserved_at_20[0x10];
5790 u8 reserved_at_40[0x8];
5793 u8 reserved_at_60[0x20];
5796 struct mlx5_ifc_destroy_rq_out_bits {
5798 u8 reserved_at_8[0x18];
5802 u8 reserved_at_40[0x40];
5805 struct mlx5_ifc_destroy_rq_in_bits {
5807 u8 reserved_at_10[0x10];
5809 u8 reserved_at_20[0x10];
5812 u8 reserved_at_40[0x8];
5815 u8 reserved_at_60[0x20];
5818 struct mlx5_ifc_destroy_rmp_out_bits {
5820 u8 reserved_at_8[0x18];
5824 u8 reserved_at_40[0x40];
5827 struct mlx5_ifc_destroy_rmp_in_bits {
5829 u8 reserved_at_10[0x10];
5831 u8 reserved_at_20[0x10];
5834 u8 reserved_at_40[0x8];
5837 u8 reserved_at_60[0x20];
5840 struct mlx5_ifc_destroy_qp_out_bits {
5842 u8 reserved_at_8[0x18];
5846 u8 reserved_at_40[0x40];
5849 struct mlx5_ifc_destroy_qp_in_bits {
5851 u8 reserved_at_10[0x10];
5853 u8 reserved_at_20[0x10];
5856 u8 reserved_at_40[0x8];
5859 u8 reserved_at_60[0x20];
5862 struct mlx5_ifc_destroy_psv_out_bits {
5864 u8 reserved_at_8[0x18];
5868 u8 reserved_at_40[0x40];
5871 struct mlx5_ifc_destroy_psv_in_bits {
5873 u8 reserved_at_10[0x10];
5875 u8 reserved_at_20[0x10];
5878 u8 reserved_at_40[0x8];
5881 u8 reserved_at_60[0x20];
5884 struct mlx5_ifc_destroy_mkey_out_bits {
5886 u8 reserved_at_8[0x18];
5890 u8 reserved_at_40[0x40];
5893 struct mlx5_ifc_destroy_mkey_in_bits {
5895 u8 reserved_at_10[0x10];
5897 u8 reserved_at_20[0x10];
5900 u8 reserved_at_40[0x8];
5901 u8 mkey_index[0x18];
5903 u8 reserved_at_60[0x20];
5906 struct mlx5_ifc_destroy_flow_table_out_bits {
5908 u8 reserved_at_8[0x18];
5912 u8 reserved_at_40[0x40];
5915 struct mlx5_ifc_destroy_flow_table_in_bits {
5917 u8 reserved_at_10[0x10];
5919 u8 reserved_at_20[0x10];
5922 u8 other_vport[0x1];
5923 u8 reserved_at_41[0xf];
5924 u8 vport_number[0x10];
5926 u8 reserved_at_60[0x20];
5929 u8 reserved_at_88[0x18];
5931 u8 reserved_at_a0[0x8];
5934 u8 reserved_at_c0[0x140];
5937 struct mlx5_ifc_destroy_flow_group_out_bits {
5939 u8 reserved_at_8[0x18];
5943 u8 reserved_at_40[0x40];
5946 struct mlx5_ifc_destroy_flow_group_in_bits {
5948 u8 reserved_at_10[0x10];
5950 u8 reserved_at_20[0x10];
5953 u8 other_vport[0x1];
5954 u8 reserved_at_41[0xf];
5955 u8 vport_number[0x10];
5957 u8 reserved_at_60[0x20];
5960 u8 reserved_at_88[0x18];
5962 u8 reserved_at_a0[0x8];
5967 u8 reserved_at_e0[0x120];
5970 struct mlx5_ifc_destroy_eq_out_bits {
5972 u8 reserved_at_8[0x18];
5976 u8 reserved_at_40[0x40];
5979 struct mlx5_ifc_destroy_eq_in_bits {
5981 u8 reserved_at_10[0x10];
5983 u8 reserved_at_20[0x10];
5986 u8 reserved_at_40[0x18];
5989 u8 reserved_at_60[0x20];
5992 struct mlx5_ifc_destroy_dct_out_bits {
5994 u8 reserved_at_8[0x18];
5998 u8 reserved_at_40[0x40];
6001 struct mlx5_ifc_destroy_dct_in_bits {
6003 u8 reserved_at_10[0x10];
6005 u8 reserved_at_20[0x10];
6008 u8 reserved_at_40[0x8];
6011 u8 reserved_at_60[0x20];
6014 struct mlx5_ifc_destroy_cq_out_bits {
6016 u8 reserved_at_8[0x18];
6020 u8 reserved_at_40[0x40];
6023 struct mlx5_ifc_destroy_cq_in_bits {
6025 u8 reserved_at_10[0x10];
6027 u8 reserved_at_20[0x10];
6030 u8 reserved_at_40[0x8];
6033 u8 reserved_at_60[0x20];
6036 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6038 u8 reserved_at_8[0x18];
6042 u8 reserved_at_40[0x40];
6045 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6047 u8 reserved_at_10[0x10];
6049 u8 reserved_at_20[0x10];
6052 u8 reserved_at_40[0x20];
6054 u8 reserved_at_60[0x10];
6055 u8 vxlan_udp_port[0x10];
6058 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6060 u8 reserved_at_8[0x18];
6064 u8 reserved_at_40[0x40];
6067 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6069 u8 reserved_at_10[0x10];
6071 u8 reserved_at_20[0x10];
6074 u8 reserved_at_40[0x60];
6076 u8 reserved_at_a0[0x8];
6077 u8 table_index[0x18];
6079 u8 reserved_at_c0[0x140];
6082 struct mlx5_ifc_delete_fte_out_bits {
6084 u8 reserved_at_8[0x18];
6088 u8 reserved_at_40[0x40];
6091 struct mlx5_ifc_delete_fte_in_bits {
6093 u8 reserved_at_10[0x10];
6095 u8 reserved_at_20[0x10];
6098 u8 other_vport[0x1];
6099 u8 reserved_at_41[0xf];
6100 u8 vport_number[0x10];
6102 u8 reserved_at_60[0x20];
6105 u8 reserved_at_88[0x18];
6107 u8 reserved_at_a0[0x8];
6110 u8 reserved_at_c0[0x40];
6112 u8 flow_index[0x20];
6114 u8 reserved_at_120[0xe0];
6117 struct mlx5_ifc_dealloc_xrcd_out_bits {
6119 u8 reserved_at_8[0x18];
6123 u8 reserved_at_40[0x40];
6126 struct mlx5_ifc_dealloc_xrcd_in_bits {
6128 u8 reserved_at_10[0x10];
6130 u8 reserved_at_20[0x10];
6133 u8 reserved_at_40[0x8];
6136 u8 reserved_at_60[0x20];
6139 struct mlx5_ifc_dealloc_uar_out_bits {
6141 u8 reserved_at_8[0x18];
6145 u8 reserved_at_40[0x40];
6148 struct mlx5_ifc_dealloc_uar_in_bits {
6150 u8 reserved_at_10[0x10];
6152 u8 reserved_at_20[0x10];
6155 u8 reserved_at_40[0x8];
6158 u8 reserved_at_60[0x20];
6161 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6163 u8 reserved_at_8[0x18];
6167 u8 reserved_at_40[0x40];
6170 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6172 u8 reserved_at_10[0x10];
6174 u8 reserved_at_20[0x10];
6177 u8 reserved_at_40[0x8];
6178 u8 transport_domain[0x18];
6180 u8 reserved_at_60[0x20];
6183 struct mlx5_ifc_dealloc_q_counter_out_bits {
6185 u8 reserved_at_8[0x18];
6189 u8 reserved_at_40[0x40];
6192 struct mlx5_ifc_dealloc_q_counter_in_bits {
6194 u8 reserved_at_10[0x10];
6196 u8 reserved_at_20[0x10];
6199 u8 reserved_at_40[0x18];
6200 u8 counter_set_id[0x8];
6202 u8 reserved_at_60[0x20];
6205 struct mlx5_ifc_dealloc_pd_out_bits {
6207 u8 reserved_at_8[0x18];
6211 u8 reserved_at_40[0x40];
6214 struct mlx5_ifc_dealloc_pd_in_bits {
6216 u8 reserved_at_10[0x10];
6218 u8 reserved_at_20[0x10];
6221 u8 reserved_at_40[0x8];
6224 u8 reserved_at_60[0x20];
6227 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6229 u8 reserved_at_8[0x18];
6233 u8 reserved_at_40[0x40];
6236 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6238 u8 reserved_at_10[0x10];
6240 u8 reserved_at_20[0x10];
6243 u8 reserved_at_40[0x10];
6244 u8 flow_counter_id[0x10];
6246 u8 reserved_at_60[0x20];
6249 struct mlx5_ifc_create_xrq_out_bits {
6251 u8 reserved_at_8[0x18];
6255 u8 reserved_at_40[0x8];
6258 u8 reserved_at_60[0x20];
6261 struct mlx5_ifc_create_xrq_in_bits {
6263 u8 reserved_at_10[0x10];
6265 u8 reserved_at_20[0x10];
6268 u8 reserved_at_40[0x40];
6270 struct mlx5_ifc_xrqc_bits xrq_context;
6273 struct mlx5_ifc_create_xrc_srq_out_bits {
6275 u8 reserved_at_8[0x18];
6279 u8 reserved_at_40[0x8];
6282 u8 reserved_at_60[0x20];
6285 struct mlx5_ifc_create_xrc_srq_in_bits {
6287 u8 reserved_at_10[0x10];
6289 u8 reserved_at_20[0x10];
6292 u8 reserved_at_40[0x40];
6294 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6296 u8 reserved_at_280[0x600];
6301 struct mlx5_ifc_create_tis_out_bits {
6303 u8 reserved_at_8[0x18];
6307 u8 reserved_at_40[0x8];
6310 u8 reserved_at_60[0x20];
6313 struct mlx5_ifc_create_tis_in_bits {
6315 u8 reserved_at_10[0x10];
6317 u8 reserved_at_20[0x10];
6320 u8 reserved_at_40[0xc0];
6322 struct mlx5_ifc_tisc_bits ctx;
6325 struct mlx5_ifc_create_tir_out_bits {
6327 u8 reserved_at_8[0x18];
6331 u8 reserved_at_40[0x8];
6334 u8 reserved_at_60[0x20];
6337 struct mlx5_ifc_create_tir_in_bits {
6339 u8 reserved_at_10[0x10];
6341 u8 reserved_at_20[0x10];
6344 u8 reserved_at_40[0xc0];
6346 struct mlx5_ifc_tirc_bits ctx;
6349 struct mlx5_ifc_create_srq_out_bits {
6351 u8 reserved_at_8[0x18];
6355 u8 reserved_at_40[0x8];
6358 u8 reserved_at_60[0x20];
6361 struct mlx5_ifc_create_srq_in_bits {
6363 u8 reserved_at_10[0x10];
6365 u8 reserved_at_20[0x10];
6368 u8 reserved_at_40[0x40];
6370 struct mlx5_ifc_srqc_bits srq_context_entry;
6372 u8 reserved_at_280[0x600];
6377 struct mlx5_ifc_create_sq_out_bits {
6379 u8 reserved_at_8[0x18];
6383 u8 reserved_at_40[0x8];
6386 u8 reserved_at_60[0x20];
6389 struct mlx5_ifc_create_sq_in_bits {
6391 u8 reserved_at_10[0x10];
6393 u8 reserved_at_20[0x10];
6396 u8 reserved_at_40[0xc0];
6398 struct mlx5_ifc_sqc_bits ctx;
6401 struct mlx5_ifc_create_scheduling_element_out_bits {
6403 u8 reserved_at_8[0x18];
6407 u8 reserved_at_40[0x40];
6409 u8 scheduling_element_id[0x20];
6411 u8 reserved_at_a0[0x160];
6414 struct mlx5_ifc_create_scheduling_element_in_bits {
6416 u8 reserved_at_10[0x10];
6418 u8 reserved_at_20[0x10];
6421 u8 scheduling_hierarchy[0x8];
6422 u8 reserved_at_48[0x18];
6424 u8 reserved_at_60[0xa0];
6426 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6428 u8 reserved_at_300[0x100];
6431 struct mlx5_ifc_create_rqt_out_bits {
6433 u8 reserved_at_8[0x18];
6437 u8 reserved_at_40[0x8];
6440 u8 reserved_at_60[0x20];
6443 struct mlx5_ifc_create_rqt_in_bits {
6445 u8 reserved_at_10[0x10];
6447 u8 reserved_at_20[0x10];
6450 u8 reserved_at_40[0xc0];
6452 struct mlx5_ifc_rqtc_bits rqt_context;
6455 struct mlx5_ifc_create_rq_out_bits {
6457 u8 reserved_at_8[0x18];
6461 u8 reserved_at_40[0x8];
6464 u8 reserved_at_60[0x20];
6467 struct mlx5_ifc_create_rq_in_bits {
6469 u8 reserved_at_10[0x10];
6471 u8 reserved_at_20[0x10];
6474 u8 reserved_at_40[0xc0];
6476 struct mlx5_ifc_rqc_bits ctx;
6479 struct mlx5_ifc_create_rmp_out_bits {
6481 u8 reserved_at_8[0x18];
6485 u8 reserved_at_40[0x8];
6488 u8 reserved_at_60[0x20];
6491 struct mlx5_ifc_create_rmp_in_bits {
6493 u8 reserved_at_10[0x10];
6495 u8 reserved_at_20[0x10];
6498 u8 reserved_at_40[0xc0];
6500 struct mlx5_ifc_rmpc_bits ctx;
6503 struct mlx5_ifc_create_qp_out_bits {
6505 u8 reserved_at_8[0x18];
6509 u8 reserved_at_40[0x8];
6512 u8 reserved_at_60[0x20];
6515 struct mlx5_ifc_create_qp_in_bits {
6517 u8 reserved_at_10[0x10];
6519 u8 reserved_at_20[0x10];
6522 u8 reserved_at_40[0x40];
6524 u8 opt_param_mask[0x20];
6526 u8 reserved_at_a0[0x20];
6528 struct mlx5_ifc_qpc_bits qpc;
6530 u8 reserved_at_800[0x80];
6535 struct mlx5_ifc_create_psv_out_bits {
6537 u8 reserved_at_8[0x18];
6541 u8 reserved_at_40[0x40];
6543 u8 reserved_at_80[0x8];
6544 u8 psv0_index[0x18];
6546 u8 reserved_at_a0[0x8];
6547 u8 psv1_index[0x18];
6549 u8 reserved_at_c0[0x8];
6550 u8 psv2_index[0x18];
6552 u8 reserved_at_e0[0x8];
6553 u8 psv3_index[0x18];
6556 struct mlx5_ifc_create_psv_in_bits {
6558 u8 reserved_at_10[0x10];
6560 u8 reserved_at_20[0x10];
6564 u8 reserved_at_44[0x4];
6567 u8 reserved_at_60[0x20];
6570 struct mlx5_ifc_create_mkey_out_bits {
6572 u8 reserved_at_8[0x18];
6576 u8 reserved_at_40[0x8];
6577 u8 mkey_index[0x18];
6579 u8 reserved_at_60[0x20];
6582 struct mlx5_ifc_create_mkey_in_bits {
6584 u8 reserved_at_10[0x10];
6586 u8 reserved_at_20[0x10];
6589 u8 reserved_at_40[0x20];
6592 u8 reserved_at_61[0x1f];
6594 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6596 u8 reserved_at_280[0x80];
6598 u8 translations_octword_actual_size[0x20];
6600 u8 reserved_at_320[0x560];
6602 u8 klm_pas_mtt[0][0x20];
6605 struct mlx5_ifc_create_flow_table_out_bits {
6607 u8 reserved_at_8[0x18];
6611 u8 reserved_at_40[0x8];
6614 u8 reserved_at_60[0x20];
6617 struct mlx5_ifc_create_flow_table_in_bits {
6619 u8 reserved_at_10[0x10];
6621 u8 reserved_at_20[0x10];
6624 u8 other_vport[0x1];
6625 u8 reserved_at_41[0xf];
6626 u8 vport_number[0x10];
6628 u8 reserved_at_60[0x20];
6631 u8 reserved_at_88[0x18];
6633 u8 reserved_at_a0[0x20];
6637 u8 reserved_at_c2[0x2];
6638 u8 table_miss_mode[0x4];
6640 u8 reserved_at_d0[0x8];
6643 u8 reserved_at_e0[0x8];
6644 u8 table_miss_id[0x18];
6646 u8 reserved_at_100[0x8];
6647 u8 lag_master_next_table_id[0x18];
6649 u8 reserved_at_120[0x80];
6652 struct mlx5_ifc_create_flow_group_out_bits {
6654 u8 reserved_at_8[0x18];
6658 u8 reserved_at_40[0x8];
6661 u8 reserved_at_60[0x20];
6665 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6666 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6667 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6670 struct mlx5_ifc_create_flow_group_in_bits {
6672 u8 reserved_at_10[0x10];
6674 u8 reserved_at_20[0x10];
6677 u8 other_vport[0x1];
6678 u8 reserved_at_41[0xf];
6679 u8 vport_number[0x10];
6681 u8 reserved_at_60[0x20];
6684 u8 reserved_at_88[0x18];
6686 u8 reserved_at_a0[0x8];
6689 u8 reserved_at_c0[0x20];
6691 u8 start_flow_index[0x20];
6693 u8 reserved_at_100[0x20];
6695 u8 end_flow_index[0x20];
6697 u8 reserved_at_140[0xa0];
6699 u8 reserved_at_1e0[0x18];
6700 u8 match_criteria_enable[0x8];
6702 struct mlx5_ifc_fte_match_param_bits match_criteria;
6704 u8 reserved_at_1200[0xe00];
6707 struct mlx5_ifc_create_eq_out_bits {
6709 u8 reserved_at_8[0x18];
6713 u8 reserved_at_40[0x18];
6716 u8 reserved_at_60[0x20];
6719 struct mlx5_ifc_create_eq_in_bits {
6721 u8 reserved_at_10[0x10];
6723 u8 reserved_at_20[0x10];
6726 u8 reserved_at_40[0x40];
6728 struct mlx5_ifc_eqc_bits eq_context_entry;
6730 u8 reserved_at_280[0x40];
6732 u8 event_bitmask[0x40];
6734 u8 reserved_at_300[0x580];
6739 struct mlx5_ifc_create_dct_out_bits {
6741 u8 reserved_at_8[0x18];
6745 u8 reserved_at_40[0x8];
6748 u8 reserved_at_60[0x20];
6751 struct mlx5_ifc_create_dct_in_bits {
6753 u8 reserved_at_10[0x10];
6755 u8 reserved_at_20[0x10];
6758 u8 reserved_at_40[0x40];
6760 struct mlx5_ifc_dctc_bits dct_context_entry;
6762 u8 reserved_at_280[0x180];
6765 struct mlx5_ifc_create_cq_out_bits {
6767 u8 reserved_at_8[0x18];
6771 u8 reserved_at_40[0x8];
6774 u8 reserved_at_60[0x20];
6777 struct mlx5_ifc_create_cq_in_bits {
6779 u8 reserved_at_10[0x10];
6781 u8 reserved_at_20[0x10];
6784 u8 reserved_at_40[0x40];
6786 struct mlx5_ifc_cqc_bits cq_context;
6788 u8 reserved_at_280[0x600];
6793 struct mlx5_ifc_config_int_moderation_out_bits {
6795 u8 reserved_at_8[0x18];
6799 u8 reserved_at_40[0x4];
6801 u8 int_vector[0x10];
6803 u8 reserved_at_60[0x20];
6807 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
6808 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
6811 struct mlx5_ifc_config_int_moderation_in_bits {
6813 u8 reserved_at_10[0x10];
6815 u8 reserved_at_20[0x10];
6818 u8 reserved_at_40[0x4];
6820 u8 int_vector[0x10];
6822 u8 reserved_at_60[0x20];
6825 struct mlx5_ifc_attach_to_mcg_out_bits {
6827 u8 reserved_at_8[0x18];
6831 u8 reserved_at_40[0x40];
6834 struct mlx5_ifc_attach_to_mcg_in_bits {
6836 u8 reserved_at_10[0x10];
6838 u8 reserved_at_20[0x10];
6841 u8 reserved_at_40[0x8];
6844 u8 reserved_at_60[0x20];
6846 u8 multicast_gid[16][0x8];
6849 struct mlx5_ifc_arm_xrq_out_bits {
6851 u8 reserved_at_8[0x18];
6855 u8 reserved_at_40[0x40];
6858 struct mlx5_ifc_arm_xrq_in_bits {
6860 u8 reserved_at_10[0x10];
6862 u8 reserved_at_20[0x10];
6865 u8 reserved_at_40[0x8];
6868 u8 reserved_at_60[0x10];
6872 struct mlx5_ifc_arm_xrc_srq_out_bits {
6874 u8 reserved_at_8[0x18];
6878 u8 reserved_at_40[0x40];
6882 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
6885 struct mlx5_ifc_arm_xrc_srq_in_bits {
6887 u8 reserved_at_10[0x10];
6889 u8 reserved_at_20[0x10];
6892 u8 reserved_at_40[0x8];
6895 u8 reserved_at_60[0x10];
6899 struct mlx5_ifc_arm_rq_out_bits {
6901 u8 reserved_at_8[0x18];
6905 u8 reserved_at_40[0x40];
6909 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
6910 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
6913 struct mlx5_ifc_arm_rq_in_bits {
6915 u8 reserved_at_10[0x10];
6917 u8 reserved_at_20[0x10];
6920 u8 reserved_at_40[0x8];
6921 u8 srq_number[0x18];
6923 u8 reserved_at_60[0x10];
6927 struct mlx5_ifc_arm_dct_out_bits {
6929 u8 reserved_at_8[0x18];
6933 u8 reserved_at_40[0x40];
6936 struct mlx5_ifc_arm_dct_in_bits {
6938 u8 reserved_at_10[0x10];
6940 u8 reserved_at_20[0x10];
6943 u8 reserved_at_40[0x8];
6944 u8 dct_number[0x18];
6946 u8 reserved_at_60[0x20];
6949 struct mlx5_ifc_alloc_xrcd_out_bits {
6951 u8 reserved_at_8[0x18];
6955 u8 reserved_at_40[0x8];
6958 u8 reserved_at_60[0x20];
6961 struct mlx5_ifc_alloc_xrcd_in_bits {
6963 u8 reserved_at_10[0x10];
6965 u8 reserved_at_20[0x10];
6968 u8 reserved_at_40[0x40];
6971 struct mlx5_ifc_alloc_uar_out_bits {
6973 u8 reserved_at_8[0x18];
6977 u8 reserved_at_40[0x8];
6980 u8 reserved_at_60[0x20];
6983 struct mlx5_ifc_alloc_uar_in_bits {
6985 u8 reserved_at_10[0x10];
6987 u8 reserved_at_20[0x10];
6990 u8 reserved_at_40[0x40];
6993 struct mlx5_ifc_alloc_transport_domain_out_bits {
6995 u8 reserved_at_8[0x18];
6999 u8 reserved_at_40[0x8];
7000 u8 transport_domain[0x18];
7002 u8 reserved_at_60[0x20];
7005 struct mlx5_ifc_alloc_transport_domain_in_bits {
7007 u8 reserved_at_10[0x10];
7009 u8 reserved_at_20[0x10];
7012 u8 reserved_at_40[0x40];
7015 struct mlx5_ifc_alloc_q_counter_out_bits {
7017 u8 reserved_at_8[0x18];
7021 u8 reserved_at_40[0x18];
7022 u8 counter_set_id[0x8];
7024 u8 reserved_at_60[0x20];
7027 struct mlx5_ifc_alloc_q_counter_in_bits {
7029 u8 reserved_at_10[0x10];
7031 u8 reserved_at_20[0x10];
7034 u8 reserved_at_40[0x40];
7037 struct mlx5_ifc_alloc_pd_out_bits {
7039 u8 reserved_at_8[0x18];
7043 u8 reserved_at_40[0x8];
7046 u8 reserved_at_60[0x20];
7049 struct mlx5_ifc_alloc_pd_in_bits {
7051 u8 reserved_at_10[0x10];
7053 u8 reserved_at_20[0x10];
7056 u8 reserved_at_40[0x40];
7059 struct mlx5_ifc_alloc_flow_counter_out_bits {
7061 u8 reserved_at_8[0x18];
7065 u8 reserved_at_40[0x10];
7066 u8 flow_counter_id[0x10];
7068 u8 reserved_at_60[0x20];
7071 struct mlx5_ifc_alloc_flow_counter_in_bits {
7073 u8 reserved_at_10[0x10];
7075 u8 reserved_at_20[0x10];
7078 u8 reserved_at_40[0x40];
7081 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7083 u8 reserved_at_8[0x18];
7087 u8 reserved_at_40[0x40];
7090 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7092 u8 reserved_at_10[0x10];
7094 u8 reserved_at_20[0x10];
7097 u8 reserved_at_40[0x20];
7099 u8 reserved_at_60[0x10];
7100 u8 vxlan_udp_port[0x10];
7103 struct mlx5_ifc_set_rate_limit_out_bits {
7105 u8 reserved_at_8[0x18];
7109 u8 reserved_at_40[0x40];
7112 struct mlx5_ifc_set_rate_limit_in_bits {
7114 u8 reserved_at_10[0x10];
7116 u8 reserved_at_20[0x10];
7119 u8 reserved_at_40[0x10];
7120 u8 rate_limit_index[0x10];
7122 u8 reserved_at_60[0x20];
7124 u8 rate_limit[0x20];
7127 struct mlx5_ifc_access_register_out_bits {
7129 u8 reserved_at_8[0x18];
7133 u8 reserved_at_40[0x40];
7135 u8 register_data[0][0x20];
7139 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7140 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7143 struct mlx5_ifc_access_register_in_bits {
7145 u8 reserved_at_10[0x10];
7147 u8 reserved_at_20[0x10];
7150 u8 reserved_at_40[0x10];
7151 u8 register_id[0x10];
7155 u8 register_data[0][0x20];
7158 struct mlx5_ifc_sltp_reg_bits {
7163 u8 reserved_at_12[0x2];
7165 u8 reserved_at_18[0x8];
7167 u8 reserved_at_20[0x20];
7169 u8 reserved_at_40[0x7];
7175 u8 reserved_at_60[0xc];
7176 u8 ob_preemp_mode[0x4];
7180 u8 reserved_at_80[0x20];
7183 struct mlx5_ifc_slrg_reg_bits {
7188 u8 reserved_at_12[0x2];
7190 u8 reserved_at_18[0x8];
7192 u8 time_to_link_up[0x10];
7193 u8 reserved_at_30[0xc];
7194 u8 grade_lane_speed[0x4];
7196 u8 grade_version[0x8];
7199 u8 reserved_at_60[0x4];
7200 u8 height_grade_type[0x4];
7201 u8 height_grade[0x18];
7206 u8 reserved_at_a0[0x10];
7207 u8 height_sigma[0x10];
7209 u8 reserved_at_c0[0x20];
7211 u8 reserved_at_e0[0x4];
7212 u8 phase_grade_type[0x4];
7213 u8 phase_grade[0x18];
7215 u8 reserved_at_100[0x8];
7216 u8 phase_eo_pos[0x8];
7217 u8 reserved_at_110[0x8];
7218 u8 phase_eo_neg[0x8];
7220 u8 ffe_set_tested[0x10];
7221 u8 test_errors_per_lane[0x10];
7224 struct mlx5_ifc_pvlc_reg_bits {
7225 u8 reserved_at_0[0x8];
7227 u8 reserved_at_10[0x10];
7229 u8 reserved_at_20[0x1c];
7232 u8 reserved_at_40[0x1c];
7235 u8 reserved_at_60[0x1c];
7236 u8 vl_operational[0x4];
7239 struct mlx5_ifc_pude_reg_bits {
7242 u8 reserved_at_10[0x4];
7243 u8 admin_status[0x4];
7244 u8 reserved_at_18[0x4];
7245 u8 oper_status[0x4];
7247 u8 reserved_at_20[0x60];
7250 struct mlx5_ifc_ptys_reg_bits {
7251 u8 reserved_at_0[0x1];
7252 u8 an_disable_admin[0x1];
7253 u8 an_disable_cap[0x1];
7254 u8 reserved_at_3[0x5];
7256 u8 reserved_at_10[0xd];
7260 u8 reserved_at_24[0x3c];
7262 u8 eth_proto_capability[0x20];
7264 u8 ib_link_width_capability[0x10];
7265 u8 ib_proto_capability[0x10];
7267 u8 reserved_at_a0[0x20];
7269 u8 eth_proto_admin[0x20];
7271 u8 ib_link_width_admin[0x10];
7272 u8 ib_proto_admin[0x10];
7274 u8 reserved_at_100[0x20];
7276 u8 eth_proto_oper[0x20];
7278 u8 ib_link_width_oper[0x10];
7279 u8 ib_proto_oper[0x10];
7281 u8 reserved_at_160[0x20];
7283 u8 eth_proto_lp_advertise[0x20];
7285 u8 reserved_at_1a0[0x60];
7288 struct mlx5_ifc_mlcr_reg_bits {
7289 u8 reserved_at_0[0x8];
7291 u8 reserved_at_10[0x20];
7293 u8 beacon_duration[0x10];
7294 u8 reserved_at_40[0x10];
7296 u8 beacon_remain[0x10];
7299 struct mlx5_ifc_ptas_reg_bits {
7300 u8 reserved_at_0[0x20];
7302 u8 algorithm_options[0x10];
7303 u8 reserved_at_30[0x4];
7304 u8 repetitions_mode[0x4];
7305 u8 num_of_repetitions[0x8];
7307 u8 grade_version[0x8];
7308 u8 height_grade_type[0x4];
7309 u8 phase_grade_type[0x4];
7310 u8 height_grade_weight[0x8];
7311 u8 phase_grade_weight[0x8];
7313 u8 gisim_measure_bits[0x10];
7314 u8 adaptive_tap_measure_bits[0x10];
7316 u8 ber_bath_high_error_threshold[0x10];
7317 u8 ber_bath_mid_error_threshold[0x10];
7319 u8 ber_bath_low_error_threshold[0x10];
7320 u8 one_ratio_high_threshold[0x10];
7322 u8 one_ratio_high_mid_threshold[0x10];
7323 u8 one_ratio_low_mid_threshold[0x10];
7325 u8 one_ratio_low_threshold[0x10];
7326 u8 ndeo_error_threshold[0x10];
7328 u8 mixer_offset_step_size[0x10];
7329 u8 reserved_at_110[0x8];
7330 u8 mix90_phase_for_voltage_bath[0x8];
7332 u8 mixer_offset_start[0x10];
7333 u8 mixer_offset_end[0x10];
7335 u8 reserved_at_140[0x15];
7336 u8 ber_test_time[0xb];
7339 struct mlx5_ifc_pspa_reg_bits {
7343 u8 reserved_at_18[0x8];
7345 u8 reserved_at_20[0x20];
7348 struct mlx5_ifc_pqdr_reg_bits {
7349 u8 reserved_at_0[0x8];
7351 u8 reserved_at_10[0x5];
7353 u8 reserved_at_18[0x6];
7356 u8 reserved_at_20[0x20];
7358 u8 reserved_at_40[0x10];
7359 u8 min_threshold[0x10];
7361 u8 reserved_at_60[0x10];
7362 u8 max_threshold[0x10];
7364 u8 reserved_at_80[0x10];
7365 u8 mark_probability_denominator[0x10];
7367 u8 reserved_at_a0[0x60];
7370 struct mlx5_ifc_ppsc_reg_bits {
7371 u8 reserved_at_0[0x8];
7373 u8 reserved_at_10[0x10];
7375 u8 reserved_at_20[0x60];
7377 u8 reserved_at_80[0x1c];
7380 u8 reserved_at_a0[0x1c];
7381 u8 wrps_status[0x4];
7383 u8 reserved_at_c0[0x8];
7384 u8 up_threshold[0x8];
7385 u8 reserved_at_d0[0x8];
7386 u8 down_threshold[0x8];
7388 u8 reserved_at_e0[0x20];
7390 u8 reserved_at_100[0x1c];
7393 u8 reserved_at_120[0x1c];
7394 u8 srps_status[0x4];
7396 u8 reserved_at_140[0x40];
7399 struct mlx5_ifc_pplr_reg_bits {
7400 u8 reserved_at_0[0x8];
7402 u8 reserved_at_10[0x10];
7404 u8 reserved_at_20[0x8];
7406 u8 reserved_at_30[0x8];
7410 struct mlx5_ifc_pplm_reg_bits {
7411 u8 reserved_at_0[0x8];
7413 u8 reserved_at_10[0x10];
7415 u8 reserved_at_20[0x20];
7417 u8 port_profile_mode[0x8];
7418 u8 static_port_profile[0x8];
7419 u8 active_port_profile[0x8];
7420 u8 reserved_at_58[0x8];
7422 u8 retransmission_active[0x8];
7423 u8 fec_mode_active[0x18];
7425 u8 reserved_at_80[0x20];
7428 struct mlx5_ifc_ppcnt_reg_bits {
7432 u8 reserved_at_12[0x8];
7436 u8 reserved_at_21[0x1c];
7439 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7442 struct mlx5_ifc_mpcnt_reg_bits {
7443 u8 reserved_at_0[0x8];
7445 u8 reserved_at_10[0xa];
7449 u8 reserved_at_21[0x1f];
7451 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7454 struct mlx5_ifc_ppad_reg_bits {
7455 u8 reserved_at_0[0x3];
7457 u8 reserved_at_4[0x4];
7463 u8 reserved_at_40[0x40];
7466 struct mlx5_ifc_pmtu_reg_bits {
7467 u8 reserved_at_0[0x8];
7469 u8 reserved_at_10[0x10];
7472 u8 reserved_at_30[0x10];
7475 u8 reserved_at_50[0x10];
7478 u8 reserved_at_70[0x10];
7481 struct mlx5_ifc_pmpr_reg_bits {
7482 u8 reserved_at_0[0x8];
7484 u8 reserved_at_10[0x10];
7486 u8 reserved_at_20[0x18];
7487 u8 attenuation_5g[0x8];
7489 u8 reserved_at_40[0x18];
7490 u8 attenuation_7g[0x8];
7492 u8 reserved_at_60[0x18];
7493 u8 attenuation_12g[0x8];
7496 struct mlx5_ifc_pmpe_reg_bits {
7497 u8 reserved_at_0[0x8];
7499 u8 reserved_at_10[0xc];
7500 u8 module_status[0x4];
7502 u8 reserved_at_20[0x60];
7505 struct mlx5_ifc_pmpc_reg_bits {
7506 u8 module_state_updated[32][0x8];
7509 struct mlx5_ifc_pmlpn_reg_bits {
7510 u8 reserved_at_0[0x4];
7511 u8 mlpn_status[0x4];
7513 u8 reserved_at_10[0x10];
7516 u8 reserved_at_21[0x1f];
7519 struct mlx5_ifc_pmlp_reg_bits {
7521 u8 reserved_at_1[0x7];
7523 u8 reserved_at_10[0x8];
7526 u8 lane0_module_mapping[0x20];
7528 u8 lane1_module_mapping[0x20];
7530 u8 lane2_module_mapping[0x20];
7532 u8 lane3_module_mapping[0x20];
7534 u8 reserved_at_a0[0x160];
7537 struct mlx5_ifc_pmaos_reg_bits {
7538 u8 reserved_at_0[0x8];
7540 u8 reserved_at_10[0x4];
7541 u8 admin_status[0x4];
7542 u8 reserved_at_18[0x4];
7543 u8 oper_status[0x4];
7547 u8 reserved_at_22[0x1c];
7550 u8 reserved_at_40[0x40];
7553 struct mlx5_ifc_plpc_reg_bits {
7554 u8 reserved_at_0[0x4];
7556 u8 reserved_at_10[0x4];
7558 u8 reserved_at_18[0x8];
7560 u8 reserved_at_20[0x10];
7561 u8 lane_speed[0x10];
7563 u8 reserved_at_40[0x17];
7565 u8 fec_mode_policy[0x8];
7567 u8 retransmission_capability[0x8];
7568 u8 fec_mode_capability[0x18];
7570 u8 retransmission_support_admin[0x8];
7571 u8 fec_mode_support_admin[0x18];
7573 u8 retransmission_request_admin[0x8];
7574 u8 fec_mode_request_admin[0x18];
7576 u8 reserved_at_c0[0x80];
7579 struct mlx5_ifc_plib_reg_bits {
7580 u8 reserved_at_0[0x8];
7582 u8 reserved_at_10[0x8];
7585 u8 reserved_at_20[0x60];
7588 struct mlx5_ifc_plbf_reg_bits {
7589 u8 reserved_at_0[0x8];
7591 u8 reserved_at_10[0xd];
7594 u8 reserved_at_20[0x20];
7597 struct mlx5_ifc_pipg_reg_bits {
7598 u8 reserved_at_0[0x8];
7600 u8 reserved_at_10[0x10];
7603 u8 reserved_at_21[0x19];
7605 u8 reserved_at_3e[0x2];
7608 struct mlx5_ifc_pifr_reg_bits {
7609 u8 reserved_at_0[0x8];
7611 u8 reserved_at_10[0x10];
7613 u8 reserved_at_20[0xe0];
7615 u8 port_filter[8][0x20];
7617 u8 port_filter_update_en[8][0x20];
7620 struct mlx5_ifc_pfcc_reg_bits {
7621 u8 reserved_at_0[0x8];
7623 u8 reserved_at_10[0x10];
7626 u8 reserved_at_24[0x4];
7627 u8 prio_mask_tx[0x8];
7628 u8 reserved_at_30[0x8];
7629 u8 prio_mask_rx[0x8];
7633 u8 reserved_at_42[0x6];
7635 u8 reserved_at_50[0x10];
7639 u8 reserved_at_62[0x6];
7641 u8 reserved_at_70[0x10];
7643 u8 reserved_at_80[0x80];
7646 struct mlx5_ifc_pelc_reg_bits {
7648 u8 reserved_at_4[0x4];
7650 u8 reserved_at_10[0x10];
7653 u8 op_capability[0x8];
7659 u8 capability[0x40];
7665 u8 reserved_at_140[0x80];
7668 struct mlx5_ifc_peir_reg_bits {
7669 u8 reserved_at_0[0x8];
7671 u8 reserved_at_10[0x10];
7673 u8 reserved_at_20[0xc];
7674 u8 error_count[0x4];
7675 u8 reserved_at_30[0x10];
7677 u8 reserved_at_40[0xc];
7679 u8 reserved_at_50[0x8];
7683 struct mlx5_ifc_pcam_enhanced_features_bits {
7684 u8 reserved_at_0[0x7e];
7686 u8 ppcnt_discard_group[0x1];
7687 u8 ppcnt_statistical_group[0x1];
7690 struct mlx5_ifc_pcam_reg_bits {
7691 u8 reserved_at_0[0x8];
7692 u8 feature_group[0x8];
7693 u8 reserved_at_10[0x8];
7694 u8 access_reg_group[0x8];
7696 u8 reserved_at_20[0x20];
7699 u8 reserved_at_0[0x80];
7700 } port_access_reg_cap_mask;
7702 u8 reserved_at_c0[0x80];
7705 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
7706 u8 reserved_at_0[0x80];
7709 u8 reserved_at_1c0[0xc0];
7712 struct mlx5_ifc_mcam_enhanced_features_bits {
7713 u8 reserved_at_0[0x7f];
7715 u8 pcie_performance_group[0x1];
7718 struct mlx5_ifc_mcam_reg_bits {
7719 u8 reserved_at_0[0x8];
7720 u8 feature_group[0x8];
7721 u8 reserved_at_10[0x8];
7722 u8 access_reg_group[0x8];
7724 u8 reserved_at_20[0x20];
7727 u8 reserved_at_0[0x80];
7728 } mng_access_reg_cap_mask;
7730 u8 reserved_at_c0[0x80];
7733 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
7734 u8 reserved_at_0[0x80];
7735 } mng_feature_cap_mask;
7737 u8 reserved_at_1c0[0x80];
7740 struct mlx5_ifc_pcap_reg_bits {
7741 u8 reserved_at_0[0x8];
7743 u8 reserved_at_10[0x10];
7745 u8 port_capability_mask[4][0x20];
7748 struct mlx5_ifc_paos_reg_bits {
7751 u8 reserved_at_10[0x4];
7752 u8 admin_status[0x4];
7753 u8 reserved_at_18[0x4];
7754 u8 oper_status[0x4];
7758 u8 reserved_at_22[0x1c];
7761 u8 reserved_at_40[0x40];
7764 struct mlx5_ifc_pamp_reg_bits {
7765 u8 reserved_at_0[0x8];
7766 u8 opamp_group[0x8];
7767 u8 reserved_at_10[0xc];
7768 u8 opamp_group_type[0x4];
7770 u8 start_index[0x10];
7771 u8 reserved_at_30[0x4];
7772 u8 num_of_indices[0xc];
7774 u8 index_data[18][0x10];
7777 struct mlx5_ifc_pcmr_reg_bits {
7778 u8 reserved_at_0[0x8];
7780 u8 reserved_at_10[0x2e];
7782 u8 reserved_at_3f[0x1f];
7784 u8 reserved_at_5f[0x1];
7787 struct mlx5_ifc_lane_2_module_mapping_bits {
7788 u8 reserved_at_0[0x6];
7790 u8 reserved_at_8[0x6];
7792 u8 reserved_at_10[0x8];
7796 struct mlx5_ifc_bufferx_reg_bits {
7797 u8 reserved_at_0[0x6];
7800 u8 reserved_at_8[0xc];
7803 u8 xoff_threshold[0x10];
7804 u8 xon_threshold[0x10];
7807 struct mlx5_ifc_set_node_in_bits {
7808 u8 node_description[64][0x8];
7811 struct mlx5_ifc_register_power_settings_bits {
7812 u8 reserved_at_0[0x18];
7813 u8 power_settings_level[0x8];
7815 u8 reserved_at_20[0x60];
7818 struct mlx5_ifc_register_host_endianness_bits {
7820 u8 reserved_at_1[0x1f];
7822 u8 reserved_at_20[0x60];
7825 struct mlx5_ifc_umr_pointer_desc_argument_bits {
7826 u8 reserved_at_0[0x20];
7830 u8 addressh_63_32[0x20];
7832 u8 addressl_31_0[0x20];
7835 struct mlx5_ifc_ud_adrs_vector_bits {
7839 u8 reserved_at_41[0x7];
7840 u8 destination_qp_dct[0x18];
7842 u8 static_rate[0x4];
7843 u8 sl_eth_prio[0x4];
7846 u8 rlid_udp_sport[0x10];
7848 u8 reserved_at_80[0x20];
7850 u8 rmac_47_16[0x20];
7856 u8 reserved_at_e0[0x1];
7858 u8 reserved_at_e2[0x2];
7859 u8 src_addr_index[0x8];
7860 u8 flow_label[0x14];
7862 u8 rgid_rip[16][0x8];
7865 struct mlx5_ifc_pages_req_event_bits {
7866 u8 reserved_at_0[0x10];
7867 u8 function_id[0x10];
7871 u8 reserved_at_40[0xa0];
7874 struct mlx5_ifc_eqe_bits {
7875 u8 reserved_at_0[0x8];
7877 u8 reserved_at_10[0x8];
7878 u8 event_sub_type[0x8];
7880 u8 reserved_at_20[0xe0];
7882 union mlx5_ifc_event_auto_bits event_data;
7884 u8 reserved_at_1e0[0x10];
7886 u8 reserved_at_1f8[0x7];
7891 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
7894 struct mlx5_ifc_cmd_queue_entry_bits {
7896 u8 reserved_at_8[0x18];
7898 u8 input_length[0x20];
7900 u8 input_mailbox_pointer_63_32[0x20];
7902 u8 input_mailbox_pointer_31_9[0x17];
7903 u8 reserved_at_77[0x9];
7905 u8 command_input_inline_data[16][0x8];
7907 u8 command_output_inline_data[16][0x8];
7909 u8 output_mailbox_pointer_63_32[0x20];
7911 u8 output_mailbox_pointer_31_9[0x17];
7912 u8 reserved_at_1b7[0x9];
7914 u8 output_length[0x20];
7918 u8 reserved_at_1f0[0x8];
7923 struct mlx5_ifc_cmd_out_bits {
7925 u8 reserved_at_8[0x18];
7929 u8 command_output[0x20];
7932 struct mlx5_ifc_cmd_in_bits {
7934 u8 reserved_at_10[0x10];
7936 u8 reserved_at_20[0x10];
7939 u8 command[0][0x20];
7942 struct mlx5_ifc_cmd_if_box_bits {
7943 u8 mailbox_data[512][0x8];
7945 u8 reserved_at_1000[0x180];
7947 u8 next_pointer_63_32[0x20];
7949 u8 next_pointer_31_10[0x16];
7950 u8 reserved_at_11b6[0xa];
7952 u8 block_number[0x20];
7954 u8 reserved_at_11e0[0x8];
7956 u8 ctrl_signature[0x8];
7960 struct mlx5_ifc_mtt_bits {
7961 u8 ptag_63_32[0x20];
7964 u8 reserved_at_38[0x6];
7969 struct mlx5_ifc_query_wol_rol_out_bits {
7971 u8 reserved_at_8[0x18];
7975 u8 reserved_at_40[0x10];
7979 u8 reserved_at_60[0x20];
7982 struct mlx5_ifc_query_wol_rol_in_bits {
7984 u8 reserved_at_10[0x10];
7986 u8 reserved_at_20[0x10];
7989 u8 reserved_at_40[0x40];
7992 struct mlx5_ifc_set_wol_rol_out_bits {
7994 u8 reserved_at_8[0x18];
7998 u8 reserved_at_40[0x40];
8001 struct mlx5_ifc_set_wol_rol_in_bits {
8003 u8 reserved_at_10[0x10];
8005 u8 reserved_at_20[0x10];
8008 u8 rol_mode_valid[0x1];
8009 u8 wol_mode_valid[0x1];
8010 u8 reserved_at_42[0xe];
8014 u8 reserved_at_60[0x20];
8018 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
8019 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
8020 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
8024 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
8025 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
8026 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
8030 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
8031 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
8032 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
8033 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
8034 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
8035 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
8036 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
8037 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
8038 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
8039 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
8040 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
8043 struct mlx5_ifc_initial_seg_bits {
8044 u8 fw_rev_minor[0x10];
8045 u8 fw_rev_major[0x10];
8047 u8 cmd_interface_rev[0x10];
8048 u8 fw_rev_subminor[0x10];
8050 u8 reserved_at_40[0x40];
8052 u8 cmdq_phy_addr_63_32[0x20];
8054 u8 cmdq_phy_addr_31_12[0x14];
8055 u8 reserved_at_b4[0x2];
8056 u8 nic_interface[0x2];
8057 u8 log_cmdq_size[0x4];
8058 u8 log_cmdq_stride[0x4];
8060 u8 command_doorbell_vector[0x20];
8062 u8 reserved_at_e0[0xf00];
8064 u8 initializing[0x1];
8065 u8 reserved_at_fe1[0x4];
8066 u8 nic_interface_supported[0x3];
8067 u8 reserved_at_fe8[0x18];
8069 struct mlx5_ifc_health_buffer_bits health_buffer;
8071 u8 no_dram_nic_offset[0x20];
8073 u8 reserved_at_1220[0x6e40];
8075 u8 reserved_at_8060[0x1f];
8078 u8 health_syndrome[0x8];
8079 u8 health_counter[0x18];
8081 u8 reserved_at_80a0[0x17fc0];
8084 struct mlx5_ifc_mtpps_reg_bits {
8085 u8 reserved_at_0[0xc];
8086 u8 cap_number_of_pps_pins[0x4];
8087 u8 reserved_at_10[0x4];
8088 u8 cap_max_num_of_pps_in_pins[0x4];
8089 u8 reserved_at_18[0x4];
8090 u8 cap_max_num_of_pps_out_pins[0x4];
8092 u8 reserved_at_20[0x24];
8093 u8 cap_pin_3_mode[0x4];
8094 u8 reserved_at_48[0x4];
8095 u8 cap_pin_2_mode[0x4];
8096 u8 reserved_at_50[0x4];
8097 u8 cap_pin_1_mode[0x4];
8098 u8 reserved_at_58[0x4];
8099 u8 cap_pin_0_mode[0x4];
8101 u8 reserved_at_60[0x4];
8102 u8 cap_pin_7_mode[0x4];
8103 u8 reserved_at_68[0x4];
8104 u8 cap_pin_6_mode[0x4];
8105 u8 reserved_at_70[0x4];
8106 u8 cap_pin_5_mode[0x4];
8107 u8 reserved_at_78[0x4];
8108 u8 cap_pin_4_mode[0x4];
8110 u8 reserved_at_80[0x80];
8113 u8 reserved_at_101[0xb];
8115 u8 reserved_at_110[0x4];
8119 u8 reserved_at_120[0x20];
8121 u8 time_stamp[0x40];
8123 u8 out_pulse_duration[0x10];
8124 u8 out_periodic_adjustment[0x10];
8126 u8 reserved_at_1a0[0x60];
8129 struct mlx5_ifc_mtppse_reg_bits {
8130 u8 reserved_at_0[0x18];
8133 u8 reserved_at_21[0x1b];
8134 u8 event_generation_mode[0x4];
8135 u8 reserved_at_40[0x40];
8138 union mlx5_ifc_ports_control_registers_document_bits {
8139 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8140 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8141 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8142 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8143 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8144 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8145 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8146 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8147 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8148 struct mlx5_ifc_pamp_reg_bits pamp_reg;
8149 struct mlx5_ifc_paos_reg_bits paos_reg;
8150 struct mlx5_ifc_pcap_reg_bits pcap_reg;
8151 struct mlx5_ifc_peir_reg_bits peir_reg;
8152 struct mlx5_ifc_pelc_reg_bits pelc_reg;
8153 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8154 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8155 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8156 struct mlx5_ifc_pifr_reg_bits pifr_reg;
8157 struct mlx5_ifc_pipg_reg_bits pipg_reg;
8158 struct mlx5_ifc_plbf_reg_bits plbf_reg;
8159 struct mlx5_ifc_plib_reg_bits plib_reg;
8160 struct mlx5_ifc_plpc_reg_bits plpc_reg;
8161 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8162 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8163 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8164 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8165 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8166 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8167 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8168 struct mlx5_ifc_ppad_reg_bits ppad_reg;
8169 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8170 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8171 struct mlx5_ifc_pplm_reg_bits pplm_reg;
8172 struct mlx5_ifc_pplr_reg_bits pplr_reg;
8173 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8174 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8175 struct mlx5_ifc_pspa_reg_bits pspa_reg;
8176 struct mlx5_ifc_ptas_reg_bits ptas_reg;
8177 struct mlx5_ifc_ptys_reg_bits ptys_reg;
8178 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8179 struct mlx5_ifc_pude_reg_bits pude_reg;
8180 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8181 struct mlx5_ifc_slrg_reg_bits slrg_reg;
8182 struct mlx5_ifc_sltp_reg_bits sltp_reg;
8183 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8184 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8185 u8 reserved_at_0[0x60e0];
8188 union mlx5_ifc_debug_enhancements_document_bits {
8189 struct mlx5_ifc_health_buffer_bits health_buffer;
8190 u8 reserved_at_0[0x200];
8193 union mlx5_ifc_uplink_pci_interface_document_bits {
8194 struct mlx5_ifc_initial_seg_bits initial_seg;
8195 u8 reserved_at_0[0x20060];
8198 struct mlx5_ifc_set_flow_table_root_out_bits {
8200 u8 reserved_at_8[0x18];
8204 u8 reserved_at_40[0x40];
8207 struct mlx5_ifc_set_flow_table_root_in_bits {
8209 u8 reserved_at_10[0x10];
8211 u8 reserved_at_20[0x10];
8214 u8 other_vport[0x1];
8215 u8 reserved_at_41[0xf];
8216 u8 vport_number[0x10];
8218 u8 reserved_at_60[0x20];
8221 u8 reserved_at_88[0x18];
8223 u8 reserved_at_a0[0x8];
8226 u8 reserved_at_c0[0x8];
8227 u8 underlay_qpn[0x18];
8228 u8 reserved_at_e0[0x120];
8232 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
8233 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8236 struct mlx5_ifc_modify_flow_table_out_bits {
8238 u8 reserved_at_8[0x18];
8242 u8 reserved_at_40[0x40];
8245 struct mlx5_ifc_modify_flow_table_in_bits {
8247 u8 reserved_at_10[0x10];
8249 u8 reserved_at_20[0x10];
8252 u8 other_vport[0x1];
8253 u8 reserved_at_41[0xf];
8254 u8 vport_number[0x10];
8256 u8 reserved_at_60[0x10];
8257 u8 modify_field_select[0x10];
8260 u8 reserved_at_88[0x18];
8262 u8 reserved_at_a0[0x8];
8265 u8 reserved_at_c0[0x4];
8266 u8 table_miss_mode[0x4];
8267 u8 reserved_at_c8[0x18];
8269 u8 reserved_at_e0[0x8];
8270 u8 table_miss_id[0x18];
8272 u8 reserved_at_100[0x8];
8273 u8 lag_master_next_table_id[0x18];
8275 u8 reserved_at_120[0x80];
8278 struct mlx5_ifc_ets_tcn_config_reg_bits {
8282 u8 reserved_at_3[0x9];
8284 u8 reserved_at_10[0x9];
8285 u8 bw_allocation[0x7];
8287 u8 reserved_at_20[0xc];
8288 u8 max_bw_units[0x4];
8289 u8 reserved_at_30[0x8];
8290 u8 max_bw_value[0x8];
8293 struct mlx5_ifc_ets_global_config_reg_bits {
8294 u8 reserved_at_0[0x2];
8296 u8 reserved_at_3[0x1d];
8298 u8 reserved_at_20[0xc];
8299 u8 max_bw_units[0x4];
8300 u8 reserved_at_30[0x8];
8301 u8 max_bw_value[0x8];
8304 struct mlx5_ifc_qetc_reg_bits {
8305 u8 reserved_at_0[0x8];
8306 u8 port_number[0x8];
8307 u8 reserved_at_10[0x30];
8309 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
8310 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8313 struct mlx5_ifc_qtct_reg_bits {
8314 u8 reserved_at_0[0x8];
8315 u8 port_number[0x8];
8316 u8 reserved_at_10[0xd];
8319 u8 reserved_at_20[0x1d];
8323 struct mlx5_ifc_mcia_reg_bits {
8325 u8 reserved_at_1[0x7];
8327 u8 reserved_at_10[0x8];
8330 u8 i2c_device_address[0x8];
8331 u8 page_number[0x8];
8332 u8 device_address[0x10];
8334 u8 reserved_at_40[0x10];
8337 u8 reserved_at_60[0x20];
8353 struct mlx5_ifc_dcbx_param_bits {
8354 u8 dcbx_cee_cap[0x1];
8355 u8 dcbx_ieee_cap[0x1];
8356 u8 dcbx_standby_cap[0x1];
8357 u8 reserved_at_0[0x5];
8358 u8 port_number[0x8];
8359 u8 reserved_at_10[0xa];
8360 u8 max_application_table_size[6];
8361 u8 reserved_at_20[0x15];
8362 u8 version_oper[0x3];
8363 u8 reserved_at_38[5];
8364 u8 version_admin[0x3];
8365 u8 willing_admin[0x1];
8366 u8 reserved_at_41[0x3];
8367 u8 pfc_cap_oper[0x4];
8368 u8 reserved_at_48[0x4];
8369 u8 pfc_cap_admin[0x4];
8370 u8 reserved_at_50[0x4];
8371 u8 num_of_tc_oper[0x4];
8372 u8 reserved_at_58[0x4];
8373 u8 num_of_tc_admin[0x4];
8374 u8 remote_willing[0x1];
8375 u8 reserved_at_61[3];
8376 u8 remote_pfc_cap[4];
8377 u8 reserved_at_68[0x14];
8378 u8 remote_num_of_tc[0x4];
8379 u8 reserved_at_80[0x18];
8381 u8 reserved_at_a0[0x160];
8384 struct mlx5_ifc_lagc_bits {
8385 u8 reserved_at_0[0x1d];
8388 u8 reserved_at_20[0x14];
8389 u8 tx_remap_affinity_2[0x4];
8390 u8 reserved_at_38[0x4];
8391 u8 tx_remap_affinity_1[0x4];
8394 struct mlx5_ifc_create_lag_out_bits {
8396 u8 reserved_at_8[0x18];
8400 u8 reserved_at_40[0x40];
8403 struct mlx5_ifc_create_lag_in_bits {
8405 u8 reserved_at_10[0x10];
8407 u8 reserved_at_20[0x10];
8410 struct mlx5_ifc_lagc_bits ctx;
8413 struct mlx5_ifc_modify_lag_out_bits {
8415 u8 reserved_at_8[0x18];
8419 u8 reserved_at_40[0x40];
8422 struct mlx5_ifc_modify_lag_in_bits {
8424 u8 reserved_at_10[0x10];
8426 u8 reserved_at_20[0x10];
8429 u8 reserved_at_40[0x20];
8430 u8 field_select[0x20];
8432 struct mlx5_ifc_lagc_bits ctx;
8435 struct mlx5_ifc_query_lag_out_bits {
8437 u8 reserved_at_8[0x18];
8441 u8 reserved_at_40[0x40];
8443 struct mlx5_ifc_lagc_bits ctx;
8446 struct mlx5_ifc_query_lag_in_bits {
8448 u8 reserved_at_10[0x10];
8450 u8 reserved_at_20[0x10];
8453 u8 reserved_at_40[0x40];
8456 struct mlx5_ifc_destroy_lag_out_bits {
8458 u8 reserved_at_8[0x18];
8462 u8 reserved_at_40[0x40];
8465 struct mlx5_ifc_destroy_lag_in_bits {
8467 u8 reserved_at_10[0x10];
8469 u8 reserved_at_20[0x10];
8472 u8 reserved_at_40[0x40];
8475 struct mlx5_ifc_create_vport_lag_out_bits {
8477 u8 reserved_at_8[0x18];
8481 u8 reserved_at_40[0x40];
8484 struct mlx5_ifc_create_vport_lag_in_bits {
8486 u8 reserved_at_10[0x10];
8488 u8 reserved_at_20[0x10];
8491 u8 reserved_at_40[0x40];
8494 struct mlx5_ifc_destroy_vport_lag_out_bits {
8496 u8 reserved_at_8[0x18];
8500 u8 reserved_at_40[0x40];
8503 struct mlx5_ifc_destroy_vport_lag_in_bits {
8505 u8 reserved_at_10[0x10];
8507 u8 reserved_at_20[0x10];
8510 u8 reserved_at_40[0x40];
8513 #endif /* MLX5_IFC_H */