2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
77 MLX5_CMD_OP_INIT_HCA = 0x102,
78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
79 MLX5_CMD_OP_ENABLE_HCA = 0x104,
80 MLX5_CMD_OP_DISABLE_HCA = 0x105,
81 MLX5_CMD_OP_QUERY_PAGES = 0x107,
82 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
83 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
84 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
85 MLX5_CMD_OP_SET_ISSI = 0x10b,
86 MLX5_CMD_OP_CREATE_MKEY = 0x200,
87 MLX5_CMD_OP_QUERY_MKEY = 0x201,
88 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
89 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
90 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
91 MLX5_CMD_OP_CREATE_EQ = 0x301,
92 MLX5_CMD_OP_DESTROY_EQ = 0x302,
93 MLX5_CMD_OP_QUERY_EQ = 0x303,
94 MLX5_CMD_OP_GEN_EQE = 0x304,
95 MLX5_CMD_OP_CREATE_CQ = 0x400,
96 MLX5_CMD_OP_DESTROY_CQ = 0x401,
97 MLX5_CMD_OP_QUERY_CQ = 0x402,
98 MLX5_CMD_OP_MODIFY_CQ = 0x403,
99 MLX5_CMD_OP_CREATE_QP = 0x500,
100 MLX5_CMD_OP_DESTROY_QP = 0x501,
101 MLX5_CMD_OP_RST2INIT_QP = 0x502,
102 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
103 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
104 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
105 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
106 MLX5_CMD_OP_2ERR_QP = 0x507,
107 MLX5_CMD_OP_2RST_QP = 0x50a,
108 MLX5_CMD_OP_QUERY_QP = 0x50b,
109 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
110 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
111 MLX5_CMD_OP_CREATE_PSV = 0x600,
112 MLX5_CMD_OP_DESTROY_PSV = 0x601,
113 MLX5_CMD_OP_CREATE_SRQ = 0x700,
114 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
115 MLX5_CMD_OP_QUERY_SRQ = 0x702,
116 MLX5_CMD_OP_ARM_RQ = 0x703,
117 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
118 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
119 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
120 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
121 MLX5_CMD_OP_CREATE_DCT = 0x710,
122 MLX5_CMD_OP_DESTROY_DCT = 0x711,
123 MLX5_CMD_OP_DRAIN_DCT = 0x712,
124 MLX5_CMD_OP_QUERY_DCT = 0x713,
125 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
126 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
127 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
128 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
129 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
130 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
131 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
132 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
133 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
134 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
135 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
136 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
137 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
138 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
139 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
140 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
141 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
142 MLX5_CMD_OP_ALLOC_PD = 0x800,
143 MLX5_CMD_OP_DEALLOC_PD = 0x801,
144 MLX5_CMD_OP_ALLOC_UAR = 0x802,
145 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
146 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
147 MLX5_CMD_OP_ACCESS_REG = 0x805,
148 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
149 MLX5_CMD_OP_DETTACH_FROM_MCG = 0x807,
150 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
151 MLX5_CMD_OP_MAD_IFC = 0x50d,
152 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
153 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
154 MLX5_CMD_OP_NOP = 0x80d,
155 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
156 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
157 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
158 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
159 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
160 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
161 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
162 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
163 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
164 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
165 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
166 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
167 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
168 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
169 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
170 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
171 MLX5_CMD_OP_CREATE_TIR = 0x900,
172 MLX5_CMD_OP_MODIFY_TIR = 0x901,
173 MLX5_CMD_OP_DESTROY_TIR = 0x902,
174 MLX5_CMD_OP_QUERY_TIR = 0x903,
175 MLX5_CMD_OP_CREATE_SQ = 0x904,
176 MLX5_CMD_OP_MODIFY_SQ = 0x905,
177 MLX5_CMD_OP_DESTROY_SQ = 0x906,
178 MLX5_CMD_OP_QUERY_SQ = 0x907,
179 MLX5_CMD_OP_CREATE_RQ = 0x908,
180 MLX5_CMD_OP_MODIFY_RQ = 0x909,
181 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
182 MLX5_CMD_OP_QUERY_RQ = 0x90b,
183 MLX5_CMD_OP_CREATE_RMP = 0x90c,
184 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
185 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
186 MLX5_CMD_OP_QUERY_RMP = 0x90f,
187 MLX5_CMD_OP_CREATE_TIS = 0x912,
188 MLX5_CMD_OP_MODIFY_TIS = 0x913,
189 MLX5_CMD_OP_DESTROY_TIS = 0x914,
190 MLX5_CMD_OP_QUERY_TIS = 0x915,
191 MLX5_CMD_OP_CREATE_RQT = 0x916,
192 MLX5_CMD_OP_MODIFY_RQT = 0x917,
193 MLX5_CMD_OP_DESTROY_RQT = 0x918,
194 MLX5_CMD_OP_QUERY_RQT = 0x919,
195 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
196 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
197 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
198 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
199 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
200 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
201 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
202 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
203 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
204 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
205 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
206 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
207 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
208 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
212 struct mlx5_ifc_flow_table_fields_supported_bits {
215 u8 outer_ether_type[0x1];
216 u8 reserved_at_3[0x1];
217 u8 outer_first_prio[0x1];
218 u8 outer_first_cfi[0x1];
219 u8 outer_first_vid[0x1];
220 u8 reserved_at_7[0x1];
221 u8 outer_second_prio[0x1];
222 u8 outer_second_cfi[0x1];
223 u8 outer_second_vid[0x1];
224 u8 reserved_at_b[0x1];
228 u8 outer_ip_protocol[0x1];
229 u8 outer_ip_ecn[0x1];
230 u8 outer_ip_dscp[0x1];
231 u8 outer_udp_sport[0x1];
232 u8 outer_udp_dport[0x1];
233 u8 outer_tcp_sport[0x1];
234 u8 outer_tcp_dport[0x1];
235 u8 outer_tcp_flags[0x1];
236 u8 outer_gre_protocol[0x1];
237 u8 outer_gre_key[0x1];
238 u8 outer_vxlan_vni[0x1];
239 u8 reserved_at_1a[0x5];
240 u8 source_eswitch_port[0x1];
244 u8 inner_ether_type[0x1];
245 u8 reserved_at_23[0x1];
246 u8 inner_first_prio[0x1];
247 u8 inner_first_cfi[0x1];
248 u8 inner_first_vid[0x1];
249 u8 reserved_at_27[0x1];
250 u8 inner_second_prio[0x1];
251 u8 inner_second_cfi[0x1];
252 u8 inner_second_vid[0x1];
253 u8 reserved_at_2b[0x1];
257 u8 inner_ip_protocol[0x1];
258 u8 inner_ip_ecn[0x1];
259 u8 inner_ip_dscp[0x1];
260 u8 inner_udp_sport[0x1];
261 u8 inner_udp_dport[0x1];
262 u8 inner_tcp_sport[0x1];
263 u8 inner_tcp_dport[0x1];
264 u8 inner_tcp_flags[0x1];
265 u8 reserved_at_37[0x9];
267 u8 reserved_at_40[0x40];
270 struct mlx5_ifc_flow_table_prop_layout_bits {
272 u8 reserved_at_1[0x1];
273 u8 flow_counter[0x1];
274 u8 flow_modify_en[0x1];
276 u8 identified_miss_table_mode[0x1];
277 u8 flow_table_modify[0x1];
278 u8 reserved_at_7[0x19];
280 u8 reserved_at_20[0x2];
281 u8 log_max_ft_size[0x6];
282 u8 reserved_at_28[0x10];
283 u8 max_ft_level[0x8];
285 u8 reserved_at_40[0x20];
287 u8 reserved_at_60[0x18];
288 u8 log_max_ft_num[0x8];
290 u8 reserved_at_80[0x18];
291 u8 log_max_destination[0x8];
293 u8 reserved_at_a0[0x18];
294 u8 log_max_flow[0x8];
296 u8 reserved_at_c0[0x40];
298 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
300 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
303 struct mlx5_ifc_odp_per_transport_service_cap_bits {
308 u8 reserved_at_4[0x1];
310 u8 reserved_at_6[0x1a];
313 struct mlx5_ifc_ipv4_layout_bits {
314 u8 reserved_at_0[0x60];
319 struct mlx5_ifc_ipv6_layout_bits {
323 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
324 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
325 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
326 u8 reserved_at_0[0x80];
329 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
346 u8 reserved_at_91[0x1];
348 u8 reserved_at_93[0x4];
354 u8 reserved_at_c0[0x20];
359 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
361 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
364 struct mlx5_ifc_fte_match_set_misc_bits {
365 u8 reserved_at_0[0x20];
367 u8 reserved_at_20[0x10];
368 u8 source_port[0x10];
370 u8 outer_second_prio[0x3];
371 u8 outer_second_cfi[0x1];
372 u8 outer_second_vid[0xc];
373 u8 inner_second_prio[0x3];
374 u8 inner_second_cfi[0x1];
375 u8 inner_second_vid[0xc];
377 u8 outer_second_vlan_tag[0x1];
378 u8 inner_second_vlan_tag[0x1];
379 u8 reserved_at_62[0xe];
380 u8 gre_protocol[0x10];
386 u8 reserved_at_b8[0x8];
388 u8 reserved_at_c0[0x20];
390 u8 reserved_at_e0[0xc];
391 u8 outer_ipv6_flow_label[0x14];
393 u8 reserved_at_100[0xc];
394 u8 inner_ipv6_flow_label[0x14];
396 u8 reserved_at_120[0xe0];
399 struct mlx5_ifc_cmd_pas_bits {
403 u8 reserved_at_34[0xc];
406 struct mlx5_ifc_uint64_bits {
413 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
414 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
415 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
416 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
417 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
418 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
419 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
420 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
421 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
422 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
425 struct mlx5_ifc_ads_bits {
428 u8 reserved_at_2[0xe];
431 u8 reserved_at_20[0x8];
437 u8 reserved_at_45[0x3];
438 u8 src_addr_index[0x8];
439 u8 reserved_at_50[0x4];
443 u8 reserved_at_60[0x4];
447 u8 rgid_rip[16][0x8];
449 u8 reserved_at_100[0x4];
452 u8 reserved_at_106[0x1];
467 struct mlx5_ifc_flow_table_nic_cap_bits {
468 u8 nic_rx_multi_path_tirs[0x1];
469 u8 reserved_at_1[0x1ff];
471 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
473 u8 reserved_at_400[0x200];
475 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
477 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
479 u8 reserved_at_a00[0x200];
481 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
483 u8 reserved_at_e00[0x7200];
486 struct mlx5_ifc_flow_table_eswitch_cap_bits {
487 u8 reserved_at_0[0x200];
489 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
491 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
493 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
495 u8 reserved_at_800[0x7800];
498 struct mlx5_ifc_e_switch_cap_bits {
499 u8 vport_svlan_strip[0x1];
500 u8 vport_cvlan_strip[0x1];
501 u8 vport_svlan_insert[0x1];
502 u8 vport_cvlan_insert_if_not_exist[0x1];
503 u8 vport_cvlan_insert_overwrite[0x1];
504 u8 reserved_at_5[0x19];
505 u8 nic_vport_node_guid_modify[0x1];
506 u8 nic_vport_port_guid_modify[0x1];
508 u8 reserved_at_20[0x7e0];
511 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
515 u8 lro_psh_flag[0x1];
516 u8 lro_time_stamp[0x1];
517 u8 reserved_at_5[0x3];
518 u8 self_lb_en_modifiable[0x1];
519 u8 reserved_at_9[0x2];
521 u8 reserved_at_10[0x4];
522 u8 rss_ind_tbl_cap[0x4];
525 u8 reserved_at_1a[0x1];
526 u8 tunnel_lso_const_out_ip_id[0x1];
527 u8 reserved_at_1c[0x2];
528 u8 tunnel_statless_gre[0x1];
529 u8 tunnel_stateless_vxlan[0x1];
531 u8 reserved_at_20[0x20];
533 u8 reserved_at_40[0x10];
534 u8 lro_min_mss_size[0x10];
536 u8 reserved_at_60[0x120];
538 u8 lro_timer_supported_periods[4][0x20];
540 u8 reserved_at_200[0x600];
543 struct mlx5_ifc_roce_cap_bits {
545 u8 reserved_at_1[0x1f];
547 u8 reserved_at_20[0x60];
549 u8 reserved_at_80[0xc];
551 u8 reserved_at_90[0x8];
552 u8 roce_version[0x8];
554 u8 reserved_at_a0[0x10];
555 u8 r_roce_dest_udp_port[0x10];
557 u8 r_roce_max_src_udp_port[0x10];
558 u8 r_roce_min_src_udp_port[0x10];
560 u8 reserved_at_e0[0x10];
561 u8 roce_address_table_size[0x10];
563 u8 reserved_at_100[0x700];
567 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
568 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
569 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
570 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
571 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
572 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
573 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
574 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
575 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
579 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
580 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
581 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
582 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
583 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
584 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
585 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
586 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
587 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
590 struct mlx5_ifc_atomic_caps_bits {
591 u8 reserved_at_0[0x40];
593 u8 atomic_req_8B_endianess_mode[0x2];
594 u8 reserved_at_42[0x4];
595 u8 supported_atomic_req_8B_endianess_mode_1[0x1];
597 u8 reserved_at_47[0x19];
599 u8 reserved_at_60[0x20];
601 u8 reserved_at_80[0x10];
602 u8 atomic_operations[0x10];
604 u8 reserved_at_a0[0x10];
605 u8 atomic_size_qp[0x10];
607 u8 reserved_at_c0[0x10];
608 u8 atomic_size_dc[0x10];
610 u8 reserved_at_e0[0x720];
613 struct mlx5_ifc_odp_cap_bits {
614 u8 reserved_at_0[0x40];
617 u8 reserved_at_41[0x1f];
619 u8 reserved_at_60[0x20];
621 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
623 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
625 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
627 u8 reserved_at_e0[0x720];
630 struct mlx5_ifc_calc_op {
631 u8 reserved_at_0[0x10];
632 u8 reserved_at_10[0x9];
633 u8 op_swap_endianness[0x1];
642 struct mlx5_ifc_vector_calc_cap_bits {
644 u8 reserved_at_1[0x1f];
645 u8 reserved_at_20[0x8];
646 u8 max_vec_count[0x8];
647 u8 reserved_at_30[0xd];
648 u8 max_chunk_size[0x3];
649 struct mlx5_ifc_calc_op calc0;
650 struct mlx5_ifc_calc_op calc1;
651 struct mlx5_ifc_calc_op calc2;
652 struct mlx5_ifc_calc_op calc3;
654 u8 reserved_at_e0[0x720];
658 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
659 MLX5_WQ_TYPE_CYCLIC = 0x1,
660 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
664 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
665 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
669 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
670 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
671 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
672 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
673 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
677 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
678 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
679 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
680 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
681 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
682 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
686 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
687 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
691 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
692 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
693 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
697 MLX5_CAP_PORT_TYPE_IB = 0x0,
698 MLX5_CAP_PORT_TYPE_ETH = 0x1,
701 struct mlx5_ifc_cmd_hca_cap_bits {
702 u8 reserved_at_0[0x80];
704 u8 log_max_srq_sz[0x8];
705 u8 log_max_qp_sz[0x8];
706 u8 reserved_at_90[0xb];
709 u8 reserved_at_a0[0xb];
711 u8 reserved_at_b0[0x10];
713 u8 reserved_at_c0[0x8];
714 u8 log_max_cq_sz[0x8];
715 u8 reserved_at_d0[0xb];
718 u8 log_max_eq_sz[0x8];
719 u8 reserved_at_e8[0x2];
720 u8 log_max_mkey[0x6];
721 u8 reserved_at_f0[0xc];
724 u8 max_indirection[0x8];
725 u8 reserved_at_108[0x1];
726 u8 log_max_mrw_sz[0x7];
727 u8 reserved_at_110[0x2];
728 u8 log_max_bsf_list_size[0x6];
729 u8 reserved_at_118[0x2];
730 u8 log_max_klm_list_size[0x6];
732 u8 reserved_at_120[0xa];
733 u8 log_max_ra_req_dc[0x6];
734 u8 reserved_at_130[0xa];
735 u8 log_max_ra_res_dc[0x6];
737 u8 reserved_at_140[0xa];
738 u8 log_max_ra_req_qp[0x6];
739 u8 reserved_at_150[0xa];
740 u8 log_max_ra_res_qp[0x6];
743 u8 cc_query_allowed[0x1];
744 u8 cc_modify_allowed[0x1];
745 u8 reserved_at_163[0xd];
746 u8 gid_table_size[0x10];
748 u8 out_of_seq_cnt[0x1];
749 u8 vport_counters[0x1];
750 u8 reserved_at_182[0x4];
752 u8 pkey_table_size[0x10];
754 u8 vport_group_manager[0x1];
755 u8 vhca_group_manager[0x1];
758 u8 reserved_at_1a4[0x1];
760 u8 nic_flow_table[0x1];
761 u8 eswitch_flow_table[0x1];
762 u8 early_vf_enable[0x1];
763 u8 reserved_at_1a9[0x2];
764 u8 local_ca_ack_delay[0x5];
765 u8 reserved_at_1af[0x2];
767 u8 reserved_at_1b2[0x1];
768 u8 disable_link_up[0x1];
773 u8 reserved_at_1c0[0x3];
775 u8 reserved_at_1c8[0x4];
777 u8 reserved_at_1d0[0x6];
780 u8 reserved_at_1d8[0x1];
789 u8 stat_rate_support[0x10];
790 u8 reserved_at_1f0[0xc];
793 u8 compact_address_vector[0x1];
795 u8 reserved_at_201[0x2];
796 u8 ipoib_basic_offloads[0x1];
797 u8 reserved_at_205[0xa];
798 u8 drain_sigerr[0x1];
799 u8 cmdif_checksum[0x2];
801 u8 reserved_at_213[0x1];
802 u8 wq_signature[0x1];
803 u8 sctr_data_cqe[0x1];
804 u8 reserved_at_216[0x1];
809 u8 reserved_at_21b[0x1];
810 u8 eth_net_offloads[0x1];
813 u8 reserved_at_21f[0x1];
817 u8 cq_moderation[0x1];
818 u8 reserved_at_223[0x3];
822 u8 reserved_at_229[0x1];
823 u8 scqe_break_moderation[0x1];
824 u8 cq_period_start_from_cqe[0x1];
826 u8 reserved_at_22d[0x1];
829 u8 umr_ptr_rlky[0x1];
831 u8 reserved_at_232[0x4];
834 u8 set_deth_sqpn[0x1];
835 u8 reserved_at_239[0x3];
841 u8 reserved_at_240[0xa];
843 u8 reserved_at_250[0x8];
847 u8 reserved_at_261[0x1];
848 u8 pad_tx_eth_packet[0x1];
849 u8 reserved_at_263[0x8];
850 u8 log_bf_reg_size[0x5];
851 u8 reserved_at_270[0x10];
853 u8 reserved_at_280[0x10];
854 u8 max_wqe_sz_sq[0x10];
856 u8 reserved_at_2a0[0x10];
857 u8 max_wqe_sz_rq[0x10];
859 u8 reserved_at_2c0[0x10];
860 u8 max_wqe_sz_sq_dc[0x10];
862 u8 reserved_at_2e0[0x7];
865 u8 reserved_at_300[0x18];
868 u8 reserved_at_320[0x3];
869 u8 log_max_transport_domain[0x5];
870 u8 reserved_at_328[0x3];
872 u8 reserved_at_330[0xb];
873 u8 log_max_xrcd[0x5];
875 u8 reserved_at_340[0x20];
877 u8 reserved_at_360[0x3];
879 u8 reserved_at_368[0x3];
881 u8 reserved_at_370[0x3];
883 u8 reserved_at_378[0x3];
886 u8 basic_cyclic_rcv_wqe[0x1];
887 u8 reserved_at_381[0x2];
889 u8 reserved_at_388[0x3];
891 u8 reserved_at_390[0x3];
892 u8 log_max_rqt_size[0x5];
893 u8 reserved_at_398[0x3];
894 u8 log_max_tis_per_sq[0x5];
896 u8 reserved_at_3a0[0x3];
897 u8 log_max_stride_sz_rq[0x5];
898 u8 reserved_at_3a8[0x3];
899 u8 log_min_stride_sz_rq[0x5];
900 u8 reserved_at_3b0[0x3];
901 u8 log_max_stride_sz_sq[0x5];
902 u8 reserved_at_3b8[0x3];
903 u8 log_min_stride_sz_sq[0x5];
905 u8 reserved_at_3c0[0x1b];
906 u8 log_max_wq_sz[0x5];
908 u8 nic_vport_change_event[0x1];
909 u8 reserved_at_3e1[0xa];
910 u8 log_max_vlan_list[0x5];
911 u8 reserved_at_3f0[0x3];
912 u8 log_max_current_mc_list[0x5];
913 u8 reserved_at_3f8[0x3];
914 u8 log_max_current_uc_list[0x5];
916 u8 reserved_at_400[0x80];
918 u8 reserved_at_480[0x3];
919 u8 log_max_l2_table[0x5];
920 u8 reserved_at_488[0x8];
921 u8 log_uar_page_sz[0x10];
923 u8 reserved_at_4a0[0x20];
924 u8 device_frequency_mhz[0x20];
925 u8 device_frequency_khz[0x20];
927 u8 reserved_at_500[0x80];
929 u8 reserved_at_580[0x3f];
930 u8 cqe_compression[0x1];
932 u8 cqe_compression_timeout[0x10];
933 u8 cqe_compression_max_num[0x10];
935 u8 reserved_at_5e0[0x220];
938 enum mlx5_flow_destination_type {
939 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
940 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
941 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
943 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
946 struct mlx5_ifc_dest_format_struct_bits {
947 u8 destination_type[0x8];
948 u8 destination_id[0x18];
950 u8 reserved_at_20[0x20];
953 struct mlx5_ifc_flow_counter_list_bits {
954 u8 reserved_at_0[0x10];
955 u8 flow_counter_id[0x10];
957 u8 reserved_at_20[0x20];
960 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
961 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
962 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
963 u8 reserved_at_0[0x40];
966 struct mlx5_ifc_fte_match_param_bits {
967 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
969 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
971 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
973 u8 reserved_at_600[0xa00];
977 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
978 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
979 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
980 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
981 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
984 struct mlx5_ifc_rx_hash_field_select_bits {
985 u8 l3_prot_type[0x1];
986 u8 l4_prot_type[0x1];
987 u8 selected_fields[0x1e];
991 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
992 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
996 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
997 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1000 struct mlx5_ifc_wq_bits {
1002 u8 wq_signature[0x1];
1003 u8 end_padding_mode[0x2];
1005 u8 reserved_at_8[0x18];
1007 u8 hds_skip_first_sge[0x1];
1008 u8 log2_hds_buf_size[0x3];
1009 u8 reserved_at_24[0x7];
1010 u8 page_offset[0x5];
1013 u8 reserved_at_40[0x8];
1016 u8 reserved_at_60[0x8];
1021 u8 hw_counter[0x20];
1023 u8 sw_counter[0x20];
1025 u8 reserved_at_100[0xc];
1026 u8 log_wq_stride[0x4];
1027 u8 reserved_at_110[0x3];
1028 u8 log_wq_pg_sz[0x5];
1029 u8 reserved_at_118[0x3];
1032 u8 reserved_at_120[0x15];
1033 u8 log_wqe_num_of_strides[0x3];
1034 u8 two_byte_shift_en[0x1];
1035 u8 reserved_at_139[0x4];
1036 u8 log_wqe_stride_size[0x3];
1038 u8 reserved_at_140[0x4c0];
1040 struct mlx5_ifc_cmd_pas_bits pas[0];
1043 struct mlx5_ifc_rq_num_bits {
1044 u8 reserved_at_0[0x8];
1048 struct mlx5_ifc_mac_address_layout_bits {
1049 u8 reserved_at_0[0x10];
1050 u8 mac_addr_47_32[0x10];
1052 u8 mac_addr_31_0[0x20];
1055 struct mlx5_ifc_vlan_layout_bits {
1056 u8 reserved_at_0[0x14];
1059 u8 reserved_at_20[0x20];
1062 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1063 u8 reserved_at_0[0xa0];
1065 u8 min_time_between_cnps[0x20];
1067 u8 reserved_at_c0[0x12];
1069 u8 reserved_at_d8[0x5];
1070 u8 cnp_802p_prio[0x3];
1072 u8 reserved_at_e0[0x720];
1075 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1076 u8 reserved_at_0[0x60];
1078 u8 reserved_at_60[0x4];
1079 u8 clamp_tgt_rate[0x1];
1080 u8 reserved_at_65[0x3];
1081 u8 clamp_tgt_rate_after_time_inc[0x1];
1082 u8 reserved_at_69[0x17];
1084 u8 reserved_at_80[0x20];
1086 u8 rpg_time_reset[0x20];
1088 u8 rpg_byte_reset[0x20];
1090 u8 rpg_threshold[0x20];
1092 u8 rpg_max_rate[0x20];
1094 u8 rpg_ai_rate[0x20];
1096 u8 rpg_hai_rate[0x20];
1100 u8 rpg_min_dec_fac[0x20];
1102 u8 rpg_min_rate[0x20];
1104 u8 reserved_at_1c0[0xe0];
1106 u8 rate_to_set_on_first_cnp[0x20];
1110 u8 dce_tcp_rtt[0x20];
1112 u8 rate_reduce_monitor_period[0x20];
1114 u8 reserved_at_320[0x20];
1116 u8 initial_alpha_value[0x20];
1118 u8 reserved_at_360[0x4a0];
1121 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1122 u8 reserved_at_0[0x80];
1124 u8 rppp_max_rps[0x20];
1126 u8 rpg_time_reset[0x20];
1128 u8 rpg_byte_reset[0x20];
1130 u8 rpg_threshold[0x20];
1132 u8 rpg_max_rate[0x20];
1134 u8 rpg_ai_rate[0x20];
1136 u8 rpg_hai_rate[0x20];
1140 u8 rpg_min_dec_fac[0x20];
1142 u8 rpg_min_rate[0x20];
1144 u8 reserved_at_1c0[0x640];
1148 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1149 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1150 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1153 struct mlx5_ifc_resize_field_select_bits {
1154 u8 resize_field_select[0x20];
1158 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1159 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1160 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1161 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1164 struct mlx5_ifc_modify_field_select_bits {
1165 u8 modify_field_select[0x20];
1168 struct mlx5_ifc_field_select_r_roce_np_bits {
1169 u8 field_select_r_roce_np[0x20];
1172 struct mlx5_ifc_field_select_r_roce_rp_bits {
1173 u8 field_select_r_roce_rp[0x20];
1177 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1178 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1179 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1180 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1181 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1182 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1183 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1184 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1185 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1186 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1189 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1190 u8 field_select_8021qaurp[0x20];
1193 struct mlx5_ifc_phys_layer_cntrs_bits {
1194 u8 time_since_last_clear_high[0x20];
1196 u8 time_since_last_clear_low[0x20];
1198 u8 symbol_errors_high[0x20];
1200 u8 symbol_errors_low[0x20];
1202 u8 sync_headers_errors_high[0x20];
1204 u8 sync_headers_errors_low[0x20];
1206 u8 edpl_bip_errors_lane0_high[0x20];
1208 u8 edpl_bip_errors_lane0_low[0x20];
1210 u8 edpl_bip_errors_lane1_high[0x20];
1212 u8 edpl_bip_errors_lane1_low[0x20];
1214 u8 edpl_bip_errors_lane2_high[0x20];
1216 u8 edpl_bip_errors_lane2_low[0x20];
1218 u8 edpl_bip_errors_lane3_high[0x20];
1220 u8 edpl_bip_errors_lane3_low[0x20];
1222 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1224 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1226 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1228 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1230 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1232 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1234 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1236 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1238 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1240 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1242 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1244 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1246 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1248 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1250 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1252 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1254 u8 rs_fec_corrected_blocks_high[0x20];
1256 u8 rs_fec_corrected_blocks_low[0x20];
1258 u8 rs_fec_uncorrectable_blocks_high[0x20];
1260 u8 rs_fec_uncorrectable_blocks_low[0x20];
1262 u8 rs_fec_no_errors_blocks_high[0x20];
1264 u8 rs_fec_no_errors_blocks_low[0x20];
1266 u8 rs_fec_single_error_blocks_high[0x20];
1268 u8 rs_fec_single_error_blocks_low[0x20];
1270 u8 rs_fec_corrected_symbols_total_high[0x20];
1272 u8 rs_fec_corrected_symbols_total_low[0x20];
1274 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1276 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1278 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1280 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1282 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1284 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1286 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1288 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1290 u8 link_down_events[0x20];
1292 u8 successful_recovery_events[0x20];
1294 u8 reserved_at_640[0x180];
1297 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1298 u8 symbol_error_counter[0x10];
1300 u8 link_error_recovery_counter[0x8];
1302 u8 link_downed_counter[0x8];
1304 u8 port_rcv_errors[0x10];
1306 u8 port_rcv_remote_physical_errors[0x10];
1308 u8 port_rcv_switch_relay_errors[0x10];
1310 u8 port_xmit_discards[0x10];
1312 u8 port_xmit_constraint_errors[0x8];
1314 u8 port_rcv_constraint_errors[0x8];
1316 u8 reserved_at_70[0x8];
1318 u8 link_overrun_errors[0x8];
1320 u8 reserved_at_80[0x10];
1322 u8 vl_15_dropped[0x10];
1324 u8 reserved_at_a0[0xa0];
1327 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1328 u8 transmit_queue_high[0x20];
1330 u8 transmit_queue_low[0x20];
1332 u8 reserved_at_40[0x780];
1335 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1336 u8 rx_octets_high[0x20];
1338 u8 rx_octets_low[0x20];
1340 u8 reserved_at_40[0xc0];
1342 u8 rx_frames_high[0x20];
1344 u8 rx_frames_low[0x20];
1346 u8 tx_octets_high[0x20];
1348 u8 tx_octets_low[0x20];
1350 u8 reserved_at_180[0xc0];
1352 u8 tx_frames_high[0x20];
1354 u8 tx_frames_low[0x20];
1356 u8 rx_pause_high[0x20];
1358 u8 rx_pause_low[0x20];
1360 u8 rx_pause_duration_high[0x20];
1362 u8 rx_pause_duration_low[0x20];
1364 u8 tx_pause_high[0x20];
1366 u8 tx_pause_low[0x20];
1368 u8 tx_pause_duration_high[0x20];
1370 u8 tx_pause_duration_low[0x20];
1372 u8 rx_pause_transition_high[0x20];
1374 u8 rx_pause_transition_low[0x20];
1376 u8 reserved_at_3c0[0x400];
1379 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1380 u8 port_transmit_wait_high[0x20];
1382 u8 port_transmit_wait_low[0x20];
1384 u8 reserved_at_40[0x780];
1387 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1388 u8 dot3stats_alignment_errors_high[0x20];
1390 u8 dot3stats_alignment_errors_low[0x20];
1392 u8 dot3stats_fcs_errors_high[0x20];
1394 u8 dot3stats_fcs_errors_low[0x20];
1396 u8 dot3stats_single_collision_frames_high[0x20];
1398 u8 dot3stats_single_collision_frames_low[0x20];
1400 u8 dot3stats_multiple_collision_frames_high[0x20];
1402 u8 dot3stats_multiple_collision_frames_low[0x20];
1404 u8 dot3stats_sqe_test_errors_high[0x20];
1406 u8 dot3stats_sqe_test_errors_low[0x20];
1408 u8 dot3stats_deferred_transmissions_high[0x20];
1410 u8 dot3stats_deferred_transmissions_low[0x20];
1412 u8 dot3stats_late_collisions_high[0x20];
1414 u8 dot3stats_late_collisions_low[0x20];
1416 u8 dot3stats_excessive_collisions_high[0x20];
1418 u8 dot3stats_excessive_collisions_low[0x20];
1420 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1422 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1424 u8 dot3stats_carrier_sense_errors_high[0x20];
1426 u8 dot3stats_carrier_sense_errors_low[0x20];
1428 u8 dot3stats_frame_too_longs_high[0x20];
1430 u8 dot3stats_frame_too_longs_low[0x20];
1432 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1434 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1436 u8 dot3stats_symbol_errors_high[0x20];
1438 u8 dot3stats_symbol_errors_low[0x20];
1440 u8 dot3control_in_unknown_opcodes_high[0x20];
1442 u8 dot3control_in_unknown_opcodes_low[0x20];
1444 u8 dot3in_pause_frames_high[0x20];
1446 u8 dot3in_pause_frames_low[0x20];
1448 u8 dot3out_pause_frames_high[0x20];
1450 u8 dot3out_pause_frames_low[0x20];
1452 u8 reserved_at_400[0x3c0];
1455 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1456 u8 ether_stats_drop_events_high[0x20];
1458 u8 ether_stats_drop_events_low[0x20];
1460 u8 ether_stats_octets_high[0x20];
1462 u8 ether_stats_octets_low[0x20];
1464 u8 ether_stats_pkts_high[0x20];
1466 u8 ether_stats_pkts_low[0x20];
1468 u8 ether_stats_broadcast_pkts_high[0x20];
1470 u8 ether_stats_broadcast_pkts_low[0x20];
1472 u8 ether_stats_multicast_pkts_high[0x20];
1474 u8 ether_stats_multicast_pkts_low[0x20];
1476 u8 ether_stats_crc_align_errors_high[0x20];
1478 u8 ether_stats_crc_align_errors_low[0x20];
1480 u8 ether_stats_undersize_pkts_high[0x20];
1482 u8 ether_stats_undersize_pkts_low[0x20];
1484 u8 ether_stats_oversize_pkts_high[0x20];
1486 u8 ether_stats_oversize_pkts_low[0x20];
1488 u8 ether_stats_fragments_high[0x20];
1490 u8 ether_stats_fragments_low[0x20];
1492 u8 ether_stats_jabbers_high[0x20];
1494 u8 ether_stats_jabbers_low[0x20];
1496 u8 ether_stats_collisions_high[0x20];
1498 u8 ether_stats_collisions_low[0x20];
1500 u8 ether_stats_pkts64octets_high[0x20];
1502 u8 ether_stats_pkts64octets_low[0x20];
1504 u8 ether_stats_pkts65to127octets_high[0x20];
1506 u8 ether_stats_pkts65to127octets_low[0x20];
1508 u8 ether_stats_pkts128to255octets_high[0x20];
1510 u8 ether_stats_pkts128to255octets_low[0x20];
1512 u8 ether_stats_pkts256to511octets_high[0x20];
1514 u8 ether_stats_pkts256to511octets_low[0x20];
1516 u8 ether_stats_pkts512to1023octets_high[0x20];
1518 u8 ether_stats_pkts512to1023octets_low[0x20];
1520 u8 ether_stats_pkts1024to1518octets_high[0x20];
1522 u8 ether_stats_pkts1024to1518octets_low[0x20];
1524 u8 ether_stats_pkts1519to2047octets_high[0x20];
1526 u8 ether_stats_pkts1519to2047octets_low[0x20];
1528 u8 ether_stats_pkts2048to4095octets_high[0x20];
1530 u8 ether_stats_pkts2048to4095octets_low[0x20];
1532 u8 ether_stats_pkts4096to8191octets_high[0x20];
1534 u8 ether_stats_pkts4096to8191octets_low[0x20];
1536 u8 ether_stats_pkts8192to10239octets_high[0x20];
1538 u8 ether_stats_pkts8192to10239octets_low[0x20];
1540 u8 reserved_at_540[0x280];
1543 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1544 u8 if_in_octets_high[0x20];
1546 u8 if_in_octets_low[0x20];
1548 u8 if_in_ucast_pkts_high[0x20];
1550 u8 if_in_ucast_pkts_low[0x20];
1552 u8 if_in_discards_high[0x20];
1554 u8 if_in_discards_low[0x20];
1556 u8 if_in_errors_high[0x20];
1558 u8 if_in_errors_low[0x20];
1560 u8 if_in_unknown_protos_high[0x20];
1562 u8 if_in_unknown_protos_low[0x20];
1564 u8 if_out_octets_high[0x20];
1566 u8 if_out_octets_low[0x20];
1568 u8 if_out_ucast_pkts_high[0x20];
1570 u8 if_out_ucast_pkts_low[0x20];
1572 u8 if_out_discards_high[0x20];
1574 u8 if_out_discards_low[0x20];
1576 u8 if_out_errors_high[0x20];
1578 u8 if_out_errors_low[0x20];
1580 u8 if_in_multicast_pkts_high[0x20];
1582 u8 if_in_multicast_pkts_low[0x20];
1584 u8 if_in_broadcast_pkts_high[0x20];
1586 u8 if_in_broadcast_pkts_low[0x20];
1588 u8 if_out_multicast_pkts_high[0x20];
1590 u8 if_out_multicast_pkts_low[0x20];
1592 u8 if_out_broadcast_pkts_high[0x20];
1594 u8 if_out_broadcast_pkts_low[0x20];
1596 u8 reserved_at_340[0x480];
1599 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1600 u8 a_frames_transmitted_ok_high[0x20];
1602 u8 a_frames_transmitted_ok_low[0x20];
1604 u8 a_frames_received_ok_high[0x20];
1606 u8 a_frames_received_ok_low[0x20];
1608 u8 a_frame_check_sequence_errors_high[0x20];
1610 u8 a_frame_check_sequence_errors_low[0x20];
1612 u8 a_alignment_errors_high[0x20];
1614 u8 a_alignment_errors_low[0x20];
1616 u8 a_octets_transmitted_ok_high[0x20];
1618 u8 a_octets_transmitted_ok_low[0x20];
1620 u8 a_octets_received_ok_high[0x20];
1622 u8 a_octets_received_ok_low[0x20];
1624 u8 a_multicast_frames_xmitted_ok_high[0x20];
1626 u8 a_multicast_frames_xmitted_ok_low[0x20];
1628 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1630 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1632 u8 a_multicast_frames_received_ok_high[0x20];
1634 u8 a_multicast_frames_received_ok_low[0x20];
1636 u8 a_broadcast_frames_received_ok_high[0x20];
1638 u8 a_broadcast_frames_received_ok_low[0x20];
1640 u8 a_in_range_length_errors_high[0x20];
1642 u8 a_in_range_length_errors_low[0x20];
1644 u8 a_out_of_range_length_field_high[0x20];
1646 u8 a_out_of_range_length_field_low[0x20];
1648 u8 a_frame_too_long_errors_high[0x20];
1650 u8 a_frame_too_long_errors_low[0x20];
1652 u8 a_symbol_error_during_carrier_high[0x20];
1654 u8 a_symbol_error_during_carrier_low[0x20];
1656 u8 a_mac_control_frames_transmitted_high[0x20];
1658 u8 a_mac_control_frames_transmitted_low[0x20];
1660 u8 a_mac_control_frames_received_high[0x20];
1662 u8 a_mac_control_frames_received_low[0x20];
1664 u8 a_unsupported_opcodes_received_high[0x20];
1666 u8 a_unsupported_opcodes_received_low[0x20];
1668 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1670 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1672 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1674 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1676 u8 reserved_at_4c0[0x300];
1679 struct mlx5_ifc_cmd_inter_comp_event_bits {
1680 u8 command_completion_vector[0x20];
1682 u8 reserved_at_20[0xc0];
1685 struct mlx5_ifc_stall_vl_event_bits {
1686 u8 reserved_at_0[0x18];
1688 u8 reserved_at_19[0x3];
1691 u8 reserved_at_20[0xa0];
1694 struct mlx5_ifc_db_bf_congestion_event_bits {
1695 u8 event_subtype[0x8];
1696 u8 reserved_at_8[0x8];
1697 u8 congestion_level[0x8];
1698 u8 reserved_at_18[0x8];
1700 u8 reserved_at_20[0xa0];
1703 struct mlx5_ifc_gpio_event_bits {
1704 u8 reserved_at_0[0x60];
1706 u8 gpio_event_hi[0x20];
1708 u8 gpio_event_lo[0x20];
1710 u8 reserved_at_a0[0x40];
1713 struct mlx5_ifc_port_state_change_event_bits {
1714 u8 reserved_at_0[0x40];
1717 u8 reserved_at_44[0x1c];
1719 u8 reserved_at_60[0x80];
1722 struct mlx5_ifc_dropped_packet_logged_bits {
1723 u8 reserved_at_0[0xe0];
1727 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1728 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1731 struct mlx5_ifc_cq_error_bits {
1732 u8 reserved_at_0[0x8];
1735 u8 reserved_at_20[0x20];
1737 u8 reserved_at_40[0x18];
1740 u8 reserved_at_60[0x80];
1743 struct mlx5_ifc_rdma_page_fault_event_bits {
1744 u8 bytes_committed[0x20];
1748 u8 reserved_at_40[0x10];
1749 u8 packet_len[0x10];
1751 u8 rdma_op_len[0x20];
1755 u8 reserved_at_c0[0x5];
1762 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1763 u8 bytes_committed[0x20];
1765 u8 reserved_at_20[0x10];
1768 u8 reserved_at_40[0x10];
1771 u8 reserved_at_60[0x60];
1773 u8 reserved_at_c0[0x5];
1780 struct mlx5_ifc_qp_events_bits {
1781 u8 reserved_at_0[0xa0];
1784 u8 reserved_at_a8[0x18];
1786 u8 reserved_at_c0[0x8];
1787 u8 qpn_rqn_sqn[0x18];
1790 struct mlx5_ifc_dct_events_bits {
1791 u8 reserved_at_0[0xc0];
1793 u8 reserved_at_c0[0x8];
1794 u8 dct_number[0x18];
1797 struct mlx5_ifc_comp_event_bits {
1798 u8 reserved_at_0[0xc0];
1800 u8 reserved_at_c0[0x8];
1805 MLX5_QPC_STATE_RST = 0x0,
1806 MLX5_QPC_STATE_INIT = 0x1,
1807 MLX5_QPC_STATE_RTR = 0x2,
1808 MLX5_QPC_STATE_RTS = 0x3,
1809 MLX5_QPC_STATE_SQER = 0x4,
1810 MLX5_QPC_STATE_ERR = 0x6,
1811 MLX5_QPC_STATE_SQD = 0x7,
1812 MLX5_QPC_STATE_SUSPENDED = 0x9,
1816 MLX5_QPC_ST_RC = 0x0,
1817 MLX5_QPC_ST_UC = 0x1,
1818 MLX5_QPC_ST_UD = 0x2,
1819 MLX5_QPC_ST_XRC = 0x3,
1820 MLX5_QPC_ST_DCI = 0x5,
1821 MLX5_QPC_ST_QP0 = 0x7,
1822 MLX5_QPC_ST_QP1 = 0x8,
1823 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1824 MLX5_QPC_ST_REG_UMR = 0xc,
1828 MLX5_QPC_PM_STATE_ARMED = 0x0,
1829 MLX5_QPC_PM_STATE_REARM = 0x1,
1830 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1831 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1835 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1836 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1840 MLX5_QPC_MTU_256_BYTES = 0x1,
1841 MLX5_QPC_MTU_512_BYTES = 0x2,
1842 MLX5_QPC_MTU_1K_BYTES = 0x3,
1843 MLX5_QPC_MTU_2K_BYTES = 0x4,
1844 MLX5_QPC_MTU_4K_BYTES = 0x5,
1845 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1849 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1850 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1851 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1852 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1853 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1854 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1855 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1856 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
1860 MLX5_QPC_CS_REQ_DISABLE = 0x0,
1861 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1862 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
1866 MLX5_QPC_CS_RES_DISABLE = 0x0,
1867 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1868 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
1871 struct mlx5_ifc_qpc_bits {
1873 u8 reserved_at_4[0x4];
1875 u8 reserved_at_10[0x3];
1877 u8 reserved_at_15[0x7];
1878 u8 end_padding_mode[0x2];
1879 u8 reserved_at_1e[0x2];
1881 u8 wq_signature[0x1];
1882 u8 block_lb_mc[0x1];
1883 u8 atomic_like_write_en[0x1];
1884 u8 latency_sensitive[0x1];
1885 u8 reserved_at_24[0x1];
1886 u8 drain_sigerr[0x1];
1887 u8 reserved_at_26[0x2];
1891 u8 log_msg_max[0x5];
1892 u8 reserved_at_48[0x1];
1893 u8 log_rq_size[0x4];
1894 u8 log_rq_stride[0x3];
1896 u8 log_sq_size[0x4];
1897 u8 reserved_at_55[0x6];
1899 u8 ulp_stateless_offload_mode[0x4];
1901 u8 counter_set_id[0x8];
1904 u8 reserved_at_80[0x8];
1905 u8 user_index[0x18];
1907 u8 reserved_at_a0[0x3];
1908 u8 log_page_size[0x5];
1909 u8 remote_qpn[0x18];
1911 struct mlx5_ifc_ads_bits primary_address_path;
1913 struct mlx5_ifc_ads_bits secondary_address_path;
1915 u8 log_ack_req_freq[0x4];
1916 u8 reserved_at_384[0x4];
1917 u8 log_sra_max[0x3];
1918 u8 reserved_at_38b[0x2];
1919 u8 retry_count[0x3];
1921 u8 reserved_at_393[0x1];
1923 u8 cur_rnr_retry[0x3];
1924 u8 cur_retry_count[0x3];
1925 u8 reserved_at_39b[0x5];
1927 u8 reserved_at_3a0[0x20];
1929 u8 reserved_at_3c0[0x8];
1930 u8 next_send_psn[0x18];
1932 u8 reserved_at_3e0[0x8];
1935 u8 reserved_at_400[0x40];
1937 u8 reserved_at_440[0x8];
1938 u8 last_acked_psn[0x18];
1940 u8 reserved_at_460[0x8];
1943 u8 reserved_at_480[0x8];
1944 u8 log_rra_max[0x3];
1945 u8 reserved_at_48b[0x1];
1946 u8 atomic_mode[0x4];
1950 u8 reserved_at_493[0x1];
1951 u8 page_offset[0x6];
1952 u8 reserved_at_49a[0x3];
1953 u8 cd_slave_receive[0x1];
1954 u8 cd_slave_send[0x1];
1957 u8 reserved_at_4a0[0x3];
1958 u8 min_rnr_nak[0x5];
1959 u8 next_rcv_psn[0x18];
1961 u8 reserved_at_4c0[0x8];
1964 u8 reserved_at_4e0[0x8];
1971 u8 reserved_at_560[0x5];
1975 u8 reserved_at_580[0x8];
1978 u8 hw_sq_wqebb_counter[0x10];
1979 u8 sw_sq_wqebb_counter[0x10];
1981 u8 hw_rq_counter[0x20];
1983 u8 sw_rq_counter[0x20];
1985 u8 reserved_at_600[0x20];
1987 u8 reserved_at_620[0xf];
1992 u8 dc_access_key[0x40];
1994 u8 reserved_at_680[0xc0];
1997 struct mlx5_ifc_roce_addr_layout_bits {
1998 u8 source_l3_address[16][0x8];
2000 u8 reserved_at_80[0x3];
2003 u8 source_mac_47_32[0x10];
2005 u8 source_mac_31_0[0x20];
2007 u8 reserved_at_c0[0x14];
2008 u8 roce_l3_type[0x4];
2009 u8 roce_version[0x8];
2011 u8 reserved_at_e0[0x20];
2014 union mlx5_ifc_hca_cap_union_bits {
2015 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2016 struct mlx5_ifc_odp_cap_bits odp_cap;
2017 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2018 struct mlx5_ifc_roce_cap_bits roce_cap;
2019 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2020 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2021 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2022 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2023 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2024 u8 reserved_at_0[0x8000];
2028 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2029 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2030 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2031 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2034 struct mlx5_ifc_flow_context_bits {
2035 u8 reserved_at_0[0x20];
2039 u8 reserved_at_40[0x8];
2042 u8 reserved_at_60[0x10];
2045 u8 reserved_at_80[0x8];
2046 u8 destination_list_size[0x18];
2048 u8 reserved_at_a0[0x8];
2049 u8 flow_counter_list_size[0x18];
2051 u8 reserved_at_c0[0x140];
2053 struct mlx5_ifc_fte_match_param_bits match_value;
2055 u8 reserved_at_1200[0x600];
2057 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2061 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2062 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2065 struct mlx5_ifc_xrc_srqc_bits {
2067 u8 log_xrc_srq_size[0x4];
2068 u8 reserved_at_8[0x18];
2070 u8 wq_signature[0x1];
2072 u8 reserved_at_22[0x1];
2074 u8 basic_cyclic_rcv_wqe[0x1];
2075 u8 log_rq_stride[0x3];
2078 u8 page_offset[0x6];
2079 u8 reserved_at_46[0x2];
2082 u8 reserved_at_60[0x20];
2084 u8 user_index_equal_xrc_srqn[0x1];
2085 u8 reserved_at_81[0x1];
2086 u8 log_page_size[0x6];
2087 u8 user_index[0x18];
2089 u8 reserved_at_a0[0x20];
2091 u8 reserved_at_c0[0x8];
2097 u8 reserved_at_100[0x40];
2099 u8 db_record_addr_h[0x20];
2101 u8 db_record_addr_l[0x1e];
2102 u8 reserved_at_17e[0x2];
2104 u8 reserved_at_180[0x80];
2107 struct mlx5_ifc_traffic_counter_bits {
2113 struct mlx5_ifc_tisc_bits {
2114 u8 reserved_at_0[0xc];
2116 u8 reserved_at_10[0x10];
2118 u8 reserved_at_20[0x100];
2120 u8 reserved_at_120[0x8];
2121 u8 transport_domain[0x18];
2123 u8 reserved_at_140[0x3c0];
2127 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2128 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2132 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2133 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2137 MLX5_RX_HASH_FN_NONE = 0x0,
2138 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2139 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2143 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2144 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2147 struct mlx5_ifc_tirc_bits {
2148 u8 reserved_at_0[0x20];
2151 u8 reserved_at_24[0x1c];
2153 u8 reserved_at_40[0x40];
2155 u8 reserved_at_80[0x4];
2156 u8 lro_timeout_period_usecs[0x10];
2157 u8 lro_enable_mask[0x4];
2158 u8 lro_max_ip_payload_size[0x8];
2160 u8 reserved_at_a0[0x40];
2162 u8 reserved_at_e0[0x8];
2163 u8 inline_rqn[0x18];
2165 u8 rx_hash_symmetric[0x1];
2166 u8 reserved_at_101[0x1];
2167 u8 tunneled_offload_en[0x1];
2168 u8 reserved_at_103[0x5];
2169 u8 indirect_table[0x18];
2172 u8 reserved_at_124[0x2];
2173 u8 self_lb_block[0x2];
2174 u8 transport_domain[0x18];
2176 u8 rx_hash_toeplitz_key[10][0x20];
2178 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2180 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2182 u8 reserved_at_2c0[0x4c0];
2186 MLX5_SRQC_STATE_GOOD = 0x0,
2187 MLX5_SRQC_STATE_ERROR = 0x1,
2190 struct mlx5_ifc_srqc_bits {
2192 u8 log_srq_size[0x4];
2193 u8 reserved_at_8[0x18];
2195 u8 wq_signature[0x1];
2197 u8 reserved_at_22[0x1];
2199 u8 reserved_at_24[0x1];
2200 u8 log_rq_stride[0x3];
2203 u8 page_offset[0x6];
2204 u8 reserved_at_46[0x2];
2207 u8 reserved_at_60[0x20];
2209 u8 reserved_at_80[0x2];
2210 u8 log_page_size[0x6];
2211 u8 reserved_at_88[0x18];
2213 u8 reserved_at_a0[0x20];
2215 u8 reserved_at_c0[0x8];
2221 u8 reserved_at_100[0x40];
2225 u8 reserved_at_180[0x80];
2229 MLX5_SQC_STATE_RST = 0x0,
2230 MLX5_SQC_STATE_RDY = 0x1,
2231 MLX5_SQC_STATE_ERR = 0x3,
2234 struct mlx5_ifc_sqc_bits {
2238 u8 flush_in_error_en[0x1];
2239 u8 reserved_at_4[0x4];
2242 u8 reserved_at_d[0x13];
2244 u8 reserved_at_20[0x8];
2245 u8 user_index[0x18];
2247 u8 reserved_at_40[0x8];
2250 u8 reserved_at_60[0xa0];
2252 u8 tis_lst_sz[0x10];
2253 u8 reserved_at_110[0x10];
2255 u8 reserved_at_120[0x40];
2257 u8 reserved_at_160[0x8];
2260 struct mlx5_ifc_wq_bits wq;
2263 struct mlx5_ifc_rqtc_bits {
2264 u8 reserved_at_0[0xa0];
2266 u8 reserved_at_a0[0x10];
2267 u8 rqt_max_size[0x10];
2269 u8 reserved_at_c0[0x10];
2270 u8 rqt_actual_size[0x10];
2272 u8 reserved_at_e0[0x6a0];
2274 struct mlx5_ifc_rq_num_bits rq_num[0];
2278 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2279 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2283 MLX5_RQC_STATE_RST = 0x0,
2284 MLX5_RQC_STATE_RDY = 0x1,
2285 MLX5_RQC_STATE_ERR = 0x3,
2288 struct mlx5_ifc_rqc_bits {
2290 u8 reserved_at_1[0x1];
2291 u8 scatter_fcs[0x1];
2293 u8 mem_rq_type[0x4];
2295 u8 reserved_at_c[0x1];
2296 u8 flush_in_error_en[0x1];
2297 u8 reserved_at_e[0x12];
2299 u8 reserved_at_20[0x8];
2300 u8 user_index[0x18];
2302 u8 reserved_at_40[0x8];
2305 u8 counter_set_id[0x8];
2306 u8 reserved_at_68[0x18];
2308 u8 reserved_at_80[0x8];
2311 u8 reserved_at_a0[0xe0];
2313 struct mlx5_ifc_wq_bits wq;
2317 MLX5_RMPC_STATE_RDY = 0x1,
2318 MLX5_RMPC_STATE_ERR = 0x3,
2321 struct mlx5_ifc_rmpc_bits {
2322 u8 reserved_at_0[0x8];
2324 u8 reserved_at_c[0x14];
2326 u8 basic_cyclic_rcv_wqe[0x1];
2327 u8 reserved_at_21[0x1f];
2329 u8 reserved_at_40[0x140];
2331 struct mlx5_ifc_wq_bits wq;
2334 struct mlx5_ifc_nic_vport_context_bits {
2335 u8 reserved_at_0[0x1f];
2338 u8 arm_change_event[0x1];
2339 u8 reserved_at_21[0x1a];
2340 u8 event_on_mtu[0x1];
2341 u8 event_on_promisc_change[0x1];
2342 u8 event_on_vlan_change[0x1];
2343 u8 event_on_mc_address_change[0x1];
2344 u8 event_on_uc_address_change[0x1];
2346 u8 reserved_at_40[0xf0];
2350 u8 system_image_guid[0x40];
2354 u8 reserved_at_200[0x140];
2355 u8 qkey_violation_counter[0x10];
2356 u8 reserved_at_350[0x430];
2360 u8 promisc_all[0x1];
2361 u8 reserved_at_783[0x2];
2362 u8 allowed_list_type[0x3];
2363 u8 reserved_at_788[0xc];
2364 u8 allowed_list_size[0xc];
2366 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2368 u8 reserved_at_7e0[0x20];
2370 u8 current_uc_mac_address[0][0x40];
2374 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2375 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2376 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2379 struct mlx5_ifc_mkc_bits {
2380 u8 reserved_at_0[0x1];
2382 u8 reserved_at_2[0xd];
2383 u8 small_fence_on_rdma_read_response[0x1];
2390 u8 access_mode[0x2];
2391 u8 reserved_at_18[0x8];
2396 u8 reserved_at_40[0x20];
2401 u8 reserved_at_63[0x2];
2402 u8 expected_sigerr_count[0x1];
2403 u8 reserved_at_66[0x1];
2407 u8 start_addr[0x40];
2411 u8 bsf_octword_size[0x20];
2413 u8 reserved_at_120[0x80];
2415 u8 translations_octword_size[0x20];
2417 u8 reserved_at_1c0[0x1b];
2418 u8 log_page_size[0x5];
2420 u8 reserved_at_1e0[0x20];
2423 struct mlx5_ifc_pkey_bits {
2424 u8 reserved_at_0[0x10];
2428 struct mlx5_ifc_array128_auto_bits {
2429 u8 array128_auto[16][0x8];
2432 struct mlx5_ifc_hca_vport_context_bits {
2433 u8 field_select[0x20];
2435 u8 reserved_at_20[0xe0];
2437 u8 sm_virt_aware[0x1];
2440 u8 grh_required[0x1];
2441 u8 reserved_at_104[0xc];
2442 u8 port_physical_state[0x4];
2443 u8 vport_state_policy[0x4];
2445 u8 vport_state[0x4];
2447 u8 reserved_at_120[0x20];
2449 u8 system_image_guid[0x40];
2457 u8 cap_mask1_field_select[0x20];
2461 u8 cap_mask2_field_select[0x20];
2463 u8 reserved_at_280[0x80];
2466 u8 reserved_at_310[0x4];
2467 u8 init_type_reply[0x4];
2469 u8 subnet_timeout[0x5];
2473 u8 reserved_at_334[0xc];
2475 u8 qkey_violation_counter[0x10];
2476 u8 pkey_violation_counter[0x10];
2478 u8 reserved_at_360[0xca0];
2481 struct mlx5_ifc_esw_vport_context_bits {
2482 u8 reserved_at_0[0x3];
2483 u8 vport_svlan_strip[0x1];
2484 u8 vport_cvlan_strip[0x1];
2485 u8 vport_svlan_insert[0x1];
2486 u8 vport_cvlan_insert[0x2];
2487 u8 reserved_at_8[0x18];
2489 u8 reserved_at_20[0x20];
2498 u8 reserved_at_60[0x7a0];
2502 MLX5_EQC_STATUS_OK = 0x0,
2503 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2507 MLX5_EQC_ST_ARMED = 0x9,
2508 MLX5_EQC_ST_FIRED = 0xa,
2511 struct mlx5_ifc_eqc_bits {
2513 u8 reserved_at_4[0x9];
2516 u8 reserved_at_f[0x5];
2518 u8 reserved_at_18[0x8];
2520 u8 reserved_at_20[0x20];
2522 u8 reserved_at_40[0x14];
2523 u8 page_offset[0x6];
2524 u8 reserved_at_5a[0x6];
2526 u8 reserved_at_60[0x3];
2527 u8 log_eq_size[0x5];
2530 u8 reserved_at_80[0x20];
2532 u8 reserved_at_a0[0x18];
2535 u8 reserved_at_c0[0x3];
2536 u8 log_page_size[0x5];
2537 u8 reserved_at_c8[0x18];
2539 u8 reserved_at_e0[0x60];
2541 u8 reserved_at_140[0x8];
2542 u8 consumer_counter[0x18];
2544 u8 reserved_at_160[0x8];
2545 u8 producer_counter[0x18];
2547 u8 reserved_at_180[0x80];
2551 MLX5_DCTC_STATE_ACTIVE = 0x0,
2552 MLX5_DCTC_STATE_DRAINING = 0x1,
2553 MLX5_DCTC_STATE_DRAINED = 0x2,
2557 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2558 MLX5_DCTC_CS_RES_NA = 0x1,
2559 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2563 MLX5_DCTC_MTU_256_BYTES = 0x1,
2564 MLX5_DCTC_MTU_512_BYTES = 0x2,
2565 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2566 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2567 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2570 struct mlx5_ifc_dctc_bits {
2571 u8 reserved_at_0[0x4];
2573 u8 reserved_at_8[0x18];
2575 u8 reserved_at_20[0x8];
2576 u8 user_index[0x18];
2578 u8 reserved_at_40[0x8];
2581 u8 counter_set_id[0x8];
2582 u8 atomic_mode[0x4];
2586 u8 atomic_like_write_en[0x1];
2587 u8 latency_sensitive[0x1];
2590 u8 reserved_at_73[0xd];
2592 u8 reserved_at_80[0x8];
2594 u8 reserved_at_90[0x3];
2595 u8 min_rnr_nak[0x5];
2596 u8 reserved_at_98[0x8];
2598 u8 reserved_at_a0[0x8];
2601 u8 reserved_at_c0[0x8];
2605 u8 reserved_at_e8[0x4];
2606 u8 flow_label[0x14];
2608 u8 dc_access_key[0x40];
2610 u8 reserved_at_140[0x5];
2613 u8 pkey_index[0x10];
2615 u8 reserved_at_160[0x8];
2616 u8 my_addr_index[0x8];
2617 u8 reserved_at_170[0x8];
2620 u8 dc_access_key_violation_count[0x20];
2622 u8 reserved_at_1a0[0x14];
2628 u8 reserved_at_1c0[0x40];
2632 MLX5_CQC_STATUS_OK = 0x0,
2633 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2634 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2638 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2639 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2643 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2644 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2645 MLX5_CQC_ST_FIRED = 0xa,
2649 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2650 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2653 struct mlx5_ifc_cqc_bits {
2655 u8 reserved_at_4[0x4];
2658 u8 reserved_at_c[0x1];
2659 u8 scqe_break_moderation_en[0x1];
2661 u8 cq_period_mode[0x2];
2662 u8 cqe_comp_en[0x1];
2663 u8 mini_cqe_res_format[0x2];
2665 u8 reserved_at_18[0x8];
2667 u8 reserved_at_20[0x20];
2669 u8 reserved_at_40[0x14];
2670 u8 page_offset[0x6];
2671 u8 reserved_at_5a[0x6];
2673 u8 reserved_at_60[0x3];
2674 u8 log_cq_size[0x5];
2677 u8 reserved_at_80[0x4];
2679 u8 cq_max_count[0x10];
2681 u8 reserved_at_a0[0x18];
2684 u8 reserved_at_c0[0x3];
2685 u8 log_page_size[0x5];
2686 u8 reserved_at_c8[0x18];
2688 u8 reserved_at_e0[0x20];
2690 u8 reserved_at_100[0x8];
2691 u8 last_notified_index[0x18];
2693 u8 reserved_at_120[0x8];
2694 u8 last_solicit_index[0x18];
2696 u8 reserved_at_140[0x8];
2697 u8 consumer_counter[0x18];
2699 u8 reserved_at_160[0x8];
2700 u8 producer_counter[0x18];
2702 u8 reserved_at_180[0x40];
2707 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2708 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2709 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2710 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2711 u8 reserved_at_0[0x800];
2714 struct mlx5_ifc_query_adapter_param_block_bits {
2715 u8 reserved_at_0[0xc0];
2717 u8 reserved_at_c0[0x8];
2718 u8 ieee_vendor_id[0x18];
2720 u8 reserved_at_e0[0x10];
2721 u8 vsd_vendor_id[0x10];
2725 u8 vsd_contd_psid[16][0x8];
2728 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2729 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2730 struct mlx5_ifc_resize_field_select_bits resize_field_select;
2731 u8 reserved_at_0[0x20];
2734 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2735 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2736 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2737 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2738 u8 reserved_at_0[0x20];
2741 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2742 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2743 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2744 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2745 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2746 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2747 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2748 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2749 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
2750 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2751 u8 reserved_at_0[0x7c0];
2754 union mlx5_ifc_event_auto_bits {
2755 struct mlx5_ifc_comp_event_bits comp_event;
2756 struct mlx5_ifc_dct_events_bits dct_events;
2757 struct mlx5_ifc_qp_events_bits qp_events;
2758 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2759 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2760 struct mlx5_ifc_cq_error_bits cq_error;
2761 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2762 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2763 struct mlx5_ifc_gpio_event_bits gpio_event;
2764 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2765 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2766 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2767 u8 reserved_at_0[0xe0];
2770 struct mlx5_ifc_health_buffer_bits {
2771 u8 reserved_at_0[0x100];
2773 u8 assert_existptr[0x20];
2775 u8 assert_callra[0x20];
2777 u8 reserved_at_140[0x40];
2779 u8 fw_version[0x20];
2783 u8 reserved_at_1c0[0x20];
2785 u8 irisc_index[0x8];
2790 struct mlx5_ifc_register_loopback_control_bits {
2792 u8 reserved_at_1[0x7];
2794 u8 reserved_at_10[0x10];
2796 u8 reserved_at_20[0x60];
2799 struct mlx5_ifc_teardown_hca_out_bits {
2801 u8 reserved_at_8[0x18];
2805 u8 reserved_at_40[0x40];
2809 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
2810 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
2813 struct mlx5_ifc_teardown_hca_in_bits {
2815 u8 reserved_at_10[0x10];
2817 u8 reserved_at_20[0x10];
2820 u8 reserved_at_40[0x10];
2823 u8 reserved_at_60[0x20];
2826 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2828 u8 reserved_at_8[0x18];
2832 u8 reserved_at_40[0x40];
2835 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2837 u8 reserved_at_10[0x10];
2839 u8 reserved_at_20[0x10];
2842 u8 reserved_at_40[0x8];
2845 u8 reserved_at_60[0x20];
2847 u8 opt_param_mask[0x20];
2849 u8 reserved_at_a0[0x20];
2851 struct mlx5_ifc_qpc_bits qpc;
2853 u8 reserved_at_800[0x80];
2856 struct mlx5_ifc_sqd2rts_qp_out_bits {
2858 u8 reserved_at_8[0x18];
2862 u8 reserved_at_40[0x40];
2865 struct mlx5_ifc_sqd2rts_qp_in_bits {
2867 u8 reserved_at_10[0x10];
2869 u8 reserved_at_20[0x10];
2872 u8 reserved_at_40[0x8];
2875 u8 reserved_at_60[0x20];
2877 u8 opt_param_mask[0x20];
2879 u8 reserved_at_a0[0x20];
2881 struct mlx5_ifc_qpc_bits qpc;
2883 u8 reserved_at_800[0x80];
2886 struct mlx5_ifc_set_roce_address_out_bits {
2888 u8 reserved_at_8[0x18];
2892 u8 reserved_at_40[0x40];
2895 struct mlx5_ifc_set_roce_address_in_bits {
2897 u8 reserved_at_10[0x10];
2899 u8 reserved_at_20[0x10];
2902 u8 roce_address_index[0x10];
2903 u8 reserved_at_50[0x10];
2905 u8 reserved_at_60[0x20];
2907 struct mlx5_ifc_roce_addr_layout_bits roce_address;
2910 struct mlx5_ifc_set_mad_demux_out_bits {
2912 u8 reserved_at_8[0x18];
2916 u8 reserved_at_40[0x40];
2920 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
2921 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
2924 struct mlx5_ifc_set_mad_demux_in_bits {
2926 u8 reserved_at_10[0x10];
2928 u8 reserved_at_20[0x10];
2931 u8 reserved_at_40[0x20];
2933 u8 reserved_at_60[0x6];
2935 u8 reserved_at_68[0x18];
2938 struct mlx5_ifc_set_l2_table_entry_out_bits {
2940 u8 reserved_at_8[0x18];
2944 u8 reserved_at_40[0x40];
2947 struct mlx5_ifc_set_l2_table_entry_in_bits {
2949 u8 reserved_at_10[0x10];
2951 u8 reserved_at_20[0x10];
2954 u8 reserved_at_40[0x60];
2956 u8 reserved_at_a0[0x8];
2957 u8 table_index[0x18];
2959 u8 reserved_at_c0[0x20];
2961 u8 reserved_at_e0[0x13];
2965 struct mlx5_ifc_mac_address_layout_bits mac_address;
2967 u8 reserved_at_140[0xc0];
2970 struct mlx5_ifc_set_issi_out_bits {
2972 u8 reserved_at_8[0x18];
2976 u8 reserved_at_40[0x40];
2979 struct mlx5_ifc_set_issi_in_bits {
2981 u8 reserved_at_10[0x10];
2983 u8 reserved_at_20[0x10];
2986 u8 reserved_at_40[0x10];
2987 u8 current_issi[0x10];
2989 u8 reserved_at_60[0x20];
2992 struct mlx5_ifc_set_hca_cap_out_bits {
2994 u8 reserved_at_8[0x18];
2998 u8 reserved_at_40[0x40];
3001 struct mlx5_ifc_set_hca_cap_in_bits {
3003 u8 reserved_at_10[0x10];
3005 u8 reserved_at_20[0x10];
3008 u8 reserved_at_40[0x40];
3010 union mlx5_ifc_hca_cap_union_bits capability;
3014 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3015 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3016 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3017 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3020 struct mlx5_ifc_set_fte_out_bits {
3022 u8 reserved_at_8[0x18];
3026 u8 reserved_at_40[0x40];
3029 struct mlx5_ifc_set_fte_in_bits {
3031 u8 reserved_at_10[0x10];
3033 u8 reserved_at_20[0x10];
3036 u8 other_vport[0x1];
3037 u8 reserved_at_41[0xf];
3038 u8 vport_number[0x10];
3040 u8 reserved_at_60[0x20];
3043 u8 reserved_at_88[0x18];
3045 u8 reserved_at_a0[0x8];
3048 u8 reserved_at_c0[0x18];
3049 u8 modify_enable_mask[0x8];
3051 u8 reserved_at_e0[0x20];
3053 u8 flow_index[0x20];
3055 u8 reserved_at_120[0xe0];
3057 struct mlx5_ifc_flow_context_bits flow_context;
3060 struct mlx5_ifc_rts2rts_qp_out_bits {
3062 u8 reserved_at_8[0x18];
3066 u8 reserved_at_40[0x40];
3069 struct mlx5_ifc_rts2rts_qp_in_bits {
3071 u8 reserved_at_10[0x10];
3073 u8 reserved_at_20[0x10];
3076 u8 reserved_at_40[0x8];
3079 u8 reserved_at_60[0x20];
3081 u8 opt_param_mask[0x20];
3083 u8 reserved_at_a0[0x20];
3085 struct mlx5_ifc_qpc_bits qpc;
3087 u8 reserved_at_800[0x80];
3090 struct mlx5_ifc_rtr2rts_qp_out_bits {
3092 u8 reserved_at_8[0x18];
3096 u8 reserved_at_40[0x40];
3099 struct mlx5_ifc_rtr2rts_qp_in_bits {
3101 u8 reserved_at_10[0x10];
3103 u8 reserved_at_20[0x10];
3106 u8 reserved_at_40[0x8];
3109 u8 reserved_at_60[0x20];
3111 u8 opt_param_mask[0x20];
3113 u8 reserved_at_a0[0x20];
3115 struct mlx5_ifc_qpc_bits qpc;
3117 u8 reserved_at_800[0x80];
3120 struct mlx5_ifc_rst2init_qp_out_bits {
3122 u8 reserved_at_8[0x18];
3126 u8 reserved_at_40[0x40];
3129 struct mlx5_ifc_rst2init_qp_in_bits {
3131 u8 reserved_at_10[0x10];
3133 u8 reserved_at_20[0x10];
3136 u8 reserved_at_40[0x8];
3139 u8 reserved_at_60[0x20];
3141 u8 opt_param_mask[0x20];
3143 u8 reserved_at_a0[0x20];
3145 struct mlx5_ifc_qpc_bits qpc;
3147 u8 reserved_at_800[0x80];
3150 struct mlx5_ifc_query_xrc_srq_out_bits {
3152 u8 reserved_at_8[0x18];
3156 u8 reserved_at_40[0x40];
3158 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3160 u8 reserved_at_280[0x600];
3165 struct mlx5_ifc_query_xrc_srq_in_bits {
3167 u8 reserved_at_10[0x10];
3169 u8 reserved_at_20[0x10];
3172 u8 reserved_at_40[0x8];
3175 u8 reserved_at_60[0x20];
3179 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3180 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3183 struct mlx5_ifc_query_vport_state_out_bits {
3185 u8 reserved_at_8[0x18];
3189 u8 reserved_at_40[0x20];
3191 u8 reserved_at_60[0x18];
3192 u8 admin_state[0x4];
3197 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
3198 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
3201 struct mlx5_ifc_query_vport_state_in_bits {
3203 u8 reserved_at_10[0x10];
3205 u8 reserved_at_20[0x10];
3208 u8 other_vport[0x1];
3209 u8 reserved_at_41[0xf];
3210 u8 vport_number[0x10];
3212 u8 reserved_at_60[0x20];
3215 struct mlx5_ifc_query_vport_counter_out_bits {
3217 u8 reserved_at_8[0x18];
3221 u8 reserved_at_40[0x40];
3223 struct mlx5_ifc_traffic_counter_bits received_errors;
3225 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3227 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3229 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3231 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3233 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3235 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3237 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3239 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3241 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3243 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3245 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3247 u8 reserved_at_680[0xa00];
3251 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3254 struct mlx5_ifc_query_vport_counter_in_bits {
3256 u8 reserved_at_10[0x10];
3258 u8 reserved_at_20[0x10];
3261 u8 other_vport[0x1];
3262 u8 reserved_at_41[0xb];
3264 u8 vport_number[0x10];
3266 u8 reserved_at_60[0x60];
3269 u8 reserved_at_c1[0x1f];
3271 u8 reserved_at_e0[0x20];
3274 struct mlx5_ifc_query_tis_out_bits {
3276 u8 reserved_at_8[0x18];
3280 u8 reserved_at_40[0x40];
3282 struct mlx5_ifc_tisc_bits tis_context;
3285 struct mlx5_ifc_query_tis_in_bits {
3287 u8 reserved_at_10[0x10];
3289 u8 reserved_at_20[0x10];
3292 u8 reserved_at_40[0x8];
3295 u8 reserved_at_60[0x20];
3298 struct mlx5_ifc_query_tir_out_bits {
3300 u8 reserved_at_8[0x18];
3304 u8 reserved_at_40[0xc0];
3306 struct mlx5_ifc_tirc_bits tir_context;
3309 struct mlx5_ifc_query_tir_in_bits {
3311 u8 reserved_at_10[0x10];
3313 u8 reserved_at_20[0x10];
3316 u8 reserved_at_40[0x8];
3319 u8 reserved_at_60[0x20];
3322 struct mlx5_ifc_query_srq_out_bits {
3324 u8 reserved_at_8[0x18];
3328 u8 reserved_at_40[0x40];
3330 struct mlx5_ifc_srqc_bits srq_context_entry;
3332 u8 reserved_at_280[0x600];
3337 struct mlx5_ifc_query_srq_in_bits {
3339 u8 reserved_at_10[0x10];
3341 u8 reserved_at_20[0x10];
3344 u8 reserved_at_40[0x8];
3347 u8 reserved_at_60[0x20];
3350 struct mlx5_ifc_query_sq_out_bits {
3352 u8 reserved_at_8[0x18];
3356 u8 reserved_at_40[0xc0];
3358 struct mlx5_ifc_sqc_bits sq_context;
3361 struct mlx5_ifc_query_sq_in_bits {
3363 u8 reserved_at_10[0x10];
3365 u8 reserved_at_20[0x10];
3368 u8 reserved_at_40[0x8];
3371 u8 reserved_at_60[0x20];
3374 struct mlx5_ifc_query_special_contexts_out_bits {
3376 u8 reserved_at_8[0x18];
3380 u8 reserved_at_40[0x20];
3385 struct mlx5_ifc_query_special_contexts_in_bits {
3387 u8 reserved_at_10[0x10];
3389 u8 reserved_at_20[0x10];
3392 u8 reserved_at_40[0x40];
3395 struct mlx5_ifc_query_rqt_out_bits {
3397 u8 reserved_at_8[0x18];
3401 u8 reserved_at_40[0xc0];
3403 struct mlx5_ifc_rqtc_bits rqt_context;
3406 struct mlx5_ifc_query_rqt_in_bits {
3408 u8 reserved_at_10[0x10];
3410 u8 reserved_at_20[0x10];
3413 u8 reserved_at_40[0x8];
3416 u8 reserved_at_60[0x20];
3419 struct mlx5_ifc_query_rq_out_bits {
3421 u8 reserved_at_8[0x18];
3425 u8 reserved_at_40[0xc0];
3427 struct mlx5_ifc_rqc_bits rq_context;
3430 struct mlx5_ifc_query_rq_in_bits {
3432 u8 reserved_at_10[0x10];
3434 u8 reserved_at_20[0x10];
3437 u8 reserved_at_40[0x8];
3440 u8 reserved_at_60[0x20];
3443 struct mlx5_ifc_query_roce_address_out_bits {
3445 u8 reserved_at_8[0x18];
3449 u8 reserved_at_40[0x40];
3451 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3454 struct mlx5_ifc_query_roce_address_in_bits {
3456 u8 reserved_at_10[0x10];
3458 u8 reserved_at_20[0x10];
3461 u8 roce_address_index[0x10];
3462 u8 reserved_at_50[0x10];
3464 u8 reserved_at_60[0x20];
3467 struct mlx5_ifc_query_rmp_out_bits {
3469 u8 reserved_at_8[0x18];
3473 u8 reserved_at_40[0xc0];
3475 struct mlx5_ifc_rmpc_bits rmp_context;
3478 struct mlx5_ifc_query_rmp_in_bits {
3480 u8 reserved_at_10[0x10];
3482 u8 reserved_at_20[0x10];
3485 u8 reserved_at_40[0x8];
3488 u8 reserved_at_60[0x20];
3491 struct mlx5_ifc_query_qp_out_bits {
3493 u8 reserved_at_8[0x18];
3497 u8 reserved_at_40[0x40];
3499 u8 opt_param_mask[0x20];
3501 u8 reserved_at_a0[0x20];
3503 struct mlx5_ifc_qpc_bits qpc;
3505 u8 reserved_at_800[0x80];
3510 struct mlx5_ifc_query_qp_in_bits {
3512 u8 reserved_at_10[0x10];
3514 u8 reserved_at_20[0x10];
3517 u8 reserved_at_40[0x8];
3520 u8 reserved_at_60[0x20];
3523 struct mlx5_ifc_query_q_counter_out_bits {
3525 u8 reserved_at_8[0x18];
3529 u8 reserved_at_40[0x40];
3531 u8 rx_write_requests[0x20];
3533 u8 reserved_at_a0[0x20];
3535 u8 rx_read_requests[0x20];
3537 u8 reserved_at_e0[0x20];
3539 u8 rx_atomic_requests[0x20];
3541 u8 reserved_at_120[0x20];
3543 u8 rx_dct_connect[0x20];
3545 u8 reserved_at_160[0x20];
3547 u8 out_of_buffer[0x20];
3549 u8 reserved_at_1a0[0x20];
3551 u8 out_of_sequence[0x20];
3553 u8 reserved_at_1e0[0x620];
3556 struct mlx5_ifc_query_q_counter_in_bits {
3558 u8 reserved_at_10[0x10];
3560 u8 reserved_at_20[0x10];
3563 u8 reserved_at_40[0x80];
3566 u8 reserved_at_c1[0x1f];
3568 u8 reserved_at_e0[0x18];
3569 u8 counter_set_id[0x8];
3572 struct mlx5_ifc_query_pages_out_bits {
3574 u8 reserved_at_8[0x18];
3578 u8 reserved_at_40[0x10];
3579 u8 function_id[0x10];
3585 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3586 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3587 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3590 struct mlx5_ifc_query_pages_in_bits {
3592 u8 reserved_at_10[0x10];
3594 u8 reserved_at_20[0x10];
3597 u8 reserved_at_40[0x10];
3598 u8 function_id[0x10];
3600 u8 reserved_at_60[0x20];
3603 struct mlx5_ifc_query_nic_vport_context_out_bits {
3605 u8 reserved_at_8[0x18];
3609 u8 reserved_at_40[0x40];
3611 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3614 struct mlx5_ifc_query_nic_vport_context_in_bits {
3616 u8 reserved_at_10[0x10];
3618 u8 reserved_at_20[0x10];
3621 u8 other_vport[0x1];
3622 u8 reserved_at_41[0xf];
3623 u8 vport_number[0x10];
3625 u8 reserved_at_60[0x5];
3626 u8 allowed_list_type[0x3];
3627 u8 reserved_at_68[0x18];
3630 struct mlx5_ifc_query_mkey_out_bits {
3632 u8 reserved_at_8[0x18];
3636 u8 reserved_at_40[0x40];
3638 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3640 u8 reserved_at_280[0x600];
3642 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
3644 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
3647 struct mlx5_ifc_query_mkey_in_bits {
3649 u8 reserved_at_10[0x10];
3651 u8 reserved_at_20[0x10];
3654 u8 reserved_at_40[0x8];
3655 u8 mkey_index[0x18];
3658 u8 reserved_at_61[0x1f];
3661 struct mlx5_ifc_query_mad_demux_out_bits {
3663 u8 reserved_at_8[0x18];
3667 u8 reserved_at_40[0x40];
3669 u8 mad_dumux_parameters_block[0x20];
3672 struct mlx5_ifc_query_mad_demux_in_bits {
3674 u8 reserved_at_10[0x10];
3676 u8 reserved_at_20[0x10];
3679 u8 reserved_at_40[0x40];
3682 struct mlx5_ifc_query_l2_table_entry_out_bits {
3684 u8 reserved_at_8[0x18];
3688 u8 reserved_at_40[0xa0];
3690 u8 reserved_at_e0[0x13];
3694 struct mlx5_ifc_mac_address_layout_bits mac_address;
3696 u8 reserved_at_140[0xc0];
3699 struct mlx5_ifc_query_l2_table_entry_in_bits {
3701 u8 reserved_at_10[0x10];
3703 u8 reserved_at_20[0x10];
3706 u8 reserved_at_40[0x60];
3708 u8 reserved_at_a0[0x8];
3709 u8 table_index[0x18];
3711 u8 reserved_at_c0[0x140];
3714 struct mlx5_ifc_query_issi_out_bits {
3716 u8 reserved_at_8[0x18];
3720 u8 reserved_at_40[0x10];
3721 u8 current_issi[0x10];
3723 u8 reserved_at_60[0xa0];
3725 u8 reserved_at_100[76][0x8];
3726 u8 supported_issi_dw0[0x20];
3729 struct mlx5_ifc_query_issi_in_bits {
3731 u8 reserved_at_10[0x10];
3733 u8 reserved_at_20[0x10];
3736 u8 reserved_at_40[0x40];
3739 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3741 u8 reserved_at_8[0x18];
3745 u8 reserved_at_40[0x40];
3747 struct mlx5_ifc_pkey_bits pkey[0];
3750 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3752 u8 reserved_at_10[0x10];
3754 u8 reserved_at_20[0x10];
3757 u8 other_vport[0x1];
3758 u8 reserved_at_41[0xb];
3760 u8 vport_number[0x10];
3762 u8 reserved_at_60[0x10];
3763 u8 pkey_index[0x10];
3767 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
3768 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
3769 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
3772 struct mlx5_ifc_query_hca_vport_gid_out_bits {
3774 u8 reserved_at_8[0x18];
3778 u8 reserved_at_40[0x20];
3781 u8 reserved_at_70[0x10];
3783 struct mlx5_ifc_array128_auto_bits gid[0];
3786 struct mlx5_ifc_query_hca_vport_gid_in_bits {
3788 u8 reserved_at_10[0x10];
3790 u8 reserved_at_20[0x10];
3793 u8 other_vport[0x1];
3794 u8 reserved_at_41[0xb];
3796 u8 vport_number[0x10];
3798 u8 reserved_at_60[0x10];
3802 struct mlx5_ifc_query_hca_vport_context_out_bits {
3804 u8 reserved_at_8[0x18];
3808 u8 reserved_at_40[0x40];
3810 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3813 struct mlx5_ifc_query_hca_vport_context_in_bits {
3815 u8 reserved_at_10[0x10];
3817 u8 reserved_at_20[0x10];
3820 u8 other_vport[0x1];
3821 u8 reserved_at_41[0xb];
3823 u8 vport_number[0x10];
3825 u8 reserved_at_60[0x20];
3828 struct mlx5_ifc_query_hca_cap_out_bits {
3830 u8 reserved_at_8[0x18];
3834 u8 reserved_at_40[0x40];
3836 union mlx5_ifc_hca_cap_union_bits capability;
3839 struct mlx5_ifc_query_hca_cap_in_bits {
3841 u8 reserved_at_10[0x10];
3843 u8 reserved_at_20[0x10];
3846 u8 reserved_at_40[0x40];
3849 struct mlx5_ifc_query_flow_table_out_bits {
3851 u8 reserved_at_8[0x18];
3855 u8 reserved_at_40[0x80];
3857 u8 reserved_at_c0[0x8];
3859 u8 reserved_at_d0[0x8];
3862 u8 reserved_at_e0[0x120];
3865 struct mlx5_ifc_query_flow_table_in_bits {
3867 u8 reserved_at_10[0x10];
3869 u8 reserved_at_20[0x10];
3872 u8 reserved_at_40[0x40];
3875 u8 reserved_at_88[0x18];
3877 u8 reserved_at_a0[0x8];
3880 u8 reserved_at_c0[0x140];
3883 struct mlx5_ifc_query_fte_out_bits {
3885 u8 reserved_at_8[0x18];
3889 u8 reserved_at_40[0x1c0];
3891 struct mlx5_ifc_flow_context_bits flow_context;
3894 struct mlx5_ifc_query_fte_in_bits {
3896 u8 reserved_at_10[0x10];
3898 u8 reserved_at_20[0x10];
3901 u8 reserved_at_40[0x40];
3904 u8 reserved_at_88[0x18];
3906 u8 reserved_at_a0[0x8];
3909 u8 reserved_at_c0[0x40];
3911 u8 flow_index[0x20];
3913 u8 reserved_at_120[0xe0];
3917 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
3918 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
3919 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
3922 struct mlx5_ifc_query_flow_group_out_bits {
3924 u8 reserved_at_8[0x18];
3928 u8 reserved_at_40[0xa0];
3930 u8 start_flow_index[0x20];
3932 u8 reserved_at_100[0x20];
3934 u8 end_flow_index[0x20];
3936 u8 reserved_at_140[0xa0];
3938 u8 reserved_at_1e0[0x18];
3939 u8 match_criteria_enable[0x8];
3941 struct mlx5_ifc_fte_match_param_bits match_criteria;
3943 u8 reserved_at_1200[0xe00];
3946 struct mlx5_ifc_query_flow_group_in_bits {
3948 u8 reserved_at_10[0x10];
3950 u8 reserved_at_20[0x10];
3953 u8 reserved_at_40[0x40];
3956 u8 reserved_at_88[0x18];
3958 u8 reserved_at_a0[0x8];
3963 u8 reserved_at_e0[0x120];
3966 struct mlx5_ifc_query_flow_counter_out_bits {
3968 u8 reserved_at_8[0x18];
3972 u8 reserved_at_40[0x40];
3974 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
3977 struct mlx5_ifc_query_flow_counter_in_bits {
3979 u8 reserved_at_10[0x10];
3981 u8 reserved_at_20[0x10];
3984 u8 reserved_at_40[0x80];
3987 u8 reserved_at_c1[0xf];
3988 u8 num_of_counters[0x10];
3990 u8 reserved_at_e0[0x10];
3991 u8 flow_counter_id[0x10];
3994 struct mlx5_ifc_query_esw_vport_context_out_bits {
3996 u8 reserved_at_8[0x18];
4000 u8 reserved_at_40[0x40];
4002 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4005 struct mlx5_ifc_query_esw_vport_context_in_bits {
4007 u8 reserved_at_10[0x10];
4009 u8 reserved_at_20[0x10];
4012 u8 other_vport[0x1];
4013 u8 reserved_at_41[0xf];
4014 u8 vport_number[0x10];
4016 u8 reserved_at_60[0x20];
4019 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4021 u8 reserved_at_8[0x18];
4025 u8 reserved_at_40[0x40];
4028 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4029 u8 reserved_at_0[0x1c];
4030 u8 vport_cvlan_insert[0x1];
4031 u8 vport_svlan_insert[0x1];
4032 u8 vport_cvlan_strip[0x1];
4033 u8 vport_svlan_strip[0x1];
4036 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4038 u8 reserved_at_10[0x10];
4040 u8 reserved_at_20[0x10];
4043 u8 other_vport[0x1];
4044 u8 reserved_at_41[0xf];
4045 u8 vport_number[0x10];
4047 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4049 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4052 struct mlx5_ifc_query_eq_out_bits {
4054 u8 reserved_at_8[0x18];
4058 u8 reserved_at_40[0x40];
4060 struct mlx5_ifc_eqc_bits eq_context_entry;
4062 u8 reserved_at_280[0x40];
4064 u8 event_bitmask[0x40];
4066 u8 reserved_at_300[0x580];
4071 struct mlx5_ifc_query_eq_in_bits {
4073 u8 reserved_at_10[0x10];
4075 u8 reserved_at_20[0x10];
4078 u8 reserved_at_40[0x18];
4081 u8 reserved_at_60[0x20];
4084 struct mlx5_ifc_query_dct_out_bits {
4086 u8 reserved_at_8[0x18];
4090 u8 reserved_at_40[0x40];
4092 struct mlx5_ifc_dctc_bits dct_context_entry;
4094 u8 reserved_at_280[0x180];
4097 struct mlx5_ifc_query_dct_in_bits {
4099 u8 reserved_at_10[0x10];
4101 u8 reserved_at_20[0x10];
4104 u8 reserved_at_40[0x8];
4107 u8 reserved_at_60[0x20];
4110 struct mlx5_ifc_query_cq_out_bits {
4112 u8 reserved_at_8[0x18];
4116 u8 reserved_at_40[0x40];
4118 struct mlx5_ifc_cqc_bits cq_context;
4120 u8 reserved_at_280[0x600];
4125 struct mlx5_ifc_query_cq_in_bits {
4127 u8 reserved_at_10[0x10];
4129 u8 reserved_at_20[0x10];
4132 u8 reserved_at_40[0x8];
4135 u8 reserved_at_60[0x20];
4138 struct mlx5_ifc_query_cong_status_out_bits {
4140 u8 reserved_at_8[0x18];
4144 u8 reserved_at_40[0x20];
4148 u8 reserved_at_62[0x1e];
4151 struct mlx5_ifc_query_cong_status_in_bits {
4153 u8 reserved_at_10[0x10];
4155 u8 reserved_at_20[0x10];
4158 u8 reserved_at_40[0x18];
4160 u8 cong_protocol[0x4];
4162 u8 reserved_at_60[0x20];
4165 struct mlx5_ifc_query_cong_statistics_out_bits {
4167 u8 reserved_at_8[0x18];
4171 u8 reserved_at_40[0x40];
4177 u8 cnp_ignored_high[0x20];
4179 u8 cnp_ignored_low[0x20];
4181 u8 cnp_handled_high[0x20];
4183 u8 cnp_handled_low[0x20];
4185 u8 reserved_at_140[0x100];
4187 u8 time_stamp_high[0x20];
4189 u8 time_stamp_low[0x20];
4191 u8 accumulators_period[0x20];
4193 u8 ecn_marked_roce_packets_high[0x20];
4195 u8 ecn_marked_roce_packets_low[0x20];
4197 u8 cnps_sent_high[0x20];
4199 u8 cnps_sent_low[0x20];
4201 u8 reserved_at_320[0x560];
4204 struct mlx5_ifc_query_cong_statistics_in_bits {
4206 u8 reserved_at_10[0x10];
4208 u8 reserved_at_20[0x10];
4212 u8 reserved_at_41[0x1f];
4214 u8 reserved_at_60[0x20];
4217 struct mlx5_ifc_query_cong_params_out_bits {
4219 u8 reserved_at_8[0x18];
4223 u8 reserved_at_40[0x40];
4225 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4228 struct mlx5_ifc_query_cong_params_in_bits {
4230 u8 reserved_at_10[0x10];
4232 u8 reserved_at_20[0x10];
4235 u8 reserved_at_40[0x1c];
4236 u8 cong_protocol[0x4];
4238 u8 reserved_at_60[0x20];
4241 struct mlx5_ifc_query_adapter_out_bits {
4243 u8 reserved_at_8[0x18];
4247 u8 reserved_at_40[0x40];
4249 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4252 struct mlx5_ifc_query_adapter_in_bits {
4254 u8 reserved_at_10[0x10];
4256 u8 reserved_at_20[0x10];
4259 u8 reserved_at_40[0x40];
4262 struct mlx5_ifc_qp_2rst_out_bits {
4264 u8 reserved_at_8[0x18];
4268 u8 reserved_at_40[0x40];
4271 struct mlx5_ifc_qp_2rst_in_bits {
4273 u8 reserved_at_10[0x10];
4275 u8 reserved_at_20[0x10];
4278 u8 reserved_at_40[0x8];
4281 u8 reserved_at_60[0x20];
4284 struct mlx5_ifc_qp_2err_out_bits {
4286 u8 reserved_at_8[0x18];
4290 u8 reserved_at_40[0x40];
4293 struct mlx5_ifc_qp_2err_in_bits {
4295 u8 reserved_at_10[0x10];
4297 u8 reserved_at_20[0x10];
4300 u8 reserved_at_40[0x8];
4303 u8 reserved_at_60[0x20];
4306 struct mlx5_ifc_page_fault_resume_out_bits {
4308 u8 reserved_at_8[0x18];
4312 u8 reserved_at_40[0x40];
4315 struct mlx5_ifc_page_fault_resume_in_bits {
4317 u8 reserved_at_10[0x10];
4319 u8 reserved_at_20[0x10];
4323 u8 reserved_at_41[0x4];
4329 u8 reserved_at_60[0x20];
4332 struct mlx5_ifc_nop_out_bits {
4334 u8 reserved_at_8[0x18];
4338 u8 reserved_at_40[0x40];
4341 struct mlx5_ifc_nop_in_bits {
4343 u8 reserved_at_10[0x10];
4345 u8 reserved_at_20[0x10];
4348 u8 reserved_at_40[0x40];
4351 struct mlx5_ifc_modify_vport_state_out_bits {
4353 u8 reserved_at_8[0x18];
4357 u8 reserved_at_40[0x40];
4360 struct mlx5_ifc_modify_vport_state_in_bits {
4362 u8 reserved_at_10[0x10];
4364 u8 reserved_at_20[0x10];
4367 u8 other_vport[0x1];
4368 u8 reserved_at_41[0xf];
4369 u8 vport_number[0x10];
4371 u8 reserved_at_60[0x18];
4372 u8 admin_state[0x4];
4373 u8 reserved_at_7c[0x4];
4376 struct mlx5_ifc_modify_tis_out_bits {
4378 u8 reserved_at_8[0x18];
4382 u8 reserved_at_40[0x40];
4385 struct mlx5_ifc_modify_tis_bitmask_bits {
4386 u8 reserved_at_0[0x20];
4388 u8 reserved_at_20[0x1f];
4392 struct mlx5_ifc_modify_tis_in_bits {
4394 u8 reserved_at_10[0x10];
4396 u8 reserved_at_20[0x10];
4399 u8 reserved_at_40[0x8];
4402 u8 reserved_at_60[0x20];
4404 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
4406 u8 reserved_at_c0[0x40];
4408 struct mlx5_ifc_tisc_bits ctx;
4411 struct mlx5_ifc_modify_tir_bitmask_bits {
4412 u8 reserved_at_0[0x20];
4414 u8 reserved_at_20[0x1b];
4416 u8 reserved_at_3c[0x1];
4418 u8 reserved_at_3e[0x1];
4422 struct mlx5_ifc_modify_tir_out_bits {
4424 u8 reserved_at_8[0x18];
4428 u8 reserved_at_40[0x40];
4431 struct mlx5_ifc_modify_tir_in_bits {
4433 u8 reserved_at_10[0x10];
4435 u8 reserved_at_20[0x10];
4438 u8 reserved_at_40[0x8];
4441 u8 reserved_at_60[0x20];
4443 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
4445 u8 reserved_at_c0[0x40];
4447 struct mlx5_ifc_tirc_bits ctx;
4450 struct mlx5_ifc_modify_sq_out_bits {
4452 u8 reserved_at_8[0x18];
4456 u8 reserved_at_40[0x40];
4459 struct mlx5_ifc_modify_sq_in_bits {
4461 u8 reserved_at_10[0x10];
4463 u8 reserved_at_20[0x10];
4467 u8 reserved_at_44[0x4];
4470 u8 reserved_at_60[0x20];
4472 u8 modify_bitmask[0x40];
4474 u8 reserved_at_c0[0x40];
4476 struct mlx5_ifc_sqc_bits ctx;
4479 struct mlx5_ifc_modify_rqt_out_bits {
4481 u8 reserved_at_8[0x18];
4485 u8 reserved_at_40[0x40];
4488 struct mlx5_ifc_rqt_bitmask_bits {
4489 u8 reserved_at_0[0x20];
4491 u8 reserved_at_20[0x1f];
4495 struct mlx5_ifc_modify_rqt_in_bits {
4497 u8 reserved_at_10[0x10];
4499 u8 reserved_at_20[0x10];
4502 u8 reserved_at_40[0x8];
4505 u8 reserved_at_60[0x20];
4507 struct mlx5_ifc_rqt_bitmask_bits bitmask;
4509 u8 reserved_at_c0[0x40];
4511 struct mlx5_ifc_rqtc_bits ctx;
4514 struct mlx5_ifc_modify_rq_out_bits {
4516 u8 reserved_at_8[0x18];
4520 u8 reserved_at_40[0x40];
4523 struct mlx5_ifc_modify_rq_in_bits {
4525 u8 reserved_at_10[0x10];
4527 u8 reserved_at_20[0x10];
4531 u8 reserved_at_44[0x4];
4534 u8 reserved_at_60[0x20];
4536 u8 modify_bitmask[0x40];
4538 u8 reserved_at_c0[0x40];
4540 struct mlx5_ifc_rqc_bits ctx;
4543 struct mlx5_ifc_modify_rmp_out_bits {
4545 u8 reserved_at_8[0x18];
4549 u8 reserved_at_40[0x40];
4552 struct mlx5_ifc_rmp_bitmask_bits {
4553 u8 reserved_at_0[0x20];
4555 u8 reserved_at_20[0x1f];
4559 struct mlx5_ifc_modify_rmp_in_bits {
4561 u8 reserved_at_10[0x10];
4563 u8 reserved_at_20[0x10];
4567 u8 reserved_at_44[0x4];
4570 u8 reserved_at_60[0x20];
4572 struct mlx5_ifc_rmp_bitmask_bits bitmask;
4574 u8 reserved_at_c0[0x40];
4576 struct mlx5_ifc_rmpc_bits ctx;
4579 struct mlx5_ifc_modify_nic_vport_context_out_bits {
4581 u8 reserved_at_8[0x18];
4585 u8 reserved_at_40[0x40];
4588 struct mlx5_ifc_modify_nic_vport_field_select_bits {
4589 u8 reserved_at_0[0x16];
4592 u8 reserved_at_18[0x1];
4594 u8 change_event[0x1];
4596 u8 permanent_address[0x1];
4597 u8 addresses_list[0x1];
4599 u8 reserved_at_1f[0x1];
4602 struct mlx5_ifc_modify_nic_vport_context_in_bits {
4604 u8 reserved_at_10[0x10];
4606 u8 reserved_at_20[0x10];
4609 u8 other_vport[0x1];
4610 u8 reserved_at_41[0xf];
4611 u8 vport_number[0x10];
4613 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4615 u8 reserved_at_80[0x780];
4617 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4620 struct mlx5_ifc_modify_hca_vport_context_out_bits {
4622 u8 reserved_at_8[0x18];
4626 u8 reserved_at_40[0x40];
4629 struct mlx5_ifc_modify_hca_vport_context_in_bits {
4631 u8 reserved_at_10[0x10];
4633 u8 reserved_at_20[0x10];
4636 u8 other_vport[0x1];
4637 u8 reserved_at_41[0xb];
4639 u8 vport_number[0x10];
4641 u8 reserved_at_60[0x20];
4643 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4646 struct mlx5_ifc_modify_cq_out_bits {
4648 u8 reserved_at_8[0x18];
4652 u8 reserved_at_40[0x40];
4656 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
4657 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
4660 struct mlx5_ifc_modify_cq_in_bits {
4662 u8 reserved_at_10[0x10];
4664 u8 reserved_at_20[0x10];
4667 u8 reserved_at_40[0x8];
4670 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4672 struct mlx5_ifc_cqc_bits cq_context;
4674 u8 reserved_at_280[0x600];
4679 struct mlx5_ifc_modify_cong_status_out_bits {
4681 u8 reserved_at_8[0x18];
4685 u8 reserved_at_40[0x40];
4688 struct mlx5_ifc_modify_cong_status_in_bits {
4690 u8 reserved_at_10[0x10];
4692 u8 reserved_at_20[0x10];
4695 u8 reserved_at_40[0x18];
4697 u8 cong_protocol[0x4];
4701 u8 reserved_at_62[0x1e];
4704 struct mlx5_ifc_modify_cong_params_out_bits {
4706 u8 reserved_at_8[0x18];
4710 u8 reserved_at_40[0x40];
4713 struct mlx5_ifc_modify_cong_params_in_bits {
4715 u8 reserved_at_10[0x10];
4717 u8 reserved_at_20[0x10];
4720 u8 reserved_at_40[0x1c];
4721 u8 cong_protocol[0x4];
4723 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4725 u8 reserved_at_80[0x80];
4727 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4730 struct mlx5_ifc_manage_pages_out_bits {
4732 u8 reserved_at_8[0x18];
4736 u8 output_num_entries[0x20];
4738 u8 reserved_at_60[0x20];
4744 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
4745 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
4746 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
4749 struct mlx5_ifc_manage_pages_in_bits {
4751 u8 reserved_at_10[0x10];
4753 u8 reserved_at_20[0x10];
4756 u8 reserved_at_40[0x10];
4757 u8 function_id[0x10];
4759 u8 input_num_entries[0x20];
4764 struct mlx5_ifc_mad_ifc_out_bits {
4766 u8 reserved_at_8[0x18];
4770 u8 reserved_at_40[0x40];
4772 u8 response_mad_packet[256][0x8];
4775 struct mlx5_ifc_mad_ifc_in_bits {
4777 u8 reserved_at_10[0x10];
4779 u8 reserved_at_20[0x10];
4782 u8 remote_lid[0x10];
4783 u8 reserved_at_50[0x8];
4786 u8 reserved_at_60[0x20];
4791 struct mlx5_ifc_init_hca_out_bits {
4793 u8 reserved_at_8[0x18];
4797 u8 reserved_at_40[0x40];
4800 struct mlx5_ifc_init_hca_in_bits {
4802 u8 reserved_at_10[0x10];
4804 u8 reserved_at_20[0x10];
4807 u8 reserved_at_40[0x40];
4810 struct mlx5_ifc_init2rtr_qp_out_bits {
4812 u8 reserved_at_8[0x18];
4816 u8 reserved_at_40[0x40];
4819 struct mlx5_ifc_init2rtr_qp_in_bits {
4821 u8 reserved_at_10[0x10];
4823 u8 reserved_at_20[0x10];
4826 u8 reserved_at_40[0x8];
4829 u8 reserved_at_60[0x20];
4831 u8 opt_param_mask[0x20];
4833 u8 reserved_at_a0[0x20];
4835 struct mlx5_ifc_qpc_bits qpc;
4837 u8 reserved_at_800[0x80];
4840 struct mlx5_ifc_init2init_qp_out_bits {
4842 u8 reserved_at_8[0x18];
4846 u8 reserved_at_40[0x40];
4849 struct mlx5_ifc_init2init_qp_in_bits {
4851 u8 reserved_at_10[0x10];
4853 u8 reserved_at_20[0x10];
4856 u8 reserved_at_40[0x8];
4859 u8 reserved_at_60[0x20];
4861 u8 opt_param_mask[0x20];
4863 u8 reserved_at_a0[0x20];
4865 struct mlx5_ifc_qpc_bits qpc;
4867 u8 reserved_at_800[0x80];
4870 struct mlx5_ifc_get_dropped_packet_log_out_bits {
4872 u8 reserved_at_8[0x18];
4876 u8 reserved_at_40[0x40];
4878 u8 packet_headers_log[128][0x8];
4880 u8 packet_syndrome[64][0x8];
4883 struct mlx5_ifc_get_dropped_packet_log_in_bits {
4885 u8 reserved_at_10[0x10];
4887 u8 reserved_at_20[0x10];
4890 u8 reserved_at_40[0x40];
4893 struct mlx5_ifc_gen_eqe_in_bits {
4895 u8 reserved_at_10[0x10];
4897 u8 reserved_at_20[0x10];
4900 u8 reserved_at_40[0x18];
4903 u8 reserved_at_60[0x20];
4908 struct mlx5_ifc_gen_eq_out_bits {
4910 u8 reserved_at_8[0x18];
4914 u8 reserved_at_40[0x40];
4917 struct mlx5_ifc_enable_hca_out_bits {
4919 u8 reserved_at_8[0x18];
4923 u8 reserved_at_40[0x20];
4926 struct mlx5_ifc_enable_hca_in_bits {
4928 u8 reserved_at_10[0x10];
4930 u8 reserved_at_20[0x10];
4933 u8 reserved_at_40[0x10];
4934 u8 function_id[0x10];
4936 u8 reserved_at_60[0x20];
4939 struct mlx5_ifc_drain_dct_out_bits {
4941 u8 reserved_at_8[0x18];
4945 u8 reserved_at_40[0x40];
4948 struct mlx5_ifc_drain_dct_in_bits {
4950 u8 reserved_at_10[0x10];
4952 u8 reserved_at_20[0x10];
4955 u8 reserved_at_40[0x8];
4958 u8 reserved_at_60[0x20];
4961 struct mlx5_ifc_disable_hca_out_bits {
4963 u8 reserved_at_8[0x18];
4967 u8 reserved_at_40[0x20];
4970 struct mlx5_ifc_disable_hca_in_bits {
4972 u8 reserved_at_10[0x10];
4974 u8 reserved_at_20[0x10];
4977 u8 reserved_at_40[0x10];
4978 u8 function_id[0x10];
4980 u8 reserved_at_60[0x20];
4983 struct mlx5_ifc_detach_from_mcg_out_bits {
4985 u8 reserved_at_8[0x18];
4989 u8 reserved_at_40[0x40];
4992 struct mlx5_ifc_detach_from_mcg_in_bits {
4994 u8 reserved_at_10[0x10];
4996 u8 reserved_at_20[0x10];
4999 u8 reserved_at_40[0x8];
5002 u8 reserved_at_60[0x20];
5004 u8 multicast_gid[16][0x8];
5007 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5009 u8 reserved_at_8[0x18];
5013 u8 reserved_at_40[0x40];
5016 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5018 u8 reserved_at_10[0x10];
5020 u8 reserved_at_20[0x10];
5023 u8 reserved_at_40[0x8];
5026 u8 reserved_at_60[0x20];
5029 struct mlx5_ifc_destroy_tis_out_bits {
5031 u8 reserved_at_8[0x18];
5035 u8 reserved_at_40[0x40];
5038 struct mlx5_ifc_destroy_tis_in_bits {
5040 u8 reserved_at_10[0x10];
5042 u8 reserved_at_20[0x10];
5045 u8 reserved_at_40[0x8];
5048 u8 reserved_at_60[0x20];
5051 struct mlx5_ifc_destroy_tir_out_bits {
5053 u8 reserved_at_8[0x18];
5057 u8 reserved_at_40[0x40];
5060 struct mlx5_ifc_destroy_tir_in_bits {
5062 u8 reserved_at_10[0x10];
5064 u8 reserved_at_20[0x10];
5067 u8 reserved_at_40[0x8];
5070 u8 reserved_at_60[0x20];
5073 struct mlx5_ifc_destroy_srq_out_bits {
5075 u8 reserved_at_8[0x18];
5079 u8 reserved_at_40[0x40];
5082 struct mlx5_ifc_destroy_srq_in_bits {
5084 u8 reserved_at_10[0x10];
5086 u8 reserved_at_20[0x10];
5089 u8 reserved_at_40[0x8];
5092 u8 reserved_at_60[0x20];
5095 struct mlx5_ifc_destroy_sq_out_bits {
5097 u8 reserved_at_8[0x18];
5101 u8 reserved_at_40[0x40];
5104 struct mlx5_ifc_destroy_sq_in_bits {
5106 u8 reserved_at_10[0x10];
5108 u8 reserved_at_20[0x10];
5111 u8 reserved_at_40[0x8];
5114 u8 reserved_at_60[0x20];
5117 struct mlx5_ifc_destroy_rqt_out_bits {
5119 u8 reserved_at_8[0x18];
5123 u8 reserved_at_40[0x40];
5126 struct mlx5_ifc_destroy_rqt_in_bits {
5128 u8 reserved_at_10[0x10];
5130 u8 reserved_at_20[0x10];
5133 u8 reserved_at_40[0x8];
5136 u8 reserved_at_60[0x20];
5139 struct mlx5_ifc_destroy_rq_out_bits {
5141 u8 reserved_at_8[0x18];
5145 u8 reserved_at_40[0x40];
5148 struct mlx5_ifc_destroy_rq_in_bits {
5150 u8 reserved_at_10[0x10];
5152 u8 reserved_at_20[0x10];
5155 u8 reserved_at_40[0x8];
5158 u8 reserved_at_60[0x20];
5161 struct mlx5_ifc_destroy_rmp_out_bits {
5163 u8 reserved_at_8[0x18];
5167 u8 reserved_at_40[0x40];
5170 struct mlx5_ifc_destroy_rmp_in_bits {
5172 u8 reserved_at_10[0x10];
5174 u8 reserved_at_20[0x10];
5177 u8 reserved_at_40[0x8];
5180 u8 reserved_at_60[0x20];
5183 struct mlx5_ifc_destroy_qp_out_bits {
5185 u8 reserved_at_8[0x18];
5189 u8 reserved_at_40[0x40];
5192 struct mlx5_ifc_destroy_qp_in_bits {
5194 u8 reserved_at_10[0x10];
5196 u8 reserved_at_20[0x10];
5199 u8 reserved_at_40[0x8];
5202 u8 reserved_at_60[0x20];
5205 struct mlx5_ifc_destroy_psv_out_bits {
5207 u8 reserved_at_8[0x18];
5211 u8 reserved_at_40[0x40];
5214 struct mlx5_ifc_destroy_psv_in_bits {
5216 u8 reserved_at_10[0x10];
5218 u8 reserved_at_20[0x10];
5221 u8 reserved_at_40[0x8];
5224 u8 reserved_at_60[0x20];
5227 struct mlx5_ifc_destroy_mkey_out_bits {
5229 u8 reserved_at_8[0x18];
5233 u8 reserved_at_40[0x40];
5236 struct mlx5_ifc_destroy_mkey_in_bits {
5238 u8 reserved_at_10[0x10];
5240 u8 reserved_at_20[0x10];
5243 u8 reserved_at_40[0x8];
5244 u8 mkey_index[0x18];
5246 u8 reserved_at_60[0x20];
5249 struct mlx5_ifc_destroy_flow_table_out_bits {
5251 u8 reserved_at_8[0x18];
5255 u8 reserved_at_40[0x40];
5258 struct mlx5_ifc_destroy_flow_table_in_bits {
5260 u8 reserved_at_10[0x10];
5262 u8 reserved_at_20[0x10];
5265 u8 other_vport[0x1];
5266 u8 reserved_at_41[0xf];
5267 u8 vport_number[0x10];
5269 u8 reserved_at_60[0x20];
5272 u8 reserved_at_88[0x18];
5274 u8 reserved_at_a0[0x8];
5277 u8 reserved_at_c0[0x140];
5280 struct mlx5_ifc_destroy_flow_group_out_bits {
5282 u8 reserved_at_8[0x18];
5286 u8 reserved_at_40[0x40];
5289 struct mlx5_ifc_destroy_flow_group_in_bits {
5291 u8 reserved_at_10[0x10];
5293 u8 reserved_at_20[0x10];
5296 u8 other_vport[0x1];
5297 u8 reserved_at_41[0xf];
5298 u8 vport_number[0x10];
5300 u8 reserved_at_60[0x20];
5303 u8 reserved_at_88[0x18];
5305 u8 reserved_at_a0[0x8];
5310 u8 reserved_at_e0[0x120];
5313 struct mlx5_ifc_destroy_eq_out_bits {
5315 u8 reserved_at_8[0x18];
5319 u8 reserved_at_40[0x40];
5322 struct mlx5_ifc_destroy_eq_in_bits {
5324 u8 reserved_at_10[0x10];
5326 u8 reserved_at_20[0x10];
5329 u8 reserved_at_40[0x18];
5332 u8 reserved_at_60[0x20];
5335 struct mlx5_ifc_destroy_dct_out_bits {
5337 u8 reserved_at_8[0x18];
5341 u8 reserved_at_40[0x40];
5344 struct mlx5_ifc_destroy_dct_in_bits {
5346 u8 reserved_at_10[0x10];
5348 u8 reserved_at_20[0x10];
5351 u8 reserved_at_40[0x8];
5354 u8 reserved_at_60[0x20];
5357 struct mlx5_ifc_destroy_cq_out_bits {
5359 u8 reserved_at_8[0x18];
5363 u8 reserved_at_40[0x40];
5366 struct mlx5_ifc_destroy_cq_in_bits {
5368 u8 reserved_at_10[0x10];
5370 u8 reserved_at_20[0x10];
5373 u8 reserved_at_40[0x8];
5376 u8 reserved_at_60[0x20];
5379 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5381 u8 reserved_at_8[0x18];
5385 u8 reserved_at_40[0x40];
5388 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5390 u8 reserved_at_10[0x10];
5392 u8 reserved_at_20[0x10];
5395 u8 reserved_at_40[0x20];
5397 u8 reserved_at_60[0x10];
5398 u8 vxlan_udp_port[0x10];
5401 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5403 u8 reserved_at_8[0x18];
5407 u8 reserved_at_40[0x40];
5410 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5412 u8 reserved_at_10[0x10];
5414 u8 reserved_at_20[0x10];
5417 u8 reserved_at_40[0x60];
5419 u8 reserved_at_a0[0x8];
5420 u8 table_index[0x18];
5422 u8 reserved_at_c0[0x140];
5425 struct mlx5_ifc_delete_fte_out_bits {
5427 u8 reserved_at_8[0x18];
5431 u8 reserved_at_40[0x40];
5434 struct mlx5_ifc_delete_fte_in_bits {
5436 u8 reserved_at_10[0x10];
5438 u8 reserved_at_20[0x10];
5441 u8 other_vport[0x1];
5442 u8 reserved_at_41[0xf];
5443 u8 vport_number[0x10];
5445 u8 reserved_at_60[0x20];
5448 u8 reserved_at_88[0x18];
5450 u8 reserved_at_a0[0x8];
5453 u8 reserved_at_c0[0x40];
5455 u8 flow_index[0x20];
5457 u8 reserved_at_120[0xe0];
5460 struct mlx5_ifc_dealloc_xrcd_out_bits {
5462 u8 reserved_at_8[0x18];
5466 u8 reserved_at_40[0x40];
5469 struct mlx5_ifc_dealloc_xrcd_in_bits {
5471 u8 reserved_at_10[0x10];
5473 u8 reserved_at_20[0x10];
5476 u8 reserved_at_40[0x8];
5479 u8 reserved_at_60[0x20];
5482 struct mlx5_ifc_dealloc_uar_out_bits {
5484 u8 reserved_at_8[0x18];
5488 u8 reserved_at_40[0x40];
5491 struct mlx5_ifc_dealloc_uar_in_bits {
5493 u8 reserved_at_10[0x10];
5495 u8 reserved_at_20[0x10];
5498 u8 reserved_at_40[0x8];
5501 u8 reserved_at_60[0x20];
5504 struct mlx5_ifc_dealloc_transport_domain_out_bits {
5506 u8 reserved_at_8[0x18];
5510 u8 reserved_at_40[0x40];
5513 struct mlx5_ifc_dealloc_transport_domain_in_bits {
5515 u8 reserved_at_10[0x10];
5517 u8 reserved_at_20[0x10];
5520 u8 reserved_at_40[0x8];
5521 u8 transport_domain[0x18];
5523 u8 reserved_at_60[0x20];
5526 struct mlx5_ifc_dealloc_q_counter_out_bits {
5528 u8 reserved_at_8[0x18];
5532 u8 reserved_at_40[0x40];
5535 struct mlx5_ifc_dealloc_q_counter_in_bits {
5537 u8 reserved_at_10[0x10];
5539 u8 reserved_at_20[0x10];
5542 u8 reserved_at_40[0x18];
5543 u8 counter_set_id[0x8];
5545 u8 reserved_at_60[0x20];
5548 struct mlx5_ifc_dealloc_pd_out_bits {
5550 u8 reserved_at_8[0x18];
5554 u8 reserved_at_40[0x40];
5557 struct mlx5_ifc_dealloc_pd_in_bits {
5559 u8 reserved_at_10[0x10];
5561 u8 reserved_at_20[0x10];
5564 u8 reserved_at_40[0x8];
5567 u8 reserved_at_60[0x20];
5570 struct mlx5_ifc_dealloc_flow_counter_out_bits {
5572 u8 reserved_at_8[0x18];
5576 u8 reserved_at_40[0x40];
5579 struct mlx5_ifc_dealloc_flow_counter_in_bits {
5581 u8 reserved_at_10[0x10];
5583 u8 reserved_at_20[0x10];
5586 u8 reserved_at_40[0x10];
5587 u8 flow_counter_id[0x10];
5589 u8 reserved_at_60[0x20];
5592 struct mlx5_ifc_create_xrc_srq_out_bits {
5594 u8 reserved_at_8[0x18];
5598 u8 reserved_at_40[0x8];
5601 u8 reserved_at_60[0x20];
5604 struct mlx5_ifc_create_xrc_srq_in_bits {
5606 u8 reserved_at_10[0x10];
5608 u8 reserved_at_20[0x10];
5611 u8 reserved_at_40[0x40];
5613 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5615 u8 reserved_at_280[0x600];
5620 struct mlx5_ifc_create_tis_out_bits {
5622 u8 reserved_at_8[0x18];
5626 u8 reserved_at_40[0x8];
5629 u8 reserved_at_60[0x20];
5632 struct mlx5_ifc_create_tis_in_bits {
5634 u8 reserved_at_10[0x10];
5636 u8 reserved_at_20[0x10];
5639 u8 reserved_at_40[0xc0];
5641 struct mlx5_ifc_tisc_bits ctx;
5644 struct mlx5_ifc_create_tir_out_bits {
5646 u8 reserved_at_8[0x18];
5650 u8 reserved_at_40[0x8];
5653 u8 reserved_at_60[0x20];
5656 struct mlx5_ifc_create_tir_in_bits {
5658 u8 reserved_at_10[0x10];
5660 u8 reserved_at_20[0x10];
5663 u8 reserved_at_40[0xc0];
5665 struct mlx5_ifc_tirc_bits ctx;
5668 struct mlx5_ifc_create_srq_out_bits {
5670 u8 reserved_at_8[0x18];
5674 u8 reserved_at_40[0x8];
5677 u8 reserved_at_60[0x20];
5680 struct mlx5_ifc_create_srq_in_bits {
5682 u8 reserved_at_10[0x10];
5684 u8 reserved_at_20[0x10];
5687 u8 reserved_at_40[0x40];
5689 struct mlx5_ifc_srqc_bits srq_context_entry;
5691 u8 reserved_at_280[0x600];
5696 struct mlx5_ifc_create_sq_out_bits {
5698 u8 reserved_at_8[0x18];
5702 u8 reserved_at_40[0x8];
5705 u8 reserved_at_60[0x20];
5708 struct mlx5_ifc_create_sq_in_bits {
5710 u8 reserved_at_10[0x10];
5712 u8 reserved_at_20[0x10];
5715 u8 reserved_at_40[0xc0];
5717 struct mlx5_ifc_sqc_bits ctx;
5720 struct mlx5_ifc_create_rqt_out_bits {
5722 u8 reserved_at_8[0x18];
5726 u8 reserved_at_40[0x8];
5729 u8 reserved_at_60[0x20];
5732 struct mlx5_ifc_create_rqt_in_bits {
5734 u8 reserved_at_10[0x10];
5736 u8 reserved_at_20[0x10];
5739 u8 reserved_at_40[0xc0];
5741 struct mlx5_ifc_rqtc_bits rqt_context;
5744 struct mlx5_ifc_create_rq_out_bits {
5746 u8 reserved_at_8[0x18];
5750 u8 reserved_at_40[0x8];
5753 u8 reserved_at_60[0x20];
5756 struct mlx5_ifc_create_rq_in_bits {
5758 u8 reserved_at_10[0x10];
5760 u8 reserved_at_20[0x10];
5763 u8 reserved_at_40[0xc0];
5765 struct mlx5_ifc_rqc_bits ctx;
5768 struct mlx5_ifc_create_rmp_out_bits {
5770 u8 reserved_at_8[0x18];
5774 u8 reserved_at_40[0x8];
5777 u8 reserved_at_60[0x20];
5780 struct mlx5_ifc_create_rmp_in_bits {
5782 u8 reserved_at_10[0x10];
5784 u8 reserved_at_20[0x10];
5787 u8 reserved_at_40[0xc0];
5789 struct mlx5_ifc_rmpc_bits ctx;
5792 struct mlx5_ifc_create_qp_out_bits {
5794 u8 reserved_at_8[0x18];
5798 u8 reserved_at_40[0x8];
5801 u8 reserved_at_60[0x20];
5804 struct mlx5_ifc_create_qp_in_bits {
5806 u8 reserved_at_10[0x10];
5808 u8 reserved_at_20[0x10];
5811 u8 reserved_at_40[0x40];
5813 u8 opt_param_mask[0x20];
5815 u8 reserved_at_a0[0x20];
5817 struct mlx5_ifc_qpc_bits qpc;
5819 u8 reserved_at_800[0x80];
5824 struct mlx5_ifc_create_psv_out_bits {
5826 u8 reserved_at_8[0x18];
5830 u8 reserved_at_40[0x40];
5832 u8 reserved_at_80[0x8];
5833 u8 psv0_index[0x18];
5835 u8 reserved_at_a0[0x8];
5836 u8 psv1_index[0x18];
5838 u8 reserved_at_c0[0x8];
5839 u8 psv2_index[0x18];
5841 u8 reserved_at_e0[0x8];
5842 u8 psv3_index[0x18];
5845 struct mlx5_ifc_create_psv_in_bits {
5847 u8 reserved_at_10[0x10];
5849 u8 reserved_at_20[0x10];
5853 u8 reserved_at_44[0x4];
5856 u8 reserved_at_60[0x20];
5859 struct mlx5_ifc_create_mkey_out_bits {
5861 u8 reserved_at_8[0x18];
5865 u8 reserved_at_40[0x8];
5866 u8 mkey_index[0x18];
5868 u8 reserved_at_60[0x20];
5871 struct mlx5_ifc_create_mkey_in_bits {
5873 u8 reserved_at_10[0x10];
5875 u8 reserved_at_20[0x10];
5878 u8 reserved_at_40[0x20];
5881 u8 reserved_at_61[0x1f];
5883 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5885 u8 reserved_at_280[0x80];
5887 u8 translations_octword_actual_size[0x20];
5889 u8 reserved_at_320[0x560];
5891 u8 klm_pas_mtt[0][0x20];
5894 struct mlx5_ifc_create_flow_table_out_bits {
5896 u8 reserved_at_8[0x18];
5900 u8 reserved_at_40[0x8];
5903 u8 reserved_at_60[0x20];
5906 struct mlx5_ifc_create_flow_table_in_bits {
5908 u8 reserved_at_10[0x10];
5910 u8 reserved_at_20[0x10];
5913 u8 other_vport[0x1];
5914 u8 reserved_at_41[0xf];
5915 u8 vport_number[0x10];
5917 u8 reserved_at_60[0x20];
5920 u8 reserved_at_88[0x18];
5922 u8 reserved_at_a0[0x20];
5924 u8 reserved_at_c0[0x4];
5925 u8 table_miss_mode[0x4];
5927 u8 reserved_at_d0[0x8];
5930 u8 reserved_at_e0[0x8];
5931 u8 table_miss_id[0x18];
5933 u8 reserved_at_100[0x100];
5936 struct mlx5_ifc_create_flow_group_out_bits {
5938 u8 reserved_at_8[0x18];
5942 u8 reserved_at_40[0x8];
5945 u8 reserved_at_60[0x20];
5949 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5950 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5951 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
5954 struct mlx5_ifc_create_flow_group_in_bits {
5956 u8 reserved_at_10[0x10];
5958 u8 reserved_at_20[0x10];
5961 u8 other_vport[0x1];
5962 u8 reserved_at_41[0xf];
5963 u8 vport_number[0x10];
5965 u8 reserved_at_60[0x20];
5968 u8 reserved_at_88[0x18];
5970 u8 reserved_at_a0[0x8];
5973 u8 reserved_at_c0[0x20];
5975 u8 start_flow_index[0x20];
5977 u8 reserved_at_100[0x20];
5979 u8 end_flow_index[0x20];
5981 u8 reserved_at_140[0xa0];
5983 u8 reserved_at_1e0[0x18];
5984 u8 match_criteria_enable[0x8];
5986 struct mlx5_ifc_fte_match_param_bits match_criteria;
5988 u8 reserved_at_1200[0xe00];
5991 struct mlx5_ifc_create_eq_out_bits {
5993 u8 reserved_at_8[0x18];
5997 u8 reserved_at_40[0x18];
6000 u8 reserved_at_60[0x20];
6003 struct mlx5_ifc_create_eq_in_bits {
6005 u8 reserved_at_10[0x10];
6007 u8 reserved_at_20[0x10];
6010 u8 reserved_at_40[0x40];
6012 struct mlx5_ifc_eqc_bits eq_context_entry;
6014 u8 reserved_at_280[0x40];
6016 u8 event_bitmask[0x40];
6018 u8 reserved_at_300[0x580];
6023 struct mlx5_ifc_create_dct_out_bits {
6025 u8 reserved_at_8[0x18];
6029 u8 reserved_at_40[0x8];
6032 u8 reserved_at_60[0x20];
6035 struct mlx5_ifc_create_dct_in_bits {
6037 u8 reserved_at_10[0x10];
6039 u8 reserved_at_20[0x10];
6042 u8 reserved_at_40[0x40];
6044 struct mlx5_ifc_dctc_bits dct_context_entry;
6046 u8 reserved_at_280[0x180];
6049 struct mlx5_ifc_create_cq_out_bits {
6051 u8 reserved_at_8[0x18];
6055 u8 reserved_at_40[0x8];
6058 u8 reserved_at_60[0x20];
6061 struct mlx5_ifc_create_cq_in_bits {
6063 u8 reserved_at_10[0x10];
6065 u8 reserved_at_20[0x10];
6068 u8 reserved_at_40[0x40];
6070 struct mlx5_ifc_cqc_bits cq_context;
6072 u8 reserved_at_280[0x600];
6077 struct mlx5_ifc_config_int_moderation_out_bits {
6079 u8 reserved_at_8[0x18];
6083 u8 reserved_at_40[0x4];
6085 u8 int_vector[0x10];
6087 u8 reserved_at_60[0x20];
6091 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
6092 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
6095 struct mlx5_ifc_config_int_moderation_in_bits {
6097 u8 reserved_at_10[0x10];
6099 u8 reserved_at_20[0x10];
6102 u8 reserved_at_40[0x4];
6104 u8 int_vector[0x10];
6106 u8 reserved_at_60[0x20];
6109 struct mlx5_ifc_attach_to_mcg_out_bits {
6111 u8 reserved_at_8[0x18];
6115 u8 reserved_at_40[0x40];
6118 struct mlx5_ifc_attach_to_mcg_in_bits {
6120 u8 reserved_at_10[0x10];
6122 u8 reserved_at_20[0x10];
6125 u8 reserved_at_40[0x8];
6128 u8 reserved_at_60[0x20];
6130 u8 multicast_gid[16][0x8];
6133 struct mlx5_ifc_arm_xrc_srq_out_bits {
6135 u8 reserved_at_8[0x18];
6139 u8 reserved_at_40[0x40];
6143 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
6146 struct mlx5_ifc_arm_xrc_srq_in_bits {
6148 u8 reserved_at_10[0x10];
6150 u8 reserved_at_20[0x10];
6153 u8 reserved_at_40[0x8];
6156 u8 reserved_at_60[0x10];
6160 struct mlx5_ifc_arm_rq_out_bits {
6162 u8 reserved_at_8[0x18];
6166 u8 reserved_at_40[0x40];
6170 MLX5_ARM_RQ_IN_OP_MOD_SRQ_ = 0x1,
6173 struct mlx5_ifc_arm_rq_in_bits {
6175 u8 reserved_at_10[0x10];
6177 u8 reserved_at_20[0x10];
6180 u8 reserved_at_40[0x8];
6181 u8 srq_number[0x18];
6183 u8 reserved_at_60[0x10];
6187 struct mlx5_ifc_arm_dct_out_bits {
6189 u8 reserved_at_8[0x18];
6193 u8 reserved_at_40[0x40];
6196 struct mlx5_ifc_arm_dct_in_bits {
6198 u8 reserved_at_10[0x10];
6200 u8 reserved_at_20[0x10];
6203 u8 reserved_at_40[0x8];
6204 u8 dct_number[0x18];
6206 u8 reserved_at_60[0x20];
6209 struct mlx5_ifc_alloc_xrcd_out_bits {
6211 u8 reserved_at_8[0x18];
6215 u8 reserved_at_40[0x8];
6218 u8 reserved_at_60[0x20];
6221 struct mlx5_ifc_alloc_xrcd_in_bits {
6223 u8 reserved_at_10[0x10];
6225 u8 reserved_at_20[0x10];
6228 u8 reserved_at_40[0x40];
6231 struct mlx5_ifc_alloc_uar_out_bits {
6233 u8 reserved_at_8[0x18];
6237 u8 reserved_at_40[0x8];
6240 u8 reserved_at_60[0x20];
6243 struct mlx5_ifc_alloc_uar_in_bits {
6245 u8 reserved_at_10[0x10];
6247 u8 reserved_at_20[0x10];
6250 u8 reserved_at_40[0x40];
6253 struct mlx5_ifc_alloc_transport_domain_out_bits {
6255 u8 reserved_at_8[0x18];
6259 u8 reserved_at_40[0x8];
6260 u8 transport_domain[0x18];
6262 u8 reserved_at_60[0x20];
6265 struct mlx5_ifc_alloc_transport_domain_in_bits {
6267 u8 reserved_at_10[0x10];
6269 u8 reserved_at_20[0x10];
6272 u8 reserved_at_40[0x40];
6275 struct mlx5_ifc_alloc_q_counter_out_bits {
6277 u8 reserved_at_8[0x18];
6281 u8 reserved_at_40[0x18];
6282 u8 counter_set_id[0x8];
6284 u8 reserved_at_60[0x20];
6287 struct mlx5_ifc_alloc_q_counter_in_bits {
6289 u8 reserved_at_10[0x10];
6291 u8 reserved_at_20[0x10];
6294 u8 reserved_at_40[0x40];
6297 struct mlx5_ifc_alloc_pd_out_bits {
6299 u8 reserved_at_8[0x18];
6303 u8 reserved_at_40[0x8];
6306 u8 reserved_at_60[0x20];
6309 struct mlx5_ifc_alloc_pd_in_bits {
6311 u8 reserved_at_10[0x10];
6313 u8 reserved_at_20[0x10];
6316 u8 reserved_at_40[0x40];
6319 struct mlx5_ifc_alloc_flow_counter_out_bits {
6321 u8 reserved_at_8[0x18];
6325 u8 reserved_at_40[0x10];
6326 u8 flow_counter_id[0x10];
6328 u8 reserved_at_60[0x20];
6331 struct mlx5_ifc_alloc_flow_counter_in_bits {
6333 u8 reserved_at_10[0x10];
6335 u8 reserved_at_20[0x10];
6338 u8 reserved_at_40[0x40];
6341 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6343 u8 reserved_at_8[0x18];
6347 u8 reserved_at_40[0x40];
6350 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6352 u8 reserved_at_10[0x10];
6354 u8 reserved_at_20[0x10];
6357 u8 reserved_at_40[0x20];
6359 u8 reserved_at_60[0x10];
6360 u8 vxlan_udp_port[0x10];
6363 struct mlx5_ifc_access_register_out_bits {
6365 u8 reserved_at_8[0x18];
6369 u8 reserved_at_40[0x40];
6371 u8 register_data[0][0x20];
6375 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
6376 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
6379 struct mlx5_ifc_access_register_in_bits {
6381 u8 reserved_at_10[0x10];
6383 u8 reserved_at_20[0x10];
6386 u8 reserved_at_40[0x10];
6387 u8 register_id[0x10];
6391 u8 register_data[0][0x20];
6394 struct mlx5_ifc_sltp_reg_bits {
6399 u8 reserved_at_12[0x2];
6401 u8 reserved_at_18[0x8];
6403 u8 reserved_at_20[0x20];
6405 u8 reserved_at_40[0x7];
6411 u8 reserved_at_60[0xc];
6412 u8 ob_preemp_mode[0x4];
6416 u8 reserved_at_80[0x20];
6419 struct mlx5_ifc_slrg_reg_bits {
6424 u8 reserved_at_12[0x2];
6426 u8 reserved_at_18[0x8];
6428 u8 time_to_link_up[0x10];
6429 u8 reserved_at_30[0xc];
6430 u8 grade_lane_speed[0x4];
6432 u8 grade_version[0x8];
6435 u8 reserved_at_60[0x4];
6436 u8 height_grade_type[0x4];
6437 u8 height_grade[0x18];
6442 u8 reserved_at_a0[0x10];
6443 u8 height_sigma[0x10];
6445 u8 reserved_at_c0[0x20];
6447 u8 reserved_at_e0[0x4];
6448 u8 phase_grade_type[0x4];
6449 u8 phase_grade[0x18];
6451 u8 reserved_at_100[0x8];
6452 u8 phase_eo_pos[0x8];
6453 u8 reserved_at_110[0x8];
6454 u8 phase_eo_neg[0x8];
6456 u8 ffe_set_tested[0x10];
6457 u8 test_errors_per_lane[0x10];
6460 struct mlx5_ifc_pvlc_reg_bits {
6461 u8 reserved_at_0[0x8];
6463 u8 reserved_at_10[0x10];
6465 u8 reserved_at_20[0x1c];
6468 u8 reserved_at_40[0x1c];
6471 u8 reserved_at_60[0x1c];
6472 u8 vl_operational[0x4];
6475 struct mlx5_ifc_pude_reg_bits {
6478 u8 reserved_at_10[0x4];
6479 u8 admin_status[0x4];
6480 u8 reserved_at_18[0x4];
6481 u8 oper_status[0x4];
6483 u8 reserved_at_20[0x60];
6486 struct mlx5_ifc_ptys_reg_bits {
6487 u8 reserved_at_0[0x8];
6489 u8 reserved_at_10[0xd];
6492 u8 reserved_at_20[0x40];
6494 u8 eth_proto_capability[0x20];
6496 u8 ib_link_width_capability[0x10];
6497 u8 ib_proto_capability[0x10];
6499 u8 reserved_at_a0[0x20];
6501 u8 eth_proto_admin[0x20];
6503 u8 ib_link_width_admin[0x10];
6504 u8 ib_proto_admin[0x10];
6506 u8 reserved_at_100[0x20];
6508 u8 eth_proto_oper[0x20];
6510 u8 ib_link_width_oper[0x10];
6511 u8 ib_proto_oper[0x10];
6513 u8 reserved_at_160[0x20];
6515 u8 eth_proto_lp_advertise[0x20];
6517 u8 reserved_at_1a0[0x60];
6520 struct mlx5_ifc_mlcr_reg_bits {
6521 u8 reserved_at_0[0x8];
6523 u8 reserved_at_10[0x20];
6525 u8 beacon_duration[0x10];
6526 u8 reserved_at_40[0x10];
6528 u8 beacon_remain[0x10];
6531 struct mlx5_ifc_ptas_reg_bits {
6532 u8 reserved_at_0[0x20];
6534 u8 algorithm_options[0x10];
6535 u8 reserved_at_30[0x4];
6536 u8 repetitions_mode[0x4];
6537 u8 num_of_repetitions[0x8];
6539 u8 grade_version[0x8];
6540 u8 height_grade_type[0x4];
6541 u8 phase_grade_type[0x4];
6542 u8 height_grade_weight[0x8];
6543 u8 phase_grade_weight[0x8];
6545 u8 gisim_measure_bits[0x10];
6546 u8 adaptive_tap_measure_bits[0x10];
6548 u8 ber_bath_high_error_threshold[0x10];
6549 u8 ber_bath_mid_error_threshold[0x10];
6551 u8 ber_bath_low_error_threshold[0x10];
6552 u8 one_ratio_high_threshold[0x10];
6554 u8 one_ratio_high_mid_threshold[0x10];
6555 u8 one_ratio_low_mid_threshold[0x10];
6557 u8 one_ratio_low_threshold[0x10];
6558 u8 ndeo_error_threshold[0x10];
6560 u8 mixer_offset_step_size[0x10];
6561 u8 reserved_at_110[0x8];
6562 u8 mix90_phase_for_voltage_bath[0x8];
6564 u8 mixer_offset_start[0x10];
6565 u8 mixer_offset_end[0x10];
6567 u8 reserved_at_140[0x15];
6568 u8 ber_test_time[0xb];
6571 struct mlx5_ifc_pspa_reg_bits {
6575 u8 reserved_at_18[0x8];
6577 u8 reserved_at_20[0x20];
6580 struct mlx5_ifc_pqdr_reg_bits {
6581 u8 reserved_at_0[0x8];
6583 u8 reserved_at_10[0x5];
6585 u8 reserved_at_18[0x6];
6588 u8 reserved_at_20[0x20];
6590 u8 reserved_at_40[0x10];
6591 u8 min_threshold[0x10];
6593 u8 reserved_at_60[0x10];
6594 u8 max_threshold[0x10];
6596 u8 reserved_at_80[0x10];
6597 u8 mark_probability_denominator[0x10];
6599 u8 reserved_at_a0[0x60];
6602 struct mlx5_ifc_ppsc_reg_bits {
6603 u8 reserved_at_0[0x8];
6605 u8 reserved_at_10[0x10];
6607 u8 reserved_at_20[0x60];
6609 u8 reserved_at_80[0x1c];
6612 u8 reserved_at_a0[0x1c];
6613 u8 wrps_status[0x4];
6615 u8 reserved_at_c0[0x8];
6616 u8 up_threshold[0x8];
6617 u8 reserved_at_d0[0x8];
6618 u8 down_threshold[0x8];
6620 u8 reserved_at_e0[0x20];
6622 u8 reserved_at_100[0x1c];
6625 u8 reserved_at_120[0x1c];
6626 u8 srps_status[0x4];
6628 u8 reserved_at_140[0x40];
6631 struct mlx5_ifc_pplr_reg_bits {
6632 u8 reserved_at_0[0x8];
6634 u8 reserved_at_10[0x10];
6636 u8 reserved_at_20[0x8];
6638 u8 reserved_at_30[0x8];
6642 struct mlx5_ifc_pplm_reg_bits {
6643 u8 reserved_at_0[0x8];
6645 u8 reserved_at_10[0x10];
6647 u8 reserved_at_20[0x20];
6649 u8 port_profile_mode[0x8];
6650 u8 static_port_profile[0x8];
6651 u8 active_port_profile[0x8];
6652 u8 reserved_at_58[0x8];
6654 u8 retransmission_active[0x8];
6655 u8 fec_mode_active[0x18];
6657 u8 reserved_at_80[0x20];
6660 struct mlx5_ifc_ppcnt_reg_bits {
6664 u8 reserved_at_12[0x8];
6668 u8 reserved_at_21[0x1c];
6671 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6674 struct mlx5_ifc_ppad_reg_bits {
6675 u8 reserved_at_0[0x3];
6677 u8 reserved_at_4[0x4];
6683 u8 reserved_at_40[0x40];
6686 struct mlx5_ifc_pmtu_reg_bits {
6687 u8 reserved_at_0[0x8];
6689 u8 reserved_at_10[0x10];
6692 u8 reserved_at_30[0x10];
6695 u8 reserved_at_50[0x10];
6698 u8 reserved_at_70[0x10];
6701 struct mlx5_ifc_pmpr_reg_bits {
6702 u8 reserved_at_0[0x8];
6704 u8 reserved_at_10[0x10];
6706 u8 reserved_at_20[0x18];
6707 u8 attenuation_5g[0x8];
6709 u8 reserved_at_40[0x18];
6710 u8 attenuation_7g[0x8];
6712 u8 reserved_at_60[0x18];
6713 u8 attenuation_12g[0x8];
6716 struct mlx5_ifc_pmpe_reg_bits {
6717 u8 reserved_at_0[0x8];
6719 u8 reserved_at_10[0xc];
6720 u8 module_status[0x4];
6722 u8 reserved_at_20[0x60];
6725 struct mlx5_ifc_pmpc_reg_bits {
6726 u8 module_state_updated[32][0x8];
6729 struct mlx5_ifc_pmlpn_reg_bits {
6730 u8 reserved_at_0[0x4];
6731 u8 mlpn_status[0x4];
6733 u8 reserved_at_10[0x10];
6736 u8 reserved_at_21[0x1f];
6739 struct mlx5_ifc_pmlp_reg_bits {
6741 u8 reserved_at_1[0x7];
6743 u8 reserved_at_10[0x8];
6746 u8 lane0_module_mapping[0x20];
6748 u8 lane1_module_mapping[0x20];
6750 u8 lane2_module_mapping[0x20];
6752 u8 lane3_module_mapping[0x20];
6754 u8 reserved_at_a0[0x160];
6757 struct mlx5_ifc_pmaos_reg_bits {
6758 u8 reserved_at_0[0x8];
6760 u8 reserved_at_10[0x4];
6761 u8 admin_status[0x4];
6762 u8 reserved_at_18[0x4];
6763 u8 oper_status[0x4];
6767 u8 reserved_at_22[0x1c];
6770 u8 reserved_at_40[0x40];
6773 struct mlx5_ifc_plpc_reg_bits {
6774 u8 reserved_at_0[0x4];
6776 u8 reserved_at_10[0x4];
6778 u8 reserved_at_18[0x8];
6780 u8 reserved_at_20[0x10];
6781 u8 lane_speed[0x10];
6783 u8 reserved_at_40[0x17];
6785 u8 fec_mode_policy[0x8];
6787 u8 retransmission_capability[0x8];
6788 u8 fec_mode_capability[0x18];
6790 u8 retransmission_support_admin[0x8];
6791 u8 fec_mode_support_admin[0x18];
6793 u8 retransmission_request_admin[0x8];
6794 u8 fec_mode_request_admin[0x18];
6796 u8 reserved_at_c0[0x80];
6799 struct mlx5_ifc_plib_reg_bits {
6800 u8 reserved_at_0[0x8];
6802 u8 reserved_at_10[0x8];
6805 u8 reserved_at_20[0x60];
6808 struct mlx5_ifc_plbf_reg_bits {
6809 u8 reserved_at_0[0x8];
6811 u8 reserved_at_10[0xd];
6814 u8 reserved_at_20[0x20];
6817 struct mlx5_ifc_pipg_reg_bits {
6818 u8 reserved_at_0[0x8];
6820 u8 reserved_at_10[0x10];
6823 u8 reserved_at_21[0x19];
6825 u8 reserved_at_3e[0x2];
6828 struct mlx5_ifc_pifr_reg_bits {
6829 u8 reserved_at_0[0x8];
6831 u8 reserved_at_10[0x10];
6833 u8 reserved_at_20[0xe0];
6835 u8 port_filter[8][0x20];
6837 u8 port_filter_update_en[8][0x20];
6840 struct mlx5_ifc_pfcc_reg_bits {
6841 u8 reserved_at_0[0x8];
6843 u8 reserved_at_10[0x10];
6846 u8 reserved_at_24[0x4];
6847 u8 prio_mask_tx[0x8];
6848 u8 reserved_at_30[0x8];
6849 u8 prio_mask_rx[0x8];
6853 u8 reserved_at_42[0x6];
6855 u8 reserved_at_50[0x10];
6859 u8 reserved_at_62[0x6];
6861 u8 reserved_at_70[0x10];
6863 u8 reserved_at_80[0x80];
6866 struct mlx5_ifc_pelc_reg_bits {
6868 u8 reserved_at_4[0x4];
6870 u8 reserved_at_10[0x10];
6873 u8 op_capability[0x8];
6879 u8 capability[0x40];
6885 u8 reserved_at_140[0x80];
6888 struct mlx5_ifc_peir_reg_bits {
6889 u8 reserved_at_0[0x8];
6891 u8 reserved_at_10[0x10];
6893 u8 reserved_at_20[0xc];
6894 u8 error_count[0x4];
6895 u8 reserved_at_30[0x10];
6897 u8 reserved_at_40[0xc];
6899 u8 reserved_at_50[0x8];
6903 struct mlx5_ifc_pcap_reg_bits {
6904 u8 reserved_at_0[0x8];
6906 u8 reserved_at_10[0x10];
6908 u8 port_capability_mask[4][0x20];
6911 struct mlx5_ifc_paos_reg_bits {
6914 u8 reserved_at_10[0x4];
6915 u8 admin_status[0x4];
6916 u8 reserved_at_18[0x4];
6917 u8 oper_status[0x4];
6921 u8 reserved_at_22[0x1c];
6924 u8 reserved_at_40[0x40];
6927 struct mlx5_ifc_pamp_reg_bits {
6928 u8 reserved_at_0[0x8];
6929 u8 opamp_group[0x8];
6930 u8 reserved_at_10[0xc];
6931 u8 opamp_group_type[0x4];
6933 u8 start_index[0x10];
6934 u8 reserved_at_30[0x4];
6935 u8 num_of_indices[0xc];
6937 u8 index_data[18][0x10];
6940 struct mlx5_ifc_pcmr_reg_bits {
6941 u8 reserved_at_0[0x8];
6943 u8 reserved_at_10[0x2e];
6945 u8 reserved_at_3f[0x1f];
6947 u8 reserved_at_5f[0x1];
6950 struct mlx5_ifc_lane_2_module_mapping_bits {
6951 u8 reserved_at_0[0x6];
6953 u8 reserved_at_8[0x6];
6955 u8 reserved_at_10[0x8];
6959 struct mlx5_ifc_bufferx_reg_bits {
6960 u8 reserved_at_0[0x6];
6963 u8 reserved_at_8[0xc];
6966 u8 xoff_threshold[0x10];
6967 u8 xon_threshold[0x10];
6970 struct mlx5_ifc_set_node_in_bits {
6971 u8 node_description[64][0x8];
6974 struct mlx5_ifc_register_power_settings_bits {
6975 u8 reserved_at_0[0x18];
6976 u8 power_settings_level[0x8];
6978 u8 reserved_at_20[0x60];
6981 struct mlx5_ifc_register_host_endianness_bits {
6983 u8 reserved_at_1[0x1f];
6985 u8 reserved_at_20[0x60];
6988 struct mlx5_ifc_umr_pointer_desc_argument_bits {
6989 u8 reserved_at_0[0x20];
6993 u8 addressh_63_32[0x20];
6995 u8 addressl_31_0[0x20];
6998 struct mlx5_ifc_ud_adrs_vector_bits {
7002 u8 reserved_at_41[0x7];
7003 u8 destination_qp_dct[0x18];
7005 u8 static_rate[0x4];
7006 u8 sl_eth_prio[0x4];
7009 u8 rlid_udp_sport[0x10];
7011 u8 reserved_at_80[0x20];
7013 u8 rmac_47_16[0x20];
7019 u8 reserved_at_e0[0x1];
7021 u8 reserved_at_e2[0x2];
7022 u8 src_addr_index[0x8];
7023 u8 flow_label[0x14];
7025 u8 rgid_rip[16][0x8];
7028 struct mlx5_ifc_pages_req_event_bits {
7029 u8 reserved_at_0[0x10];
7030 u8 function_id[0x10];
7034 u8 reserved_at_40[0xa0];
7037 struct mlx5_ifc_eqe_bits {
7038 u8 reserved_at_0[0x8];
7040 u8 reserved_at_10[0x8];
7041 u8 event_sub_type[0x8];
7043 u8 reserved_at_20[0xe0];
7045 union mlx5_ifc_event_auto_bits event_data;
7047 u8 reserved_at_1e0[0x10];
7049 u8 reserved_at_1f8[0x7];
7054 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
7057 struct mlx5_ifc_cmd_queue_entry_bits {
7059 u8 reserved_at_8[0x18];
7061 u8 input_length[0x20];
7063 u8 input_mailbox_pointer_63_32[0x20];
7065 u8 input_mailbox_pointer_31_9[0x17];
7066 u8 reserved_at_77[0x9];
7068 u8 command_input_inline_data[16][0x8];
7070 u8 command_output_inline_data[16][0x8];
7072 u8 output_mailbox_pointer_63_32[0x20];
7074 u8 output_mailbox_pointer_31_9[0x17];
7075 u8 reserved_at_1b7[0x9];
7077 u8 output_length[0x20];
7081 u8 reserved_at_1f0[0x8];
7086 struct mlx5_ifc_cmd_out_bits {
7088 u8 reserved_at_8[0x18];
7092 u8 command_output[0x20];
7095 struct mlx5_ifc_cmd_in_bits {
7097 u8 reserved_at_10[0x10];
7099 u8 reserved_at_20[0x10];
7102 u8 command[0][0x20];
7105 struct mlx5_ifc_cmd_if_box_bits {
7106 u8 mailbox_data[512][0x8];
7108 u8 reserved_at_1000[0x180];
7110 u8 next_pointer_63_32[0x20];
7112 u8 next_pointer_31_10[0x16];
7113 u8 reserved_at_11b6[0xa];
7115 u8 block_number[0x20];
7117 u8 reserved_at_11e0[0x8];
7119 u8 ctrl_signature[0x8];
7123 struct mlx5_ifc_mtt_bits {
7124 u8 ptag_63_32[0x20];
7127 u8 reserved_at_38[0x6];
7132 struct mlx5_ifc_query_wol_rol_out_bits {
7134 u8 reserved_at_8[0x18];
7138 u8 reserved_at_40[0x10];
7142 u8 reserved_at_60[0x20];
7145 struct mlx5_ifc_query_wol_rol_in_bits {
7147 u8 reserved_at_10[0x10];
7149 u8 reserved_at_20[0x10];
7152 u8 reserved_at_40[0x40];
7155 struct mlx5_ifc_set_wol_rol_out_bits {
7157 u8 reserved_at_8[0x18];
7161 u8 reserved_at_40[0x40];
7164 struct mlx5_ifc_set_wol_rol_in_bits {
7166 u8 reserved_at_10[0x10];
7168 u8 reserved_at_20[0x10];
7171 u8 rol_mode_valid[0x1];
7172 u8 wol_mode_valid[0x1];
7173 u8 reserved_at_42[0xe];
7177 u8 reserved_at_60[0x20];
7181 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
7182 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
7183 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
7187 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
7188 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
7189 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
7193 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
7194 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
7195 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
7196 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
7197 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
7198 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
7199 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
7200 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
7201 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
7202 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
7203 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
7206 struct mlx5_ifc_initial_seg_bits {
7207 u8 fw_rev_minor[0x10];
7208 u8 fw_rev_major[0x10];
7210 u8 cmd_interface_rev[0x10];
7211 u8 fw_rev_subminor[0x10];
7213 u8 reserved_at_40[0x40];
7215 u8 cmdq_phy_addr_63_32[0x20];
7217 u8 cmdq_phy_addr_31_12[0x14];
7218 u8 reserved_at_b4[0x2];
7219 u8 nic_interface[0x2];
7220 u8 log_cmdq_size[0x4];
7221 u8 log_cmdq_stride[0x4];
7223 u8 command_doorbell_vector[0x20];
7225 u8 reserved_at_e0[0xf00];
7227 u8 initializing[0x1];
7228 u8 reserved_at_fe1[0x4];
7229 u8 nic_interface_supported[0x3];
7230 u8 reserved_at_fe8[0x18];
7232 struct mlx5_ifc_health_buffer_bits health_buffer;
7234 u8 no_dram_nic_offset[0x20];
7236 u8 reserved_at_1220[0x6e40];
7238 u8 reserved_at_8060[0x1f];
7241 u8 health_syndrome[0x8];
7242 u8 health_counter[0x18];
7244 u8 reserved_at_80a0[0x17fc0];
7247 union mlx5_ifc_ports_control_registers_document_bits {
7248 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
7249 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
7250 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
7251 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
7252 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
7253 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
7254 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
7255 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
7256 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
7257 struct mlx5_ifc_pamp_reg_bits pamp_reg;
7258 struct mlx5_ifc_paos_reg_bits paos_reg;
7259 struct mlx5_ifc_pcap_reg_bits pcap_reg;
7260 struct mlx5_ifc_peir_reg_bits peir_reg;
7261 struct mlx5_ifc_pelc_reg_bits pelc_reg;
7262 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
7263 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
7264 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
7265 struct mlx5_ifc_pifr_reg_bits pifr_reg;
7266 struct mlx5_ifc_pipg_reg_bits pipg_reg;
7267 struct mlx5_ifc_plbf_reg_bits plbf_reg;
7268 struct mlx5_ifc_plib_reg_bits plib_reg;
7269 struct mlx5_ifc_plpc_reg_bits plpc_reg;
7270 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
7271 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
7272 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
7273 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
7274 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
7275 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
7276 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
7277 struct mlx5_ifc_ppad_reg_bits ppad_reg;
7278 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
7279 struct mlx5_ifc_pplm_reg_bits pplm_reg;
7280 struct mlx5_ifc_pplr_reg_bits pplr_reg;
7281 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
7282 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
7283 struct mlx5_ifc_pspa_reg_bits pspa_reg;
7284 struct mlx5_ifc_ptas_reg_bits ptas_reg;
7285 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7286 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
7287 struct mlx5_ifc_pude_reg_bits pude_reg;
7288 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
7289 struct mlx5_ifc_slrg_reg_bits slrg_reg;
7290 struct mlx5_ifc_sltp_reg_bits sltp_reg;
7291 u8 reserved_at_0[0x60e0];
7294 union mlx5_ifc_debug_enhancements_document_bits {
7295 struct mlx5_ifc_health_buffer_bits health_buffer;
7296 u8 reserved_at_0[0x200];
7299 union mlx5_ifc_uplink_pci_interface_document_bits {
7300 struct mlx5_ifc_initial_seg_bits initial_seg;
7301 u8 reserved_at_0[0x20060];
7304 struct mlx5_ifc_set_flow_table_root_out_bits {
7306 u8 reserved_at_8[0x18];
7310 u8 reserved_at_40[0x40];
7313 struct mlx5_ifc_set_flow_table_root_in_bits {
7315 u8 reserved_at_10[0x10];
7317 u8 reserved_at_20[0x10];
7320 u8 other_vport[0x1];
7321 u8 reserved_at_41[0xf];
7322 u8 vport_number[0x10];
7324 u8 reserved_at_60[0x20];
7327 u8 reserved_at_88[0x18];
7329 u8 reserved_at_a0[0x8];
7332 u8 reserved_at_c0[0x140];
7336 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = 0x1,
7339 struct mlx5_ifc_modify_flow_table_out_bits {
7341 u8 reserved_at_8[0x18];
7345 u8 reserved_at_40[0x40];
7348 struct mlx5_ifc_modify_flow_table_in_bits {
7350 u8 reserved_at_10[0x10];
7352 u8 reserved_at_20[0x10];
7355 u8 other_vport[0x1];
7356 u8 reserved_at_41[0xf];
7357 u8 vport_number[0x10];
7359 u8 reserved_at_60[0x10];
7360 u8 modify_field_select[0x10];
7363 u8 reserved_at_88[0x18];
7365 u8 reserved_at_a0[0x8];
7368 u8 reserved_at_c0[0x4];
7369 u8 table_miss_mode[0x4];
7370 u8 reserved_at_c8[0x18];
7372 u8 reserved_at_e0[0x8];
7373 u8 table_miss_id[0x18];
7375 u8 reserved_at_100[0x100];
7378 struct mlx5_ifc_ets_tcn_config_reg_bits {
7382 u8 reserved_at_3[0x9];
7384 u8 reserved_at_10[0x9];
7385 u8 bw_allocation[0x7];
7387 u8 reserved_at_20[0xc];
7388 u8 max_bw_units[0x4];
7389 u8 reserved_at_30[0x8];
7390 u8 max_bw_value[0x8];
7393 struct mlx5_ifc_ets_global_config_reg_bits {
7394 u8 reserved_at_0[0x2];
7396 u8 reserved_at_3[0x1d];
7398 u8 reserved_at_20[0xc];
7399 u8 max_bw_units[0x4];
7400 u8 reserved_at_30[0x8];
7401 u8 max_bw_value[0x8];
7404 struct mlx5_ifc_qetc_reg_bits {
7405 u8 reserved_at_0[0x8];
7406 u8 port_number[0x8];
7407 u8 reserved_at_10[0x30];
7409 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
7410 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
7413 struct mlx5_ifc_qtct_reg_bits {
7414 u8 reserved_at_0[0x8];
7415 u8 port_number[0x8];
7416 u8 reserved_at_10[0xd];
7419 u8 reserved_at_20[0x1d];
7423 struct mlx5_ifc_mcia_reg_bits {
7425 u8 reserved_at_1[0x7];
7427 u8 reserved_at_10[0x8];
7430 u8 i2c_device_address[0x8];
7431 u8 page_number[0x8];
7432 u8 device_address[0x10];
7434 u8 reserved_at_40[0x10];
7437 u8 reserved_at_60[0x20];
7453 #endif /* MLX5_IFC_H */