1 /* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved.
2 * Copyright (C) 2015 Linaro Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
16 #include <linux/platform_device.h>
18 extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
19 extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
21 #define QCOM_SCM_HDCP_MAX_REQ_CNT 5
23 struct qcom_scm_hdcp_req {
28 extern bool qcom_scm_is_available(void);
30 extern bool qcom_scm_hdcp_available(void);
31 extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
34 extern bool qcom_scm_pas_supported(u32 peripheral);
35 extern int qcom_scm_restart_proc(u32 pid, int restart, u32 *resp);
36 extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size);
37 extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size);
38 extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
39 extern int qcom_scm_pas_shutdown(u32 peripheral);
41 #define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0
42 #define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1
44 extern void qcom_scm_cpu_power_down(u32 flags);
46 #define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
48 extern u32 qcom_scm_get_version(void);
50 extern int qcom_scm_pil_init_image_cmd(u32 proc, u64 image_addr);
51 extern int qcom_scm_pil_mem_setup_cmd(u32 proc, u64 start_addr, u32 len);
52 extern int qcom_scm_pil_auth_and_reset_cmd(u32 proc);
53 extern int qcom_scm_pil_shutdown_cmd(u32 proc);
55 extern int qcom_scm_iommu_dump_fault_regs(u32 id, u32 context, u64 addr,
57 extern int qcom_scm_iommu_set_cp_pool_size(u32 size, u32 spare);
58 extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, int psize[2]);
59 extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
60 extern int qcom_scm_iommu_secure_map(u64 list, u32 list_size, u32 size,
61 u32 id, u32 ctx_id, u64 va,
62 u32 info_size, u32 flags);
63 extern int qcom_scm_iommu_secure_unmap(u32 id, u32 ctx_id, u64 va,
66 extern int qcom_scm_is_call_available(u32 svc_id, u32 cmd_id);
67 extern int qcom_scm_get_feat_version(u32 feat);
68 extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
70 extern int qcom_scm_set_video_state(u32 state, u32 spare);
71 extern int qcom_scm_mem_protect_video_var(u32 start, u32 size,