1 /*----------------------------------------------------------------------------+
3 | This source code has been made available to you by IBM on an AS-IS
4 | basis. Anyone receiving this source is licensed under IBM
5 | copyrights to use it in any way he or she deems fit, including
6 | copying it, modifying it, compiling it, and redistributing it either
7 | with or without modifications. No license under IBM patents or
8 | patent applications is to be implied by the copyright license.
10 | Any user of this software should understand that IBM cannot provide
11 | technical support for this software and will not be responsible for
12 | any consequences resulting from the use of this software.
14 | Any person who transfers this source code or any derivative work
15 | must include the IBM copyright notice, this paragraph, and the
16 | preceding two paragraphs in the transferred software.
18 | COPYRIGHT I B M CORPORATION 1999
19 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 +----------------------------------------------------------------------------*/
25 #if defined(CONFIG_440)
32 * Macro for generating register field mnemonics
34 #define PPC_REG_BITS 32
35 #define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit)))
38 * Elide casts when assembling register mnemonics
41 #define static_cast(type, val) (type)(val)
43 #define static_cast(type, val) (val)
47 * Common stuff for 4xx (405 and 440)
50 #define EXC_OFF_SYS_RESET 0x0100 /* System reset */
51 #define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000)
53 #define RESET_VECTOR 0xfffffffc
54 #define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache
57 #define CPR0_DCR_BASE 0x0C
58 #define cprcfga (CPR0_DCR_BASE+0x0)
59 #define cprcfgd (CPR0_DCR_BASE+0x1)
61 #define SDR_DCR_BASE 0x0E
62 #define sdrcfga (SDR_DCR_BASE+0x0)
63 #define sdrcfgd (SDR_DCR_BASE+0x1)
65 #define SDRAM_DCR_BASE 0x10
66 #define memcfga (SDRAM_DCR_BASE+0x0)
67 #define memcfgd (SDRAM_DCR_BASE+0x1)
69 #define EBC_DCR_BASE 0x12
70 #define ebccfga (EBC_DCR_BASE+0x0)
71 #define ebccfgd (EBC_DCR_BASE+0x1)
74 * Macros for indirect DCR access
76 #define mtcpr(reg, d) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0)
77 #define mfcpr(reg, d) do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0)
79 #define mtebc(reg, d) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0)
80 #define mfebc(reg, d) do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0)
82 #define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0)
83 #define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0)
85 #define mtsdr(reg, d) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0)
86 #define mfsdr(reg, d) do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0)
92 unsigned long freqDDR;
93 unsigned long freqEBC;
94 unsigned long freqOPB;
95 unsigned long freqPCI;
96 unsigned long freqPLB;
97 unsigned long freqTmrClk;
98 unsigned long freqUART;
99 unsigned long freqProcessor;
100 unsigned long freqVCOHz;
101 unsigned long freqVCOMhz; /* in MHz */
102 unsigned long pciClkSync; /* PCI clock is synchronous */
103 unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
104 unsigned long pllExtBusDiv;
105 unsigned long pllFbkDiv;
106 unsigned long pllFwdDiv;
107 unsigned long pllFwdDivA;
108 unsigned long pllFwdDivB;
109 unsigned long pllOpbDiv;
110 unsigned long pllPciDiv;
111 unsigned long pllPlbDiv;
114 #endif /* __ASSEMBLY__ */
116 #endif /* __PPC4XX_H__ */