4 * Copyright (C) 2008-2009, Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra
8 * Data type definitions, declarations, prototypes.
10 * Started by: Thomas Gleixner and Ingo Molnar
12 * For licencing details see kernel-base/COPYING
14 #ifndef _UAPI_LINUX_PERF_EVENT_H
15 #define _UAPI_LINUX_PERF_EVENT_H
17 #include <linux/types.h>
18 #include <linux/ioctl.h>
19 #include <asm/byteorder.h>
22 * User-space ABI bits:
29 PERF_TYPE_HARDWARE = 0,
30 PERF_TYPE_SOFTWARE = 1,
31 PERF_TYPE_TRACEPOINT = 2,
32 PERF_TYPE_HW_CACHE = 3,
34 PERF_TYPE_BREAKPOINT = 5,
36 PERF_TYPE_MAX, /* non-ABI */
40 * Generalized performance event event_id types, used by the
41 * attr.event_id parameter of the sys_perf_event_open()
46 * Common hardware events, generalized by the kernel:
48 PERF_COUNT_HW_CPU_CYCLES = 0,
49 PERF_COUNT_HW_INSTRUCTIONS = 1,
50 PERF_COUNT_HW_CACHE_REFERENCES = 2,
51 PERF_COUNT_HW_CACHE_MISSES = 3,
52 PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4,
53 PERF_COUNT_HW_BRANCH_MISSES = 5,
54 PERF_COUNT_HW_BUS_CYCLES = 6,
55 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7,
56 PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8,
57 PERF_COUNT_HW_REF_CPU_CYCLES = 9,
59 PERF_COUNT_HW_MAX, /* non-ABI */
63 * Generalized hardware cache events:
65 * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x
66 * { read, write, prefetch } x
67 * { accesses, misses }
69 enum perf_hw_cache_id {
70 PERF_COUNT_HW_CACHE_L1D = 0,
71 PERF_COUNT_HW_CACHE_L1I = 1,
72 PERF_COUNT_HW_CACHE_LL = 2,
73 PERF_COUNT_HW_CACHE_DTLB = 3,
74 PERF_COUNT_HW_CACHE_ITLB = 4,
75 PERF_COUNT_HW_CACHE_BPU = 5,
76 PERF_COUNT_HW_CACHE_NODE = 6,
78 PERF_COUNT_HW_CACHE_MAX, /* non-ABI */
81 enum perf_hw_cache_op_id {
82 PERF_COUNT_HW_CACHE_OP_READ = 0,
83 PERF_COUNT_HW_CACHE_OP_WRITE = 1,
84 PERF_COUNT_HW_CACHE_OP_PREFETCH = 2,
86 PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */
89 enum perf_hw_cache_op_result_id {
90 PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0,
91 PERF_COUNT_HW_CACHE_RESULT_MISS = 1,
93 PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */
97 * Special "software" events provided by the kernel, even if the hardware
98 * does not support performance events. These events measure various
99 * physical and sw events of the kernel (and allow the profiling of them as
103 PERF_COUNT_SW_CPU_CLOCK = 0,
104 PERF_COUNT_SW_TASK_CLOCK = 1,
105 PERF_COUNT_SW_PAGE_FAULTS = 2,
106 PERF_COUNT_SW_CONTEXT_SWITCHES = 3,
107 PERF_COUNT_SW_CPU_MIGRATIONS = 4,
108 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5,
109 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6,
110 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7,
111 PERF_COUNT_SW_EMULATION_FAULTS = 8,
112 PERF_COUNT_SW_DUMMY = 9,
113 PERF_COUNT_SW_BPF_OUTPUT = 10,
115 PERF_COUNT_SW_MAX, /* non-ABI */
119 * Bits that can be set in attr.sample_type to request information
120 * in the overflow packets.
122 enum perf_event_sample_format {
123 PERF_SAMPLE_IP = 1U << 0,
124 PERF_SAMPLE_TID = 1U << 1,
125 PERF_SAMPLE_TIME = 1U << 2,
126 PERF_SAMPLE_ADDR = 1U << 3,
127 PERF_SAMPLE_READ = 1U << 4,
128 PERF_SAMPLE_CALLCHAIN = 1U << 5,
129 PERF_SAMPLE_ID = 1U << 6,
130 PERF_SAMPLE_CPU = 1U << 7,
131 PERF_SAMPLE_PERIOD = 1U << 8,
132 PERF_SAMPLE_STREAM_ID = 1U << 9,
133 PERF_SAMPLE_RAW = 1U << 10,
134 PERF_SAMPLE_BRANCH_STACK = 1U << 11,
135 PERF_SAMPLE_REGS_USER = 1U << 12,
136 PERF_SAMPLE_STACK_USER = 1U << 13,
137 PERF_SAMPLE_WEIGHT = 1U << 14,
138 PERF_SAMPLE_DATA_SRC = 1U << 15,
139 PERF_SAMPLE_IDENTIFIER = 1U << 16,
140 PERF_SAMPLE_TRANSACTION = 1U << 17,
141 PERF_SAMPLE_REGS_INTR = 1U << 18,
143 PERF_SAMPLE_MAX = 1U << 19, /* non-ABI */
147 * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set
149 * If the user does not pass priv level information via branch_sample_type,
150 * the kernel uses the event's priv level. Branch and event priv levels do
151 * not have to match. Branch priv level is checked for permissions.
153 * The branch types can be combined, however BRANCH_ANY covers all types
154 * of branches and therefore it supersedes all the other types.
156 enum perf_branch_sample_type_shift {
157 PERF_SAMPLE_BRANCH_USER_SHIFT = 0, /* user branches */
158 PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, /* kernel branches */
159 PERF_SAMPLE_BRANCH_HV_SHIFT = 2, /* hypervisor branches */
161 PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, /* any branch types */
162 PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, /* any call branch */
163 PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, /* any return branch */
164 PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, /* indirect calls */
165 PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, /* transaction aborts */
166 PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, /* in transaction */
167 PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, /* not in transaction */
168 PERF_SAMPLE_BRANCH_COND_SHIFT = 10, /* conditional branches */
170 PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, /* call/ret stack */
171 PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12, /* indirect jumps */
172 PERF_SAMPLE_BRANCH_CALL_SHIFT = 13, /* direct call */
174 PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14, /* no flags */
175 PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15, /* no cycles */
177 PERF_SAMPLE_BRANCH_MAX_SHIFT /* non-ABI */
180 enum perf_branch_sample_type {
181 PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT,
182 PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT,
183 PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT,
185 PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT,
186 PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT,
187 PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT,
188 PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT,
189 PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT,
190 PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT,
191 PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT,
192 PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT,
194 PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT,
195 PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT,
196 PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT,
198 PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT,
199 PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT,
201 PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT,
204 #define PERF_SAMPLE_BRANCH_PLM_ALL \
205 (PERF_SAMPLE_BRANCH_USER|\
206 PERF_SAMPLE_BRANCH_KERNEL|\
207 PERF_SAMPLE_BRANCH_HV)
210 * Values to determine ABI of the registers dump.
212 enum perf_sample_regs_abi {
213 PERF_SAMPLE_REGS_ABI_NONE = 0,
214 PERF_SAMPLE_REGS_ABI_32 = 1,
215 PERF_SAMPLE_REGS_ABI_64 = 2,
219 * Values for the memory transaction event qualifier, mostly for
220 * abort events. Multiple bits can be set.
223 PERF_TXN_ELISION = (1 << 0), /* From elision */
224 PERF_TXN_TRANSACTION = (1 << 1), /* From transaction */
225 PERF_TXN_SYNC = (1 << 2), /* Instruction is related */
226 PERF_TXN_ASYNC = (1 << 3), /* Instruction not related */
227 PERF_TXN_RETRY = (1 << 4), /* Retry possible */
228 PERF_TXN_CONFLICT = (1 << 5), /* Conflict abort */
229 PERF_TXN_CAPACITY_WRITE = (1 << 6), /* Capacity write abort */
230 PERF_TXN_CAPACITY_READ = (1 << 7), /* Capacity read abort */
232 PERF_TXN_MAX = (1 << 8), /* non-ABI */
234 /* bits 32..63 are reserved for the abort code */
236 PERF_TXN_ABORT_MASK = (0xffffffffULL << 32),
237 PERF_TXN_ABORT_SHIFT = 32,
241 * The format of the data returned by read() on a perf event fd,
242 * as specified by attr.read_format:
244 * struct read_format {
246 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED
247 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING
248 * { u64 id; } && PERF_FORMAT_ID
249 * } && !PERF_FORMAT_GROUP
252 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED
253 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING
255 * { u64 id; } && PERF_FORMAT_ID
257 * } && PERF_FORMAT_GROUP
260 enum perf_event_read_format {
261 PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0,
262 PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1,
263 PERF_FORMAT_ID = 1U << 2,
264 PERF_FORMAT_GROUP = 1U << 3,
266 PERF_FORMAT_MAX = 1U << 4, /* non-ABI */
269 #define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */
270 #define PERF_ATTR_SIZE_VER1 72 /* add: config2 */
271 #define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */
272 #define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */
273 /* add: sample_stack_user */
274 #define PERF_ATTR_SIZE_VER4 104 /* add: sample_regs_intr */
275 #define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */
278 * Hardware event_id to monitor via a performance monitoring event:
280 * @sample_max_stack: Max number of frame pointers in a callchain,
281 * should be < /proc/sys/kernel/perf_event_max_stack
283 struct perf_event_attr {
286 * Major type: hardware/software/tracepoint/etc.
291 * Size of the attr structure, for fwd/bwd compat.
296 * Type specific configuration information.
308 __u64 disabled : 1, /* off by default */
309 inherit : 1, /* children inherit it */
310 pinned : 1, /* must always be on PMU */
311 exclusive : 1, /* only group on PMU */
312 exclude_user : 1, /* don't count user */
313 exclude_kernel : 1, /* ditto kernel */
314 exclude_hv : 1, /* ditto hypervisor */
315 exclude_idle : 1, /* don't count when idle */
316 mmap : 1, /* include mmap data */
317 comm : 1, /* include comm data */
318 freq : 1, /* use freq, not period */
319 inherit_stat : 1, /* per task counts */
320 enable_on_exec : 1, /* next exec enables */
321 task : 1, /* trace fork/exit */
322 watermark : 1, /* wakeup_watermark */
326 * 0 - SAMPLE_IP can have arbitrary skid
327 * 1 - SAMPLE_IP must have constant skid
328 * 2 - SAMPLE_IP requested to have 0 skid
329 * 3 - SAMPLE_IP must have 0 skid
331 * See also PERF_RECORD_MISC_EXACT_IP
333 precise_ip : 2, /* skid constraint */
334 mmap_data : 1, /* non-exec mmap data */
335 sample_id_all : 1, /* sample_type all events */
337 exclude_host : 1, /* don't count in host */
338 exclude_guest : 1, /* don't count in guest */
340 exclude_callchain_kernel : 1, /* exclude kernel callchains */
341 exclude_callchain_user : 1, /* exclude user callchains */
342 mmap2 : 1, /* include mmap with inode data */
343 comm_exec : 1, /* flag comm events that are due to an exec */
344 use_clockid : 1, /* use @clockid for time fields */
345 context_switch : 1, /* context switch data */
346 write_backward : 1, /* Write ring buffer from end to beginning */
347 namespaces : 1, /* include namespaces data */
351 __u32 wakeup_events; /* wakeup every n events */
352 __u32 wakeup_watermark; /* bytes before wakeup */
358 __u64 config1; /* extension of config */
362 __u64 config2; /* extension of config1 */
364 __u64 branch_sample_type; /* enum perf_branch_sample_type */
367 * Defines set of user regs to dump on samples.
368 * See asm/perf_regs.h for details.
370 __u64 sample_regs_user;
373 * Defines size of the user stack to dump on samples.
375 __u32 sample_stack_user;
379 * Defines set of regs to dump for each sample
381 * - precise = 0: PMU interrupt
382 * - precise > 0: sampled instruction
384 * See asm/perf_regs.h for details.
386 __u64 sample_regs_intr;
389 * Wakeup watermark for AUX area
392 __u16 sample_max_stack;
393 __u16 __reserved_2; /* align to __u64 */
396 #define perf_flags(attr) (*(&(attr)->read_format + 1))
399 * Ioctls that can be done on a perf event fd:
401 #define PERF_EVENT_IOC_ENABLE _IO ('$', 0)
402 #define PERF_EVENT_IOC_DISABLE _IO ('$', 1)
403 #define PERF_EVENT_IOC_REFRESH _IO ('$', 2)
404 #define PERF_EVENT_IOC_RESET _IO ('$', 3)
405 #define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64)
406 #define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5)
407 #define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *)
408 #define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *)
409 #define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32)
410 #define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32)
412 enum perf_event_ioc_flags {
413 PERF_IOC_FLAG_GROUP = 1U << 0,
417 * Structure of the page that can be mapped via mmap
419 struct perf_event_mmap_page {
420 __u32 version; /* version number of this structure */
421 __u32 compat_version; /* lowest version this is compat with */
424 * Bits needed to read the hw events in user-space.
426 * u32 seq, time_mult, time_shift, index, width;
427 * u64 count, enabled, running;
428 * u64 cyc, time_offset;
435 * enabled = pc->time_enabled;
436 * running = pc->time_running;
438 * if (pc->cap_usr_time && enabled != running) {
440 * time_offset = pc->time_offset;
441 * time_mult = pc->time_mult;
442 * time_shift = pc->time_shift;
446 * count = pc->offset;
447 * if (pc->cap_user_rdpmc && index) {
448 * width = pc->pmc_width;
449 * pmc = rdpmc(index - 1);
453 * } while (pc->lock != seq);
455 * NOTE: for obvious reason this only works on self-monitoring
458 __u32 lock; /* seqlock for synchronization */
459 __u32 index; /* hardware event identifier */
460 __s64 offset; /* add to hardware event value */
461 __u64 time_enabled; /* time event active */
462 __u64 time_running; /* time event on cpu */
466 __u64 cap_bit0 : 1, /* Always 0, deprecated, see commit 860f085b74e9 */
467 cap_bit0_is_deprecated : 1, /* Always 1, signals that bit 0 is zero */
469 cap_user_rdpmc : 1, /* The RDPMC instruction can be used to read counts */
470 cap_user_time : 1, /* The time_* fields are used */
471 cap_user_time_zero : 1, /* The time_zero field is used */
477 * If cap_user_rdpmc this field provides the bit-width of the value
478 * read using the rdpmc() or equivalent instruction. This can be used
479 * to sign extend the result like:
481 * pmc <<= 64 - width;
482 * pmc >>= 64 - width; // signed shift right
488 * If cap_usr_time the below fields can be used to compute the time
489 * delta since time_enabled (in ns) using rdtsc or similar.
494 * quot = (cyc >> time_shift);
495 * rem = cyc & (((u64)1 << time_shift) - 1);
496 * delta = time_offset + quot * time_mult +
497 * ((rem * time_mult) >> time_shift);
499 * Where time_offset,time_mult,time_shift and cyc are read in the
500 * seqcount loop described above. This delta can then be added to
501 * enabled and possible running (if index), improving the scaling:
507 * quot = count / running;
508 * rem = count % running;
509 * count = quot * enabled + (rem * enabled) / running;
515 * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated
516 * from sample timestamps.
518 * time = timestamp - time_zero;
519 * quot = time / time_mult;
520 * rem = time % time_mult;
521 * cyc = (quot << time_shift) + (rem << time_shift) / time_mult;
525 * quot = cyc >> time_shift;
526 * rem = cyc & (((u64)1 << time_shift) - 1);
527 * timestamp = time_zero + quot * time_mult +
528 * ((rem * time_mult) >> time_shift);
531 __u32 size; /* Header size up to __reserved[] fields. */
534 * Hole for extension of the self monitor capabilities
537 __u8 __reserved[118*8+4]; /* align to 1k. */
540 * Control data for the mmap() data buffer.
542 * User-space reading the @data_head value should issue an smp_rmb(),
543 * after reading this value.
545 * When the mapping is PROT_WRITE the @data_tail value should be
546 * written by userspace to reflect the last read data, after issueing
547 * an smp_mb() to separate the data read from the ->data_tail store.
548 * In this case the kernel will not over-write unread data.
550 * See perf_output_put_handle() for the data ordering.
552 * data_{offset,size} indicate the location and size of the perf record
553 * buffer within the mmapped area.
555 __u64 data_head; /* head in the data section */
556 __u64 data_tail; /* user-space written tail */
557 __u64 data_offset; /* where the buffer starts */
558 __u64 data_size; /* data buffer size */
561 * AUX area is defined by aux_{offset,size} fields that should be set
562 * by the userspace, so that
564 * aux_offset >= data_offset + data_size
566 * prior to mmap()ing it. Size of the mmap()ed area should be aux_size.
568 * Ring buffer pointers aux_{head,tail} have the same semantics as
569 * data_{head,tail} and same ordering rules apply.
577 #define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0)
578 #define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0)
579 #define PERF_RECORD_MISC_KERNEL (1 << 0)
580 #define PERF_RECORD_MISC_USER (2 << 0)
581 #define PERF_RECORD_MISC_HYPERVISOR (3 << 0)
582 #define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0)
583 #define PERF_RECORD_MISC_GUEST_USER (5 << 0)
586 * Indicates that /proc/PID/maps parsing are truncated by time out.
588 #define PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT (1 << 12)
590 * PERF_RECORD_MISC_MMAP_DATA and PERF_RECORD_MISC_COMM_EXEC are used on
591 * different events so can reuse the same bit position.
592 * Ditto PERF_RECORD_MISC_SWITCH_OUT.
594 #define PERF_RECORD_MISC_MMAP_DATA (1 << 13)
595 #define PERF_RECORD_MISC_COMM_EXEC (1 << 13)
596 #define PERF_RECORD_MISC_SWITCH_OUT (1 << 13)
598 * Indicates that the content of PERF_SAMPLE_IP points to
599 * the actual instruction that triggered the event. See also
600 * perf_event_attr::precise_ip.
602 #define PERF_RECORD_MISC_EXACT_IP (1 << 14)
604 * Reserve the last bit to indicate some extended misc field
606 #define PERF_RECORD_MISC_EXT_RESERVED (1 << 15)
608 struct perf_event_header {
614 struct perf_ns_link_info {
628 NR_NAMESPACES, /* number of available namespaces */
631 enum perf_event_type {
634 * If perf_event_attr.sample_id_all is set then all event types will
635 * have the sample_type selected fields related to where/when
636 * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU,
637 * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed
638 * just after the perf_event_header and the fields already present for
639 * the existing fields, i.e. at the end of the payload. That way a newer
640 * perf.data file will be supported by older perf tools, with these new
641 * optional fields being ignored.
644 * { u32 pid, tid; } && PERF_SAMPLE_TID
645 * { u64 time; } && PERF_SAMPLE_TIME
646 * { u64 id; } && PERF_SAMPLE_ID
647 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID
648 * { u32 cpu, res; } && PERF_SAMPLE_CPU
649 * { u64 id; } && PERF_SAMPLE_IDENTIFIER
650 * } && perf_event_attr::sample_id_all
652 * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. The
653 * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed
654 * relative to header.size.
658 * The MMAP events record the PROT_EXEC mappings so that we can
659 * correlate userspace IPs to code. They have the following structure:
662 * struct perf_event_header header;
669 * struct sample_id sample_id;
672 PERF_RECORD_MMAP = 1,
676 * struct perf_event_header header;
679 * struct sample_id sample_id;
682 PERF_RECORD_LOST = 2,
686 * struct perf_event_header header;
690 * struct sample_id sample_id;
693 PERF_RECORD_COMM = 3,
697 * struct perf_event_header header;
701 * struct sample_id sample_id;
704 PERF_RECORD_EXIT = 4,
708 * struct perf_event_header header;
712 * struct sample_id sample_id;
715 PERF_RECORD_THROTTLE = 5,
716 PERF_RECORD_UNTHROTTLE = 6,
720 * struct perf_event_header header;
724 * struct sample_id sample_id;
727 PERF_RECORD_FORK = 7,
731 * struct perf_event_header header;
734 * struct read_format values;
735 * struct sample_id sample_id;
738 PERF_RECORD_READ = 8,
742 * struct perf_event_header header;
745 * # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID.
746 * # The advantage of PERF_SAMPLE_IDENTIFIER is that its position
747 * # is fixed relative to header.
750 * { u64 id; } && PERF_SAMPLE_IDENTIFIER
751 * { u64 ip; } && PERF_SAMPLE_IP
752 * { u32 pid, tid; } && PERF_SAMPLE_TID
753 * { u64 time; } && PERF_SAMPLE_TIME
754 * { u64 addr; } && PERF_SAMPLE_ADDR
755 * { u64 id; } && PERF_SAMPLE_ID
756 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID
757 * { u32 cpu, res; } && PERF_SAMPLE_CPU
758 * { u64 period; } && PERF_SAMPLE_PERIOD
760 * { struct read_format values; } && PERF_SAMPLE_READ
763 * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN
766 * # The RAW record below is opaque data wrt the ABI
768 * # That is, the ABI doesn't make any promises wrt to
769 * # the stability of its content, it may vary depending
770 * # on event, hardware, kernel version and phase of
773 * # In other words, PERF_SAMPLE_RAW contents are not an ABI.
777 * char data[size];}&& PERF_SAMPLE_RAW
780 * { u64 from, to, flags } lbr[nr];} && PERF_SAMPLE_BRANCH_STACK
782 * { u64 abi; # enum perf_sample_regs_abi
783 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER
787 * u64 dyn_size; } && PERF_SAMPLE_STACK_USER
789 * { u64 weight; } && PERF_SAMPLE_WEIGHT
790 * { u64 data_src; } && PERF_SAMPLE_DATA_SRC
791 * { u64 transaction; } && PERF_SAMPLE_TRANSACTION
792 * { u64 abi; # enum perf_sample_regs_abi
793 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR
796 PERF_RECORD_SAMPLE = 9,
799 * The MMAP2 records are an augmented version of MMAP, they add
800 * maj, min, ino numbers to be used to uniquely identify each mapping
803 * struct perf_event_header header;
812 * u64 ino_generation;
815 * struct sample_id sample_id;
818 PERF_RECORD_MMAP2 = 10,
821 * Records that new data landed in the AUX buffer part.
824 * struct perf_event_header header;
829 * struct sample_id sample_id;
832 PERF_RECORD_AUX = 11,
835 * Indicates that instruction trace has started
838 * struct perf_event_header header;
843 PERF_RECORD_ITRACE_START = 12,
846 * Records the dropped/lost sample number.
849 * struct perf_event_header header;
852 * struct sample_id sample_id;
855 PERF_RECORD_LOST_SAMPLES = 13,
858 * Records a context switch in or out (flagged by
859 * PERF_RECORD_MISC_SWITCH_OUT). See also
860 * PERF_RECORD_SWITCH_CPU_WIDE.
863 * struct perf_event_header header;
864 * struct sample_id sample_id;
867 PERF_RECORD_SWITCH = 14,
870 * CPU-wide version of PERF_RECORD_SWITCH with next_prev_pid and
871 * next_prev_tid that are the next (switching out) or previous
872 * (switching in) pid/tid.
875 * struct perf_event_header header;
878 * struct sample_id sample_id;
881 PERF_RECORD_SWITCH_CPU_WIDE = 15,
885 * struct perf_event_header header;
889 * { u64 dev, inode; } [nr_namespaces];
890 * struct sample_id sample_id;
893 PERF_RECORD_NAMESPACES = 16,
895 PERF_RECORD_MAX, /* non-ABI */
898 #define PERF_MAX_STACK_DEPTH 127
899 #define PERF_MAX_CONTEXTS_PER_STACK 8
901 enum perf_callchain_context {
902 PERF_CONTEXT_HV = (__u64)-32,
903 PERF_CONTEXT_KERNEL = (__u64)-128,
904 PERF_CONTEXT_USER = (__u64)-512,
906 PERF_CONTEXT_GUEST = (__u64)-2048,
907 PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176,
908 PERF_CONTEXT_GUEST_USER = (__u64)-2560,
910 PERF_CONTEXT_MAX = (__u64)-4095,
914 * PERF_RECORD_AUX::flags bits
916 #define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */
917 #define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */
918 #define PERF_AUX_FLAG_PARTIAL 0x04 /* record contains gaps */
920 #define PERF_FLAG_FD_NO_GROUP (1UL << 0)
921 #define PERF_FLAG_FD_OUTPUT (1UL << 1)
922 #define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */
923 #define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */
925 #if defined(__LITTLE_ENDIAN_BITFIELD)
926 union perf_mem_data_src {
929 __u64 mem_op:5, /* type of opcode */
930 mem_lvl:14, /* memory hierarchy level */
931 mem_snoop:5, /* snoop mode */
932 mem_lock:2, /* lock instr */
933 mem_dtlb:7, /* tlb access */
937 #elif defined(__BIG_ENDIAN_BITFIELD)
938 union perf_mem_data_src {
942 mem_dtlb:7, /* tlb access */
943 mem_lock:2, /* lock instr */
944 mem_snoop:5, /* snoop mode */
945 mem_lvl:14, /* memory hierarchy level */
946 mem_op:5; /* type of opcode */
950 #error "Unknown endianness"
953 /* type of opcode (load/store/prefetch,code) */
954 #define PERF_MEM_OP_NA 0x01 /* not available */
955 #define PERF_MEM_OP_LOAD 0x02 /* load instruction */
956 #define PERF_MEM_OP_STORE 0x04 /* store instruction */
957 #define PERF_MEM_OP_PFETCH 0x08 /* prefetch */
958 #define PERF_MEM_OP_EXEC 0x10 /* code (execution) */
959 #define PERF_MEM_OP_SHIFT 0
961 /* memory hierarchy (memory level, hit or miss) */
962 #define PERF_MEM_LVL_NA 0x01 /* not available */
963 #define PERF_MEM_LVL_HIT 0x02 /* hit level */
964 #define PERF_MEM_LVL_MISS 0x04 /* miss level */
965 #define PERF_MEM_LVL_L1 0x08 /* L1 */
966 #define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */
967 #define PERF_MEM_LVL_L2 0x20 /* L2 */
968 #define PERF_MEM_LVL_L3 0x40 /* L3 */
969 #define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */
970 #define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */
971 #define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */
972 #define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */
973 #define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */
974 #define PERF_MEM_LVL_IO 0x1000 /* I/O memory */
975 #define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */
976 #define PERF_MEM_LVL_SHIFT 5
979 #define PERF_MEM_SNOOP_NA 0x01 /* not available */
980 #define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */
981 #define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */
982 #define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */
983 #define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */
984 #define PERF_MEM_SNOOP_SHIFT 19
986 /* locked instruction */
987 #define PERF_MEM_LOCK_NA 0x01 /* not available */
988 #define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */
989 #define PERF_MEM_LOCK_SHIFT 24
992 #define PERF_MEM_TLB_NA 0x01 /* not available */
993 #define PERF_MEM_TLB_HIT 0x02 /* hit level */
994 #define PERF_MEM_TLB_MISS 0x04 /* miss level */
995 #define PERF_MEM_TLB_L1 0x08 /* L1 */
996 #define PERF_MEM_TLB_L2 0x10 /* L2 */
997 #define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/
998 #define PERF_MEM_TLB_OS 0x40 /* OS fault handler */
999 #define PERF_MEM_TLB_SHIFT 26
1001 #define PERF_MEM_S(a, s) \
1002 (((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT)
1005 * single taken branch record layout:
1007 * from: source instruction (may not always be a branch insn)
1009 * mispred: branch target was mispredicted
1010 * predicted: branch target was predicted
1012 * support for mispred, predicted is optional. In case it
1013 * is not supported mispred = predicted = 0.
1015 * in_tx: running in a hardware transaction
1016 * abort: aborting a hardware transaction
1017 * cycles: cycles from last branch (or 0 if not supported)
1019 struct perf_branch_entry {
1022 __u64 mispred:1, /* target mispredicted */
1023 predicted:1,/* target predicted */
1024 in_tx:1, /* in transaction */
1025 abort:1, /* transaction abort */
1026 cycles:16, /* cycle count to last branch */
1030 #endif /* _UAPI_LINUX_PERF_EVENT_H */