1 //==========================================================================
3 // devs_eth_arm_tx27.inl
5 // Board ethernet I/O definitions.
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
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40 //===========================================================================
42 #include <cyg/hal/hal_intr.h> // CYGNUM_HAL_INTERRUPT_ETHR
43 #include <cyg/hal/hal_if.h>
46 #include <pkgconf/redboot.h>
47 #ifdef CYGSEM_REDBOOT_FLASH_CONFIG
49 #include <flash_config.h>
53 extern unsigned int sys_ver;
57 #ifdef CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0
59 #ifdef CYGPKG_DEVS_ETH_PHY
61 static char mxc_fec_name[] = "mxc_fec";
63 #define OCR_SHIFT(bit) (((bit) * 2) % 32)
64 #define OCR_MASK(bit) (3 << (OCR_SHIFT(bit)))
65 #define OCR_VAL(bit,val) (((val) << (OCR_SHIFT(bit))) & (OCR_MASK(bit)))
66 #define GPR_SHIFT(bit) (bit)
67 #define GPR_MASK(bit) (1 << (GPR_SHIFT(bit)))
68 #define GPR_VAL(bit,val) (((val) << (GPR_SHIFT(bit))) & (GPR_MASK(bit)))
70 static inline void tx27_set_reg(unsigned long addr, CYG_WORD32 set, CYG_WORD32 clr)
73 HAL_READ_UINT32(addr, val);
74 //diag_printf("Changing reg %08lx from %08x to %08x\n", addr, val, (val & ~clr) | set);
75 val = (val & ~clr) | set;
76 HAL_WRITE_UINT32(addr, val);
79 static inline void tx27_phy_power_off(void)
81 if (net_debug) diag_printf("Switching PHY POWER off\n");
84 tx27_set_reg(SOC_GPIOD_BASE + GPIO_OCR1, 0xffffffff, 0);
85 tx27_set_reg(SOC_GPIOD_BASE + GPIO_DR, 0, 0xffff);
86 tx27_set_reg(SOC_GPIOD_BASE + GPIO_DDIR, 0xffff, 0);
87 tx27_set_reg(SOC_GPIOD_BASE + GPIO_GIUS, 0xffff, 0);
90 tx27_set_reg(SOC_GPIOD_BASE + GPIO_OCR2, OCR_MASK(16), 0);
91 tx27_set_reg(SOC_GPIOD_BASE + GPIO_DR, 0, GPR_MASK(16));
92 tx27_set_reg(SOC_GPIOD_BASE + GPIO_DDIR, GPR_MASK(16), 0);
93 tx27_set_reg(SOC_GPIOD_BASE + GPIO_GIUS, GPR_MASK(16), 0);
96 tx27_set_reg(SOC_GPIOF_BASE + GPIO_OCR2, OCR_MASK(23), 0);
97 tx27_set_reg(SOC_GPIOF_BASE + GPIO_DR, 0, GPR_MASK(23));
98 tx27_set_reg(SOC_GPIOF_BASE + GPIO_DDIR, GPR_MASK(23), 0);
99 tx27_set_reg(SOC_GPIOF_BASE + GPIO_GIUS, GPR_MASK(23), 0);
101 tx27_set_reg(SOC_GPIOB_BASE + GPIO_DR, 0, GPR_MASK(27) | GPR_MASK(30));
104 static bool mxc_fec_init(struct cyg_netdevtab_entry *tab);
105 static bool tx27_fec_init(struct cyg_netdevtab_entry *tab)
110 /* Check, whether MAC address is enabled */
111 ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
112 "fec_esa", &esa_set, CONFIG_BOOL);
113 if (!(ok && esa_set)) {
114 diag_printf("FEC disabled; set fec_esa=true to enable networking\n");
117 return mxc_fec_init(tab);
120 static void tx27_fec_phy_init(void)
124 int phy_reset_delay = 100;
126 ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
127 "fec_esa", &esa_set, CONFIG_BOOL);
128 if (!(ok && esa_set)) {
129 tx27_phy_power_off();
134 * make sure the ETH PHY strap pins are pulled to the right voltage
135 * before deasserting the PHY reset GPIO
148 // assert FEC PHY Reset (PB30) and switch PHY power on
149 /* PB22, PB27, PB30 => GPIO out */
151 if (!gpio_tst_bit(1, 27)) {
152 if (net_debug) diag_printf("Switching PHY POWER on\n");
153 tx27_set_reg(SOC_GPIOB_BASE + GPIO_DR, GPR_MASK(27), GPR_MASK(30));
154 /* wait for 22ms for LAN8700 to power up */
155 phy_reset_delay = 22000;
157 if (net_debug) diag_printf("Asserting PHY RESET\n");
158 tx27_set_reg(SOC_GPIOB_BASE + GPIO_DR, 0, GPR_MASK(30));
161 const unsigned int phy_mode_mask = 0x1060;
162 // deassert PD0-15 (except 5,6,12 => PHY MODE[0..2])
163 tx27_set_reg(SOC_GPIOD_BASE + GPIO_OCR1, 0xffffffff, 0);
164 tx27_set_reg(SOC_GPIOD_BASE + GPIO_DR, phy_mode_mask, ~phy_mode_mask);
165 tx27_set_reg(SOC_GPIOD_BASE + GPIO_DDIR, 0xffff, 0);
166 tx27_set_reg(SOC_GPIOD_BASE + GPIO_GIUS, 0xffff, 0);
169 tx27_set_reg(SOC_GPIOD_BASE + GPIO_OCR2, OCR_MASK(16), 0);
170 tx27_set_reg(SOC_GPIOD_BASE + GPIO_DR, 0, GPR_MASK(16));
171 tx27_set_reg(SOC_GPIOD_BASE + GPIO_DDIR, GPR_MASK(16), 0);
172 tx27_set_reg(SOC_GPIOD_BASE + GPIO_GIUS, GPR_MASK(16), 0);
175 tx27_set_reg(SOC_GPIOF_BASE + GPIO_OCR2, OCR_MASK(23), 0);
176 tx27_set_reg(SOC_GPIOF_BASE + GPIO_DR, 0, GPR_MASK(23));
177 tx27_set_reg(SOC_GPIOF_BASE + GPIO_DDIR, GPR_MASK(23), 0);
178 tx27_set_reg(SOC_GPIOF_BASE + GPIO_GIUS, GPR_MASK(23), 0);
180 /* wait for 100us according to LAN8700 spec. before ... */
181 HAL_DELAY_US(phy_reset_delay);
183 /* ... deasserting FEC PHY reset */
184 if (net_debug) diag_printf("Releasing PHY RESET\n");
185 tx27_set_reg(SOC_GPIOB_BASE + GPIO_DR, GPR_MASK(30), 0);
187 // program PF23 as FEC_TXEN
188 tx27_set_reg(SOC_GPIOF_BASE + GPIO_OCR2, 0, OCR_MASK(23));
189 tx27_set_reg(SOC_GPIOF_BASE + GPIO_DDIR, GPR_MASK(23), 0);
190 tx27_set_reg(SOC_GPIOF_BASE + GPIO_GIUS, GPR_MASK(23), 0);
192 tx27_set_reg(SOC_GPIOD_BASE + GPIO_OCR2, 0, OCR_MASK(16));
193 tx27_set_reg(SOC_GPIOD_BASE + GPIO_OCR1, 0, 0x000C00FF);
194 tx27_set_reg(SOC_GPIOD_BASE + GPIO_ICONFA1, 0, 0xFFF0FF00);
195 tx27_set_reg(SOC_GPIOD_BASE + GPIO_GPR, GPR_MASK(8), 0);
196 tx27_set_reg(SOC_GPIOD_BASE + GPIO_DDIR, 0x0001020F, 0x0001FFFF);
197 tx27_set_reg(SOC_GPIOD_BASE + GPIO_GIUS, 0x0001FEFF, 0x0001FFFF);
200 ETH_PHY_REG_LEVEL_ACCESS_FUNS(eth0_phy,
206 static mxc_fec_priv_t mxc_fec_private = {
207 .phy = ð0_phy, // PHY access routines
210 ETH_DRV_SC(mxc_fec_sc,
211 &mxc_fec_private, // Driver specific data
219 mxc_fec_deliver, // "pseudoDSR" called from fast net thread
220 mxc_fec_poll, // poll function, encapsulates ISR and DSR
223 NETDEVTAB_ENTRY(mxc_fec_netdev,
229 #if defined(CYGPKG_REDBOOT) && defined(CYGSEM_REDBOOT_FLASH_CONFIG)
230 RedBoot_config_option("Set FEC network hardware address [MAC]",
232 ALWAYS_ENABLED, true,
235 RedBoot_config_option("FEC network hardware address [MAC]",
240 #endif // CYGPKG_REDBOOT && CYGSEM_REDBOOT_FLASH_CONFIG
242 #ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
243 // Note that this section *is* active in an application, outside RedBoot,
244 // where the above section is not included.
246 #include <cyg/hal/hal_if.h>
249 #define CONFIG_ESA (6)
252 #define CONFIG_BOOL (1)
255 #ifndef CYGSEM_REDBOOT_FLASH_CONFIG
256 void _tx27_provide_fec_esa(void)
262 ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
263 "fec_esa", &set_esa, CONFIG_BOOL);
264 diag_printf("%s: Ethernet FEC MAC address from %p: ", __FUNCTION__, SOC_FEC_MAC_BASE2);
266 CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
267 "fec_esa_data", addr, CONFIG_ESA);
268 addr[0] = readl(SOC_FEC_MAC_BASE2 + 0x0);
269 addr[1] = readl(SOC_FEC_MAC_BASE2 + 0x4);
270 addr[2] = readl(SOC_FEC_MAC_BASE2 + 0x8);
271 addr[3] = readl(SOC_FEC_MAC_BASE2 + 0xC);
272 addr[4] = readl(SOC_FEC_MAC_BASE2 + 0x10);
273 addr[5] = readl(SOC_FEC_MAC_BASE2 + 0x14);
275 diag_printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
276 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
278 diag_printf("is not set\n");
282 RedBoot_init(_tx27_provide_fec_esa, RedBoot_INIT_LAST);
283 #endif // CYGSEM_REDBOOT_FLASH_CONFIG
284 #endif // CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
285 #endif // CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0
287 #endif // __WANT_DEVS