1 #ifndef CYGONCE_DEVS_ETH_VIA_RHINE_H
2 #define CYGONCE_DEVS_ETH_VIA_RHINE_H
3 //==========================================================================
7 // VIA Rhine Ethernet chip
9 //==========================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15 // eCos is free software; you can redistribute it and/or modify it under
16 // the terms of the GNU General Public License as published by the Free
17 // Software Foundation; either version 2 or (at your option) any later version.
19 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
20 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
21 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 // You should have received a copy of the GNU General Public License along
25 // with eCos; if not, write to the Free Software Foundation, Inc.,
26 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28 // As a special exception, if other files instantiate templates or use macros
29 // or inline functions from this file, or you compile this file and link it
30 // with other works to produce a work based on this file, this file does not
31 // by itself cause the resulting work to be covered by the GNU General Public
32 // License. However the source code for this file must still be made available
33 // in accordance with section (3) of the GNU General Public License.
35 // This exception does not invalidate any other reasons why a work based on
36 // this file might be covered by the GNU General Public License.
38 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
39 // at http://sources.redhat.com/ecos/ecos-license/
40 // -------------------------------------------
41 //####ECOSGPLCOPYRIGHTEND####
42 //==========================================================================
43 //#####DESCRIPTIONBEGIN####
46 // Contributors: jskov
48 // Purpose: Hardware description of VIA Rhine series.
51 //####DESCRIPTIONEND####
53 //==========================================================================
55 #include <cyg/hal/hal_io.h>
56 #include <cyg/io/pci_hw.h> // HAL_PCI_ macros
58 //------------------------------------------------------------------------
59 // Get macros from platform header
61 #include CYGDAT_DEVS_ETH_VIA_RHINE_INL
64 //------------------------------------------------------------------------
66 // 0 disables all debug output
67 // 1 for process debug output
68 // 2 for added data IO output: get_reg, put_reg
69 // 4 for packet allocation/free output
70 // 8 for only startup status, so we can tell we're installed OK
74 # define DEBUG_FUNCTION() do { diag_printf("%s\n", __FUNCTION__); } while (0)
76 # define DEBUG_FUNCTION() do {} while(0)
79 // ------------------------------------------------------------------------
80 // Macros for keeping track of statistics
81 #if defined(ETH_DRV_GET_IF_STATS) || defined (ETH_DRV_GET_IF_STATS_UD)
82 #define KEEP_STATISTICS
85 #ifdef KEEP_STATISTICS
86 #define INCR_STAT( _x_ ) (cpd->stats. _x_ ++)
88 #define INCR_STAT( _x_ ) CYG_EMPTY_STATEMENT
91 //------------------------------------------------------------------------
93 #ifndef CYGARC_UNCACHED_ADDRESS
94 # define CYGARC_UNCACHED_ADDRESS(x) (x)
97 //------------------------------------------------------------------------
98 // Address translation
99 #ifndef HAL_PCI_CPU_TO_BUS
100 # error "HAL PCI support must define translation macros"
103 //------------------------------------------------------------------------
104 // Macros for accessing structure elements
106 #define _SU8( _base_, _offset_) \
107 *((volatile cyg_uint8 *)((CYG_ADDRWORD)_base_+(_offset_)))
108 #define _SU16( _base_, _offset_) \
109 *((volatile cyg_uint16 *)((CYG_ADDRWORD)_base_+(_offset_)))
110 #define _SU32( _base_, _offset_) \
111 *((volatile cyg_uint32 *)((CYG_ADDRWORD)_base_+(_offset_)))
113 #define _SI8( _base_, _offset_) \
114 *((volatile cyg_int8 *)((CYG_ADDRWORD)_base_+(_offset_)))
115 #define _SI16( _base_, _offset_) \
116 *((volatile cyg_int16 *)((CYG_ADDRWORD)_base_+(_offset_)))
117 #define _SI32( _base_, _offset_) \
118 *((volatile cyg_int32 *)((CYG_ADDRWORD)_base_+(_offset_)))
120 // ------------------------------------------------------------------------
121 // Macros for accessing controller registers
122 #ifndef HAL_PCI_IO_READ_UINT8
123 # define HAL_PCI_IO_READ_UINT8(addr, datum) HAL_READ_UINT8(addr, datum)
124 # define HAL_PCI_IO_WRITE_UINT8(addr, datum) HAL_WRITE_UINT8(addr, datum)
125 # define HAL_PCI_IO_READ_UINT16(addr, datum) HAL_READ_UINT16(addr, datum)
126 # define HAL_PCI_IO_WRITE_UINT16(addr, datum) HAL_WRITE_UINT16(addr, datum)
127 # define HAL_PCI_IO_READ_UINT32(addr, datum) HAL_READ_UINT32(addr, datum)
128 # define HAL_PCI_IO_WRITE_UINT32(addr, datum) HAL_WRITE_UINT32(addr, datum)
131 // ------------------------------------------------------------------------
133 #define RHINE_PAR0 0x00
134 #define RHINE_PAR1 0x01
135 #define RHINE_PAR2 0x02
136 #define RHINE_PAR3 0x03
137 #define RHINE_PAR4 0x04
138 #define RHINE_PAR5 0x05
140 #define RHINE_RCR 0x06
141 #define RHINE_TCR 0x07
142 #define RHINE_CR0 0x08
143 #define RHINE_CR1 0x09
145 #define RHINE_ISR 0x0c // 16 bit
146 #define RHINE_IMR 0x0e // 16 bit
148 #define RHINE_CUR_RX 0x18
149 #define RHINE_CUR_TX 0x1c
152 #define RHINE_PHYADR 0x6c
153 #define RHINE_MIISR 0x6d
154 #define RHINE_BCR0 0x6e
155 #define RHINE_BCR1 0x6f
156 #define RHINE_MIICR 0x70
157 #define RHINE_MIIAD 0x71
158 #define RHINE_MIIDATA 0x72 // 16 bit
161 #define RHINE_EECSR 0x74
163 #define RHINE_CFGA 0x78
164 #define RHINE_CFGB 0x79
165 #define RHINE_CFGC 0x7a
166 #define RHINE_CFGD 0x7b
168 #define RHINE_STICKYHW 0x83
169 #define RHINE_WOL_CR_CLR 0xa4
170 #define RHINE_WOL_CG_CLR 0xa7
171 #define RHINE_PWR_CSR_CLR 0xac
173 #define RHINE_RCR_RRSF 0x80
174 #define RHINE_RCR_RFT_64 0x00
175 #define RHINE_RCR_RFT_SF 0x60
176 #define RHINE_RCR_PRO 0x10
177 #define RHINE_RCR_AB 0x08
178 #define RHINE_RCR_AM 0x04
179 #define RHINE_RCR_AR 0x02
180 #define RHINE_RCR_SEP 0x01
182 #define RHINE_TCR_RTSF 0x80
183 #define RHINE_TCR_TFT_64 0x00
184 #define RHINE_TCR_TFT_SF 0x60
185 #define RHINE_TCR_OFFSET 0x08
186 #define RHINE_TCR_LB1 0x04
187 #define RHINE_TCR_LB0 0x02
189 #define RHINE_CR0_RDMD 0x40
190 #define RHINE_CR0_TDMD 0x20
191 #define RHINE_CR0_TXON 0x10
192 #define RHINE_CR0_RXON 0x08
193 #define RHINE_CR0_STOP 0x04
194 #define RHINE_CR0_STRT 0x02
195 #define RHINE_CR0_INIT 0x01
197 #define RHINE_CR1_SRST 0x80
198 #define RHINE_CR1_DPOLL 0x08
199 #define RHINE_CR1_FDX 0x04
200 #define RHINE_CR1_ETEN 0x02
201 #define RHINE_CR1_EREN 0x01
203 #define RHINE_ISR_KEYI 0x8000
204 #define RHINE_ISR_SRCI 0x4000
205 #define RHINE_ISR_ABTI 0x2000
206 #define RHINE_ISR_NORBF 0x1000
207 #define RHINE_ISR_PKRACE 0x0800
208 #define RHINE_ISR_OVFI 0x0400
209 #define RHINE_ISR_ETI 0x0200
210 #define RHINE_ISR_ERI 0x0100
211 #define RHINE_ISR_CNT 0x0080
212 #define RHINE_ISR_BE 0x0040
213 #define RHINE_ISR_RU 0x0020
214 #define RHINE_ISR_TU 0x0010
215 #define RHINE_ISR_TXE 0x0008
216 #define RHINE_ISR_RXE 0x0004
217 #define RHINE_ISR_PTX 0x0002
218 #define RHINE_ISR_PRX 0x0001
220 #define RHINE_IMR_KEYI 0x8000
221 #define RHINE_IMR_SRCI 0x4000
222 #define RHINE_IMR_ABTI 0x2000
223 #define RHINE_IMR_NORBF 0x1000
224 #define RHINE_IMR_PKRACE 0x0800
225 #define RHINE_IMR_OVFI 0x0400
226 #define RHINE_IMR_ETI 0x0200
227 #define RHINE_IMR_ERI 0x0100
228 #define RHINE_IMR_CNT 0x0080
229 #define RHINE_IMR_BE 0x0040
230 #define RHINE_IMR_RU 0x0020
231 #define RHINE_IMR_TU 0x0010
232 #define RHINE_IMR_TXE 0x0008
233 #define RHINE_IMR_RXE 0x0004
234 #define RHINE_IMR_PTX 0x0002
235 #define RHINE_IMR_PRX 0x0001
237 #define RHINE_IMR_INIT (RHINE_IMR_PTX | RHINE_IMR_PRX | RHINE_IMR_RU)
239 #define RHINE_BCR0_MAGIC_INIT 0x00
241 #define RHINE_BCR1_POT2 0x04
242 #define RHINE_BCR1_POT1 0x02
243 #define RHINE_BCR1_MAGIC_INIT (RHINE_BCR1_POT1|RHINE_BCR1_POT2)
246 #define RHINE_MIICR_MAUTO 0x80
247 #define RHINE_MIICR_RCMD 0x40
248 #define RHINE_MIICR_WCMD 0x20
249 #define RHINE_MIICR_MDPM 0x10
250 #define RHINE_MIICR_MOUT 0x08
251 #define RHINE_MIICR_MDO 0x04
252 #define RHINE_MIICR_MDI 0x02
253 #define RHINE_MIICR_MDC 0x01
255 #define RHINE_MIISR_GPIO1POL 0x80
256 #define RHINE_MIISR_MFDC 0x20
257 #define RHINE_MIISR_PHYOPT 0x10
258 #define RHINE_MIISR_MIIERR 0x08
259 #define RHINE_MIISR_MRERR 0x04
260 #define RHINE_MIISR_LNKFL 0x02
261 #define RHINE_MIISR_SPEED 0x01
263 #define RHINE_EECSR_EEPR 0x80
264 #define RHINE_EECSR_EMBP 0x40
265 #define RHINE_EECSR_LOAD 0x20
266 #define RHINE_EECSR_DPM 0x10
267 #define RHINE_EECSR_ECS 0x08
268 #define RHINE_EECSR_ECK 0x04
269 #define RHINE_EECSR_EDI 0x02
270 #define RHINE_EECSR_EDO 0x01
274 #define RHINE_CFGA_EELOAD 0x80
275 #define RHINE_CFGA_JUMPER 0x40
276 #define RHINE_CFGA_MMIEN 0x20
277 #define RHINE_CFGA_MIIOPT 0x10
278 #define RHINE_CFGA_AUTOOPT 0x08
279 #define RHINE_CFGA_GPIO2I 0x04
280 #define RHINE_CFGA_GPIO2O 0x02
281 #define RHINE_CFGA_GPIO2OE 0x01
283 #define RHINE_CFGB_QPKTDIS 0x80
284 #define RHINE_CFGB_TRACEN 0x40
285 #define RHINE_CFGB_MRDM 0x20
286 #define RHINE_CFGB_TXARBIT 0x10
287 #define RHINE_CFGB_RXARBIT 0x08
288 #define RHINE_CFGB_MWWAIT 0x04
289 #define RHINE_CFGB_MRWAIT 0x02
290 #define RHINE_CFGB_LATMEN 0x01
292 #define RHINE_CFGC_BROPT 0x40
293 #define RHINE_CFGC_DLYEN 0x20
294 #define RHINE_CFGC_BTSEL 0x08
295 #define RHINE_CFGC_BPS2 0x04
296 #define RHINE_CFGC_BPS1 0x02
297 #define RHINE_CFGC_BPS0 0x01
299 #define RHINE_CFGD_GPIOEN 0x80
300 #define RHINE_CFGD_DIAG 0x40
301 #define RHINE_CFGD_MRDLEN 0x20
302 #define RHINE_CFGD_MAGIC 0x10
303 #define RHINE_CFGD_CRANDOM 0x08
304 #define RHINE_CFGD_CAP 0x04
305 #define RHINE_CFGD_MBA 0x02
306 #define RHINE_CFGD_BAKOPT 0x01
311 //----------------------------------------------------------------------------
312 // Receive buffer Descriptor
313 #define RHINE_RDES0 0x00 // frame length, status registers
314 #define RHINE_RDES1 0x04 // receive length
315 #define RHINE_RDES2 0x08 // rx data buffer
316 #define RHINE_RDES3 0x0c // next
317 #define RHINE_RD_SIZE 0x10
319 #define RHINE_RDES0_OWN 0x80000000
320 #define RHINE_RDES0_FLNG_mask 0x07ff0000
321 #define RHINE_RDES0_FLNG_shift 16
322 #define RHINE_RDES0_RXOK 0x00008000
323 #define RHINE_RDES0_RES1 0x00004000
324 #define RHINE_RDES0_MAR 0x00002000
325 #define RHINE_RDES0_BAR 0x00001000
326 #define RHINE_RDES0_PHY 0x00000800
327 #define RHINE_RDES0_CHN 0x00000400
328 #define RHINE_RDES0_STP 0x00000200
329 #define RHINE_RDES0_EDP 0x00000100
330 #define RHINE_RDES0_BUFF 0x00000080
331 #define RHINE_RDES0_SERR 0x00000040
332 #define RHINE_RDES0_RUNT 0x00000020
333 #define RHINE_RDES0_LONG 0x00000010
334 #define RHINE_RDES0_FOV 0x00000008
335 #define RHINE_RDES0_FAE 0x00000004
336 #define RHINE_RDES0_CRC 0x00000002
337 #define RHINE_RDES0_RERR 0x00000001
339 #define RHINE_RD_RLEN_IC 0x00800000
340 #define RHINE_RD_RLEN_C 0x00008000
341 #define RHINE_RD_RLEN_RLEN_mask 0x000007ff
344 //----------------------------------------------------------------------------
345 // Transmit buffer Descriptor
346 #define RHINE_TDES0 0x00 // status & own
347 #define RHINE_TDES1 0x04 // tx config & length
348 #define RHINE_TDES2 0x08 // tx data buffer
349 #define RHINE_TDES3 0x0c // next
350 #define RHINE_TD_SIZE 0x10
352 #define RHINE_TDES0_OWN 0x80000000
353 #define RHINE_TDES0_TXOK 0x00008000
354 #define RHINE_TDES0_JAB 0x00004000
355 #define RHINE_TDES0_SERR 0x00002000
356 #define RHINE_TDES0_RES1 0x00001000
357 #define RHINE_TDES0_RES2 0x00000800
358 #define RHINE_TDES0_CRS 0x00000400
359 #define RHINE_TDES0_OWC 0x00000200
360 #define RHINE_TDES0_ABT 0x00000100
361 #define RHINE_TDES0_CDH 0x00000080
362 #define RHINE_TDES0_NCR_mask 0x00000038
363 #define RHINE_TDES0_NCR_shift 3
364 #define RHINE_TDES0_RES3 0x00000004
365 #define RHINE_TDES0_UDF 0x00000002
366 #define RHINE_TDES0_DFR 0x00000001
368 #define RHINE_TDES1_TCR_mask 0x00ff0000
369 #define RHINE_TDES1_TCR_shift 16
370 #define RHINE_TDES1_IC 0x00800000
371 #define RHINE_TDES1_EDP 0x00400000
372 #define RHINE_TDES1_STP 0x00200000
373 #define RHINE_TDES1_CRC 0x00010000
374 #define RHINE_TDES1_C 0x00008000
375 #define RHINE_TDES1_TLNG_mask 0x000007ff
377 // ------------------------------------------------------------------------
382 #define MII_BMCR_RENEGOTIATE 0x3300
384 #define MII_BMSR_AN_COMPLETE 0x0020
385 #define MII_BMSR_LINK 0x0004
387 // ------------------------------------------------------------------------
389 #ifdef KEEP_STATISTICS
390 struct via_rhine_stats {
391 unsigned int tx_good ;
392 unsigned int tx_max_collisions ;
393 unsigned int tx_late_collisions ;
394 unsigned int tx_underrun ;
395 unsigned int tx_carrier_loss ;
396 unsigned int tx_deferred ;
397 unsigned int tx_sqetesterrors ;
398 unsigned int tx_single_collisions;
399 unsigned int tx_mult_collisions ;
400 unsigned int tx_total_collisions ;
401 unsigned int rx_good ;
402 unsigned int rx_crc_errors ;
403 unsigned int rx_align_errors ;
404 unsigned int rx_resource_errors ;
405 unsigned int rx_overrun_errors ;
406 unsigned int rx_collisions ;
407 unsigned int rx_short_frames ;
408 unsigned int rx_too_long_frames ;
409 unsigned int rx_symbol_errors ;
410 unsigned int interrupts ;
411 unsigned int rx_count ;
412 unsigned int rx_deliver ;
413 unsigned int rx_resource ;
414 unsigned int rx_restart ;
415 unsigned int tx_count ;
416 unsigned int tx_complete ;
417 unsigned int tx_dropped ;
421 typedef struct rhine_priv_data {
423 cyg_uint8 // (split up for atomic byte access)
424 found:1, // was hardware discovered?
425 mac_addr_ok:1, // can we bring up?
426 active:1, // has this if been brung up?
427 hardwired_esa:1, // set if ESA is hardwired via CDL
430 int txbusy; // A packet has been sent
431 unsigned long txkey; // Used to ack when packet sent
432 unsigned char* base; // Base address of controller IO region
433 cyg_vector_t interrupt; // Interrupt vector used by controller
434 unsigned char esa[6]; // Controller ESA
435 // Function to configure the ESA - may fetch ESA from EPROM or
436 // RedBoot config option.
437 void (*config_esa)(struct rhine_priv_data* cpd);
438 void *ndp; // Network Device Pointer
440 cyg_handle_t interrupt_handle;
441 cyg_interrupt interrupt_object;
445 int phys_id; // ID of physical MII controller
447 cyg_uint8* rx_buffers; // ptr to base of buffer mem
448 cyg_uint8* rx_ring; // ptr to base of rx ring memory
449 int rx_ring_cnt; // number of entries in ring
450 int rx_ring_log_cnt; // log of above
451 int rx_ring_next; // index of next full ring entry
453 cyg_uint8* tx_buffers;
457 int tx_ring_free; // index of next free ring entry
458 int tx_ring_alloc; // index of first controller owned ring
459 int tx_ring_owned; // number of controller owned ring entries
462 #ifdef KEEP_STATISTICS
463 struct via_rhine_stats stats;
467 // ------------------------------------------------------------------------
468 #endif CYGONCE_DEVS_ETH_VIA_RHINE_H