1 #ifndef CYGONCE_KARO_TX25_H
2 #define CYGONCE_KARO_TX25_H
4 //=============================================================================
6 // Platform specific support (register layout, etc)
8 //=============================================================================
9 //####ECOSGPLCOPYRIGHTBEGIN####
10 // -------------------------------------------
11 // This file is part of eCos, the Embedded Configurable Operating System.
12 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
14 // eCos is free software; you can redistribute it and/or modify it under
15 // the terms of the GNU General Public License as published by the Free
16 // Software Foundation; either version 2 or (at your option) any later version.
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19 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
23 // You should have received a copy of the GNU General Public License along
24 // with eCos; if not, write to the Free Software Foundation, Inc.,
25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27 // As a special exception, if other files instantiate templates or use macros
28 // or inline functions from this file, or you compile this file and link it
29 // with other works to produce a work based on this file, this file does not
30 // by itself cause the resulting work to be covered by the GNU General Public
31 // License. However the source code for this file must still be made available
32 // in accordance with section (3) of the GNU General Public License.
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38 // at http://sources.redhat.com/ecos/ecos-license/
39 // -------------------------------------------
40 //####ECOSGPLCOPYRIGHTEND####
41 //===========================================================================
43 #include <cyg/hal/hal_soc.h> // Hardware definitions
45 #include CYGHWR_MEMORY_LAYOUT_H
47 #define SZ_1K 0x00000400
48 #define SZ_2K 0x00000800
49 #define SZ_4K 0x00001000
50 #define SZ_8K 0x00002000
51 #define SZ_16K 0x00004000
52 #define SZ_32K 0x00008000
53 #define SZ_64K 0x00010000
54 #define SZ_128K 0x00020000
55 #define SZ_256K 0x00040000
56 #define SZ_512K 0x00080000
57 #define SZ_1M 0x00100000
58 #define SZ_2M 0x00200000
59 #define SZ_4M 0x00400000
60 #define SZ_8M 0x00800000
61 #define SZ_16M 0x01000000
62 #define SZ_32M 0x02000000
63 #define SZ_64M 0x04000000
64 #define SZ_128M 0x08000000
65 #define SZ_256M 0x10000000
66 #define SZ_512M 0x20000000
67 #define SZ_1G 0x40000000
69 #define RAM_BANK0_BASE CSD0_BASE_ADDR
70 #define RAM_BANK1_BASE CSD1_BASE_ADDR
71 #if SDRAM_SIZE > SZ_32M
72 #define RAM_BANK0_SIZE (SDRAM_SIZE / 2)
73 #define RAM_BANK1_SIZE (SDRAM_SIZE / 2)
75 #define RAM_BANK0_SIZE SDRAM_SIZE
77 #define TX25_SDRAM_SIZE SDRAM_SIZE
79 #define TX25_LED_MASK (1 << 7)
80 #define TX25_LED_REG_ADDR (GPIO2_BASE_ADDR + GPIO_DR)
84 #define LED_IS_ON(n) ({ \
86 HAL_READ_UINT32(TX25_LED_REG_ADDR, __val); \
87 __val & TX25_LED_MASK; \
90 #define TURN_LED_ON(n) \
93 HAL_READ_UINT32(TX25_LED_REG_ADDR, __val); \
94 __val |= TX25_LED_MASK; \
95 HAL_WRITE_UINT32(TX25_LED_REG_ADDR, __val); \
98 #define TURN_LED_OFF(n) \
101 HAL_READ_UINT32(TX25_LED_REG_ADDR, __val); \
102 __val &= ~TX25_LED_MASK; \
103 HAL_WRITE_UINT32(TX25_LED_REG_ADDR, __val); \
106 #define BOARD_DEBUG_LED(n) \
108 if (n >= 0 && n < LED_MAX_NUM) { \
116 #define BLINK_LED(l, n) \
119 for (_i = 0; _i < (n); _i++) { \
120 BOARD_DEBUG_LED(l); \
121 HAL_DELAY_US(200000); \
122 BOARD_DEBUG_LED(l); \
123 HAL_DELAY_US(300000); \
125 HAL_DELAY_US(1000000); \
128 #if !defined(__ASSEMBLER__)
133 #define gpio_tst_bit(grp, gpio) _gpio_tst_bit(grp, gpio, __FUNCTION__, __LINE__)
134 static inline int _gpio_tst_bit(int grp, int gpio, const char *func, int line)
141 reg = GPIO1_BASE_ADDR;
144 reg = GPIO2_BASE_ADDR;
147 reg = GPIO3_BASE_ADDR;
150 reg = GPIO4_BASE_ADDR;
156 if (gpio < 0 || gpio > 31) {
159 val = readl(reg + GPIO_PSR0);
160 return !!(val & (1 << gpio));
163 static inline void gpio_set_bit(int grp, int gpio)
170 reg = GPIO1_BASE_ADDR;
173 reg = GPIO2_BASE_ADDR;
176 reg = GPIO3_BASE_ADDR;
179 reg = GPIO4_BASE_ADDR;
185 if (gpio < 0 || gpio > 31) {
188 val = readl(reg + GPIO_DR);
189 writel(val | (1 << gpio), reg + GPIO_DR);
192 static inline void gpio_clr_bit(int grp, int gpio)
199 reg = GPIO1_BASE_ADDR;
202 reg = GPIO2_BASE_ADDR;
205 reg = GPIO3_BASE_ADDR;
208 reg = GPIO4_BASE_ADDR;
214 if (gpio < 0 || gpio > 31) {
217 val = readl(reg + GPIO_DR);
218 writel(val & ~(1 << gpio), reg + GPIO_DR);
222 #endif /* CYGONCE_KARO_TX25_H */