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34 # ====================================================================
35 ######DESCRIPTIONBEGIN####
38 # Original data: gthomas
42 #####DESCRIPTIONEND####
44 # ====================================================================
45 cdl_package CYGPKG_HAL_ARM_MX25 {
46 display "Freescale SoC architecture"
50 define_header hal_arm_soc.h
52 This HAL variant package provides generic
53 support for the Freescale SoC. It is also
54 necessary to select a specific target platform HAL
57 implements CYGINT_HAL_ARM_ARCH_ARM9
58 implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
60 # Let the architectural HAL see this variant's interrupts file -
61 # the SoC has no variation between targets here.
63 puts $::cdl_header "#define CYGBLD_HAL_VAR_INTS_H <cyg/hal/hal_var_ints.h>"
64 puts $::cdl_system_header "#define CYGBLD_HAL_ARM_VAR_IO_H"
66 puts $::cdl_header "#define CYGPRI_KERNEL_TESTS_DHRYSTONE_PASSES 1000000"
69 compile soc_diag.c soc_misc.c
70 compile -library=libextras.a cmds.c
72 cdl_option CYGHWR_MX25_MDDR {
73 display "mDDR/DDR2 support"
76 When this option is enabled, it indicates support
77 for Mobile DDR on the MX25 3stack CPU board. mDDR
78 was used on TO1.0 boards. Subsequent boards use
81 puts $::cdl_system_header "#define MEMORY_MDDR_ENABLE"
85 cdl_option CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK {
86 display "Processor clock rate"
87 active_if { CYG_HAL_STARTUP == "ROM" }
89 legal_values 150000 200000
90 default_value { CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT ?
91 CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT : 150000}
93 The processor can run at various frequencies.
94 These values are expressed in KHz. Note that there are
95 several steppings of the rated to run at different
96 maximum frequencies. Check the specs to make sure that your
97 particular processor can run at the rate you select here."
100 # Real-time clock/counter specifics
101 cdl_component CYGNUM_HAL_RTC_CONSTANTS {
102 display "Real-time clock constants"
106 cdl_option CYGNUM_HAL_RTC_NUMERATOR {
107 display "Real-time clock numerator"
109 calculated 1000000000
111 cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
112 display "Real-time clock denominator"
116 This option selects the heartbeat rate for the real-time clock.
117 The rate is specified in ticks per second. Change this value
118 with caution - too high and your system will become saturated
119 just handling clock interrupts, too low and some operations
120 such as thread scheduling may become sluggish."
122 cdl_option CYGNUM_HAL_RTC_PERIOD {
123 display "Real-time clock period"
125 calculated (3686400/CYGNUM_HAL_RTC_DENOMINATOR) ;# Clock for OS Timer is 3.6864MHz
129 # Control over hardware layout.
130 cdl_interface CYGHWR_HAL_ARM_SOC_UART1 {
131 display "UART1 available as diagnostic/debug channel"
133 The chip has multiple serial channels which may be
134 used for different things on different platforms. This
135 interface allows a platform to indicate that the specified
136 serial port can be used as a diagnostic and/or debug channel."
139 cdl_interface CYGHWR_HAL_ARM_SOC_UART2 {
140 display "UART2 available as diagnostic/debug channel"
142 The chip has multiple serial channels which may be
143 used for different things on different platforms. This
144 interface allows a platform to indicate that the specified
145 serial port can be used as a diagnostic and/or debug channel."
148 cdl_interface CYGHWR_HAL_ARM_SOC_UART3 {
149 display "UART3 available as diagnostic/debug channel"
151 The chip has multiple serial channels which may be
152 used for different things on different platforms. This
153 interface allows a platform to indicate that the specified
154 serial port can be used as a diagnostic and/or debug channel."
157 cdl_interface CYGHWR_HAL_ARM_SOC_UART4 {
158 display "UART4 available as diagnostic/debug channel"
160 The chip has multiple serial channels which may be
161 used for different things on different platforms. This
162 interface allows a platform to indicate that the specified
163 serial port can be used as a diagnostic and/or debug channel."
166 cdl_interface CYGHWR_HAL_ARM_SOC_UART5 {
167 display "UART5 available as diagnostic/debug channel"
169 The chip has multiple serial channels which may be
170 used for different things on different platforms. This
171 interface allows a platform to indicate that the specified
172 serial port can be used as a diagnostic and/or debug channel."
175 cdl_interface CYGINT_DEVS_ETH_FEC_REQUIRED {
176 display "FEC ethernet driver required"
179 implements CYGINT_DEVS_ETH_FEC_REQUIRED