1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 //=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
16 // eCos is free software; you can redistribute it and/or modify it under
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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29 // As a special exception, if other files instantiate templates or use macros
30 // or inline functions from this file, or you compile this file and link it
31 // with other works to produce a work based on this file, this file does not
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40 // at http://sources.redhat.com/ecos/ecos-license/
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //===========================================================================
45 #include <pkgconf/system.h> // System-wide configuration info
46 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
47 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
48 #include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
49 #include <cyg/hal/hal_mmu.h> // MMU definitions
50 #include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
52 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
53 #define PLATFORM_SETUP1 _platform_setup1
54 #define CYGHWR_HAL_ARM_HAS_MMU
56 #ifdef CYG_HAL_STARTUP_ROMRAM
57 #define CYGSEM_HAL_ROM_RESET_USES_JUMP
60 #define CYGHWR_HAL_ROM_VADDR 0x0
62 // This macro represents the initial startup code for the platform
63 // r11 is reserved to contain chip rev info in this file
64 .macro _platform_setup1
65 FSL_BOARD_SETUP_START:
66 // invalidate I/D cache/TLB and drain write buffer
68 mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
69 mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
70 mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
75 mov r0, #SDRAM_NON_FLASH_BOOT
76 ldr r1, AVIC_VECTOR0_ADDR_W
77 str r0, [r1] // for checking boot source from nand, nor or sdram
79 // setup System Controls
80 ldr r0, SOC_SYSCTRL_BASE_W
82 str r1, [r0, #(SOC_SYSCTRL_PCSR - SOC_SYSCTRL_BASE)]
83 ldr r1, [r0, #(SOC_SYSCTRL_FMCR - SOC_SYSCTRL_BASE)]
84 and r1, r1, #0xFFFFFFF0
86 str r1, [r0, #(SOC_SYSCTRL_FMCR - SOC_SYSCTRL_BASE)]
90 init_drive_strength_start:
95 // check if sdram has been setup
96 cmp pc, #SDRAM_BASE_ADDR
98 cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE)
99 blo HWInitialise_skip_SDRAM_setup
103 // Now we must boot from Flash
104 mov r0, #NOR_FLASH_BOOT
105 ldr r1, AVIC_VECTOR0_ADDR_W
111 HWInitialise_skip_SDRAM_setup:
113 add r2, r0, #0x800 // 2K window
115 blo Normal_Boot_Continue
117 bhi Normal_Boot_Continue
119 /* Copy image from flash to SDRAM first */
120 ldr r1, MXC_REDBOOT_ROM_START
122 1: ldmia r0!, {r3-r10}
129 and r0, pc, r1 /* offset of pc */
130 ldr r1, MXC_REDBOOT_ROM_START
139 // Check if x16/2kb page
140 ldr r7, SOC_SYSCTRL_BASE_W
142 ands r7, r7, #(1 << 5)
144 mov r0, #NAND_FLASH_BOOT
145 ldr r1, AVIC_VECTOR0_ADDR_W
148 ldr r1, AVIC_VECTOR1_ADDR_W
151 ldr r0, NFC_BASE_W //r0: nfc base. Reloaded after each page copying
152 mov r1, #0x800 //r1: starting flash addr to be copied. Updated constantly
153 add r2, r0, #0x800 //2K Page:: r2: end of 1st RAM buf. Doesn't change
154 addeq r2, r0, #0x200 //512 Page:: r2: end of 1st RAM buf. Doesn't change
155 add r12, r0, #0xE00 //r12: NFC register base. Doesn't change
156 ldr r11, MXC_REDBOOT_ROM_START
157 add r13, r11, #REDBOOT_IMAGE_SIZE //r13: end of SDRAM address for copying. Doesn't change
158 add r11, r11, r1 //r11: starting SDRAM address for copying. Updated constantly
160 //unlock internal buffer
165 // NFC_CMD_INPUT(FLASH_Read_Mode1);
169 // Check if x16/2kb page
170 ldr r7, SOC_SYSCTRL_BASE_W
172 ands r7, r7, #(1 << 5)
175 // start_nfc_addr_ops(ADDRESS_INPUT_READ_PAGE, addr, nflash_dev_info->base_mask);
177 do_addr_input //1st addr cycle
179 do_addr_input //2nd addr cycle
181 do_addr_input //3rd addr cycle
183 do_addr_input //4th addr cycle
184 b end_of_nfc_addr_ops
187 // start_nfc_addr_ops(ADDRESS_INPUT_READ_PAGE, addr, nflash_dev_info->base_mask);
189 do_addr_input //1st addr cycle
191 do_addr_input //2nd addr cycle
193 do_addr_input //3rd addr cycle
195 do_addr_input //4th addr cycle
197 do_addr_input //4th addr cycle
199 // NFC_CMD_INPUT(FLASH_Read_Mode1_2K);
204 // NFC_DATA_OUTPUT(buf, FDO_PAGE_SPARE_VAL);
205 // writew(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN,
206 // NAND_FLASH_CONFIG1_REG);
210 // Check if x16/2kb page
211 ldr r7, SOC_SYSCTRL_BASE_W
213 ands r7, r7, #(1 << 5)
215 beq nfc_addr_data_output_done_512
217 // For 2K page - 2nd 512
233 // check for bad block
234 mov r3, r1, lsl #(32-17) // get rid of block number
235 cmp r3, #(0x800 << (32-17)) // check if not page 0 or 1
236 b nfc_addr_data_output_done
237 nfc_addr_data_output_done_512:
238 // check for bad block
239 mov r3, r1, lsl #(32-5-9) // get rid of block number
240 cmp r3, #(512 << (32-5-9)) // check if not page 0 or 1
242 nfc_addr_data_output_done:
244 add r4, r0, #0x800 //r3 -> spare area buf 0
249 // really sucks. Bad block!!!!
252 // even suckier since we already read the first page!
254 // Check if x16/2kb page
255 ldr r7, SOC_SYSCTRL_BASE_W
257 ands r7, r7, #(1 << 5)
259 subeq r11, r11, #512 //rewind 1 page for the sdram pointer
260 subeq r1, r1, #512 //rewind 1 page for the flash pointer
263 subne r11, r11, #0x800 //rewind 1 page for the sdram pointer
264 subne r1, r1, #0x800 //rewind 1 page for the flash pointer
267 // Check if x16/2kb page
268 ldr r7, SOC_SYSCTRL_BASE_W
270 ands r7, r7, #(1 << 5)
272 addeq r1, r1, #(32*512)
273 addne r1, r1, #(64*2048)
278 1: ldmia r0!, {r3-r10}
283 bge NAND_Copy_Main_done
284 // Check if x16/2kb page
285 ldr r7, SOC_SYSCTRL_BASE_W
287 ands r7, r7, #(1 << 5)
296 Normal_Boot_Continue:
298 #ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
299 /* Copy image from flash to SDRAM first */
302 ldr r1, MXC_REDBOOT_ROM_START
304 beq HWInitialise_skip_SDRAM_copy
306 add r2, r0, #REDBOOT_IMAGE_SIZE
308 1: ldmia r0!, {r3-r10}
315 and r0, pc, r1 /* offset of pc */
316 ldr r1, =(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000 + 0x8)
322 #endif /* CYG_HAL_STARTUP_ROMRAM */
324 HWInitialise_skip_SDRAM_copy:
331 ldr r1, =(SOC_CRM_BASE)
332 ldr r2, [r1, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
333 /*Get chip ID://eq:i.MX27 TO1; neq:i.MX27 TO2*/
334 ldr r1, =SOC_SI_ID_REG
336 ands r1, r1, #0xF0000000
338 orreq r2, r2, #0xF000
339 orrne r2, r2, #0x01C0
341 ldr r1, =(SOC_CRM_BASE)
342 str r2, [r1, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
344 /* end of NAND clock divider setup */
346 // TLSbo76381: enable USB/PP/DMA burst override bits in GPCR
347 ldr r1, =(SOC_SYSCTRL_GPCR)
352 // Set up a stack [for calling C code]
353 ldr r1, =__startup_stack
354 ldr r2, =RAM_BANK0_BASE
362 mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
363 orr r1, r1, #7 // enable MMU bit
364 mcr MMU_CP, 0, r1, MMU_Control, c0
365 mov pc,r2 /* Change address spaces */
370 // Save shadow copy of BCR, also hardware configuration
374 str r9,[r1] // Saved far above...
376 .endm // _platform_setup1
380 ldrh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
381 ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
383 bx lr // do_wait_op_done
386 mov r3, #(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN)
387 strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
389 // writew(buf_no, RAM_BUFFER_ADDRESS_REG);
390 strh r8, [r12, #RAM_BUFFER_ADDRESS_REG_OFF]
391 // writew(FDO_PAGE_SPARE_VAL & 0xFF, NAND_FLASH_CONFIG2_REG);
392 mov r3, #FDO_PAGE_SPARE_VAL
393 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
396 #else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
397 #define PLATFORM_SETUP1
401 ldr r0, SOC_CRM_BASE_W
402 // disable MPLL/SPLL first
403 ldr r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
405 str r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
407 /* Get the chip version and configure PLLs*/
408 ldr r1, SOC_SI_ID_REG_W
410 ands r1, r1, #0xF0000000
412 ldreq r1, CRM_MPCTL0_VAL_W
413 ldrne r1, CRM_MPCTL0_VAL2_W
414 str r1, [r0, #(SOC_CRM_MPCTL0 - SOC_CRM_BASE)]
416 ldreq r1, CRM_SPCTL0_VAL_W
417 ldrne r1, CRM_SPCTL0_VAL2_W
418 str r1, [r0, #(SOC_CRM_SPCTL0 - SOC_CRM_BASE)]
420 // enable/restart SPLL/MPLL
421 ldr r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
422 #ifdef PLL_REF_CLK_32768HZ
423 // Make sure to use CKIL
424 bic r1, r1, #(3 << 16)
426 orr r1, r1, #(3 << 16) // select 26MHz
428 orr r1, r1, #0x000C0000
429 orr r1, r1, #0x00000003
430 str r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
432 // add some delay here
437 //Check The chip version TO1 or TO2
438 ldr r1, SOC_SI_ID_REG_W
440 ands r1, r1, #0xF0000000
442 ldreq r2, SOC_CRM_CSCR_W
443 ldrne r2, SOC_CRM_CSCR2_W
444 str r2, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
446 //for i.MX27 TO2, Set divider of H264_CLK to zero, NFC to 3.
447 ldrne r2, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
448 bicne r2, r2, #0x0000FC00
449 strne r2, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
452 /* Configure PCDR1 */
453 ldr r1, SOC_CRM_PCDR1_W
454 str r1, [r0, #(SOC_CRM_PCDR1 - SOC_CRM_BASE)]
456 // Configure PCCR0 and PCCR1
457 ldr r1, SOC_CRM_PCCR0_W
458 str r1, [r0, #(SOC_CRM_PCCR0 - SOC_CRM_BASE)]
460 ldr r1, [r0, #(SOC_CRM_PCCR1 - SOC_CRM_BASE)]
462 str r1, [r0, #(SOC_CRM_PCCR1 - SOC_CRM_BASE)]
463 // make default CLKO to be FCLK
464 ldr r1, [r0, #(SOC_CRM_CCSR - SOC_CRM_BASE)]
465 and r1, r1, #0xFFFFFFE0
467 str r1, [r0, #(SOC_CRM_CCSR - SOC_CRM_BASE)]
470 /* CS0 sync mode setup */
473 * Sync mode (AHB Clk = 133MHz ; BCLK = 44.3MHz):
475 /* Flash reset command */
476 ldr r0, CS0_BASE_ADDR_W
480 ldr r2, CS0_CMD_0xAAA
485 ldr r2, CS0_CMD_0x554
490 ldr r2, CS0_CMD_0xAAA
494 /* Write flash config register */
495 ldr r1, CS0_CFG_0x66CA
497 /* Flash reset command */
501 ldr r0, =SOC_CS0_CTL_BASE
502 ldr r1, CS0_0x23524E80
503 str r1, [r0, #CSCRU_OFFSET]
504 ldr r1, CS0_0x10000D03
505 str r1, [r0, #CSCRL_OFFSET]
506 ldr r1, CS0_0x00720900
507 str r1, [r0, #CSCRA_OFFSET]
508 .endm /* init_cs0_sync */
510 .macro init_cs5 /* 3-Stack board expanded IOs */
511 ldr r1, SOC_CS5_CTL_BASE_W
512 ldr r2, CS5_CSCRU_0x0000DCF6
513 str r2, [r1, #CSCRU_OFFSET]
514 ldr r2, CS5_CSCRL_0x444A4541
515 str r2, [r1, #CSCRL_OFFSET]
516 ldr r2, CS5_CSCRA_0x44443302
517 str r2, [r1, #CSCRA_OFFSET]
521 // setup AIPI1 and AIPI2
522 mov r0, #SOC_AIPI1_BASE
523 ldr r1, AIPI1_0x20040304
524 str r1, [r0] /* PSR0 */
525 ldr r2, AIPI1_0xDFFBFCFB
526 str r2, [r0, #4] /* PSR1 */
527 // set r0 = AIPI2 base
530 str r1, [r0] /* PSR0 */
532 str r2, [r0, #4] /* PSR1 */
536 ldr r0, SOC_MAX_BASE_W
537 add r1, r0, #MAX_SLAVE_PORT1_OFFSET
538 add r2, r0, #MAX_SLAVE_PORT2_OFFSET
539 add r0, r0, #MAX_SLAVE_PORT0_OFFSET
542 ldr r6, SOC_MAX_0x00302145 /* Priority SLCD>EMMA>DMA>Codec>DAHB>IAHB */
543 str r6, [r0, #MAX_SLAVE_MPR_OFFSET] /* same for all slave ports */
544 str r6, [r0, #MAX_SLAVE_AMPR_OFFSET]
545 str r6, [r1, #MAX_SLAVE_MPR_OFFSET]
546 str r6, [r1, #MAX_SLAVE_AMPR_OFFSET]
547 str r6, [r2, #MAX_SLAVE_MPR_OFFSET]
548 str r6, [r2, #MAX_SLAVE_AMPR_OFFSET]
551 .macro init_drive_strength
552 ldr r0, SOC_SYSCTRL_BASE_W
553 ldr r1, DS_0x55555555
554 str r1, [r0, #(SOC_SYSCTRL_DSCR3 - SOC_SYSCTRL_BASE)]
555 str r1, [r0, #(SOC_SYSCTRL_DSCR5 - SOC_SYSCTRL_BASE)]
556 str r1, [r0, #(SOC_SYSCTRL_DSCR6 - SOC_SYSCTRL_BASE)]
557 ldr r1, DS_0x00005005
558 str r1, [r0, #(SOC_SYSCTRL_DSCR7 - SOC_SYSCTRL_BASE)]
559 ldr r1, DS_0x15555555
560 str r1, [r0, #(SOC_SYSCTRL_DSCR8 - SOC_SYSCTRL_BASE)]
561 .endm // init_drive_strength
563 .macro setup_sdram_ddr
564 ldr r0, SOC_ESDCTL_BASE_W
565 mov r2, #SOC_CSD0_BASE
566 mov r1, #0x8 // initial reset
568 // Hold for more than 200ns
577 //Check The chip version TO1 or TO2
578 ldr r1, SOC_SI_ID_REG_W
580 ands r1, r1, #0xF0000000
581 // add Latency on CAS only for TO2
582 ldreq r1, SDRAM_0x00795729
583 ldrne r1, SDRAM_0x00795429
586 ldr r1, SDRAM_0x92200000
589 ldr r1, SDRAM_0xA2200000
593 ldr r1, SDRAM_0xB2200000
596 add r3, r2, #0x1000000
598 ldr r1, SDRAM_0x82228485
600 .endm // setup_sdram_ddr
603 strh r3, [r12, #NAND_FLASH_CMD_REG_OFF]
604 mov r3, #NAND_FLASH_CONFIG2_FCMD_EN;
605 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
607 .endm // nfc_cmd_input
611 strh r3, [r12, #NAND_FLASH_ADD_REG_OFF]
612 mov r3, #NAND_FLASH_CONFIG2_FADD_EN
613 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
615 .endm // do_addr_input
617 #define PLATFORM_VECTORS _platform_vectors
618 .macro _platform_vectors
619 .globl _board_BCR, _board_CFG
620 _board_BCR: .long 0 // Board Control register shadow
621 _board_CFG: .long 0 // Board Configuration (read at RESET)
624 MXC_REDBOOT_ROM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
625 CONST_0xFFF: .word 0xFFF
626 AVIC_VECTOR0_ADDR_W: .word MXCBOOT_FLAG_REG
627 AVIC_VECTOR1_ADDR_W: .word MXCFIS_FLAG_REG
628 SOC_SYSCTRL_BASE_W: .word SOC_SYSCTRL_BASE
629 SOC_MAX_BASE_W: .word SOC_MAX_BASE
630 SOC_MAX_0x00302145: .word 0x00302145
631 SOC_CRM_BASE_W: .word SOC_CRM_BASE
632 CRM_MPCTL0_VAL_W: .word CRM_MPCTL0_VAL
633 CRM_SPCTL0_VAL_W: .word CRM_SPCTL0_VAL
634 SOC_CRM_CSCR_W: .word CRM_CSCR_VAL
635 CRM_MPCTL0_VAL2_W: .word CRM_MPCTL0_VAL2
636 CRM_SPCTL0_VAL2_W: .word CRM_SPCTL0_VAL2
637 SOC_CRM_CSCR2_W: .word CRM_CSCR_VAL2
638 SOC_CRM_PCDR1_W: .word 0x09030913 // p1=20 p2=10 p3=4 p4=10
639 SOC_CRM_PCCR0_W: .word 0x3108480F
640 SOC_CS5_CTL_BASE_W: .word SOC_CS5_CTL_BASE
641 CS5_CSCRU_0x0000DCF6: .word 0x0000DCF6
642 CS5_CSCRL_0x444A4541: .word 0x444A4541
643 CS5_CSCRA_0x44443302: .word 0x44443302
644 NFC_BASE_W: .word NFC_BASE
645 SOC_ESDCTL_BASE_W: .word SOC_ESDCTL_BASE
646 SDRAM_0x00795429: .word 0x00795429
647 SDRAM_0x00795729: .word 0x00795729
648 SDRAM_0x92200000: .word 0x92200000
649 SDRAM_0xA2200000: .word 0xA2200000
650 SDRAM_0xB2200000: .word 0xB2200000
651 SDRAM_0x82228485: .word 0x82228485
652 CS0_0x0000CC03: .word 0x0000CC03
653 CS0_0xA0330D01: .word 0xA0330D01
654 CS0_0x00220800: .word 0x00220800
655 CS0_0x23524E80: .word 0x23524E80
656 CS0_0x10000D03: .word 0x10000D03
657 CS0_0x00720900: .word 0x00720900
658 CS0_CMD_0xAAA: .word 0x0AAA
659 CS0_CMD_0x554: .word 0x0554
660 CS0_CFG_0x66CA: .word 0x66CA
661 CS0_BASE_ADDR_W: .word CS0_BASE_ADDR
662 SOC_CS0_CTL_BASE_W: .word SOC_CS0_CTL_BASE
663 DS_0x55555555: .word 0x55555555
664 DS_0x00005005: .word 0x00005005
665 DS_0x15555555: .word 0x15555555
666 AIPI1_0x20040304: .word 0x20040304
667 AIPI1_0xDFFBFCFB: .word 0xDFFBFCFB
668 PBC_BASE_W: .word PBC_BASE
669 SOC_SI_ID_REG_W: .word SOC_SI_ID_REG
671 /*---------------------------------------------------------------------------*/
672 /* end of hal_platform_setup.h */
673 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */