1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 //=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
16 // eCos is free software; you can redistribute it and/or modify it under
17 // the terms of the GNU General Public License as published by the Free
18 // Software Foundation; either version 2 or (at your option) any later version.
20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 // You should have received a copy of the GNU General Public License along
26 // with eCos; if not, write to the Free Software Foundation, Inc.,
27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
29 // As a special exception, if other files instantiate templates or use macros
30 // or inline functions from this file, or you compile this file and link it
31 // with other works to produce a work based on this file, this file does not
32 // by itself cause the resulting work to be covered by the GNU General Public
33 // License. However the source code for this file must still be made available
34 // in accordance with section (3) of the GNU General Public License.
36 // This exception does not invalidate any other reasons why a work based on
37 // this file might be covered by the GNU General Public License.
39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
40 // at http://sources.redhat.com/ecos/ecos-license/
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //===========================================================================
45 #include <pkgconf/system.h> // System-wide configuration info
46 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
47 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
48 #include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
49 #include <cyg/hal/hal_mmu.h> // MMU definitions
50 #include CYGBLD_HAL_PLF_DEFS_H // Platform specific hardware definitions
51 #include CYGHWR_MEMORY_LAYOUT_H
53 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
54 #define PLATFORM_SETUP1 _platform_setup1
55 #define CYGHWR_HAL_ARM_HAS_MMU
57 #ifdef CYG_HAL_STARTUP_ROMRAM
58 #define CYGSEM_HAL_ROM_RESET_USES_JUMP
61 #define TX27_NAND_PAGE_SIZE 2048
62 #define TX27_NAND_BLKS_PER_PAGE 64
64 #define CYGHWR_HAL_ROM_VADDR 0x0
66 #define DEBUG_LED_BIT 13
67 #define DEBUG_LED_PORT GPIOF_BASE
69 #ifndef CYGOPT_HAL_ARM_TX27_DEBUG
79 #define CYGHWR_LED_MACRO LED_BLINK #\x
80 #define LED_ON bl led_on
81 #define LED_OFF bl led_off
98 // switch user LED (PF13) on STK5
99 ldr r10, DEBUG_LED_PORT
103 ldr r9, [r10, #GPIO_DR]
104 orrne r9, #(1 << DEBUG_LED_BIT) // LED ON
105 biceq r9, #(1 << DEBUG_LED_BIT) // LED OFF
106 str r9, [r10, #GPIO_DR]
125 // initialize GPIO PF13 for LED on STK5
126 ldr r10, DEBUG_LED_PORT
128 ldr r9, [r10, #GPIO_DR]
129 bic r9, #(1 << DEBUG_LED_BIT)
130 str r9, [r10, #GPIO_DR]
132 ldr r9, [r10, #GPIO_OCR1]
133 orr r9, #(3 << (2 * (DEBUG_LED_BIT % 16)))
134 str r9, [r10, #GPIO_OCR1]
136 ldr r9, [r10, #GPIO_GIUS]
137 orr r9, r9, #(1 << DEBUG_LED_BIT)
138 str r9, [r10, #GPIO_GIUS]
140 ldr r9, [r10, #GPIO_DDIR]
141 orr r9, #(1 << DEBUG_LED_BIT)
142 str r9, [r10, #GPIO_DDIR]
146 ldr r10, SOC_CRM_BASE_W
147 ldr r9, [r10, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
148 orr r9, r9, #(1 << 2) /* enable FPM */
149 str r9, [r10, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
155 // This macro represents the initial startup code for the platform
156 // r11 is reserved to contain chip rev info in this file
157 .macro _platform_setup1
158 KARO_TX27_SETUP_START:
159 // invalidate I/D cache/TLB
161 mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
162 mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
163 mcr 15, 0, r0, c7, c10, 4 /* Data Write Barrier */
168 /* configure GPIO PB22 (OSC26M enable) as output high */
171 ldr r9, [r10, #GPIO_OCR2]
172 orr r9, #(3 << (2 * (22 % 16)))
173 str r9, [r10, #GPIO_OCR2]
175 ldr r9, [r10, #GPIO_DR]
176 orr r9, r9, #(1 << 22)
177 str r9, [r10, #GPIO_DR]
179 ldr r9, [r10, #GPIO_GIUS]
180 orr r9, r9, #(1 << 22)
181 str r9, [r10, #GPIO_GIUS]
183 ldr r9, [r10, #GPIO_DDIR]
185 str r9, [r10, #GPIO_DDIR]
189 // setup System Controls
190 ldr r0, SOC_SYSCTRL_BASE_W
192 str r1, [r0, #(SOC_SYSCTRL_PCSR - SOC_SYSCTRL_BASE)]
193 // select 2kpage NAND (NF_FMS), CSD0, CS3
194 mvn r1, #(FMCR_SDCS1_SEL | FMCR_NF_16BIT | FMCR_SLCDC_SEL)
195 str r1, [r0, #(SOC_SYSCTRL_FMCR - SOC_SYSCTRL_BASE)]
199 init_drive_strength_start:
200 @ init_drive_strength
202 // check if sdram has been setup
203 cmp pc, #SDRAM_BASE_ADDR
205 cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE)
206 blo HWInitialise_skip_SDRAM_setup
214 HWInitialise_skip_SDRAM_setup:
216 add r2, r0, #0x800 // 2K window
218 blo Normal_Boot_Continue
220 bhi Normal_Boot_Continue
223 /* Copy image from flash to SDRAM first */
224 ldr r1, MXC_REDBOOT_RAM_START
232 ldr r1, MXC_REDBOOT_RAM_START
245 #ifdef CYGOPT_HAL_ARM_TX27_DEBUG
257 ldr r0, NFC_BASE_W //r0: nfc base. Reloaded after each page copying
258 mov r1, #TX27_NAND_PAGE_SIZE //r1: starting flash addr to be copied. Updated constantly
259 add r2, r0, #TX27_NAND_PAGE_SIZE //r2: end of 1st RAM buf. Doesn't change
260 add r4, r0, #0xE00 //r4: NFC register base. Doesn't change
261 ldr r5, MXC_REDBOOT_RAM_START
262 add r6, r5, #REDBOOT_IMAGE_SIZE //r6: end of SDRAM address for copying. Doesn't change
263 add r5, r5, r1 //r5: starting SDRAM address for copying. Updated constantly
265 // enable ECC, disable interrupts
266 mov r3, #(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN)
267 strh r3, [r4, #NAND_FLASH_CONFIG1_REG_OFF]
269 //unlock internal buffer
276 strh r8, [r4, #RAM_BUFFER_ADDRESS_REG_OFF]
286 bl nfc_addr_input //2nd addr cycle
289 bl nfc_addr_input //3rd addr cycle
292 bl nfc_addr_input //4th addr cycle
301 strh r8, [r4, #RAM_BUFFER_ADDRESS_REG_OFF]
304 strh r8, [r4, #RAM_BUFFER_ADDRESS_REG_OFF]
307 strh r8, [r4, #RAM_BUFFER_ADDRESS_REG_OFF]
310 // check for bad block
311 mov r3, r1, lsl #(32-17) // get rid of block number
312 cmp r3, #(TX27_NAND_PAGE_SIZE << (32-17)) // check if not first or second page in block
315 add r9, r0, #TX27_NAND_PAGE_SIZE //r3 -> spare area buf 0
320 // really sucks. Bad block!!!!
323 // even suckier since we already read the first page!
324 sub r5, r5, #TX27_NAND_PAGE_SIZE //rewind 1 page for the sdram pointer
325 sub r1, r1, #TX27_NAND_PAGE_SIZE //rewind 1 page for the flash pointer
327 #ifdef CYGOPT_HAL_ARM_TX27_DEBUG
331 add r1, r1, #(TX27_NAND_BLKS_PER_PAGE*TX27_NAND_PAGE_SIZE)
345 bge NAND_Copy_Main_done
347 add r1, r1, #TX27_NAND_PAGE_SIZE
352 Normal_Boot_Continue:
354 // Code and all data used up to here must fit within the first 2KiB of FLASH ROM!
355 #ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
356 /* Copy image from flash to SDRAM first */
359 ldr r1, MXC_REDBOOT_RAM_START
361 beq HWInitialise_skip_SDRAM_copy
363 add r2, r0, #REDBOOT_IMAGE_SIZE
373 #endif /* CYG_HAL_STARTUP_ROMRAM */
375 HWInitialise_skip_SDRAM_copy:
382 ldr r1, =(SOC_CRM_BASE)
383 ldr r2, [r1, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
386 ldr r1, =(SOC_CRM_BASE)
387 str r2, [r1, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
389 /* end of NAND clock divider setup */
391 // TLSbo76381: enable USB/PP/DMA burst override bits in GPCR
392 ldr r1, =(SOC_SYSCTRL_GPCR)
397 // Set up a stack [for calling C code]
398 ldr r1, =__startup_stack
399 ldr r2, =RAM_BANK0_BASE
409 mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
410 orr r1, r1, #7 // enable MMU bit
411 mcr MMU_CP, 0, r1, MMU_Control, c0
415 mov pc, r2 /* Change address spaces */
418 .endm // _platform_setup1
420 #else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
421 #define PLATFORM_SETUP1
425 ldr r0, SOC_CRM_BASE_W
426 // disable MPLL/SPLL first
427 ldr r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
429 str r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
432 ldr r1, CRM_MPCTL0_VAL2_W
433 str r1, [r0, #(SOC_CRM_MPCTL0 - SOC_CRM_BASE)]
436 ldr r1, CRM_SPCTL0_VAL2_W
437 str r1, [r0, #(SOC_CRM_SPCTL0 - SOC_CRM_BASE)]
439 ldr r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
440 #ifdef PLL_REF_CLK_32768HZ
441 // Make sure to use CKIL
442 bic r1, r1, #(3 << 16)
444 orr r1, r1, #(3 << 16) // select 26MHz
446 orr r1, r1, #0x000C0000 // restart SPLL and MPLL
447 orr r1, r1, #0x00000003 // enable SPLL and MPLL
448 str r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
450 ldr r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
454 ldr r1, SOC_CRM_CSCR2_W
455 str r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
457 // Set divider of H264_CLK to zero, NFC to 3.
458 ldr r1, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
459 bic r1, r1, #0x0000FC00
460 str r1, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
462 /* Configure PCDR1 */
463 ldr r1, SOC_CRM_PCDR1_W
464 str r1, [r0, #(SOC_CRM_PCDR1 - SOC_CRM_BASE)]
466 // Configure PCCR0 and PCCR1
467 ldr r1, SOC_CRM_PCCR0_W
468 str r1, [r0, #(SOC_CRM_PCCR0 - SOC_CRM_BASE)]
470 ldr r1, [r0, #(SOC_CRM_PCCR1 - SOC_CRM_BASE)]
472 str r1, [r0, #(SOC_CRM_PCCR1 - SOC_CRM_BASE)]
473 // make default CLKO to be FCLK
474 ldr r1, [r0, #(SOC_CRM_CCSR - SOC_CRM_BASE)]
475 and r1, r1, #0xFFFFFFE0
477 str r1, [r0, #(SOC_CRM_CCSR - SOC_CRM_BASE)]
481 ldr r1, SOC_CS0_CTL_BASE_W
482 ldr r2, CS0_CSCRU_VAL
483 str r2, [r1, #CSCRU_OFFSET]
484 ldr r2, CS0_CSCRL_VAL
485 str r2, [r1, #CSCRL_OFFSET]
486 ldr r2, CS0_CSCRA_VAL
487 str r2, [r1, #CSCRA_OFFSET]
490 /* CS0 sync mode setup */
493 * Sync mode (AHB Clk = 133MHz ; BCLK = 44.3MHz):
495 ldr r0, =SOC_CS0_CTL_BASE
496 ldr r1, CS0_CSCRU_SYNC_VAL
497 str r1, [r0, #CSCRU_OFFSET]
498 ldr r1, CS0_CSCRL_SYNC_VAL
499 str r1, [r0, #CSCRL_OFFSET]
500 ldr r1, CS0_CSCRA_SYNC_VAL
501 str r1, [r0, #CSCRA_OFFSET]
502 .endm /* init_cs0_sync */
504 .macro init_cs4 /* ADS board expanded IOs */
505 ldr r1, SOC_CS4_CTL_BASE_W
506 ldr r2, CS4_CSCRU_VAL
507 str r2, [r1, #CSCRU_OFFSET]
508 ldr r2, CS4_CSCRL_VAL
509 str r2, [r1, #CSCRL_OFFSET]
510 ldr r2, CS4_CSCRA_VAL
511 str r2, [r1, #CSCRA_OFFSET]
515 // setup AIPI1 and AIPI2
516 mov r0, #SOC_AIPI1_BASE
517 ldr r1, AIPI1_PSR0_VAL
518 str r1, [r0] /* PSR0 */
519 ldr r2, AIPI1_PSR1_VAL
520 str r2, [r0, #4] /* PSR1 */
521 // set r0 = AIPI2 base
524 str r1, [r0] /* PSR0 */
526 str r2, [r0, #4] /* PSR1 */
530 ldr r0, SOC_MAX_BASE_W
531 add r1, r0, #MAX_SLAVE_PORT1_OFFSET
532 add r2, r0, #MAX_SLAVE_PORT2_OFFSET
533 add r0, r0, #MAX_SLAVE_PORT0_OFFSET
536 ldr r6, SOC_MAX_MPR_VAL /* Priority SLCD>EMMA>DMA>Codec>DAHB>IAHB */
537 str r6, [r0, #MAX_SLAVE_MPR_OFFSET] /* same for all slave ports */
538 str r6, [r0, #MAX_SLAVE_AMPR_OFFSET]
539 str r6, [r1, #MAX_SLAVE_MPR_OFFSET]
540 str r6, [r1, #MAX_SLAVE_AMPR_OFFSET]
541 str r6, [r2, #MAX_SLAVE_MPR_OFFSET]
542 str r6, [r2, #MAX_SLAVE_AMPR_OFFSET]
545 .macro init_drive_strength
546 ldr r0, SOC_SYSCTRL_BASE_W
548 str r1, [r0, #(SOC_SYSCTRL_DSCR3 - SOC_SYSCTRL_BASE)]
549 str r1, [r0, #(SOC_SYSCTRL_DSCR5 - SOC_SYSCTRL_BASE)]
550 str r1, [r0, #(SOC_SYSCTRL_DSCR6 - SOC_SYSCTRL_BASE)]
552 str r1, [r0, #(SOC_SYSCTRL_DSCR7 - SOC_SYSCTRL_BASE)]
554 str r1, [r0, #(SOC_SYSCTRL_DSCR8 - SOC_SYSCTRL_BASE)]
555 .endm // init_drive_strength
557 .macro setup_sdram_ddr
558 // SDRAM controller base address
559 ldr r0, SOC_ESDCTL_BASE_W
560 // base address of SDRAM for SET MODE commands written to SDRAM via address lines
561 mov r2, #SOC_CSD0_BASE
563 mov r1, #(1 << 1) // SDRAM controller reset
564 str r1, [r0, #ESDCTL_ESDMISC]
566 // wait until SDRAMRDY bit is set indicating SDRAM is usable
567 ldr r1, [r0, #ESDCTL_ESDMISC]
571 mov r1, #(1 << 3) @ delay line soft reset
572 str r1, [r0, #ESDCTL_ESDMISC]
574 // wait until SDRAMRDY bit is set indicating SDRAM is usable
575 ldr r1, [r0, #ESDCTL_ESDMISC]
579 mov r1, #(1 << 2) @ enable DDR pipeline
580 str r1, [r0, #ESDCTL_ESDMISC]
582 ldr r1, SDRAM_ESDCFG0_VAL
583 str r1, [r0, #ESDCTL_ESDCFG0]
585 ldr r1, SDRAM_DLY_VAL
586 str r1, [r0, #ESDCTL_ESDCDLY1]
587 str r1, [r0, #ESDCTL_ESDCDLY2]
588 str r1, [r0, #ESDCTL_ESDCDLY3]
589 str r1, [r0, #ESDCTL_ESDCDLY4]
590 str r1, [r0, #ESDCTL_ESDCDLY5]
592 ldr r1, SDRAM_PRE_ALL_CMD
593 str r1, [r0, #ESDCTL_ESDCTL0]
595 str r1, [r2, #(1 << 10)] @ contents of r1 irrelevant, data written via A0-A11
597 ldr r1, SDRAM_AUTO_REF_CMD
598 str r1, [r0, #ESDCTL_ESDCTL0]
599 @ initiate 2 auto refresh cycles
604 ldr r1, SDRAM_SET_MODE_REG_CMD
605 str r1, [r0, #ESDCTL_ESDCTL0]
607 @ address offset for extended mode register
608 add r3, r2, #(2 << 24)
609 @ select drive strength via extended mode register:
610 @ 0=full 1=half 2=quarter 3=3-quarter
611 ldrb r1, [r3, #(0 << 5)]
613 ldrb r1, [r2, #0x033] @ write to SDRAM MODE register (via A0-A12)
615 ldr r1, SDRAM_NORMAL_MODE
616 str r1, [r0, #ESDCTL_ESDCTL0]
619 mov r1, #((1 << 3) | (1 << 2) | (1 << 5))
620 str r1, [r0, #ESDCTL_ESDMISC]
621 .endm // setup_sdram_ddr
623 #ifdef CYGOPT_HAL_ARM_TX27_DEBUG
627 mov r9, #(1 << 13) // LED ON
628 str r9, [r10, #GPIO_DR]
634 mov r9, #0 // LED OFF
635 str r9, [r10, #GPIO_DR]
640 strh r3, [r4, #NAND_FLASH_CMD_REG_OFF]
641 mov r3, #NAND_FLASH_CONFIG2_FCMD_EN
642 strh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
647 strh r3, [r4, #NAND_FLASH_ADD_REG_OFF]
648 mov r3, #NAND_FLASH_CONFIG2_FADD_EN
649 strh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
653 mov r3, #FDO_PAGE_SPARE_VAL
654 strh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
660 ldrh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
661 ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
663 strneh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
671 mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
672 mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
673 mcr 15, 0, r0, c7, c10, 4 /* Data Write Barrier */
674 ldr r0, SDRAM_ADDR_MASK
675 ldr r1, MXC_REDBOOT_RAM_START
681 #define PLATFORM_VECTORS _platform_vectors
682 .macro _platform_vectors
686 .globl _KARO_STRUCT_SIZE
688 .word 0 // reserve space structure length
690 .globl _KARO_CECFG_START
693 .word 0 // reserve space for CE configuration
696 .globl _KARO_CECFG_END
701 .ascii "KARO TX27 " __DATE__ " " __TIME__
704 /* SDRAM configuration */
705 #define RA_BITS 2 /* row addr bits - 11 */
706 #define CA_BITS (SDRAM_SIZE / SZ_64M) /* 0-2: col addr bits - 8 3: rsrvd */
707 #define DSIZ 2 /* 0: D[31..16] 1: D[15..D0] 2: D[31..0] 3: rsrvd */
708 #define SREFR 3 /* 0: disabled 1-5: 2^n rows/clock *: rsrvd */
709 #define PWDT 1 /* 0: disabled 1: precharge pwdn
710 2: pwdn after 64 clocks 3: pwdn after 128 clocks */
711 #define FP 0 /* 0: not full page 1: full page */
712 #define BL 1 /* 0: 4(not for LPDDR) 1: 8 */
713 #define PRCT 5 /* 0: disabled *: clks / 2 (0..63) */
714 #define ESDCTLVAL (0x80000000 | (RA_BITS << 24) | (CA_BITS << 20) | \
715 (DSIZ << 16) | (SREFR << 13) | (PWDT << 10) | (FP << 8) | \
716 (BL << 7) | (PRCT << 0))
718 /* SDRAM timing definitions */
719 #define SDRAM_CLK 133
720 #define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
722 .macro CK_VAL, name, clks, offs
727 .set \name, \clks - \offs
734 .macro NS_VAL, name, ns, offs
738 CK_VAL \name, NS_TO_CK(\ns), \offs
742 #if SDRAM_SIZE <= SZ_64M
743 /* MT46H16M32LF-75 */
744 CK_VAL tXP, 2, 1 /* clks - 1 (0..7) */
745 CK_VAL tWTR, 2, 1 /* clks - 1 (0..1) */
746 NS_VAL tRP, 23, 2 /* clks - 2 (0..3) */
747 CK_VAL tMRD, 2, 1 /* clks - 1 (0..3) */
748 NS_VAL tWR, 15, 2 /* clks - 2 (0..1) */
749 NS_VAL tRAS, 45, 1 /* clks - 1 (0..15) */
750 CK_VAL tCAS, 3, 0 /* clks - 1 (0..3) */
751 NS_VAL tRRD, 15, 1 /* clks - 1 (0..3) */
752 NS_VAL tRCD, 23, 1 /* clks - 1 (0..7) */
753 /* tRC is actually max(tRC,tRFC,tXSR) */
754 NS_VAL tRC, 120, 1 /* 0: 20 *: clks - 1 (0..15) */
756 /* MT46H32M32LF-6 or -75 */
757 NS_VAL tXP, 25, 1 /* clks - 1 (0..7) */
758 CK_VAL tWTR, 1, 1 /* clks - 1 (0..1) */
759 NS_VAL tRP, 23, 2 /* clks - 2 (0..3) */
760 CK_VAL tMRD, 2, 1 /* clks - 1 (0..3) */
761 NS_VAL tWR, 15, 2 /* clks - 2 (0..1) */
762 NS_VAL tRAS, 45, 1 /* clks - 1 (0..15) */
763 CK_VAL tCAS, 3, 0 /* clks - 1 (0..3) */
764 NS_VAL tRRD, 15, 1 /* clks - 1 (0..3) */
765 NS_VAL tRCD, 23, 1 /* clks - 1 (0..7) */
766 NS_VAL tRC, 138, 1 /* 0: 20 *: clks - 1 (0..15) */
769 #define ESDCFGVAL ((tXP << 21) | (tWTR << 20) | (tRP << 18) | (tMRD << 16) | \
770 (tWR << 15) | (tRAS << 12) | (tRRD << 10) | (tCAS << 8) | \
771 (tRCD << 4) | (tRC << 0))
773 // All these constants need to be in the first 2KiB of FLASH
774 WDOG_BASE: .word WDOG_BASE_ADDR
775 GPIOB_BASE: .word 0x10015100
776 GPIOF_BASE: .word 0x10015500
777 SDRAM_ADDR_MASK: .word 0xffff0000
778 MXC_REDBOOT_RAM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - REDBOOT_OFFSET
779 SOC_SYSCTRL_BASE_W: .word SOC_SYSCTRL_BASE
780 SOC_MAX_BASE_W: .word SOC_MAX_BASE
781 SOC_MAX_MPR_VAL: .word 0x00302145
782 SOC_CRM_BASE_W: .word SOC_CRM_BASE
783 CRM_MPCTL0_VAL2_W: .word CRM_MPCTL0_VAL2
784 CRM_SPCTL0_VAL2_W: .word CRM_SPCTL0_VAL2
785 SOC_CRM_CSCR2_W: .word CRM_CSCR_VAL2
786 SOC_CRM_PCDR1_W: .word 0x09030913 // p1=20 p2=10 p3=4 p4=10
787 SOC_CRM_PCCR0_W: .word 0x3108480F
788 SOC_CS4_CTL_BASE_W: .word SOC_CS4_CTL_BASE
789 CS4_CSCRU_VAL: .word 0x0000DCF6
790 CS4_CSCRL_VAL: .word 0x444A4541
791 CS4_CSCRA_VAL: .word 0x44443302
792 NFC_BASE_W: .word NFC_BASE
793 SOC_ESDCTL_BASE_W: .word SOC_ESDCTL_BASE
794 SDRAM_ESDCFG0_VAL: .word ESDCFGVAL
795 SDRAM_DLY_VAL: .word 0x002c0000
796 SDRAM_PRE_ALL_CMD: .word 0x92120000
797 SDRAM_AUTO_REF_CMD: .word 0xA2120000
798 SDRAM_SET_MODE_REG_CMD: .word 0xB2120000
799 SDRAM_NORMAL_MODE: .word ESDCTLVAL
800 CS0_CSCRU_VAL: .word 0x0000CC03
801 CS0_CSCRL_VAL: .word 0xA0330D01
802 CS0_CSCRA_VAL: .word 0x00220800
803 CS0_CSCRU_SYNC_VAL: .word 0x23524E80
804 CS0_CSCRL_SYNC_VAL: .word 0x10000D03
805 CS0_CSCRA_SYNC_VAL: .word 0x00720900
806 CS0_BASE_ADDR_W: .word CS0_BASE_ADDR
807 SOC_CS0_CTL_BASE_W: .word SOC_CS0_CTL_BASE
808 DS_DSCR_VAL: .word 0x55555555
809 DS_DSCR7_VAL: .word 0x00005005
810 DS_DSCR8_VAL: .word 0x15555555
811 AIPI1_PSR0_VAL: .word 0x20040304
812 AIPI1_PSR1_VAL: .word 0xDFFBFCFB
814 /*----------------------------------------------------------------------*/
815 /* end of hal_platform_setup.h */
816 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */