1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 //=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
16 // eCos is free software; you can redistribute it and/or modify it under
17 // the terms of the GNU General Public License as published by the Free
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21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
29 // As a special exception, if other files instantiate templates or use macros
30 // or inline functions from this file, or you compile this file and link it
31 // with other works to produce a work based on this file, this file does not
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40 // at http://sources.redhat.com/ecos/ecos-license/
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //===========================================================================
45 #include <pkgconf/system.h> // System-wide configuration info
46 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
47 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
48 #include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
49 #include <cyg/hal/hal_mmu.h> // MMU definitions
50 #include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
52 //#define BOOT_FROM_MMC
54 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
55 #define PLATFORM_SETUP1 _platform_setup1
56 #if defined(BOOT_FROM_MMC)
57 #define PLATFORM_PREAMBLE flash_header
59 #define CYGHWR_HAL_ARM_HAS_MMU
61 #ifdef CYG_HAL_STARTUP_ROMRAM
62 #define CYGSEM_HAL_ROM_RESET_USES_JUMP
68 //#define NFC_2K_BI_SWAP
69 #define SDRAM_FULL_PAGE_BIT 0x100
70 #define SDRAM_FULL_PAGE_MODE 0x37
71 #define SDRAM_BURST_MODE 0x33
73 #define MMC_BLK_LEN 0x200
74 #define MMC_START_ADDR 0x0
75 #define MMC_LOAD_SIZE 0x30000
76 #define CYGHWR_HAL_ROM_VADDR 0x0
79 #define UNALIGNED_ACCESS_ENABLE
80 #define SET_T_BIT_DISABLE
81 #define BRANCH_PREDICTION_ENABLE
84 //#define TURN_OFF_IMPRECISE_ABORT
88 //Start code from offset 1K, gap left for MBR
93 MMC_SDHC1_BASE_ADDR_W: .word MMC_SDHC1_BASE_ADDR
94 ESDHC_INTERRUPT_ENABLE_W: .word ESDHC_INTERRUPT_ENABLE
95 ESDHC_CLEAR_INTERRUPT_W: .word ESDHC_CLEAR_INTERRUPT
96 MXC_REDBOOT_ROM_ST_ADDR: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
97 REDBOOT_RESET_VECTOR: .word reset_vector
99 /* Check if booting from IRAM for MMC boot */
100 mov r0, #SDRAM_BASE_ADDR
103 setup_sdram ddr X32 DDR 0
107 ldr r0, REDBOOT_RESET_VECTOR
114 //Configure interface block and number of blocks 1 block and size is 512 Bytes
116 ldr r3, MMC_SDHC1_BASE_ADDR_W
117 str r2, [r3, #ESDHC_REG_BLK_LEN]
119 str r2, [r3, #ESDHC_REG_NOB]
120 //set block size and number of blocks of card
121 mov r1, #MMC_START_ADDR
124 ldr r11, MXC_REDBOOT_ROM_ST_ADDR
125 mov r12, #MMC_LOAD_SIZE
128 //set read data length, Comfigure command CMD16 for single block read
135 //set read data address
136 //CMD17 data_present Y
147 ldr r4, ESDHC_INTERRUPT_ENABLE_W
148 str r4, [r3, #ESDHC_REG_INT_STATUS_ENABLE]
150 ldr r4, [r3, #ESDHC_REG_INT_STATUS]
151 mov r2, #0x80 //ESDHC_STATUS_BUF_READ_RDY_MSK
155 four_times: //transfer data from SDHC buffer to ddr(4 words once)
156 ldr r4, [r3, #ESDHC_REG_BUFFER_DATA]
159 ldr r4, [r3, #ESDHC_REG_BUFFER_DATA]
162 ldr r4, [r3, #ESDHC_REG_BUFFER_DATA]
165 ldr r4, [r3, #ESDHC_REG_BUFFER_DATA]
171 check_tran_done: //check if the transfer is over
172 ldr r4, [r3, #ESDHC_REG_INT_STATUS]
173 mov r2, #0x800 //ESDHC_STATUS_TRANSFER_COMPLETE_MSK
183 .macro send_cmd_wait_resp
185 ldr r3, MMC_SDHC1_BASE_ADDR_W
187 str r4, [r3, #ESDHC_REG_CLK]
189 //wait until the clk has started
191 ldr r4, [r3, #ESDHC_REG_INT_STATUS]
196 //Clear Interrupt status register
197 ldr r4, ESDHC_CLEAR_INTERRUPT_W
198 str r4, [r3, #ESDHC_REG_INT_STATUS]
199 /* Enable Interrupt */
200 ldr r4, [r3, #ESDHC_REG_INT_STATUS_ENABLE]
201 ldr r5, ESDHC_INTERRUPT_ENABLE_W
203 str r4, [r3, #ESDHC_REG_INT_STATUS_ENABLE]
205 /* Write Command Argument in Command Argument Register */
206 str r1, [r3, #ESDHC_REG_COMMAND]
207 str r0, [r3, #ESDHC_REG_COMMAND_TRANS_TYPE]
208 str r2, [r3, #ESDHC_REG_COMMAND_DAT_CONT]
210 2: //wait for responds
218 ldr r0, [r3, #ESDHC_REG_INT_STATUS]
225 str r4, [r3, #ESDHC_REG_INT_STATUS_ENABLE]
228 // This macro represents the initial startup code for the platform
229 // r11 is reserved to contain chip rev info in this file
230 .macro _platform_setup1
231 FSL_BOARD_SETUP_START:
234 * - invalidate I/D cache/TLB and drain write buffer;
235 * - invalidate L2 cache
237 * - branch predictions
239 #ifdef TURN_OFF_IMPRECISE_ABORT
246 mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
247 mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
248 mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
250 /* Also setup the Peripheral Port Remap register inside the core */
251 ldr r0, ARM_PPMRR /* start from AIPS 2GB region */
252 mcr p15, 0, r0, c15, c2, 4
254 /* Reload data from spare area to 0x400 of main area if booting from NAND */
261 #ifdef NFC_2K_BI_SWAP
262 ldr r3, [r0, #0x7D0] // load word at addr 464 of last 512 RAM buffer
263 and r3, r3, #0xFFFFFF00 // mask off the LSB
264 ldr r4, [r0, #0x834] // load word at addr 4 of the 3rd spare area buffer
265 mov r4, r4, lsr #8 // shift it to get the byte at addr 5
266 and r4, r4, #0xFF // throw away upper 3 bytes
267 add r3, r4, r3 // construct the word
268 str r3, [r0, #0x7D0] // write back
272 /*** L2 Cache setup/invalidation/disable ***/
273 /* Disable L2 cache first */
274 mov r0, #L2CC_BASE_ADDR
275 ldr r2, [r0, #L2_CACHE_CTL_REG]
277 str r2, [r0, #L2_CACHE_CTL_REG]
279 * Configure L2 Cache:
280 * - 128k size(16k way)
281 * - 8-way associativity
282 * - 0 ws TAG/VALID/DIRTY
285 ldr r1, [r0, #L2_CACHE_AUX_CTL_REG]
286 and r1, r1, #0xFE000000
287 ldr r2, L2CACHE_PARAM
289 str r1, [r0, #L2_CACHE_AUX_CTL_REG]
293 str r1, [r0, #L2_CACHE_INV_WAY_REG]
295 /* Poll Invalidate By Way register */
296 ldr r2, [r0, #L2_CACHE_INV_WAY_REG]
299 /*** End of L2 operations ***/
301 mov r0, #SDRAM_NON_FLASH_BOOT
302 ldr r1, AVIC_VECTOR0_ADDR_W
303 str r0, [r1] // for checking boot source from nand or sdram
305 * End of ARM1136 init
316 ldr r11, =CHIP_REV_1_0
317 ldr r0, IIM_SREV_REG_VAL
320 ldrne r11, =CHIP_REV_1_1
323 /* If SDRAM has been setup, bypass clock/WEIM setup */
325 ldreq r1, AVIC_VECTOR0_ADDR_W
329 cmp pc, #SDRAM_BASE_ADDR
331 cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE)
332 blo HWInitialise_skip_SDRAM_setup
334 mov r0, #NOR_FLASH_BOOT
335 ldr r1, AVIC_VECTOR0_ADDR_W
345 beq HWInitialise_skip_SDRAM_setup
347 /* Based on chip rev, setup params for SDRAM controller */
349 mov r4, #SDRAM_BURST_MODE
352 #ifndef BOOT_FROM_MMC
353 /* Assuming DDR memory first */
354 setup_sdram ddr X32 DDR 0
357 HWInitialise_skip_SDRAM_setup:
360 add r2, r0, #0x800 // 2K window
362 blo Normal_Boot_Continue
364 bhi Normal_Boot_Continue
366 /* Copy image from flash to SDRAM first */
367 ldr r1, MXC_REDBOOT_ROM_START
369 1: ldmia r0!, {r3-r10}
375 and r0, pc, r1 /* offset of pc */
376 ldr r1, MXC_REDBOOT_ROM_START
384 // Check if x16/2kb page
385 ldr r7, CCM_BASE_ADDR_W
387 ands r7, r7, #(1 << 30)
389 mov r0, #NAND_FLASH_BOOT
390 ldr r1, AVIC_VECTOR0_ADDR_W
393 ldr r1, AVIC_VECTOR1_ADDR_W
396 mov r0, #NFC_BASE; //r0: nfc base. Reloaded after each page copying
397 mov r1, #0x800 //r1: starting flash addr to be copied. Updated constantly
398 add r2, r0, #0x800 //r2: end of 3rd RAM buf. Doesn't change
399 addeq r2, r0, #0x200 //r2: end of 1st RAM buf. Doesn't change
400 add r12, r0, #0xE00 //r12: NFC register base. Doesn't change
401 ldr r11, MXC_REDBOOT_ROM_START
402 add r13, r11, #REDBOOT_IMAGE_SIZE //r13: end of SDRAM address for copying. Doesn't change
403 add r11, r11, r1 //r11: starting SDRAM address for copying. Updated constantly
405 //unlock internal buffer
410 // NFC_CMD_INPUT(FLASH_Read_Mode1);
414 // Check if x16/2kb page
415 ldr r7, CCM_BASE_ADDR_W
417 ands r7, r7, #(1 << 30)
419 // start_nfc_addr_ops(ADDRESS_INPUT_READ_PAGE, addr, nflash_dev_info->base_mask);
421 do_addr_input //1st addr cycle
423 do_addr_input //2nd addr cycle
425 do_addr_input //3rd addr cycle
427 do_addr_input //4th addr cycle
428 b end_of_nfc_addr_ops
431 // start_nfc_addr_ops(ADDRESS_INPUT_READ_PAGE, addr, nflash_dev_info->base_mask);
433 do_addr_input //1st addr cycle
435 do_addr_input //2nd addr cycle
437 do_addr_input //3rd addr cycle
439 do_addr_input //4th addr cycle
441 do_addr_input //5th addr cycle
443 // NFC_CMD_INPUT(FLASH_Read_Mode1_2K);
448 // NFC_DATA_OUTPUT(buf, FDO_PAGE_SPARE_VAL);
449 // writew(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN,
450 // NAND_FLASH_CONFIG1_REG);
454 // Check if x16/2kb page
455 ldr r7, CCM_BASE_ADDR_W
457 ands r7, r7, #(1 << 30)
458 beq nfc_addr_data_output_done_512
460 // For 2K page - 2nd 512
475 #ifdef NFC_2K_BI_SWAP
476 ldr r3, [r0, #0x7D0] // load word at addr 464 of last 512 RAM buffer
477 and r3, r3, #0xFFFFFF00 // mask off the LSB
478 ldr r4, [r0, #0x834] // load word at addr 4 of the 3rd spare area buffer
479 mov r4, r4, lsr #8 // shift it to get the byte at addr 5
480 and r4, r4, #0xFF // throw away upper 3 bytes
481 add r3, r4, r3 // construct the word
482 str r3, [r0, #0x7D0] // write back
484 // check for bad block
485 mov r3, r1, lsl #(32-17) // get rid of block number
486 cmp r3, #(0x800 << (32-17)) // check if not page 0 or 1
487 b nfc_addr_data_output_done
489 nfc_addr_data_output_done_512:
490 // check for bad block
491 mov r3, r1, lsl #(32-5-9) // get rid of block number
492 cmp r3, #(512 << (32-5-9)) // check if not page 0 or 1
494 nfc_addr_data_output_done:
496 add r4, r0, #0x800 //r3 -> spare area buf 0
501 // really sucks. Bad block!!!!
504 // even suckier since we already read the first page!
505 // Check if x16/2kb page
506 ldr r7, CCM_BASE_ADDR_W
508 ands r7, r7, #(1 << 30)
510 subeq r11, r11, #512 //rewind 1 page for the sdram pointer
511 subeq r1, r1, #512 //rewind 1 page for the flash pointer
514 subne r11, r11, #0x800 //rewind 1 page for the sdram pointer
515 subne r1, r1, #0x800 //rewind 1 page for the flash pointer
518 // Check if x16/2kb page
519 ldr r7, CCM_BASE_ADDR_W
521 ands r7, r7, #(1 << 30)
523 addeq r1, r1, #(32*512)
524 addne r1, r1, #(64*2048)
529 1: ldmia r0!, {r3-r10}
534 bge NAND_Copy_Main_done
535 // Check if x16/2kb page
536 ldr r7, CCM_BASE_ADDR_W
538 ands r7, r7, #(1 << 30)
546 Normal_Boot_Continue:
548 #ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
549 /* Copy image from flash to SDRAM first */
552 ldr r1, MXC_REDBOOT_ROM_START
554 beq HWInitialise_skip_SDRAM_copy
556 add r2, r0, #REDBOOT_IMAGE_SIZE
558 1: ldmia r0!, {r3-r10}
564 and r0, pc, r1 /* offset of pc */
565 ldr r1, =(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000 + 0x8)
571 #endif /* CYG_HAL_STARTUP_ROMRAM */
573 HWInitialise_skip_SDRAM_copy:
579 * IOMUX/PBC setup is done in C function plf_hardware_init() for simplicity
583 // Set up a stack [for calling C code]
584 ldr r1, =__startup_stack
585 ldr r2, =RAM_BANK0_BASE
593 mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
594 orr r1, r1, #7 // enable MMU bit
595 orr r1, r1, #0x800 // enable z bit
596 mcr MMU_CP, 0, r1, MMU_Control, c0
597 mov pc,r2 /* Change address spaces */
603 // Save shadow copy of BCR, also hardware configuration
607 str r9, [r1] // Saved far above...
609 .endm // _platform_setup1
613 ldrh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
614 ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
616 bx lr // do_wait_op_done
619 mov r3, #(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN)
620 strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
622 // writew(buf_no, RAM_BUFFER_ADDRESS_REG);
623 strh r8, [r12, #RAM_BUFFER_ADDRESS_REG_OFF]
624 // writew(FDO_PAGE_SPARE_VAL & 0xFF, NAND_FLASH_CONFIG2_REG);
625 mov r3, #FDO_PAGE_SPARE_VAL
626 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
629 #else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
630 #define PLATFORM_SETUP1
635 .endm /* init_spba */
637 /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
640 * Set all MPROTx to be non-bufferable, trusted for R/W,
641 * not forced to user-mode.
643 ldr r0, AIPS1_CTRL_BASE_ADDR_W
644 ldr r1, AIPS1_PARAM_W
647 ldr r0, AIPS2_CTRL_BASE_ADDR_W
652 * Clear the on and off peripheral modules Supervisor Protect bit
653 * for SDMA to access them. Did not change the AIPS control registers
654 * (offset 0x20) access type
656 ldr r0, AIPS1_CTRL_BASE_ADDR_W
663 and r1, r1, #0x00FFFFFF
666 ldr r0, AIPS2_CTRL_BASE_ADDR_W
673 and r1, r1, #0x00FFFFFF
675 .endm /* init_aips */
677 /* MAX (Multi-Layer AHB Crossbar Switch) setup */
679 ldr r0, MAX_BASE_ADDR_W
680 /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
682 str r1, [r0, #0x000] /* for S0 */
683 str r1, [r0, #0x100] /* for S1 */
684 str r1, [r0, #0x200] /* for S2 */
685 str r1, [r0, #0x300] /* for S3 */
686 str r1, [r0, #0x400] /* for S4 */
687 /* SGPCR - always park on last master */
689 str r1, [r0, #0x010] /* for S0 */
690 str r1, [r0, #0x110] /* for S1 */
691 str r1, [r0, #0x210] /* for S2 */
692 str r1, [r0, #0x310] /* for S3 */
693 str r1, [r0, #0x410] /* for S4 */
694 /* MGPCR - restore default values */
696 str r1, [r0, #0x800] /* for M0 */
697 str r1, [r0, #0x900] /* for M1 */
698 str r1, [r0, #0xA00] /* for M2 */
699 str r1, [r0, #0xB00] /* for M3 */
700 str r1, [r0, #0xC00] /* for M4 */
701 str r1, [r0, #0xD00] /* for M5 */
706 ldr r0, IPU_CTRL_BASE_ADDR_W
710 ldr r0, CCM_BASE_ADDR_W
711 ldr r2, CCM_CCMR_0x074B0BF5
712 ldr r3, CCM_CCMR_0x074B0BFD
713 ldr r4, CCM_CCMR_0x074B0B7D
715 // Make sure to use CKIH
716 ldr r1, [r0, #CLKCTL_CCMR]
717 bic r1, r1, #0x8 // disable PLL first
718 str r1, [r0, #CLKCTL_CCMR]
719 str r2, [r0, #CLKCTL_CCMR] // select CKIH (26MHz) as PLL ref clock
724 str r3, [r0, #CLKCTL_CCMR] // enable PLL
725 str r4, [r0, #CLKCTL_CCMR] // switch to PLL (SPLL for FIR)
729 str r1, [r0, #CLKCTL_PDR0]
730 ldr r1, MPCTL_PARAM_W
731 str r1, [r0, #CLKCTL_MPCTL]
733 /* Set UPLL=240MHz, USB=60MHz */
734 ldr r1, CCM_PDR1_0x49FCFE7F
735 str r1, [r0, #CLKCTL_PDR1]
736 ldr r1, CCM_UPCTL_PARAM_240
737 str r1, [r0, #CLKCTL_UPCTL]
738 // default CLKO to 1/8 of the ARM core
740 add r1, r1, #0x00000006
741 str r1, [r0, #CLKCTL_COSR]
742 .endm /* init_clock */
746 /* Configure M3IF registers */
749 * M3IF Control Register (M3IFCTL)
750 * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
751 * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
752 * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
753 * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
754 * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
755 * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
756 * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
757 * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
762 str r0, [r1] /* M3IF control reg */
763 .endm /* init_m3if */
765 /* CPLD on CS5 setup */
767 ldr r0, WEIM_CTRL_CS5_W
768 ldr r1, CS5_0x0000D843
770 ldr r1, CS5_0x22252521
772 ldr r1, CS5_0x22220A00
776 .macro setup_sdram, name, bus_width, mode, full_page
778 ESDCTL_BASE_W: .word ESDCTL_BASE
779 SDRAM_PARAM1_DDR: .word 0x4
780 SDRAM_PARAM1_SDR: .word 0x0
781 SDRAM_PARAM2_DDR: .word 0x80000F00
782 SDRAM_PARAM2_SDR: .word 0x80000400
783 SDRAM_PARAM3_DDR: .word 0x00100000
784 SDRAM_PARAM3_SDR: .word 0x0
785 SDRAM_PARAM4_X32: .word 0x00010000
786 SDRAM_PARAM4_X16: .word 0x0
787 SDRAM_0x55555555: .word 0x55555555
788 SDRAM_0xAAAAAAAA: .word 0xAAAAAAAA
789 SDRAM_0x92100000: .word 0x92100000
790 SDRAM_0xA2100000: .word 0xA2100000
791 SDRAM_0xB2100000: .word 0xB2100000
792 SDRAM_0x82116080: .word 0x82116080
793 SDRAM_0x0075E73A: .word 0x0075E73A
795 /* It sets the "Z" flag in the CPSR at the end of the macro */
796 ldr r0, ESDCTL_BASE_W
797 mov r2, #SDRAM_BASE_ADDR
798 ldr r1, SDRAM_0x0075E73A
800 ldr r1, =0x2 // reset
802 ldr r1, SDRAM_PARAM1_\mode
804 // Hold for more than 200ns
810 ldr r1, SDRAM_0x92100000
813 ldr r12, SDRAM_PARAM2_\mode
815 ldr r1, SDRAM_0xA2100000
819 ldr r1, SDRAM_0xB2100000
824 strb r1, [r2, #SDRAM_FULL_PAGE_MODE]
826 strb r1, [r2, #SDRAM_BURST_MODE]
832 ldr r3, SDRAM_0x82116080
833 ldr r4, SDRAM_PARAM3_\mode
835 ldr r4, SDRAM_PARAM4_\bus_width
838 add r3, r3, #0x100 /* Force to full page mode */
844 /* Below only for DDR */
847 ldrne r1, =0x0000000C
848 strne r1, [r0, #0x10]
849 /* Testing if it is truly DDR */
850 ldr r1, SDRAM_0x55555555
851 ldr r0, =SDRAM_BASE_ADDR
853 ldr r2, SDRAM_0xAAAAAAAA
860 strh r3, [r12, #NAND_FLASH_CMD_REG_OFF]
861 mov r3, #NAND_FLASH_CONFIG2_FCMD_EN;
862 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
864 .endm // nfc_cmd_input
868 strh r3, [r12, #NAND_FLASH_ADD_REG_OFF]
869 mov r3, #NAND_FLASH_CONFIG2_FADD_EN
870 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
872 .endm // do_addr_input
874 /* To support 133MHz DDR */
875 .macro init_drive_strength
877 * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
878 * in SW_PAD_CTL registers
882 ldr r1, IOMUXC_BASE_ADDR_W
884 // Now r1 = (IOMUX_BASE_ADDR + 0x200)
886 bic r0, r0, #(1 << 12)
891 bic r0, r0, #(1 << 22)
896 bic r0, r0, #(1 << 2)
901 bic r0, r0, #(1 << 22)
906 bic r0, r0, #(1 << 22)
909 // DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
910 ldr r2, =22 // (0x2E0 - 0x288) / 4 = 22
913 bic r0, r0, #(1 << 22)
914 bic r0, r0, #(1 << 12)
915 bic r0, r0, #(1 << 2)
920 .endm /* init_drive_strength */
922 #define PLATFORM_VECTORS _platform_vectors
923 .macro _platform_vectors
924 .globl _board_BCR, _board_CFG
925 _board_BCR: .long 0 // Board Control register shadow
926 _board_CFG: .long 0 // Board Configuration (read at RESET)
929 ARM_PPMRR: .word 0x40000015
930 L2CACHE_PARAM: .word 0x00030024
931 IIM_SREV_REG_VAL: .word IIM_BASE_ADDR + IIM_SREV_OFF
932 AIPS1_CTRL_BASE_ADDR_W: .word AIPS1_CTRL_BASE_ADDR
933 AIPS2_CTRL_BASE_ADDR_W: .word AIPS2_CTRL_BASE_ADDR
934 AIPS1_PARAM_W: .word 0x77777777
935 MAX_BASE_ADDR_W: .word MAX_BASE_ADDR
936 MAX_PARAM1: .word 0x00302154
937 CLKCTL_BASE_ADDR_W: .word CLKCTL_BASE_ADDR
938 M3IF_BASE_W: .word M3IF_BASE
939 IOMUXC_BASE_ADDR_W: .word IOMUXC_BASE_ADDR
941 CCM_PDR0_W: .word PDR0_399_133_66
942 MPCTL_PARAM_W: .word MPCTL_PARAM_399
945 CCM_PDR0_W: .word PDR0_532_133_66
946 MPCTL_PARAM_W: .word MPCTL_PARAM_532
949 MPCTL_PARAM_532_27_W: .word MPCTL_PARAM_532_27
950 CCM_PDR1_0x49FCFE7F: .word 0x49FCFE7F
951 CCM_UPCTL_PARAM_240: .word UPCTL_PARAM_240
952 CCM_UPCTL_PARAM_240_27: .word UPCTL_PARAM_240_27
953 AVIC_VECTOR0_ADDR_W: .word MXCBOOT_FLAG_REG
954 AVIC_VECTOR1_ADDR_W: .word MXCFIS_FLAG_REG
955 MXC_REDBOOT_ROM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
956 CONST_0x0FFF: .word 0x0FFF
957 CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
958 IPU_CTRL_BASE_ADDR_W: .word IPU_CTRL_BASE_ADDR
959 CCM_CCMR_0x074B0BF5: .word 0x074B0BF5
960 CCM_CCMR_0x074B0BFD: .word 0x074B0BFD
961 CCM_CCMR_0x074B0B7D: .word 0x074B0B7D
962 WEIM_CTRL_CS5_W: .word WEIM_CTRL_CS5
963 CS5_0x0000D843: .word 0x0000D843
964 CS5_0x22252521: .word 0x22252521
965 CS5_0x22220A00: .word 0x22220A00
967 /*---------------------------------------------------------------------------*/
968 /* end of hal_platform_setup.h */
969 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */