1 #ifndef CYGONCE_FSL_BOARD_H
2 #define CYGONCE_FSL_BOARD_H
4 //=============================================================================
6 // Platform specific support (register layout, etc)
8 //=============================================================================
9 //####ECOSGPLCOPYRIGHTBEGIN####
10 // -------------------------------------------
11 // This file is part of eCos, the Embedded Configurable Operating System.
12 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
14 // eCos is free software; you can redistribute it and/or modify it under
15 // the terms of the GNU General Public License as published by the Free
16 // Software Foundation; either version 2 or (at your option) any later version.
18 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
19 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
23 // You should have received a copy of the GNU General Public License along
24 // with eCos; if not, write to the Free Software Foundation, Inc.,
25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27 // As a special exception, if other files instantiate templates or use macros
28 // or inline functions from this file, or you compile this file and link it
29 // with other works to produce a work based on this file, this file does not
30 // by itself cause the resulting work to be covered by the GNU General Public
31 // License. However the source code for this file must still be made available
32 // in accordance with section (3) of the GNU General Public License.
34 // This exception does not invalidate any other reasons why a work based on
35 // this file might be covered by the GNU General Public License.
37 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
38 // at http://sources.redhat.com/ecos/ecos-license/
39 // -------------------------------------------
40 //####ECOSGPLCOPYRIGHTEND####
41 //===========================================================================
43 #include <cyg/hal/hal_soc.h> // Hardware definitions
45 #define PMIC_SPI_BASE CSPI2_BASE_ADDR
46 #define PMIC_SPI_CHIP_SELECT_NO SPI_CTRL_CS2
48 #define PBC_BASE CS4_BASE_ADDR /* Peripheral Bus Controller */
49 #define PBC_VERSION (PBC_BASE + 0x00000)
50 #define PBC_CTRL1_SET (PBC_BASE + 0x00008)
51 #define PBC_CTRL1_CLR (PBC_BASE + 0x0000C)
52 #define PBC_CTRL2_SET (PBC_BASE + 0x00010)
53 #define PBC_CTRL2_CLR (PBC_BASE + 0x00014)
54 #define PBC_IMASK1_SET (PBC_BASE + 0x00018)
55 #define PBC_IMASK1_CLR (PBC_BASE + 0x0001C)
56 #define PBC_IMASK2_SET (PBC_BASE + 0x00020)
57 #define PBC_IMASK2_CLR (PBC_BASE + 0x00024)
58 #define PBC_STAT (PBC_BASE + 0x00028)
59 #define PBC_INT_STAT (PBC_BASE + 0x0002C)
61 #define BOARD_CS_UART_BASE (PBC_BASE + 0x20000)
62 #define BOARD_CS_LAN_BASE (PBC_BASE + 0x40000)
64 #define LAN92XX_REG_BASE BOARD_CS_LAN_BASE
66 #define REDBOOT_IMAGE_SIZE 0x40000
69 /* MX31 ADS SDRAM is from 0x80000000, 128M */
70 #define BOARD_FLASH_START CS0_BASE_ADDR
71 #define SDRAM_BASE_ADDR CSD1_BASE_ADDR
72 #define SDRAM_SIZE 0x08000000
73 #define RAM_BANK0_BASE CSD0_BASE_ADDR
74 #define RAM_BANK1_BASE CSD1_BASE_ADDR
76 #define FEC_PHY_ADDR 0
79 //#define LED_IS_ON(n) ((readw(PBC_LED_CTRL) & (1<<(n))) != 0)
80 //#define TURN_LED_ON(n) writew((readw(PBC_LED_CTRL)|(1<<(n))), PBC_LED_CTRL)
81 //#define TURN_LED_OFF(n) writew((readw(PBC_LED_CTRL)&(~(1<<(n)))), PBC_LED_CTRL)
83 #define BOARD_DEBUG_LED(n)
85 #define BOARD_DEBUG_LED(n) \
87 if (n >= 0 && n < LED_MAX_NUM) { \
95 #endif /* CYGONCE_FSL_BOARD_H */