1 #ifndef CYGONCE_HAL_CACHE_H
2 #define CYGONCE_HAL_CACHE_H
4 //=============================================================================
8 // HAL cache control API
10 //=============================================================================
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43 //=============================================================================
45 #include <cyg/infra/cyg_type.h>
46 #include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
48 //-----------------------------------------------------------------------------
52 #define HAL_DCACHE_SIZE 0x4000 // 16KB Size of data cache in bytes
53 #define HAL_DCACHE_LINE_SIZE 32 // Size of a data cache line
54 #define HAL_DCACHE_WAYS 64 // Associativity of the cache
57 #define HAL_ICACHE_SIZE 0x4000 // Size of cache in bytes
58 #define HAL_ICACHE_LINE_SIZE 32 // Size of a cache line
59 #define HAL_ICACHE_WAYS 64 // Associativity of the cache
61 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE / (HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
62 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE / (HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
64 #define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
65 #define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP 0x20
66 #define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x100
67 //-----------------------------------------------------------------------------
68 // Global control of data cache
70 // Enable the data cache
71 #define HAL_DCACHE_ENABLE_L1() \
74 "mrc p15, 0, r1, c1, c0, 0;" \
75 "orr r1, r1, #0x0007;" /* enable DCache (also ensures */ \
76 /* the MMU, alignment faults, and */ \
77 "mcr p15, 0, r1, c1, c0, 0" \
80 : "r1" /* Clobber list */ \
84 // Disable the data cache
85 #define HAL_DCACHE_DISABLE_L1() \
89 "mcr p15, 0, r1, c7, c6, 0;" /* clear data cache */ \
90 "mrc p15, 0, r1, c1, c0, 0;" \
91 "bic r1, r1, #0x0004;" /* disable DCache */ \
92 /* but not MMU and alignment faults */ \
93 "mcr p15, 0, r1, c1, c0, 0" \
96 : "r1" /* Clobber list */ \
100 // Invalidate the entire cache
101 #define HAL_DCACHE_INVALIDATE_ALL_L1() \
102 CYG_MACRO_START /* this macro can discard dirty cache lines. */ \
105 "mcr p15, 0, r0, c7, c6, 0;" /* flush d-cache */ \
106 "mcr p15, 0, r0, c8, c7, 0;" /* flush i+d-TLBs */ \
109 : "r0","memory" /* clobber list */ \
113 // Synchronize the contents of the cache with memory.
114 // using ARM9's defined(CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX)
115 #define HAL_DCACHE_SYNC_L1() \
125 "mcr p15, 0, r0, c7, c14, 0;" /* clean, invalidate Dcache*/ \
126 "mcr p15, 0, r0, c7, c10, 4;" /* drain the write buffer */ \
127 "mcr p15, 0, r0, c7, c10, 5;" /* data memory barrier */ \
130 : "r0" /* Clobber list */ \
134 // Query the state of the data cache
135 #define HAL_DCACHE_IS_ENABLED(_state_) \
144 "mrc p15, 0, %0, c1, c0, 0;" \
148 (_state_) = (0 != (4 & reg)); /* Bit 2 is DCache enable */ \
151 //-----------------------------------------------------------------------------
152 // Global control of Instruction cache
154 // Enable the instruction cache
155 #define HAL_ICACHE_ENABLE_L1() \
158 "mrc p15, 0, r1, c1, c0, 0;" \
159 "orr r1, r1, #0x1000;" \
160 "orr r1, r1, #0x0003;" /* enable ICache (also ensures */ \
161 /* that MMU and alignment faults */ \
163 "mcr p15, 0, r1, c1, c0, 0" \
166 : "r1" /* Clobber list */ \
170 // Query the state of the instruction cache
171 #define HAL_ICACHE_IS_ENABLED(_state_) \
173 register cyg_uint32 reg; \
175 "mrc p15, 0, %0, c1, c0, 0" \
180 (_state_) = (0 != (0x1000 & reg)); /* Bit 12 is ICache enable */ \
183 // Disable the instruction cache
184 #define HAL_ICACHE_DISABLE_L1() \
187 "mrc p15, 0, r1, c1, c0, 0;" \
188 "bic r1, r1, #0x1000;" /* disable ICache (but not MMU, etc) */ \
189 "mcr p15, 0, r1, c1, c0, 0;" \
191 "mcr p15, 0, r1, c7, c5, 0;" /* flush ICache */ \
192 "mcr p15, 0, r1, c7, c5, 4;" /* flush prefetch buffer */ \
193 "nop;" /* next few instructions may be via cache */ \
201 : "r1" /* Clobber list */ \
205 // Invalidate the entire cache
206 #define HAL_ICACHE_INVALIDATE_ALL_L1() \
208 /* this macro can discard dirty cache lines (N/A for ICache) */ \
211 "mcr p15, 0, r1, c7, c5, 0;" /* flush ICache */ \
212 "mcr p15, 0, r1, c8, c5, 0;" /* flush ITLB only */ \
213 "mcr p15, 0, r1, c7, c5, 4;" /* flush prefetch buffer */ \
214 "nop;" /* next few instructions may be via cache */ \
222 : "r1" /* Clobber list */ \
226 // Synchronize the contents of the cache with memory.
227 // (which includes flushing out pending writes)
228 #define HAL_ICACHE_SYNC() \
230 HAL_DCACHE_SYNC(); /* ensure data gets to RAM */ \
231 HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */ \
235 #define HAL_DCACHE_ENABLE_L1()
236 #define HAL_DCACHE_DISABLE_L1()
237 #define HAL_DCACHE_INVALIDATE_ALL_L1()
238 #define HAL_DCACHE_SYNC_L1()
240 #define HAL_DCACHE_IS_ENABLED(_state_) \
249 "mrc p15, 0, %0, c1, c0, 0;" \
253 (_state_) = (0 != (4 & reg)); /* Bit 2 is DCache enable */ \
256 #define HAL_ICACHE_ENABLE_L1()
258 #define HAL_ICACHE_IS_ENABLED(_state_) \
260 register cyg_uint32 reg; \
262 "mrc p15, 0, %0, c1, c0, 0" \
267 (_state_) = (0 != (0x1000 & reg)); /* Bit 12 is ICache enable */ \
270 #define HAL_ICACHE_DISABLE_L1()
271 #define HAL_ICACHE_INVALIDATE_ALL_L1()
272 #define HAL_ICACHE_SYNC()
275 // Query the state of the L2 cache
276 #define HAL_L2CACHE_IS_ENABLED(_state_) \
278 _state_ = (*(unsigned long *)(0x30000100)) & 0x1; \
283 #define HAL_ENABLE_L2() \
286 "ldr r0, =0x30000100;" \
288 "orr r1, r1, #0x1;" \
292 : "r0", "r1" /* Clobber list */ \
296 #define HAL_DISABLE_L2() \
299 "ldr r0, =0x30000000;" \
300 "ldr r1, [r0, #0x100];" \
301 "bic r1, r1, #0x1;" \
302 "str r1, [r0, #0x100];" \
305 : "r0", "r1" /* Clobber list */ \
309 #define HAL_SYNC_L2() \
312 "ldr r0, =0x30000000;" \
314 "str r1, [r0, #0x730];" \
317 : "r0", "r1" /* Clobber list */ \
321 #define HAL_INVALIDATE_L2() \
324 "ldr r0, =0x30000000;" \
326 "str r1, [r0, #0x77C];" \
328 "ldr r1, [r0, #0x77C];" \
333 : "r0", "r1" /* Clobber list */ \
337 #define HAL_CLEAN_INVALIDATE_L2() \
340 "ldr r0, =0x30000000;" \
342 "str r1, [r0, #0x7FC];" \
344 "ldr r1, [r0, #0x7FC];" \
349 : "r0", "r1" /* Clobber list */ \
354 #define HAL_ENABLE_L2()
355 #define HAL_DISABLE_L2()
356 #define HAL_INVALIDATE_L2()
357 #define HAL_CLEAN_INVALIDATE_L2()
358 #define HAL_SYNC_L2()
359 #endif //L2CC_ENABLED
361 /*********************** Exported macros *******************/
363 #define HAL_DCACHE_ENABLE() { \
364 HAL_DCACHE_ENABLE_L1(); \
368 #define HAL_DCACHE_DISABLE() { \
369 HAL_DCACHE_DISABLE_L1(); \
373 #define HAL_DCACHE_INVALIDATE_ALL() { \
374 HAL_DCACHE_INVALIDATE_ALL_L1(); \
375 HAL_CLEAN_INVALIDATE_L2(); \
378 #define HAL_DCACHE_SYNC() { \
379 HAL_DCACHE_SYNC_L1(); \
383 #define HAL_ICACHE_INVALIDATE_ALL() { \
384 HAL_ICACHE_INVALIDATE_ALL_L1(); \
385 HAL_CLEAN_INVALIDATE_L2(); \
388 #define HAL_ICACHE_DISABLE() { \
389 HAL_ICACHE_DISABLE_L1(); \
392 #define HAL_ICACHE_ENABLE() { \
393 HAL_ICACHE_ENABLE_L1(); \
396 #define CYGARC_HAL_EXEC_FIXUP() \
398 "moveq r0, #0x30000000;\n" \
399 "moveq r1, #0x1;\n" \
400 "streq r1, [r0, #0x100];\n" \
402 #endif // ifndef CYGONCE_HAL_CACHE_H
403 // End of hal_cache.h