1 //==========================================================================
5 // SoC chip definitions
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12 // Copyright (C) 2002 Gary Thomas
14 // eCos is free software; you can redistribute it and/or modify it under
15 // the terms of the GNU General Public License as published by the Free
16 // Software Foundation; either version 2 or (at your option) any later version.
18 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
19 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
23 // You should have received a copy of the GNU General Public License along
24 // with eCos; if not, write to the Free Software Foundation, Inc.,
25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27 // As a special exception, if other files instantiate templates or use macros
28 // or inline functions from this file, or you compile this file and link it
29 // with other works to produce a work based on this file, this file does not
30 // by itself cause the resulting work to be covered by the GNU General Public
31 // License. However the source code for this file must still be made available
32 // in accordance with section (3) of the GNU General Public License.
34 // This exception does not invalidate any other reasons why a work based on
35 // this file might be covered by the GNU General Public License.
37 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
38 // at http://sources.redhat.com/ecos/ecos-license/
39 // -------------------------------------------
40 //####ECOSGPLCOPYRIGHTEND####
41 //========================================================================*/
49 #define REG8_VAL(a) (a)
50 #define REG16_VAL(a) (a)
51 #define REG32_VAL(a) (a)
53 #define REG8_PTR(a) (a)
54 #define REG16_PTR(a) (a)
55 #define REG32_PTR(a) (a)
57 #else /* __ASSEMBLER__ */
59 #define VA(a) ((void *)(a))
61 extern char HAL_PLATFORM_EXTRA[40];
62 externC void plf_hardware_init(void);
64 #define REG8_VAL(a) ((unsigned char)(a))
65 #define REG16_VAL(a) ((unsigned short)(a))
66 #define REG32_VAL(a) ((unsigned int)(a))
68 #define REG8_PTR(a) ((volatile unsigned char *)(a))
69 #define REG16_PTR(a) ((volatile unsigned short *)(a))
70 #define REG32_PTR(a) ((volatile unsigned int *)(a))
71 #define readb(a) (*(volatile unsigned char *)(a))
72 #define readw(a) (*(volatile unsigned short *)(a))
73 #define readl(a) (*(volatile unsigned int *)(a))
74 #define writeb(v,a) (*(volatile unsigned char *)(a) = (v))
75 #define writew(v,a) (*(volatile unsigned short *)(a) = (v))
76 #define writel(v,a) (*(volatile unsigned int *)(a) = (v))
78 #endif /* __ASSEMBLER__ */
81 * Default Memory Layout Definitions
84 #define MXC_NAND_BASE_DUMMY 0
87 * UART Chip level Configuration that a user may not have to edit. These
88 * configuration vary depending on how the UART module is integrated with
93 * This option is used to set or clear the RXDMUXSEL bit in control reg 3.
94 * Certain platforms need this bit to be set in order to receive Irda data.
96 #define MXC_UART_IR_RXDMUX 0x0004
98 * This option is used to set or clear the RXDMUXSEL bit in control reg 3.
99 * Certain platforms need this bit to be set in order to receive UART data.
101 #define MXC_UART_RXDMUX 0x0004
106 #define IRAM_BASE_ADDR UL(0x1FFE2000) /* 96K internal ram */
111 #define ROM_BASE_ADDR UL(0x00000000)
112 #define ROM_BASE_ADDR_VIRT VA(0x20000000)
114 #define ROM_SI_REV_OFFSET 0x48
119 #define NFC_BASE_ADDR_AXI UL(0xCFFF0000)
120 #define NFC_BASE NFC_BASE_ADDR_AXI
122 #define PLATFORM_BASE_ADDR UL(0x83FA0000)
123 #define PLATFORM_ICGC 0x14
125 * Graphics Memory of GPU
127 #define GPU_BASE_ADDR UL(0x20000000)
129 #define TZIC_BASE_ADDR UL(0x8FFFC000)
131 #define DEBUG_BASE_ADDR UL(0x60000000)
132 #define DEBUG_ROM_ADDR (DEBUG_BASE_ADDR + 0x0)
133 #define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000)
134 #define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000)
135 #define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000)
136 #define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000)
137 #define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000)
138 #define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000)
139 #define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000)
140 #define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000)
143 * SPBA global module enabled #0
145 #define SPBA0_BASE_ADDR UL(0x70000000)
147 #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
148 #define ESDHC1_REG_BASE MMC_SDHC1_BASE_ADDR
149 #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
150 #define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
152 #define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
153 #define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
154 #define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
155 #define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
156 #define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000)
157 #define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000)
158 #define SLIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000)
159 #define HSI2C_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000)
160 #define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
163 * defines for SPBA modules
165 #define SPBA_SDHC1 0x04
166 #define SPBA_SDHC2 0x08
167 #define SPBA_UART3 0x0C
168 #define SPBA_CSPI1 0x10
169 #define SPBA_SSI2 0x14
170 #define SPBA_SDHC3 0x20
171 #define SPBA_SDHC4 0x24
172 #define SPBA_SPDIF 0x28
173 #define SPBA_ATA 0x30
174 #define SPBA_SLIM 0x34
175 #define SPBA_HSI2C 0x38
176 #define SPBA_CTRL 0x3C
182 #define AIPS1_BASE_ADDR UL(0x73F00000)
183 #define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
184 #define USBOH3_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
185 #define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
186 #define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
187 #define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
188 #define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
189 #define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
190 #define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
191 #define WDOG_BASE_ADDR WDOG1_BASE_ADDR
192 #define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
193 #define GPT_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
194 #define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
195 #define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
196 #define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
197 #define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
198 #define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
199 #define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
200 #define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
201 #define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000)
202 #define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000)
203 #define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000)
204 #define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000)
209 #define AIPS2_BASE_ADDR UL(0x83F00000)
210 #define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR
211 #define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
212 #define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
213 #define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
214 #define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
215 #define MAX_BASE_ADDR AHBMAX_BASE_ADDR
216 #define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
217 #define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
218 #define ARM_ELBOW_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000)
219 #define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
220 #define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000)
222 #define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
223 #define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
224 #define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000)
225 #define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000)
226 #define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000)
228 #define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
229 #define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
230 #define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
231 #define I2C_BASE_ADDR I2C1_BASE_ADDR
232 #define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
233 #define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
234 #define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
235 #define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000)
236 #define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000)
237 #define NFC_IP_BASE (AIPS2_BASE_ADDR + 0x000DB000)
238 #define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00)
239 #define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
240 #define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
241 #define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000)
242 #define SSI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000)
243 #define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
244 #define SOC_FEC_BASE FEC_BASE_ADDR
245 #define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000)
246 #define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000)
247 #define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000)
250 * Memory regions and CS
252 #define GPU_CTRL_BASE_ADDR UL(0x30000000)
253 #define IPU_CTRL_BASE_ADDR UL(0x40000000)
254 #define CSD0_BASE_ADDR UL(0x90000000)
255 #define CSD1_BASE_ADDR UL(0xA0000000)
256 #define CS0_BASE_ADDR UL(0xB0000000)
257 #define CS1_BASE_ADDR UL(0xB8000000)
258 #define CS2_BASE_ADDR UL(0xC0000000)
259 #define CS3_BASE_ADDR UL(0xC8000000)
260 #define CS4_BASE_ADDR UL(0xCC000000)
261 #define CS5_BASE_ADDR UL(0xCE000000)
264 * DMA request assignments
266 #define DMA_REQ_SSI3_TX1 47
267 #define DMA_REQ_SSI3_RX1 46
268 #define DMA_REQ_SPDIF 45
269 #define DMA_REQ_UART3_TX 44
270 #define DMA_REQ_UART3_RX 43
271 #define DMA_REQ_SLIM_B_TX 42
272 #define DMA_REQ_SDHC4 41
273 #define DMA_REQ_SDHC3 40
274 #define DMA_REQ_CSPI_TX 39
275 #define DMA_REQ_CSPI_RX 38
276 #define DMA_REQ_SSI3_TX2 37
277 #define DMA_REQ_IPU 36
278 #define DMA_REQ_SSI3_RX2 35
279 #define DMA_REQ_EPIT2 34
280 #define DMA_REQ_CTI2_1 33
281 #define DMA_REQ_EMI_WR 32
282 #define DMA_REQ_CTI2_0 31
283 #define DMA_REQ_EMI_RD 30
284 #define DMA_REQ_SSI1_TX1 29
285 #define DMA_REQ_SSI1_RX1 28
286 #define DMA_REQ_SSI1_TX2 27
287 #define DMA_REQ_SSI1_RX2 26
288 #define DMA_REQ_SSI2_TX1 25
289 #define DMA_REQ_SSI2_RX1 24
290 #define DMA_REQ_SSI2_TX2 23
291 #define DMA_REQ_SSI2_RX2 22
292 #define DMA_REQ_SDHC2_I2C2 21
293 #define DMA_REQ_SDHC1_I2C1 20
294 #define DMA_REQ_UART1_TX 19
295 #define DMA_REQ_UART1_RX 18
296 #define DMA_REQ_UART2_TX 17
297 #define DMA_REQ_UART2_RX 16
298 #define DMA_REQ_GPU_GPIO1_0 15
299 #define DMA_REQ_GPIO1_1 14
300 #define DMA_REQ_FIRI_TX 13
301 #define DMA_REQ_FIRI_RX 12
302 #define DMA_REQ_HS_I2C_RX 11
303 #define DMA_REQ_HS_I2C_TX 10
304 #define DMA_REQ_CSPI2_TX 9
305 #define DMA_REQ_CSPI2_RX 8
306 #define DMA_REQ_CSPI1_TX 7
307 #define DMA_REQ_CSPI1_RX 6
308 #define DMA_REQ_SLIM_B 5
309 #define DMA_REQ_ATA_TX_END 4
310 #define DMA_REQ_ATA_TX 3
311 #define DMA_REQ_ATA_RX 2
312 #define DMA_REQ_GPC 1
313 #define DMA_REQ_VPU 0
318 #define MXC_INT_BASE 0
319 #define MXC_INT_RESV0 0
320 #define MXC_INT_MMC_SDHC1 1
321 #define MXC_INT_MMC_SDHC2 2
322 #define MXC_INT_MMC_SDHC3 3
323 #define MXC_INT_MMC_SDHC4 4
324 #define MXC_INT_RESV5 5
325 #define MXC_INT_SDMA 6
326 #define MXC_INT_IOMUX 7
327 #define MXC_INT_NFC 8
328 #define MXC_INT_VPU 9
329 #define MXC_INT_IPU_ERR 10
330 #define MXC_INT_IPU_SYN 11
331 #define MXC_INT_GPU 12
332 #define MXC_INT_RESV13 13
333 #define MXC_INT_USB_H1 14
334 #define MXC_INT_EMI 15
335 #define MXC_INT_USB_H2 16
336 #define MXC_INT_USB_H3 17
337 #define MXC_INT_USB_OTG 18
338 #define MXC_INT_SAHARA_H0 19
339 #define MXC_INT_SAHARA_H1 20
340 #define MXC_INT_SCC_SMN 21
341 #define MXC_INT_SCC_STZ 22
342 #define MXC_INT_SCC_SCM 23
343 #define MXC_INT_SRTC_NTZ 24
344 #define MXC_INT_SRTC_TZ 25
345 #define MXC_INT_RTIC 26
346 #define MXC_INT_CSU 27
347 #define MXC_INT_SLIM_B 28
348 #define MXC_INT_SSI1 29
349 #define MXC_INT_SSI2 30
350 #define MXC_INT_UART1 31
351 #define MXC_INT_UART2 32
352 #define MXC_INT_UART3 33
353 #define MXC_INT_RESV34 34
354 #define MXC_INT_RESV35 35
355 #define MXC_INT_CSPI1 36
356 #define MXC_INT_CSPI2 37
357 #define MXC_INT_CSPI 38
358 #define MXC_INT_GPT 39
359 #define MXC_INT_EPIT1 40
360 #define MXC_INT_EPIT2 41
361 #define MXC_INT_GPIO1_INT7 42
362 #define MXC_INT_GPIO1_INT6 43
363 #define MXC_INT_GPIO1_INT5 44
364 #define MXC_INT_GPIO1_INT4 45
365 #define MXC_INT_GPIO1_INT3 46
366 #define MXC_INT_GPIO1_INT2 47
367 #define MXC_INT_GPIO1_INT1 48
368 #define MXC_INT_GPIO1_INT0 49
369 #define MXC_INT_GPIO1_LOW 50
370 #define MXC_INT_GPIO1_HIGH 51
371 #define MXC_INT_GPIO2_LOW 52
372 #define MXC_INT_GPIO2_HIGH 53
373 #define MXC_INT_GPIO3_LOW 54
374 #define MXC_INT_GPIO3_HIGH 55
375 #define MXC_INT_GPIO4_LOW 56
376 #define MXC_INT_GPIO4_HIGH 57
377 #define MXC_INT_WDOG1 58
378 #define MXC_INT_WDOG2 59
379 #define MXC_INT_KPP 60
380 #define MXC_INT_PWM1 61
381 #define MXC_INT_I2C1 62
382 #define MXC_INT_I2C2 63
383 #define MXC_INT_HS_I2C 64
384 #define MXC_INT_RESV65 65
385 #define MXC_INT_RESV66 66
386 #define MXC_INT_SIM_IPB 67
387 #define MXC_INT_SIM_DAT 68
388 #define MXC_INT_IIM 69
389 #define MXC_INT_ATA 70
390 #define MXC_INT_CCM1 71
391 #define MXC_INT_CCM2 72
392 #define MXC_INT_GPC1 73
393 #define MXC_INT_GPC2 74
394 #define MXC_INT_SRC 75
395 #define MXC_INT_NM 76
396 #define MXC_INT_PMU 77
397 #define MXC_INT_CTI_IRQ 78
398 #define MXC_INT_CTI1_TG0 79
399 #define MXC_INT_CTI1_TG1 80
400 #define MXC_INT_MCG_ERR 81
401 #define MXC_INT_MCG_TMR 82
402 #define MXC_INT_MCG_FUNC 83
403 #define MXC_INT_RESV84 84
404 #define MXC_INT_RESV85 85
405 #define MXC_INT_RESV86 86
406 #define MXC_INT_FEC 87
407 #define MXC_INT_OWIRE 88
408 #define MXC_INT_CTI1_TG2 89
409 #define MXC_INT_SJC 90
410 #define MXC_INT_SPDIF 91
411 #define MXC_INT_TVE 92
412 #define MXC_INT_FIFI 93
413 #define MXC_INT_PWM2 94
414 #define MXC_INT_SLIM_EXP 95
415 #define MXC_INT_SSI3 96
416 #define MXC_INT_RESV97 97
417 #define MXC_INT_CTI1_TG3 98
418 #define MXC_INT_SMC_RX 99
419 #define MXC_INT_VPU_IDLE 100
420 #define MXC_INT_RESV101 101
421 #define MXC_INT_GPU_IDLE 102
424 * Number of GPIO port as defined in the IC Spec
426 #define GPIO_PORT_NUM 4
428 * Number of GPIO pins per port
430 #define GPIO_NUM_PIN 32
433 #define CLKCTL_CCR 0x00
434 #define CLKCTL_CCDR 0x04
435 #define CLKCTL_CSR 0x08
436 #define CLKCTL_CCSR 0x0C
437 #define CLKCTL_CACRR 0x10
438 #define CLKCTL_CBCDR 0x14
439 #define CLKCTL_CBCMR 0x18
440 #define CLKCTL_CSCMR1 0x1C
441 #define CLKCTL_CSCMR2 0x20
442 #define CLKCTL_CSCDR1 0x24
443 #define CLKCTL_CS1CDR 0x28
444 #define CLKCTL_CS2CDR 0x2C
445 #define CLKCTL_CDCDR 0x30
446 #define CLKCTL_CHSCCDR 0x34
447 #define CLKCTL_CSCDR2 0x38
448 #define CLKCTL_CSCDR3 0x3C
449 #define CLKCTL_CSCDR4 0x40
450 #define CLKCTL_CWDR 0x44
451 #define CLKCTL_CDHIPR 0x48
452 #define CLKCTL_CDCR 0x4C
453 #define CLKCTL_CTOR 0x50
454 #define CLKCTL_CLPCR 0x54
455 #define CLKCTL_CISR 0x58
456 #define CLKCTL_CIMR 0x5C
457 #define CLKCTL_CCOSR 0x60
458 #define CLKCTL_CGPR 0x64
459 #define CLKCTL_CCGR0 0x68
460 #define CLKCTL_CCGR1 0x6C
461 #define CLKCTL_CCGR2 0x70
462 #define CLKCTL_CCGR3 0x74
463 #define CLKCTL_CCGR4 0x78
464 #define CLKCTL_CCGR5 0x7C
465 #define CLKCTL_CCGR6 0x80
466 #define CLKCTL_CMEOR 0x84
468 #define FREQ_24MHZ 24000000
469 #define FREQ_32768HZ (32768 * 1024)
470 #define FREQ_38400HZ (38400 * 1024)
471 #define FREQ_32000HZ (32000 * 1024)
472 #define PLL_REF_CLK FREQ_24MHZ
473 #define CKIH 22579200
474 //#define PLL_REF_CLK FREQ_32768HZ
475 //#define PLL_REF_CLK FREQ_32000HZ
485 #define M4IF_FBPM0 0x40
486 #define M4IF_FBPM1 0x44
487 #define M4IF_FIDBP 0x48
488 #define M4IF_MIF4 0x48
489 #define M4IF_FPWC 0x9C
492 #define ESDCTL_ESDCTL0 0x00
493 #define ESDCTL_ESDCFG0 0x04
494 #define ESDCTL_ESDCTL1 0x08
495 #define ESDCTL_ESDCFG1 0x0C
496 #define ESDCTL_ESDMISC 0x10
497 #define ESDCTL_ESDSCR 0x14
498 #define ESDCTL_ESDCDLY1 0x20
499 #define ESDCTL_ESDCDLY2 0x24
500 #define ESDCTL_ESDCDLY3 0x28
501 #define ESDCTL_ESDCDLY4 0x2C
502 #define ESDCTL_ESDCDLY5 0x30
503 #define ESDCTL_ESDCDLYGD 0x34
506 #define PLL_DP_CTL 0x00
507 #define PLL_DP_CONFIG 0x04
508 #define PLL_DP_OP 0x08
509 #define PLL_DP_MFD 0x0C
510 #define PLL_DP_MFN 0x10
511 #define PLL_DP_MFNMINUS 0x14
512 #define PLL_DP_MFNPLUS 0x18
513 #define PLL_DP_HFS_OP 0x1C
514 #define PLL_DP_HFS_MFD 0x20
515 #define PLL_DP_HFS_MFN 0x24
516 #define PLL_DP_TOGC 0x28
517 #define PLL_DP_DESTAT 0x2C
519 #define CHIP_REV_1_0 0x0 /* PASS 1.0 */
520 #define CHIP_REV_1_1 0x1 /* PASS 1.1 */
521 #define CHIP_REV_2_0 0x2 /* PASS 2.0 */
522 #define CHIP_LATEST CHIP_REV_1_1
524 #define IIM_STAT_OFF 0x00
525 #define IIM_STAT_BUSY (1 << 7)
526 #define IIM_STAT_PRGD (1 << 1)
527 #define IIM_STAT_SNSD (1 << 0)
528 #define IIM_STATM_OFF 0x04
529 #define IIM_ERR_OFF 0x08
530 #define IIM_ERR_PRGE (1 << 7)
531 #define IIM_ERR_WPE (1 << 6)
532 #define IIM_ERR_OPE (1 << 5)
533 #define IIM_ERR_RPE (1 << 4)
534 #define IIM_ERR_WLRE (1 << 3)
535 #define IIM_ERR_SNSE (1 << 2)
536 #define IIM_ERR_PARITYE (1 << 1)
537 #define IIM_EMASK_OFF 0x0C
538 #define IIM_FCTL_OFF 0x10
539 #define IIM_UA_OFF 0x14
540 #define IIM_LA_OFF 0x18
541 #define IIM_SDAT_OFF 0x1C
542 #define IIM_PREV_OFF 0x20
543 #define IIM_SREV_OFF 0x24
544 #define IIM_PREG_P_OFF 0x28
545 #define IIM_SCS0_OFF 0x2C
546 #define IIM_SCS1_P_OFF 0x30
547 #define IIM_SCS2_OFF 0x34
548 #define IIM_SCS3_P_OFF 0x38
550 #define IIM_PROD_REV_SH 3
551 #define IIM_PROD_REV_LEN 5
552 #define IIM_SREV_REV_SH 4
553 #define IIM_SREV_REV_LEN 4
554 #define PROD_SIGNATURE_MX51 0x1
556 #define EPIT_BASE_ADDR EPIT1_BASE_ADDR
560 #define EPITCMPR 0x0C
574 /* Assuming 24MHz input clock with doubler ON */
576 #define DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
577 #define DP_MFD_850 (48 - 1)
578 #define DP_MFN_850 41
580 #define DP_OP_800 ((8 << 4) + ((1 - 1) << 0))
581 #define DP_MFD_800 (3 - 1)
584 #define DP_OP_700 ((7 << 4) + ((1 - 1) << 0))
585 #define DP_MFD_700 (24 - 1)
588 #define DP_OP_400 ((8 << 4) + ((2 - 1) << 0))
589 #define DP_MFD_400 (3 - 1)
592 #define DP_OP_532 ((5 << 4) + ((1 - 1) << 0))
593 #define DP_MFD_532 (24 - 1)
594 #define DP_MFN_532 13
596 #define DP_OP_665 ((6 << 4) + ((1 - 1) << 0))
597 #define DP_MFD_665 (96 - 1)
598 #define DP_MFN_665 89
600 #define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
601 #define DP_MFD_216 (4 - 1)
604 #define PROD_SIGNATURE_SUPPORTED PROD_SIGNATURE_MX51
606 #define CHIP_VERSION_NONE 0xFFFFFFFF // invalid product ID
607 #define CHIP_VERSION_UNKNOWN 0xDEADBEEF // invalid chip rev
609 #define PART_NUMBER_OFFSET 12
610 #define MAJOR_NUMBER_OFFSET 4
611 #define MINOR_NUMBER_OFFSET 0
613 //#define BARKER_CODE_SWAP_LOC 0x404
614 #define BARKER_CODE_VAL 0xB1
617 // This defines the register base for the NAND AXI registers
618 #define NAND_REG_BASE (NFC_BASE_ADDR_AXI + 0x1E00)
620 #define NAND_CMD_REG (NAND_REG_BASE + 0x00)
621 #define NAND_ADD0_REG (NAND_REG_BASE + 0x04)
622 #define NAND_ADD1_REG (NAND_REG_BASE + 0x08)
623 #define NAND_ADD2_REG (NAND_REG_BASE + 0x0C)
624 #define NAND_ADD3_REG (NAND_REG_BASE + 0x10)
625 #define NAND_ADD4_REG (NAND_REG_BASE + 0x14)
626 #define NAND_ADD5_REG (NAND_REG_BASE + 0x18)
627 #define NAND_ADD6_REG (NAND_REG_BASE + 0x1C)
628 #define NAND_ADD7_REG (NAND_REG_BASE + 0x20)
629 #define NAND_ADD8_REG (NAND_REG_BASE + 0x24)
630 #define NAND_ADD9_REG (NAND_REG_BASE + 0x28)
631 #define NAND_ADD10_REG (NAND_REG_BASE + 0x2C)
632 #define NAND_ADD11_REG (NAND_REG_BASE + 0x30)
634 #define NAND_CONFIGURATION1_REG (NAND_REG_BASE + 0x34)
635 #define NAND_CONFIGURATION1_NFC_RST (1 << 2)
636 #define NAND_CONFIGURATION1_NF_CE (1 << 1)
637 #define NAND_CONFIGURATION1_SP_EN (1 << 0)
639 #define NAND_ECC_STATUS_RESULT_REG (NAND_REG_BASE + 0x38)
641 #define NAND_STATUS_SUM_REG (NAND_REG_BASE + 0x3C)
643 #define NAND_LAUNCH_REG (NAND_REG_BASE + 0x40)
644 #define NAND_LAUNCH_FCMD (1 << 0)
645 #define NAND_LAUNCH_FADD (1 << 1)
646 #define NAND_LAUNCH_FDI (1 << 2)
647 #define NAND_LAUNCH_AUTO_PROG (1 << 6)
648 #define NAND_LAUNCH_AUTO_READ (1 << 7)
649 #define NAND_LAUNCH_AUTO_READ_CONT (1 << 8)
650 #define NAND_LAUNCH_AUTO_ERASE (1 << 9)
651 #define NAND_LAUNCH_COPY_BACK0 (1 << 10)
652 #define NAND_LAUNCH_COPY_BACK1 (1 << 11)
653 #define NAND_LAUNCH_AUTO_STAT (1 << 12)
655 #define NFC_WR_PROT_REG (NFC_IP_BASE + 0x00)
656 #define UNLOCK_BLK_ADD0_REG (NFC_IP_BASE + 0x04)
657 #define UNLOCK_BLK_ADD1_REG (NFC_IP_BASE + 0x08)
658 #define UNLOCK_BLK_ADD2_REG (NFC_IP_BASE + 0x0C)
659 #define UNLOCK_BLK_ADD3_REG (NFC_IP_BASE + 0x10)
660 #define UNLOCK_BLK_ADD4_REG (NFC_IP_BASE + 0x14)
661 #define UNLOCK_BLK_ADD5_REG (NFC_IP_BASE + 0x18)
662 #define UNLOCK_BLK_ADD6_REG (NFC_IP_BASE + 0x1C)
663 #define UNLOCK_BLK_ADD7_REG (NFC_IP_BASE + 0x20)
665 #define NFC_FLASH_CONFIG2_REG (NFC_IP_BASE + 0x24)
666 #define NFC_FLASH_CONFIG2_ECC_EN (1 << 3)
668 #define NFC_FLASH_CONFIG3_REG (NFC_IP_BASE + 0x28)
670 #define NFC_IPC_REG (NFC_IP_BASE + 0x2C)
671 #define NFC_IPC_INT (1 << 31)
672 #define NFC_IPC_AUTO_DONE (1 << 30)
673 #define NFC_IPC_LPS (1 << 29)
674 #define NFC_IPC_RB_B (1 << 28)
675 #define NFC_IPC_CACK (1 << 1)
676 #define NFC_IPC_CREQ (1 << 0)
677 #define NFC_AXI_ERR_ADD_REG (NFC_IP_BASE + 0x30)
679 #define MXC_MMC_BASE_DUMMY 0x00000000
681 #define NAND_FLASH_BOOT 0x10000000
682 #define FROM_NAND_FLASH NAND_FLASH_BOOT
684 #define SDRAM_NON_FLASH_BOOT 0x20000000
686 #define MMC_FLASH_BOOT 0x40000000
687 #define FROM_MMC_FLASH MMC_FLASH_BOOT
689 #define SPI_NOR_FLASH_BOOT 0x80000000
690 #define FROM_SPI_NOR_FLASH SPI_NOR_FLASH_BOOT
692 #define IS_BOOTING_FROM_NAND() 0
693 #define IS_BOOTING_FROM_SPI_NOR() 0
694 #define IS_BOOTING_FROM_NOR() 0
695 #define IS_BOOTING_FROM_SDRAM() 0
696 #define IS_BOOTING_FROM_MMC() 0
698 #ifndef MXCFLASH_SELECT_NAND
699 #define IS_FIS_FROM_NAND() 0
701 #define IS_FIS_FROM_NAND() (_mxc_fis == FROM_NAND_FLASH)
704 #ifndef MXCFLASH_SELECT_MMC
705 #define IS_FIS_FROM_MMC() 0
707 #define IS_FIS_FROM_MMC() (_mxc_fis == FROM_MMC_FLASH)
710 #define IS_FIS_FROM_SPI_NOR() (_mxc_fis == FROM_SPI_NOR_FLASH)
712 #define IS_FIS_FROM_NOR() 0
714 #define SOC_MAC_ADDR_FUSE_BANK 1
715 #define SOC_MAC_ADDR_FUSE 9
716 #define SOC_MAC_ADDR_LOCK_FUSE 0
717 #define SOC_MAC_ADDR_LOCK_BIT 4
720 * This macro is used to get certain bit field from a number
722 #define MXC_GET_FIELD(val, len, sh) ((val >> sh) & ((1 << len) - 1))
725 * This macro is used to set certain bit field inside a number
727 #define MXC_SET_FIELD(val, len, sh, nval) ((val & ~(((1 << len) - 1) << sh)) | (nval << sh))
730 #define UART_WIDTH_32 /* internal UART is 32bit access only */
732 #if !defined(__ASSEMBLER__)
733 extern void fuse_blow_row(int bank, int row, int value);
734 extern unsigned int sense_fuse(int bank, int row, int bit);
736 void cyg_hal_plf_serial_init(void);
737 void cyg_hal_plf_serial_stop(void);
738 void hal_delay_us(unsigned int usecs);
739 #define HAL_DELAY_US(n) hal_delay_us(n)
741 extern unsigned int system_rev;
768 SPI1_CLK = CSPI1_BASE_ADDR,
769 SPI2_CLK = CSPI2_BASE_ADDR,
772 extern unsigned int pll_clock(enum plls pll);
774 extern unsigned int get_main_clock(enum main_clocks clk);
776 extern unsigned int get_peri_clock(enum peri_clocks clk);
778 typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int, unsigned int);
780 extern void increase_core_voltage(bool);
782 #endif //#if !defined(__ASSEMBLER__)
784 #endif /* __HAL_SOC_H__ */