1 //==========================================================================
5 // SoC chip definitions
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12 // Copyright (C) 2002 Gary Thomas
14 // eCos is free software; you can redistribute it and/or modify it under
15 // the terms of the GNU General Public License as published by the Free
16 // Software Foundation; either version 2 or (at your option) any later version.
18 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
19 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
23 // You should have received a copy of the GNU General Public License along
24 // with eCos; if not, write to the Free Software Foundation, Inc.,
25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27 // As a special exception, if other files instantiate templates or use macros
28 // or inline functions from this file, or you compile this file and link it
29 // with other works to produce a work based on this file, this file does not
30 // by itself cause the resulting work to be covered by the GNU General Public
31 // License. However the source code for this file must still be made available
32 // in accordance with section (3) of the GNU General Public License.
34 // This exception does not invalidate any other reasons why a work based on
35 // this file might be covered by the GNU General Public License.
37 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
38 // at http://sources.redhat.com/ecos/ecos-license/
39 // -------------------------------------------
40 //####ECOSGPLCOPYRIGHTEND####
41 //========================================================================*/
48 #define REG8_VAL(a) (a)
49 #define REG16_VAL(a) (a)
50 #define REG32_VAL(a) (a)
52 #define REG8_PTR(a) (a)
53 #define REG16_PTR(a) (a)
54 #define REG32_PTR(a) (a)
56 #else /* __ASSEMBLER__ */
58 extern char HAL_PLATFORM_EXTRA[];
59 #define REG8_VAL(a) ((unsigned char)(a))
60 #define REG16_VAL(a) ((unsigned short)(a))
61 #define REG32_VAL(a) ((unsigned int)(a))
63 #define REG8_PTR(a) ((volatile unsigned char *)(a))
64 #define REG16_PTR(a) ((volatile unsigned short *)(a))
65 #define REG32_PTR(a) ((volatile unsigned int *)(a))
66 #define readb(a) (*(volatile unsigned char *)(a))
67 #define readw(a) (*(volatile unsigned short *)(a))
68 #define readl(a) (*(volatile unsigned int *)(a))
69 #define writeb(v,a) (*(volatile unsigned char *)(a) = (v))
70 #define writew(v,a) (*(volatile unsigned short *)(a) = (v))
71 #define writel(v,a) (*(volatile unsigned int *)(a) = (v))
73 #endif /* __ASSEMBLER__ */
76 * Default Memory Layout Definitions
80 * UART Chip level Configuration that a user may not have to edit. These
81 * configuration vary depending on how the UART module is integrated with
86 * This option is used to set or clear the RXDMUXSEL bit in control reg 3.
87 * Certain platforms need this bit to be set in order to receive Irda data.
89 #define MXC_UART_IR_RXDMUX 0x0004
91 * This option is used to set or clear the RXDMUXSEL bit in control reg 3.
92 * Certain platforms need this bit to be set in order to receive UART data.
94 #define MXC_UART_RXDMUX 0x0004
99 #define IRAM_BASE_ADDR 0x1FFE8000 /* 96K internal ram */
104 #define ROM_BASE_ADDRESS 0x0
105 #define ROM_BASE_ADDRESS_VIRT 0x20000000
107 #define ROM_SI_REV_OFFSET 0x48
112 #define NFC_BASE_ADDR_AXI 0xCFFF0000
113 #define NFC_BASE NFC_BASE_ADDR_AXI
115 #define PLATFORM_BASE_ADDR 0x83FA0000
116 #define PLATFORM_ICGC 0x14
118 * Graphics Memory of GPU
120 #define GPU_BASE_ADDR 0x20000000
122 #define TZIC_BASE_ADDR 0x8FFFC000
124 #define DEBUG_BASE_ADDR 0x60000000
125 #define DEBUG_ROM_ADDR (DEBUG_BASE_ADDR + 0x0)
126 #define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000)
127 #define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000)
128 #define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000)
129 #define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000)
130 #define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000)
131 #define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000)
132 #define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000)
133 #define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000)
136 * SPBA global module enabled #0
138 #define SPBA0_BASE_ADDR 0x70000000
140 #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
141 #define ESDHC1_REG_BASE MMC_SDHC1_BASE_ADDR
142 #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
143 #define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
145 #define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
146 #define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
147 #define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
148 #define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
149 #define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000)
150 #define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000)
151 #define SLIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000)
152 #define HSI2C_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000)
153 #define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
156 * defines for SPBA modules
158 #define SPBA_SDHC1 0x04
159 #define SPBA_SDHC2 0x08
160 #define SPBA_UART3 0x0C
161 #define SPBA_CSPI1 0x10
162 #define SPBA_SSI2 0x14
163 #define SPBA_SDHC3 0x20
164 #define SPBA_SDHC4 0x24
165 #define SPBA_SPDIF 0x28
166 #define SPBA_ATA 0x30
167 #define SPBA_SLIM 0x34
168 #define SPBA_HSI2C 0x38
169 #define SPBA_CTRL 0x3C
175 #define AIPS1_BASE_ADDR 0x73F00000
176 #define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
177 #define USBOH3_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
178 #define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
179 #define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
180 #define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
181 #define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
182 #define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
183 #define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
184 #define WDOG_BASE_ADDR WDOG1_BASE_ADDR
185 #define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
186 #define GPT_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
187 #define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
188 #define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
189 #define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
190 #define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
191 #define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
192 #define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
193 #define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
194 #define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000)
195 #define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000)
196 #define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000)
197 #define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000)
202 #define AIPS2_BASE_ADDR 0x83F00000
203 #define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR
204 #define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
205 #define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
206 #define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
207 #define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
208 #define MAX_BASE_ADDR AHBMAX_BASE_ADDR
209 #define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
210 #define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
211 #define ARM_ELBOW_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000)
212 #define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
213 #define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000)
215 #define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
216 #define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
217 #define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000)
218 #define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000)
219 #define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000)
221 #define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
222 #define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
223 #define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
224 #define I2C_BASE_ADDR I2C1_BASE_ADDR
225 #define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
226 #define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
227 #define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
228 #define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000)
229 #define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000)
230 #define NFC_IP_BASE (AIPS2_BASE_ADDR + 0x000DB000)
231 #define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00)
232 #define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
233 #define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
234 #define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000)
235 #define SSI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000)
236 #define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
237 #define SOC_FEC_BASE FEC_BASE_ADDR
238 #define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000)
239 #define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000)
240 #define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000)
243 * Memory regions and CS
245 #define GPU_CTRL_BASE_ADDR 0x30000000
246 #define IPU_CTRL_BASE_ADDR 0x40000000
247 #define CSD0_BASE_ADDR 0x90000000
248 #define CSD1_BASE_ADDR 0xA0000000
249 #define CS0_BASE_ADDR 0xB0000000
250 #define CS1_BASE_ADDR 0xB8000000
251 #define CS2_BASE_ADDR 0xC0000000
252 #define CS3_BASE_ADDR 0xC8000000
253 #define CS4_BASE_ADDR 0xCC000000
254 #define CS5_BASE_ADDR 0xCE000000
257 * DMA request assignments
259 #define DMA_REQ_SSI3_TX1 47
260 #define DMA_REQ_SSI3_RX1 46
261 #define DMA_REQ_SPDIF 45
262 #define DMA_REQ_UART3_TX 44
263 #define DMA_REQ_UART3_RX 43
264 #define DMA_REQ_SLIM_B_TX 42
265 #define DMA_REQ_SDHC4 41
266 #define DMA_REQ_SDHC3 40
267 #define DMA_REQ_CSPI_TX 39
268 #define DMA_REQ_CSPI_RX 38
269 #define DMA_REQ_SSI3_TX2 37
270 #define DMA_REQ_IPU 36
271 #define DMA_REQ_SSI3_RX2 35
272 #define DMA_REQ_EPIT2 34
273 #define DMA_REQ_CTI2_1 33
274 #define DMA_REQ_EMI_WR 32
275 #define DMA_REQ_CTI2_0 31
276 #define DMA_REQ_EMI_RD 30
277 #define DMA_REQ_SSI1_TX1 29
278 #define DMA_REQ_SSI1_RX1 28
279 #define DMA_REQ_SSI1_TX2 27
280 #define DMA_REQ_SSI1_RX2 26
281 #define DMA_REQ_SSI2_TX1 25
282 #define DMA_REQ_SSI2_RX1 24
283 #define DMA_REQ_SSI2_TX2 23
284 #define DMA_REQ_SSI2_RX2 22
285 #define DMA_REQ_SDHC2_I2C2 21
286 #define DMA_REQ_SDHC1_I2C1 20
287 #define DMA_REQ_UART1_TX 19
288 #define DMA_REQ_UART1_RX 18
289 #define DMA_REQ_UART2_TX 17
290 #define DMA_REQ_UART2_RX 16
291 #define DMA_REQ_GPU_GPIO1_0 15
292 #define DMA_REQ_GPIO1_1 14
293 #define DMA_REQ_FIRI_TX 13
294 #define DMA_REQ_FIRI_RX 12
295 #define DMA_REQ_HS_I2C_RX 11
296 #define DMA_REQ_HS_I2C_TX 10
297 #define DMA_REQ_CSPI2_TX 9
298 #define DMA_REQ_CSPI2_RX 8
299 #define DMA_REQ_CSPI1_TX 7
300 #define DMA_REQ_CSPI1_RX 6
301 #define DMA_REQ_SLIM_B 5
302 #define DMA_REQ_ATA_TX_END 4
303 #define DMA_REQ_ATA_TX 3
304 #define DMA_REQ_ATA_RX 2
305 #define DMA_REQ_GPC 1
306 #define DMA_REQ_VPU 0
311 #define MXC_INT_BASE 0
312 #define MXC_INT_RESV0 0
313 #define MXC_INT_MMC_SDHC1 1
314 #define MXC_INT_MMC_SDHC2 2
315 #define MXC_INT_MMC_SDHC3 3
316 #define MXC_INT_MMC_SDHC4 4
317 #define MXC_INT_RESV5 5
318 #define MXC_INT_SDMA 6
319 #define MXC_INT_IOMUX 7
320 #define MXC_INT_NFC 8
321 #define MXC_INT_VPU 9
322 #define MXC_INT_IPU_ERR 10
323 #define MXC_INT_IPU_SYN 11
324 #define MXC_INT_GPU 12
325 #define MXC_INT_RESV13 13
326 #define MXC_INT_USB_H1 14
327 #define MXC_INT_EMI 15
328 #define MXC_INT_USB_H2 16
329 #define MXC_INT_USB_H3 17
330 #define MXC_INT_USB_OTG 18
331 #define MXC_INT_SAHARA_H0 19
332 #define MXC_INT_SAHARA_H1 20
333 #define MXC_INT_SCC_SMN 21
334 #define MXC_INT_SCC_STZ 22
335 #define MXC_INT_SCC_SCM 23
336 #define MXC_INT_SRTC_NTZ 24
337 #define MXC_INT_SRTC_TZ 25
338 #define MXC_INT_RTIC 26
339 #define MXC_INT_CSU 27
340 #define MXC_INT_SLIM_B 28
341 #define MXC_INT_SSI1 29
342 #define MXC_INT_SSI2 30
343 #define MXC_INT_UART1 31
344 #define MXC_INT_UART2 32
345 #define MXC_INT_UART3 33
346 #define MXC_INT_RESV34 34
347 #define MXC_INT_RESV35 35
348 #define MXC_INT_CSPI1 36
349 #define MXC_INT_CSPI2 37
350 #define MXC_INT_CSPI 38
351 #define MXC_INT_GPT 39
352 #define MXC_INT_EPIT1 40
353 #define MXC_INT_EPIT2 41
354 #define MXC_INT_GPIO1_INT7 42
355 #define MXC_INT_GPIO1_INT6 43
356 #define MXC_INT_GPIO1_INT5 44
357 #define MXC_INT_GPIO1_INT4 45
358 #define MXC_INT_GPIO1_INT3 46
359 #define MXC_INT_GPIO1_INT2 47
360 #define MXC_INT_GPIO1_INT1 48
361 #define MXC_INT_GPIO1_INT0 49
362 #define MXC_INT_GPIO1_LOW 50
363 #define MXC_INT_GPIO1_HIGH 51
364 #define MXC_INT_GPIO2_LOW 52
365 #define MXC_INT_GPIO2_HIGH 53
366 #define MXC_INT_GPIO3_LOW 54
367 #define MXC_INT_GPIO3_HIGH 55
368 #define MXC_INT_GPIO4_LOW 56
369 #define MXC_INT_GPIO4_HIGH 57
370 #define MXC_INT_WDOG1 58
371 #define MXC_INT_WDOG2 59
372 #define MXC_INT_KPP 60
373 #define MXC_INT_PWM1 61
374 #define MXC_INT_I2C1 62
375 #define MXC_INT_I2C2 63
376 #define MXC_INT_HS_I2C 64
377 #define MXC_INT_RESV65 65
378 #define MXC_INT_RESV66 66
379 #define MXC_INT_SIM_IPB 67
380 #define MXC_INT_SIM_DAT 68
381 #define MXC_INT_IIM 69
382 #define MXC_INT_ATA 70
383 #define MXC_INT_CCM1 71
384 #define MXC_INT_CCM2 72
385 #define MXC_INT_GPC1 73
386 #define MXC_INT_GPC2 74
387 #define MXC_INT_SRC 75
388 #define MXC_INT_NM 76
389 #define MXC_INT_PMU 77
390 #define MXC_INT_CTI_IRQ 78
391 #define MXC_INT_CTI1_TG0 79
392 #define MXC_INT_CTI1_TG1 80
393 #define MXC_INT_MCG_ERR 81
394 #define MXC_INT_MCG_TMR 82
395 #define MXC_INT_MCG_FUNC 83
396 #define MXC_INT_RESV84 84
397 #define MXC_INT_RESV85 85
398 #define MXC_INT_RESV86 86
399 #define MXC_INT_FEC 87
400 #define MXC_INT_OWIRE 88
401 #define MXC_INT_CTI1_TG2 89
402 #define MXC_INT_SJC 90
403 #define MXC_INT_SPDIF 91
404 #define MXC_INT_TVE 92
405 #define MXC_INT_FIFI 93
406 #define MXC_INT_PWM2 94
407 #define MXC_INT_SLIM_EXP 95
408 #define MXC_INT_SSI3 96
409 #define MXC_INT_RESV97 97
410 #define MXC_INT_CTI1_TG3 98
411 #define MXC_INT_SMC_RX 99
412 #define MXC_INT_VPU_IDLE 100
413 #define MXC_INT_RESV101 101
414 #define MXC_INT_GPU_IDLE 102
417 * Number of GPIO port as defined in the IC Spec
419 #define GPIO_PORT_NUM 4
421 * Number of GPIO pins per port
423 #define GPIO_NUM_PIN 32
426 #define CLKCTL_CCR 0x00
427 #define CLKCTL_CCDR 0x04
428 #define CLKCTL_CSR 0x08
429 #define CLKCTL_CCSR 0x0C
430 #define CLKCTL_CACRR 0x10
431 #define CLKCTL_CBCDR 0x14
432 #define CLKCTL_CBCMR 0x18
433 #define CLKCTL_CSCMR1 0x1C
434 #define CLKCTL_CSCMR2 0x20
435 #define CLKCTL_CSCDR1 0x24
436 #define CLKCTL_CS1CDR 0x28
437 #define CLKCTL_CS2CDR 0x2C
438 #define CLKCTL_CDCDR 0x30
439 #define CLKCTL_CHSCCDR 0x34
440 #define CLKCTL_CSCDR2 0x38
441 #define CLKCTL_CSCDR3 0x3C
442 #define CLKCTL_CSCDR4 0x40
443 #define CLKCTL_CWDR 0x44
444 #define CLKCTL_CDHIPR 0x48
445 #define CLKCTL_CDCR 0x4C
446 #define CLKCTL_CTOR 0x50
447 #define CLKCTL_CLPCR 0x54
448 #define CLKCTL_CISR 0x58
449 #define CLKCTL_CIMR 0x5C
450 #define CLKCTL_CCOSR 0x60
451 #define CLKCTL_CGPR 0x64
452 #define CLKCTL_CCGR0 0x68
453 #define CLKCTL_CCGR1 0x6C
454 #define CLKCTL_CCGR2 0x70
455 #define CLKCTL_CCGR3 0x74
456 #define CLKCTL_CCGR4 0x78
457 #define CLKCTL_CCGR5 0x7C
458 #define CLKCTL_CMEOR 0x84
460 #define FREQ_24MHZ 24000000
461 #define FREQ_32768HZ (32768 * 1024)
462 #define FREQ_38400HZ (38400 * 1024)
463 #define FREQ_32000HZ (32000 * 1024)
464 #define PLL_REF_CLK FREQ_24MHZ
465 #define CKIH 22579200
466 //#define PLL_REF_CLK FREQ_32768HZ
467 //#define PLL_REF_CLK FREQ_32000HZ
477 #define M4IF_FBPM0 0x40
478 #define M4IF_FIDBP 0x48
479 #define M4IF_MIF4 0x48
482 #define ESDCTL_ESDCTL0 0x00
483 #define ESDCTL_ESDCFG0 0x04
484 #define ESDCTL_ESDCTL1 0x08
485 #define ESDCTL_ESDCFG1 0x0C
486 #define ESDCTL_ESDMISC 0x10
487 #define ESDCTL_ESDSCR 0x14
488 #define ESDCTL_ESDCDLY1 0x20
489 #define ESDCTL_ESDCDLY2 0x24
490 #define ESDCTL_ESDCDLY3 0x28
491 #define ESDCTL_ESDCDLY4 0x2C
492 #define ESDCTL_ESDCDLY5 0x30
493 #define ESDCTL_ESDCDLYGD 0x34
496 #define PLL_DP_CTL 0x00
497 #define PLL_DP_CONFIG 0x04
498 #define PLL_DP_OP 0x08
499 #define PLL_DP_MFD 0x0C
500 #define PLL_DP_MFN 0x10
501 #define PLL_DP_MFNMINUS 0x14
502 #define PLL_DP_MFNPLUS 0x18
503 #define PLL_DP_HFS_OP 0x1C
504 #define PLL_DP_HFS_MFD 0x20
505 #define PLL_DP_HFS_MFN 0x24
506 #define PLL_DP_TOGC 0x28
507 #define PLL_DP_DESTAT 0x2C
509 #define CHIP_REV_1_0 0x0 /* PASS 1.0 */
510 #define CHIP_REV_1_1 0x1 /* PASS 1.1 */
511 #define CHIP_REV_2_0 0x2 /* PASS 2.0 */
512 #define CHIP_LATEST CHIP_REV_1_1
514 #define IIM_STAT_OFF 0x00
515 #define IIM_STAT_BUSY (1 << 7)
516 #define IIM_STAT_PRGD (1 << 1)
517 #define IIM_STAT_SNSD (1 << 0)
518 #define IIM_STATM_OFF 0x04
519 #define IIM_ERR_OFF 0x08
520 #define IIM_ERR_PRGE (1 << 7)
521 #define IIM_ERR_WPE (1 << 6)
522 #define IIM_ERR_OPE (1 << 5)
523 #define IIM_ERR_RPE (1 << 4)
524 #define IIM_ERR_WLRE (1 << 3)
525 #define IIM_ERR_SNSE (1 << 2)
526 #define IIM_ERR_PARITYE (1 << 1)
527 #define IIM_EMASK_OFF 0x0C
528 #define IIM_FCTL_OFF 0x10
529 #define IIM_UA_OFF 0x14
530 #define IIM_LA_OFF 0x18
531 #define IIM_SDAT_OFF 0x1C
532 #define IIM_PREV_OFF 0x20
533 #define IIM_SREV_OFF 0x24
534 #define IIM_PREG_P_OFF 0x28
535 #define IIM_SCS0_OFF 0x2C
536 #define IIM_SCS1_P_OFF 0x30
537 #define IIM_SCS2_OFF 0x34
538 #define IIM_SCS3_P_OFF 0x38
540 #define IIM_PROD_REV_SH 3
541 #define IIM_PROD_REV_LEN 5
542 #define IIM_SREV_REV_SH 4
543 #define IIM_SREV_REV_LEN 4
544 #define PROD_SIGNATURE_MX51 0x1
546 #define EPIT_BASE_ADDR EPIT1_BASE_ADDR
550 #define EPITCMPR 0x0C
564 /* Assuming 24MHz input clock with doubler ON */
566 #define DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
567 #define DP_MFD_850 (48 - 1)
568 #define DP_MFN_850 41
570 #define DP_OP_800 ((8 << 4) + ((1 - 1) << 0))
571 #define DP_MFD_800 (3 - 1)
574 #define DP_OP_700 ((7 << 4) + ((1 - 1) << 0))
575 #define DP_MFD_700 (24 - 1)
578 #define DP_OP_400 ((8 << 4) + ((2 - 1) << 0))
579 #define DP_MFD_400 (3 - 1)
582 #define DP_OP_532 ((5 << 4) + ((1 - 1) << 0))
583 #define DP_MFD_532 (24 - 1)
584 #define DP_MFN_532 13
586 #define DP_OP_665 ((6 << 4) + ((1 - 1) << 0))
587 #define DP_MFD_665 (96 - 1)
588 #define DP_MFN_665 89
590 #define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
591 #define DP_MFD_216 (4 - 1)
594 #define PROD_SIGNATURE_SUPPORTED PROD_SIGNATURE_MX51
596 #define CHIP_VERSION_NONE 0xFFFFFFFF // invalid product ID
597 #define CHIP_VERSION_UNKNOWN 0xDEADBEEF // invalid chip rev
599 #define PART_NUMBER_OFFSET (12)
600 #define MAJOR_NUMBER_OFFSET (4)
601 #define MINOR_NUMBER_OFFSET (0)
604 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_WE_B (IOMUXC_BASE_ADDR + 0x108) // 0x108
605 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_RE_B (IOMUXC_BASE_ADDR + 0x10C) // 0x10c
606 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_ALE (IOMUXC_BASE_ADDR + 0x110) // 0x110
607 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_CLE (IOMUXC_BASE_ADDR + 0x114) // 0x114
608 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_WP_B (IOMUXC_BASE_ADDR + 0x118) // 0x118
609 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB0 (IOMUXC_BASE_ADDR + 0x11C) // 0x11c
610 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB1 (IOMUXC_BASE_ADDR + 0x120) // 0x120
611 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB2 (IOMUXC_BASE_ADDR + 0x124) // 0x124
612 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB3 (IOMUXC_BASE_ADDR + 0x128) // 0x128
613 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB4 (IOMUXC_BASE_ADDR + 0x12C) // 0x12c
614 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB5 (IOMUXC_BASE_ADDR + 0x130) // 0x130
615 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB6 (IOMUXC_BASE_ADDR + 0x134) // 0x134
616 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB7 (IOMUXC_BASE_ADDR + 0x138) // 0x138
617 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS0 (IOMUXC_BASE_ADDR + 0x13C) // 0x13c
618 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS1 (IOMUXC_BASE_ADDR + 0x140) // 0x140
619 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS2 (IOMUXC_BASE_ADDR + 0x144) // 0x144
620 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS3 (IOMUXC_BASE_ADDR + 0x148) // 0x148
621 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS4 (IOMUXC_BASE_ADDR + 0x14C) // 0x14c
622 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS5 (IOMUXC_BASE_ADDR + 0x150) // 0x150
623 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS6 (IOMUXC_BASE_ADDR + 0x154) // 0x154
624 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS7 (IOMUXC_BASE_ADDR + 0x158) // 0x158
625 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_RDY_INT (IOMUXC_BASE_ADDR + 0x15C) // 0x15c
626 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D15 (IOMUXC_BASE_ADDR + 0x160) // 0x160
627 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D14 (IOMUXC_BASE_ADDR + 0x164) // 0x164
628 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D13 (IOMUXC_BASE_ADDR + 0x168) // 0x168
629 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D12 (IOMUXC_BASE_ADDR + 0x16C) // 0x16c
630 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D11 (IOMUXC_BASE_ADDR + 0x170) // 0x170
631 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D10 (IOMUXC_BASE_ADDR + 0x174) // 0x174
632 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D9 (IOMUXC_BASE_ADDR + 0x178) // 0x178
633 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D8 (IOMUXC_BASE_ADDR + 0x17C) // 0x17c
634 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D7 (IOMUXC_BASE_ADDR + 0x180) // 0x180
635 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D6 (IOMUXC_BASE_ADDR + 0x184) // 0x184
636 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D5 (IOMUXC_BASE_ADDR + 0x188) // 0x188
637 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D4 (IOMUXC_BASE_ADDR + 0x18C) // 0x18c
638 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D3 (IOMUXC_BASE_ADDR + 0x190) // 0x190
639 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D2 (IOMUXC_BASE_ADDR + 0x194) // 0x194
640 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D1 (IOMUXC_BASE_ADDR + 0x198) // 0x198
641 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D0 (IOMUXC_BASE_ADDR + 0x19C) // 0x19c
643 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_WE_B (IOMUXC_BASE_ADDR + 0x5B0) // 0x5b0
644 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_RE_B (IOMUXC_BASE_ADDR + 0x5B4) // 0x5b4
645 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_ALE (IOMUXC_BASE_ADDR + 0x5B8) // 0x5b8
646 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_CLE (IOMUXC_BASE_ADDR + 0x5BC) // 0x5bc
647 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_WP_B (IOMUXC_BASE_ADDR + 0x5C0) // 0x5c0
648 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB0 (IOMUXC_BASE_ADDR + 0x5C4) // 0x5c4
649 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB1 (IOMUXC_BASE_ADDR + 0x5C8) // 0x5c8
650 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB2 (IOMUXC_BASE_ADDR + 0x5CC) // 0x5cc
651 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB3 (IOMUXC_BASE_ADDR + 0x5D0) // 0x5d0
652 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB4 (IOMUXC_BASE_ADDR + 0x5D4) // 0x5d4
653 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB5 (IOMUXC_BASE_ADDR + 0x5D8) // 0x5d8
654 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB6 (IOMUXC_BASE_ADDR + 0x5DC) // 0x5dc
655 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB7 (IOMUXC_BASE_ADDR + 0x5E0) // 0x5e0
656 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS0 (IOMUXC_BASE_ADDR + 0x5E4) // 0x5e4
657 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS1 (IOMUXC_BASE_ADDR + 0x5E8) // 0x5e8
658 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS2 (IOMUXC_BASE_ADDR + 0x5EC) // 0x5ec
659 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS3 (IOMUXC_BASE_ADDR + 0x5F0) // 0x5f0
660 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS4 (IOMUXC_BASE_ADDR + 0x5F4) // 0x5f4
661 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS5 (IOMUXC_BASE_ADDR + 0x5F8) // 0x5f8
662 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS6 (IOMUXC_BASE_ADDR + 0x5FC) // 0x5fc
663 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS7 (IOMUXC_BASE_ADDR + 0x600) // 0x600
664 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_RDY_INT (IOMUXC_BASE_ADDR + 0x604) // 0x604
665 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D15 (IOMUXC_BASE_ADDR + 0x608) // 0x608
666 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D14 (IOMUXC_BASE_ADDR + 0x60C) // 0x60c
667 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D13 (IOMUXC_BASE_ADDR + 0x610) // 0x610
668 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D12 (IOMUXC_BASE_ADDR + 0x614) // 0x614
669 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D11 (IOMUXC_BASE_ADDR + 0x618) // 0x618
670 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D10 (IOMUXC_BASE_ADDR + 0x61C) // 0x61c
671 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D9 (IOMUXC_BASE_ADDR + 0x620) // 0x620
672 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D8 (IOMUXC_BASE_ADDR + 0x624) // 0x624
673 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D7 (IOMUXC_BASE_ADDR + 0x628) // 0x628
674 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D6 (IOMUXC_BASE_ADDR + 0x62C) // 0x62c
675 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D5 (IOMUXC_BASE_ADDR + 0x630) // 0x630
676 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D4 (IOMUXC_BASE_ADDR + 0x634) // 0x634
677 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D3 (IOMUXC_BASE_ADDR + 0x638) // 0x638
678 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D2 (IOMUXC_BASE_ADDR + 0x63C) // 0x63c
679 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D1 (IOMUXC_BASE_ADDR + 0x640) // 0x640
680 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D0 (IOMUXC_BASE_ADDR + 0x644) // 0x644
683 //#define BARKER_CODE_SWAP_LOC 0x404
684 #define BARKER_CODE_VAL 0xB1
685 #define NFC_V3_0 0x30
686 // This defines the register base for the NAND AXI registers
687 #define NAND_REG_BASE (NFC_BASE_ADDR_AXI + 0x1E00)
689 #define NAND_CMD_REG (NAND_REG_BASE + 0x00)
690 #define NAND_ADD0_REG (NAND_REG_BASE + 0x04)
691 #define NAND_ADD1_REG (NAND_REG_BASE + 0x08)
692 #define NAND_ADD2_REG (NAND_REG_BASE + 0x0C)
693 #define NAND_ADD3_REG (NAND_REG_BASE + 0x10)
694 #define NAND_ADD4_REG (NAND_REG_BASE + 0x14)
695 #define NAND_ADD5_REG (NAND_REG_BASE + 0x18)
696 #define NAND_ADD6_REG (NAND_REG_BASE + 0x1C)
697 #define NAND_ADD7_REG (NAND_REG_BASE + 0x20)
698 #define NAND_ADD8_REG (NAND_REG_BASE + 0x24)
699 #define NAND_ADD9_REG (NAND_REG_BASE + 0x28)
700 #define NAND_ADD10_REG (NAND_REG_BASE + 0x2C)
701 #define NAND_ADD11_REG (NAND_REG_BASE + 0x30)
703 #define NAND_CONFIGURATION1_REG (NAND_REG_BASE + 0x34)
704 #define NAND_CONFIGURATION1_NFC_RST (1 << 2)
705 #define NAND_CONFIGURATION1_NF_CE (1 << 1)
706 #define NAND_CONFIGURATION1_SP_EN (1 << 0)
708 #define NAND_ECC_STATUS_RESULT_REG (NAND_REG_BASE + 0x38)
710 #define NAND_STATUS_SUM_REG (NAND_REG_BASE + 0x3C)
712 #define NAND_LAUNCH_REG (NAND_REG_BASE + 0x40)
713 #define NAND_LAUNCH_FCMD (1 << 0)
714 #define NAND_LAUNCH_FADD (1 << 1)
715 #define NAND_LAUNCH_FDI (1 << 2)
716 #define NAND_LAUNCH_AUTO_PROG (1 << 6)
717 #define NAND_LAUNCH_AUTO_READ (1 << 7)
718 #define NAND_LAUNCH_AUTO_READ_CONT (1 << 8)
719 #define NAND_LAUNCH_AUTO_ERASE (1 << 9)
720 #define NAND_LAUNCH_COPY_BACK0 (1 << 10)
721 #define NAND_LAUNCH_COPY_BACK1 (1 << 11)
722 #define NAND_LAUNCH_AUTO_STAT (1 << 12)
724 #define NFC_WR_PROT_REG (NFC_IP_BASE + 0x00)
725 #define UNLOCK_BLK_ADD0_REG (NFC_IP_BASE + 0x04)
726 #define UNLOCK_BLK_ADD1_REG (NFC_IP_BASE + 0x08)
727 #define UNLOCK_BLK_ADD2_REG (NFC_IP_BASE + 0x0C)
728 #define UNLOCK_BLK_ADD3_REG (NFC_IP_BASE + 0x10)
729 #define UNLOCK_BLK_ADD4_REG (NFC_IP_BASE + 0x14)
730 #define UNLOCK_BLK_ADD5_REG (NFC_IP_BASE + 0x18)
731 #define UNLOCK_BLK_ADD6_REG (NFC_IP_BASE + 0x1C)
732 #define UNLOCK_BLK_ADD7_REG (NFC_IP_BASE + 0x20)
734 #define NFC_FLASH_CONFIG2_REG (NFC_IP_BASE + 0x24)
735 #define NFC_FLASH_CONFIG2_ECC_EN (1 << 3)
737 #define NFC_FLASH_CONFIG3_REG (NFC_IP_BASE + 0x28)
739 #define NFC_IPC_REG (NFC_IP_BASE + 0x2C)
740 #define NFC_IPC_INT (1 << 31)
741 #define NFC_IPC_AUTO_DONE (1 << 30)
742 #define NFC_IPC_LPS (1 << 29)
743 #define NFC_IPC_RB_B (1 << 28)
744 #define NFC_IPC_CACK (1 << 1)
745 #define NFC_IPC_CREQ (1 << 0)
746 #define NFC_AXI_ERR_ADD_REG (NFC_IP_BASE + 0x30)
748 #define MXC_MMC_BASE_DUMMY 0x00000000
750 #define NAND_FLASH_BOOT 0x10000000
751 #define FROM_NAND_FLASH NAND_FLASH_BOOT
753 #define SDRAM_NON_FLASH_BOOT 0x20000000
755 #define MMC_FLASH_BOOT 0x40000000
756 #define FROM_MMC_FLASH MMC_FLASH_BOOT
758 #define SPI_NOR_FLASH_BOOT 0x80000000
759 #define FROM_SPI_NOR_FLASH SPI_NOR_FLASH_BOOT
761 #define IS_BOOTING_FROM_NAND() (0)
762 #define IS_BOOTING_FROM_SPI_NOR() (0)
763 #define IS_BOOTING_FROM_NOR() (0)
764 #define IS_BOOTING_FROM_SDRAM() (0)
765 #define IS_BOOTING_FROM_MMC() (0)
767 #ifndef MXCFLASH_SELECT_NAND
768 #define IS_FIS_FROM_NAND() 0
770 #define IS_FIS_FROM_NAND() (_mxc_fis == FROM_NAND_FLASH)
773 #ifndef MXCFLASH_SELECT_MMC
774 #define IS_FIS_FROM_MMC() 0
776 #define IS_FIS_FROM_MMC() (_mxc_fis == FROM_MMC_FLASH)
779 #define IS_FIS_FROM_SPI_NOR() (_mxc_fis == FROM_SPI_NOR_FLASH)
781 #define IS_FIS_FROM_NOR() 0
784 * This macro is used to get certain bit field from a number
786 #define MXC_GET_FIELD(val, len, sh) ((val >> sh) & ((1 << len) - 1))
789 * This macro is used to set certain bit field inside a number
791 #define MXC_SET_FIELD(val, len, sh, nval) ((val & ~(((1 << len) - 1) << sh)) | (nval << sh))
794 #define UART_WIDTH_32 /* internal UART is 32bit access only */
796 #if !defined(__ASSEMBLER__)
797 void cyg_hal_plf_serial_init(void);
798 void cyg_hal_plf_serial_stop(void);
799 void hal_delay_us(unsigned int usecs);
800 #define HAL_DELAY_US(n) hal_delay_us(n)
802 extern unsigned int system_rev;
829 SPI1_CLK = CSPI1_BASE_ADDR,
830 SPI2_CLK = CSPI2_BASE_ADDR,
833 unsigned int pll_clock(enum plls pll);
835 unsigned int get_main_clock(enum main_clocks clk);
837 unsigned int get_peri_clock(enum peri_clocks clk);
839 typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int, unsigned int);
841 #endif //#if !defined(__ASSEMBLER__)
843 #endif /* __HAL_SOC_H__ */