1 //==========================================================================
5 // SoC chip definitions
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12 // Copyright (C) 2002 Gary Thomas
14 // eCos is free software; you can redistribute it and/or modify it under
15 // the terms of the GNU General Public License as published by the Free
16 // Software Foundation; either version 2 or (at your option) any later version.
18 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
19 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
23 // You should have received a copy of the GNU General Public License along
24 // with eCos; if not, write to the Free Software Foundation, Inc.,
25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27 // As a special exception, if other files instantiate templates or use macros
28 // or inline functions from this file, or you compile this file and link it
29 // with other works to produce a work based on this file, this file does not
30 // by itself cause the resulting work to be covered by the GNU General Public
31 // License. However the source code for this file must still be made available
32 // in accordance with section (3) of the GNU General Public License.
34 // This exception does not invalidate any other reasons why a work based on
35 // this file might be covered by the GNU General Public License.
37 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
38 // at http://sources.redhat.com/ecos/ecos-license/
39 // -------------------------------------------
40 //####ECOSGPLCOPYRIGHTEND####
41 //========================================================================*/
53 #else /* __ASSEMBLER__ */
55 #define VA(a) ((void *)(a))
57 extern char HAL_PLATFORM_EXTRA[40];
58 externC void plf_hardware_init(void);
60 extern int adjust_core_voltage(unsigned int);
62 #define REG8(a) (*(volatile unsigned char *)(a))
63 #define REG16(a) (*(volatile unsigned short *)(a))
64 #define REG32(a) (*(volatile unsigned int *)(a))
66 #define readb(a) (*(volatile unsigned char *)(a))
67 #define readw(a) (*(volatile unsigned short *)(a))
68 #define readl(a) (*(volatile unsigned int *)(a))
69 #define writeb(v,a) (*(volatile unsigned char *)(a) = (v))
70 #define writew(v,a) (*(volatile unsigned short *)(a) = (v))
71 #define writel(v,a) (*(volatile unsigned int *)(a) = (v))
73 #endif /* __ASSEMBLER__ */
75 #include <cyg/hal/mx53_iomux.h>
78 * Default Memory Layout Definitions
81 #define MXC_NAND_BASE_DUMMY 0
84 * UART Chip level Configuration that a user may not have to edit. These
85 * configuration vary depending on how the UART module is integrated with
90 * This option is used to set or clear the RXDMUXSEL bit in control reg 3.
91 * Certain platforms need this bit to be set in order to receive Irda data.
93 #define MXC_UART_IR_RXDMUX 0x0004
95 * This option is used to set or clear the RXDMUXSEL bit in control reg 3.
96 * Certain platforms need this bit to be set in order to receive UART data.
98 #define MXC_UART_RXDMUX 0x0004
103 #define ROM_BASE_ADDR UL(0x00000000)
104 //#define ROM_BASE_ADDR_VIRT VA(0x20000000)
106 //#define ROM_SI_REV_OFFSET 0x48
108 #define PLATFORM_BASE_ADDR ARM_ELBOW_BASE_ADDR
109 #define PLATFORM_ICGC 0x14
112 * GPU control registers
114 #define IPU_CTRL_BASE_ADDR UL(0x18000000)
115 #define GPU_2D_BASE_ADDR UL(0x20000000)
116 #define GPU_3D_BASE_ADDR UL(0x30000000)
118 #define TZIC_BASE_ADDR UL(0x0FFFC000)
120 #define DEBUG_BASE_ADDR UL(0x40000000)
121 #define DEBUG_ROM_ADDR (DEBUG_BASE_ADDR + 0x0)
122 #define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000)
123 #define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000)
124 #define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000)
125 #define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000)
126 #define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000)
127 #define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000)
128 #define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000)
129 #define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000)
132 * SPBA global module enabled #0
134 #define SPBA0_BASE_ADDR UL(0x50000000)
136 #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
137 #define ESDHC1_REG_BASE MMC_SDHC1_BASE_ADDR
138 #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
139 #define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
141 #define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
142 #define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
143 #define ESAI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000)
144 #define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
145 #define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
146 #define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000)
147 #define ASRC_BASE_ADDR (SPBA0_BASE_ADDR + 0x0002C000)
148 #define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000)
149 #define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
154 #define AIPS1_BASE_ADDR UL(0x53F00000)
155 #define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
156 #define USBOH3_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
157 #define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
158 #define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
159 #define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
160 #define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
161 #define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
162 #define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
163 #define WDOG_BASE_ADDR WDOG1_BASE_ADDR
164 #define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
165 #define GPT_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
166 #define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
167 #define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
168 #define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
169 #define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
170 #define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
171 #define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
172 #define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
173 #define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000)
175 #define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000)
176 #define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000)
177 #define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000)
178 #define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000)
179 #define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000)
180 #define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000)
181 #define PATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E8000)
182 #define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x000EC000)
184 #define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000)
189 #define AIPS2_BASE_ADDR UL(0x63F00000)
190 #define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR
191 #define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
192 #define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
193 #define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
194 #define PLL4_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000)
195 #define UART5_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000)
196 #define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
197 #define MAX_BASE_ADDR AHBMAX_BASE_ADDR
198 #define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
199 #define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
200 #define ARM_ELBOW_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000)
201 #define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
202 #define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000)
204 #define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
205 #define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
206 #define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000)
207 #define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000)
208 #define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000)
210 #define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
211 #define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
212 #define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
213 #define I2C_BASE_ADDR I2C1_BASE_ADDR
214 #define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
215 #define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
217 #define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
218 #define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000)
219 #define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000)
220 #define NFC_IP_BASE (AIPS2_BASE_ADDR + 0x000DB000)
221 #define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00)
222 #define SSI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000)
223 #define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
224 #define SOC_FEC_BASE FEC_BASE_ADDR
225 #define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000)
226 #define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000)
227 #define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000)
230 * Memory regions and CS
232 #define CSD0_BASE_ADDR UL(0x70000000)
233 #define CSD1_BASE_ADDR UL(0xB0000000)
234 #define CS0_BASE_ADDR UL(0xF0000000)
235 #define CS1_BASE_ADDR UL(0xF4000000)
240 #define NFC_BASE_ADDR_AXI UL(0xF7FF0000)
241 #define NFC_BASE NFC_BASE_ADDR_AXI
246 #define IRAM_BASE_ADDR UL(0xF8000000) /* 128K internal ram */
249 * Graphics Memory of GPU
251 #define GPU_MEM_BASE_ADDR UL(0xF8020000)
254 * Number of GPIO ports as defined in the IC Spec
256 #define GPIO_PORT_NUM 7
258 * Number of GPIO pins per port
260 #define GPIO_NUM_PIN 32
263 #define CLKCTL_CCR 0x00
264 #define CLKCTL_CCDR 0x04
265 #define CLKCTL_CSR 0x08
266 #define CLKCTL_CCSR 0x0C
267 #define CLKCTL_CACRR 0x10
268 #define CLKCTL_CBCDR 0x14
269 #define CLKCTL_CBCMR 0x18
270 #define CLKCTL_CSCMR1 0x1C
271 #define CLKCTL_CSCMR2 0x20
272 #define CLKCTL_CSCDR1 0x24
273 #define CLKCTL_CS1CDR 0x28
274 #define CLKCTL_CS2CDR 0x2C
275 #define CLKCTL_CDCDR 0x30
276 #define CLKCTL_CHSCCDR 0x34
277 #define CLKCTL_CSCDR2 0x38
278 #define CLKCTL_CSCDR3 0x3C
279 #define CLKCTL_CSCDR4 0x40
280 #define CLKCTL_CWDR 0x44
281 #define CLKCTL_CDHIPR 0x48
282 #define CLKCTL_CDCR 0x4C
283 #define CLKCTL_CTOR 0x50
284 #define CLKCTL_CLPCR 0x54
285 #define CLKCTL_CISR 0x58
286 #define CLKCTL_CIMR 0x5C
287 #define CLKCTL_CCOSR 0x60
288 #define CLKCTL_CGPR 0x64
289 #define CLKCTL_CCGR0 0x68
290 #define CLKCTL_CCGR1 0x6C
291 #define CLKCTL_CCGR2 0x70
292 #define CLKCTL_CCGR3 0x74
293 #define CLKCTL_CCGR4 0x78
294 #define CLKCTL_CCGR5 0x7C
295 #define CLKCTL_CCGR6 0x80
296 #define CLKCTL_CCGR7 0x84
297 #define CLKCTL_CMEOR 0x88
299 #define FREQ_24MHZ 24000000
300 #define FREQ_32768HZ (32768 * 1024)
301 #define FREQ_38400HZ (38400 * 1024)
302 #define FREQ_32000HZ (32000 * 1024)
303 #define PLL_REF_CLK FREQ_24MHZ
304 #define CKIH 22579200
305 //#define PLL_REF_CLK FREQ_32768HZ
306 //#define PLL_REF_CLK FREQ_32000HZ
316 #define M4IF_FBPM0 0x40
317 #define M4IF_FBPM1 0x44
318 #define M4IF_FIDBP 0x48
319 #define M4IF_MIF4 0x48
320 #define M4IF_FPWC 0x9C
323 #define ESDCTL_ESDCTL0 0x00
324 #define ESDCTL_ESDCFG0 0x04
325 #define ESDCTL_ESDCTL1 0x08
326 #define ESDCTL_ESDCFG1 0x0C
327 #define ESDCTL_ESDMISC 0x18
328 #define ESDCTL_ESDSCR 0x1c
329 #define ESDCTL_ESDMRR 0x34
330 #define ESDCTL_WLGCR 0x48
331 #define ESDCTL_RDDLHWCTL 0xa0
332 #define ESDCTL_WRDLHWCTL 0xa4
335 #define PLL_DP_CTL 0x00
336 #define PLL_DP_CONFIG 0x04
337 #define PLL_DP_OP 0x08
338 #define PLL_DP_MFD 0x0C
339 #define PLL_DP_MFN 0x10
340 #define PLL_DP_MFNMINUS 0x14
341 #define PLL_DP_MFNPLUS 0x18
342 #define PLL_DP_HFS_OP 0x1C
343 #define PLL_DP_HFS_MFD 0x20
344 #define PLL_DP_HFS_MFN 0x24
345 #define PLL_DP_TOGC 0x28
346 #define PLL_DP_DESTAT 0x2C
348 #define CHIP_REV_1_0 0x0 /* PASS 1.0 */
349 #define CHIP_REV_1_1 0x1 /* PASS 1.1 */
350 #define CHIP_REV_2_0 0x2 /* PASS 2.0 */
351 #define CHIP_LATEST CHIP_REV_1_1
353 #define IIM_STAT_OFF 0x00
354 #define IIM_STAT_BUSY (1 << 7)
355 #define IIM_STAT_PRGD (1 << 1)
356 #define IIM_STAT_SNSD (1 << 0)
357 #define IIM_STATM_OFF 0x04
358 #define IIM_ERR_OFF 0x08
359 #define IIM_ERR_PRGE (1 << 7)
360 #define IIM_ERR_WPE (1 << 6)
361 #define IIM_ERR_OPE (1 << 5)
362 #define IIM_ERR_RPE (1 << 4)
363 #define IIM_ERR_WLRE (1 << 3)
364 #define IIM_ERR_SNSE (1 << 2)
365 #define IIM_ERR_PARITYE (1 << 1)
366 #define IIM_EMASK_OFF 0x0C
367 #define IIM_FCTL_OFF 0x10
368 #define IIM_UA_OFF 0x14
369 #define IIM_LA_OFF 0x18
370 #define IIM_SDAT_OFF 0x1C
371 #define IIM_PREV_OFF 0x20
372 #define IIM_SREV_OFF 0x24
373 #define IIM_PREG_P_OFF 0x28
374 #define IIM_SCS0_OFF 0x2C
375 #define IIM_SCS1_P_OFF 0x30
376 #define IIM_SCS2_OFF 0x34
377 #define IIM_SCS3_P_OFF 0x38
379 #define IIM_PROD_REV_SH 3
380 #define IIM_PROD_REV_LEN 5
381 #define IIM_SREV_REV_SH 4
382 #define IIM_SREV_REV_LEN 4
383 #define PROD_SIGNATURE_MX53 0x1
385 #define EPIT_BASE_ADDR EPIT1_BASE_ADDR
389 #define EPITCMPR 0x0C
403 /* Assuming 24MHz input clock with doubler ON */
405 #define DP_OP_1000 ((10 << 4) + ((1 - 1) << 0))
406 #define DP_MFD_1000 (12 - 1)
407 #define DP_MFN_1000 5
409 #define DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
410 #define DP_MFD_850 (48 - 1)
411 #define DP_MFN_850 41
413 #define DP_OP_800 ((8 << 4) + ((1 - 1) << 0))
414 #define DP_MFD_800 (3 - 1)
417 #define DP_OP_700 ((7 << 4) + ((1 - 1) << 0))
418 #define DP_MFD_700 (24 - 1)
421 #define DP_OP_400 ((8 << 4) + ((2 - 1) << 0))
422 #define DP_MFD_400 (3 - 1)
425 #define DP_OP_532 ((5 << 4) + ((1 - 1) << 0))
426 #define DP_MFD_532 (24 - 1)
427 #define DP_MFN_532 13
429 #define DP_OP_665 ((6 << 4) + ((1 - 1) << 0))
430 #define DP_MFD_665 (96 - 1)
431 #define DP_MFN_665 89
433 #define DP_OP_666 ((6 << 4) + ((1 - 1) << 0))
434 #define DP_MFD_666 (16 - 1)
435 #define DP_MFN_666 15
437 #define DP_OP_333 ((6 << 4) + ((2 - 1) << 0))
438 #define DP_MFD_333 (16 - 1)
439 #define DP_MFN_333 15
441 #define DP_OP_266 ((5 << 4) + ((2 - 1) << 0))
442 #define DP_MFD_266 (24 - 1)
443 #define DP_MFN_266 13
445 #define DP_OP_216 ((9 << 4) + ((4 - 1) << 0))
446 #define DP_MFD_216 (1 - 1)
449 #define PROD_SIGNATURE_SUPPORTED PROD_SIGNATURE_MX51
451 #define CHIP_VERSION_NONE 0xFFFFFFFF // invalid product ID
452 #define CHIP_VERSION_UNKNOWN 0xDEADBEEF // invalid chip rev
454 #define PART_NUMBER_OFFSET 12
455 #define MAJOR_NUMBER_OFFSET 4
456 #define MINOR_NUMBER_OFFSET 0
458 //#define BARKER_CODE_SWAP_LOC 0x404
459 #define BARKER_CODE_VAL 0xB1
462 // This defines the register base for the NAND AXI registers
463 #define NAND_REG_BASE (NFC_BASE_ADDR_AXI + 0x1E00)
465 #define NAND_CMD_REG (NAND_REG_BASE + 0x00)
466 #define NAND_ADD0_REG (NAND_REG_BASE + 0x04)
467 #define NAND_ADD1_REG (NAND_REG_BASE + 0x08)
468 #define NAND_ADD2_REG (NAND_REG_BASE + 0x0C)
469 #define NAND_ADD3_REG (NAND_REG_BASE + 0x10)
470 #define NAND_ADD4_REG (NAND_REG_BASE + 0x14)
471 #define NAND_ADD5_REG (NAND_REG_BASE + 0x18)
472 #define NAND_ADD6_REG (NAND_REG_BASE + 0x1C)
473 #define NAND_ADD7_REG (NAND_REG_BASE + 0x20)
474 #define NAND_ADD8_REG (NAND_REG_BASE + 0x24)
475 #define NAND_ADD9_REG (NAND_REG_BASE + 0x28)
476 #define NAND_ADD10_REG (NAND_REG_BASE + 0x2C)
477 #define NAND_ADD11_REG (NAND_REG_BASE + 0x30)
479 #define NAND_CONFIGURATION1_REG (NAND_REG_BASE + 0x34)
480 #define NAND_CONFIGURATION1_NFC_RST (1 << 2)
481 #define NAND_CONFIGURATION1_NF_CE (1 << 1)
482 #define NAND_CONFIGURATION1_SP_EN (1 << 0)
484 #define NAND_ECC_STATUS_RESULT_REG (NAND_REG_BASE + 0x38)
486 #define NAND_STATUS_SUM_REG (NAND_REG_BASE + 0x3C)
488 #define NAND_LAUNCH_REG (NAND_REG_BASE + 0x40)
489 #define NAND_LAUNCH_FCMD (1 << 0)
490 #define NAND_LAUNCH_FADD (1 << 1)
491 #define NAND_LAUNCH_FDI (1 << 2)
492 #define NAND_LAUNCH_AUTO_PROG (1 << 6)
493 #define NAND_LAUNCH_AUTO_READ (1 << 7)
494 #define NAND_LAUNCH_AUTO_READ_CONT (1 << 8)
495 #define NAND_LAUNCH_AUTO_ERASE (1 << 9)
496 #define NAND_LAUNCH_COPY_BACK0 (1 << 10)
497 #define NAND_LAUNCH_COPY_BACK1 (1 << 11)
498 #define NAND_LAUNCH_AUTO_STAT (1 << 12)
500 #define NFC_WR_PROT_REG (NFC_IP_BASE + 0x00)
501 #define UNLOCK_BLK_ADD0_REG (NFC_IP_BASE + 0x04)
502 #define UNLOCK_BLK_ADD1_REG (NFC_IP_BASE + 0x08)
503 #define UNLOCK_BLK_ADD2_REG (NFC_IP_BASE + 0x0C)
504 #define UNLOCK_BLK_ADD3_REG (NFC_IP_BASE + 0x10)
505 #define UNLOCK_BLK_ADD4_REG (NFC_IP_BASE + 0x14)
506 #define UNLOCK_BLK_ADD5_REG (NFC_IP_BASE + 0x18)
507 #define UNLOCK_BLK_ADD6_REG (NFC_IP_BASE + 0x1C)
508 #define UNLOCK_BLK_ADD7_REG (NFC_IP_BASE + 0x20)
510 #define NFC_FLASH_CONFIG2_REG (NFC_IP_BASE + 0x24)
511 #define NFC_FLASH_CONFIG2_ECC_EN (1 << 3)
513 #define NFC_FLASH_CONFIG3_REG (NFC_IP_BASE + 0x28)
515 #define NFC_IPC_REG (NFC_IP_BASE + 0x2C)
516 #define NFC_IPC_INT (1 << 31)
517 #define NFC_IPC_AUTO_DONE (1 << 30)
518 #define NFC_IPC_LPS (1 << 29)
519 #define NFC_IPC_RB_B (1 << 28)
520 #define NFC_IPC_CACK (1 << 1)
521 #define NFC_IPC_CREQ (1 << 0)
522 #define NFC_AXI_ERR_ADD_REG (NFC_IP_BASE + 0x30)
524 #define MXC_MMC_BASE_DUMMY 0x00000000
526 #define NAND_FLASH_BOOT (1 << 28)
527 #define FROM_NAND_FLASH NAND_FLASH_BOOT
529 #define SDRAM_NON_FLASH_BOOT (1 << 29)
531 #define MMC_FLASH_BOOT (1 << 30)
532 #define FROM_MMC_FLASH MMC_FLASH_BOOT
534 #define SPI_NOR_FLASH_BOOT 0x80000000
535 #define FROM_SPI_NOR_FLASH SPI_NOR_FLASH_BOOT
537 #define IS_BOOTING_FROM_NAND() 1
538 #define IS_BOOTING_FROM_SPI_NOR() 0
539 #define IS_BOOTING_FROM_NOR() 0
540 #define IS_BOOTING_FROM_SDRAM() 0
541 #define IS_BOOTING_FROM_MMC() 0
543 #define IS_FIS_FROM_NAND() 1
544 #define IS_FIS_FROM_NOR() 0
546 #define SOC_MAC_ADDR_FUSE_BANK 1
547 #define SOC_MAC_ADDR_FUSE 9
548 #define SOC_MAC_ADDR_LOCK_FUSE 0
549 #define SOC_MAC_ADDR_LOCK_BIT 4
552 * This macro is used to get certain bit field from a number
554 #define MXC_GET_FIELD(val, len, sh) ((val >> sh) & ((1 << len) - 1))
557 * This macro is used to set certain bit field inside a number
559 #define MXC_SET_FIELD(val, len, sh, nval) ((val & ~(((1 << len) - 1) << sh)) | (nval << sh))
562 #define UART_WIDTH_32 /* internal UART is 32bit access only */
564 #if !defined(__ASSEMBLER__)
565 extern void fuse_blow_row(int bank, int row, int value);
566 extern unsigned int sense_fuse(int bank, int row, int bit);
568 void cyg_hal_plf_serial_init(void);
569 void cyg_hal_plf_serial_stop(void);
570 void hal_delay_us(unsigned int usecs);
571 #define HAL_DELAY_US(n) hal_delay_us(n)
573 extern unsigned int system_rev;
604 SPI1_CLK = CSPI1_BASE_ADDR,
605 SPI2_CLK = CSPI2_BASE_ADDR,
608 extern unsigned int pll_clock(enum plls pll);
610 extern unsigned int get_main_clock(enum main_clocks clk);
612 extern unsigned int get_peri_clock(enum peri_clocks clk);
614 typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int, unsigned int);
616 #endif //#if !defined(__ASSEMBLER__)
618 #endif /* __HAL_SOC_H__ */