1 //==========================================================================
5 // HAL misc board support code
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
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38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //========================================================================*/
43 #include <pkgconf/hal.h>
44 #include <pkgconf/system.h>
45 #include CYGBLD_HAL_PLATFORM_H
47 #include <cyg/infra/cyg_type.h> // base types
48 #include <cyg/infra/cyg_trac.h> // tracing macros
49 #include <cyg/infra/cyg_ass.h> // assertion macros
51 #include <cyg/hal/hal_io.h> // IO macros
52 #include <cyg/hal/hal_arch.h> // Register state info
53 #include <cyg/hal/hal_diag.h>
54 #include <cyg/hal/hal_intr.h> // Interrupt names
55 #include <cyg/hal/hal_cache.h>
56 #include <cyg/hal/hal_soc.h> // Hardware definitions
57 #include <cyg/hal/fsl_board.h> // Platform specifics
59 #include <cyg/infra/diag.h> // diag_printf
61 // All the MM table layout is here:
62 #include <cyg/hal/hal_mm.h>
64 extern unsigned int pmic_reg(unsigned int reg, unsigned int val, unsigned int write);
65 externC void* memset(void *, int, size_t);
67 void hal_mmu_init(void)
69 unsigned long ttb_base = RAM_BANK0_BASE + 0x4000;
73 * Set the TTB register
75 asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
78 * Set the Domain Access Control Register
80 i = ARM_ACCESS_DACR_DEFAULT;
81 asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
84 * First clear all TT entries - ie Set them to Faulting
86 memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
88 /* Actual Virtual Size Attributes Function */
89 /* Base Base MB cached? buffered? access permissions */
90 /* xxx00000 xxx00000 */
91 X_ARM_MMU_SECTION(0x000, 0xF00, 0x1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* ROM */
92 X_ARM_MMU_SECTION(0x300, 0x300, 0x1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* L2CC */
93 X_ARM_MMU_SECTION(0x43F, 0x43F, 0x3C1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Internal Regsisters upto SDRAM*/
94 X_ARM_MMU_SECTION(0x900, 0x000, 0x40, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
95 X_ARM_MMU_SECTION(0x900, 0x900, 0x40, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
96 X_ARM_MMU_SECTION(0xA00, 0xA00, 0x40, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Flash */
97 X_ARM_MMU_SECTION(0xB00, 0xB00, 0x10, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* External I/O */
98 X_ARM_MMU_SECTION(0xB40, 0xB40, 0x10, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* External I/O */
99 X_ARM_MMU_SECTION(0xB60, 0xB60, 0x10, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* External I/O */
100 X_ARM_MMU_SECTION(0xB80, 0xB80, 0x80, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* EIM control*/
104 // Platform specific initialization
107 void plf_hardware_init(void)
111 // For x16 bit 2K page
112 v = readl(SRC_BASE_ADDR + SRC_SSCR);
114 writel(v, SRC_BASE_ADDR + SRC_SSCR);
117 writel(NFC_IPC_CREQ, NFC_IPC_REG);
121 // Why does this cause the system hang? !!!!
122 while ((readl(NFC_IPC_REG) & NFC_IPC_CACK) != 0) {
127 v = readl(NFC_FLASH_CONFIG2_REG);
128 v = (v & ~0xFBF) | NFC_FLASH_CONFIG2_EDC2 | NFC_FLASH_CONFIG2_PPB_64 |
129 NFC_FLASH_CONFIG2_ECC_EN | NFC_FLASH_CONFIG2_SYM |
130 NFC_FLASH_CONFIG2_DLP_DISABLE;
131 writel(v, NFC_FLASH_CONFIG2_REG);
133 writel(0xFFFF0000, UNLOCK_BLK_ADD0_REG);
134 writel(0xFFFF0000, UNLOCK_BLK_ADD1_REG);
135 writel(0xFFFF0000, UNLOCK_BLK_ADD2_REG);
136 writel(0xFFFF0000, UNLOCK_BLK_ADD3_REG);
138 v = readl(NFC_WR_PROT_REG);
139 v = (v & ~0x00330007) | NFC_WR_PROTECT_CS0 | NFC_WR_PROTECT_BLS_UNLOCK |
141 writel(v, NFC_WR_PROT_REG);
143 writel(0, NFC_IPC_REG);
146 static void board_raise_voltage(void)
148 /* Increase core voltages */
149 pmic_reg(24, 0x00E38E, 1);
150 pmic_reg(25, 0x00018E, 1);
151 pmic_reg(26, 0x024928, 1);
154 RedBoot_init(board_raise_voltage, RedBoot_INIT_PRIO(101));
156 #include CYGHWR_MEMORY_LAYOUT_H
158 typedef void code_fun(void);
160 void board_program_new_stack(void *func)
162 register CYG_ADDRESS stack_ptr asm("sp");
163 register CYG_ADDRESS old_stack asm("r4");
164 register code_fun *new_func asm("r0");
165 old_stack = stack_ptr;
166 stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS);
167 new_func = (code_fun*)func;
169 stack_ptr = old_stack;
172 // ------------------------------------------------------------------------