packages/hal/arm/sa11x0/sa1100mm/v2_0/include/hal_platform_setup.h

   1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
   2 #define CYGONCE_HAL_PLATFORM_SETUP_H
   3
   4 /*=============================================================================
   5 //
   6 //      hal_platform_setup.h
   7 //
   8 //      Platform specific support for HAL (assembly code)
   9 //
  10 //=============================================================================
  11 //####ECOSGPLCOPYRIGHTBEGIN####
  12 // -------------------------------------------
  13 // This file is part of eCos, the Embedded Configurable Operating System.
  14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  15 //
  16 // eCos is free software; you can redistribute it and/or modify it under
  17 // the terms of the GNU General Public License as published by the Free
  18 // Software Foundation; either version 2 or (at your option) any later version.
  19 //
  20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  22 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  23 // for more details.
  24 //
  25 // You should have received a copy of the GNU General Public License along
  26 // with eCos; if not, write to the Free Software Foundation, Inc.,
  27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  28 //
  29 // As a special exception, if other files instantiate templates or use macros
  30 // or inline functions from this file, or you compile this file and link it
  31 // with other works to produce a work based on this file, this file does not
  32 // by itself cause the resulting work to be covered by the GNU General Public
  33 // License. However the source code for this file must still be made available
  34 // in accordance with section (3) of the GNU General Public License.
  35 //
  36 // This exception does not invalidate any other reasons why a work based on
  37 // this file might be covered by the GNU General Public License.
  38 //
  39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  40 // at http://sources.redhat.com/ecos/ecos-license/
  41 // -------------------------------------------
  42 //####ECOSGPLCOPYRIGHTEND####
  43 //=============================================================================
  44 //#####DESCRIPTIONBEGIN####
  45 //
  46 // Author(s):    gthomas
  47 // Contributors: gthomas, dmoseley
  48 //               Travis C. Furrer <furrer@mit.edu>
  49 // Date:         2000-05-08
  50 // Purpose:      Intel SA1100 Multimedia platform specific support routines
  51 // Description:
  52 // Usage:        #include <cyg/hal/hal_platform_setup.h>
  53 //     This file should only be used by "vectors.S"
  54 //
  55 //####DESCRIPTIONEND####
  56 //
  57 //===========================================================================*/
  58
  59 #include <pkgconf/system.h>             // System-wide configuration info
  60 #include CYGBLD_HAL_PLATFORM_H          // Platform specific configuration
  61 #include <cyg/hal/hal_sa11x0.h>         // Platform specific hardware definitions
  62 #include <cyg/hal/hal_mmu.h>            // MMU definitions
  63
  64 #if defined(CYG_HAL_STARTUP_ROM)
  65 #define PLATFORM_SETUP1 _platform_setup1
  66 #define CYGHWR_HAL_ARM_HAS_MMU
  67
  68 #if (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 59000)
  69 #define SA11X0_PLL_CLOCK 0x0
  70 #elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 73700)
  71 #define SA11X0_PLL_CLOCK 0x1
  72 #elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 88500)
  73 #define SA11X0_PLL_CLOCK 0x2
  74 #elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 103200)
  75 #define SA11X0_PLL_CLOCK 0x3
  76 #elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 118000)
  77 #define SA11X0_PLL_CLOCK 0x4
  78 #elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 132700)
  79 #define SA11X0_PLL_CLOCK 0x5
  80 #elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 147500)
  81 #define SA11X0_PLL_CLOCK 0x6
  82 #elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 162200)
  83 #define SA11X0_PLL_CLOCK 0x7
  84 #elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 176900)
  85 #define SA11X0_PLL_CLOCK 0x8
  86 #elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 191700)
  87 #define SA11X0_PLL_CLOCK 0x9
  88 #elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 206400)
  89 #define SA11X0_PLL_CLOCK 0xA
  90 #elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 221200)
  91 #define SA11X0_PLL_CLOCK 0xB
  92 #else
  93 #error Invalid processor clock speed
  94 #endif
  95
  96 // This function is called very early on by the boot ROM (or by any ROM
  97 // based startup).  It's job is to initialize the hardware to a known state
  98 // so that eCos applications can execute properly.
  99
 100 // This version of the code is patterned after the contribution from
 101 // Travis Furer (@MIT)
 102
 103
 104 // Define macro used to diddle the LEDs during early initialization.
 105 // Can use r0+r1.  Argument in \x.
 106
 107 #define CYGHWR_LED_MACRO _set_LEDS \x
 108
 109 // Initialize GPIOs
 110 #define GPIO_GRER (SA11X0_GPIO_RISING_EDGE_DETECT-SA11X0_GPIO_PIN_LEVEL)
 111 #define GPIO_GFER (SA11X0_GPIO_FALLING_EDGE_DETECT-SA11X0_GPIO_PIN_LEVEL)
 112 #define GPIO_GAFR (SA11X0_GPIO_ALTERNATE_FUNCTION-SA11X0_GPIO_PIN_LEVEL)
 113 #define GPIO_GEDR (SA11X0_GPIO_EDGE_DETECT_STATUS-SA11X0_GPIO_PIN_LEVEL)
 114 #define GPIO_GPDR (SA11X0_GPIO_PIN_DIRECTION-SA11X0_GPIO_PIN_LEVEL)
 115 #define GPIO_GPCR (SA11X0_GPIO_PIN_OUTPUT_CLEAR-SA11X0_GPIO_PIN_LEVEL)
 116         .macro  _init_GPIO
 117         ldr     r1,=SA11X0_GPIO_PIN_LEVEL
 118         mov     r0,#0
 119         str     r0,[r1,#GPIO_GRER]      // Disable rising edge detects
 120         str     r0,[r1,#GPIO_GFER]      // Disable falling edge detects
 121         str     r0,[r1,#GPIO_GAFR]      // No alt. funcs. during init
 122         sub     r0,r0,#1
 123         str     r0,[r1,#GPIO_GPCR]      // Force all outputs to low
 124         str     r0,[r1,#GPIO_GEDR]      // Clear edge detect status
 125         ldr     r0,=0x00100300
 126         str     r0,[r1,#GPIO_GPDR]      // Only LEDs outputs (for now)
 127         .endm
 128
 129 #define DISCRETE_LED_REG_BASE     0x18800000
 130 #define KEYPAD_IO_O               0x4
 131 #define DISCRETE_LED_O            0x6
 132 #define HEX_LED_REG_BASE          0x18c00000
 133 #define HEX_LED_O                 0x0
 134 #define HEX_DATA_MASK             0x0F
 135 #define HEX_LED_0_STROBE          0x10
 136 #define HEX_LED_1_STROBE          0x20
 137 #define HEX_LED_BOTH_STROBES      (HEX_LED_0_STROBE | HEX_LED_1_STROBE)
 138
 139 // Display value on hex LED display
 140         .macro  _set_LEDS,val
 141         ldr     r1, =HEX_LED_REG_BASE
 142
 143         ldr     r2, =\val
 144         and     r2, r2, #0xf
 145         orr     r0, r2, #HEX_LED_0_STROBE
 146         str     r0, [r1, #HEX_LED_O]
 147
 148         ldr     r2, =\val
 149         mov     r2, r2, LSR #4
 150         orr     r0, r2, #HEX_LED_1_STROBE
 151         str     r0, [r1, #HEX_LED_O]
 152
 153         nop
 154         .endm
 155
 156 // Initialize HEX display.
 157         .macro  _init_HEX_DISPLAY
 158         ldr     r1, =DISCRETE_LED_REG_BASE
 159         ldr     r2, =~0
 160         str     r2, [r1, #KEYPAD_IO_O]
 161         str     r2, [r1, #DISCRETE_LED_O]
 162         _set_LEDS 0x23
 163         .endm
 164
 165 // Setup pin directions:
 166 //  inputs: all serial receive pins
 167 // outputs: all LCD pins, all serial transmit pins
 168         .macro  _init_PERIPHERAL_PINS
 169         ldr     r0,=0x00355FFF
 170         ldr     r1,=SA11X0_PPC_PIN_DIRECTION
 171         str     r0,[r1]
 172         mov     r0,#0                           // Force initial state
 173         ldr     r1,=SA11X0_PPC_PIN_STATE
 174         str     r0,[r1]
 175         ldr     r1,=SA11X0_PPC_PIN_ASSIGNMENT   // Disable any reassignments
 176         str     r0,[r1]
 177         .endm
 178
 179 // Set core frequency (this can take up to 150us)
 180         .macro  _set_CLOCK_FREQUENCY
 181         mov     r0,#SA11X0_PLL_CLOCK
 182         ldr     r1,=SA11X0_PWR_MGR_PLL_CONFIG
 183         str     r0,[r1]
 184         .endm
 185
 186 // Enable clock switching (must be done after setting core frequency)
 187         .macro  _enable_CLOCK_SWITCHING
 188         mcr     p15,0,r1,c15,c1,2
 189         .endm
 190
 191 // Initialize memory interfaces. (ROM, SRAM, Flash, DRAM, etc)
 192 //
 193 // SA1100 Multimedia memory is as follows:
 194 //   ROM     128K (assuming 32 bit accesses)
 195 //   Flash   4M (assuming 32 bit accesses)
 196 //   RAM     8M
 197 //
 198 // From SA11X0 Manual, Section 10.7.1:
 199 //
 200 //  The following flow should be followed when coming out of
 201 //  reset, whether for sleep or power-up:
 202 //
 203 //    - Read boot ROM and write to memory configuration
 204 //      registers, but do not enable DRAM banks.
 205 //
 206 //    - If necessary, finish any DRAM power-up wait period
 207 //      (usually about 100us).
 208 //
 209 //    - If coming out of sleep, see Section 9.5, Power
 210 //      Manager on page 9-26 on how to release the nCAS and
 211 //      nRAS pins from their self-refresh state.
 212 //
 213 //    - If coming out of sleep, wait the DRAM-specific
 214 //      post-self-refresh precharge period before issuing
 215 //      a new DRAM transaction.
 216 //
 217 //    - If power-on reset, perform the number of
 218 //      initialization refreshes required by the specific
 219 //      DRAM part by reading disabled banks. A read from
 220 //      any disabled bank will refresh all four banks.
 221 //
 222 //    - Enable DRAM banks by setting MDCNFG:DE3:0.
 223 //
 224 #define DRAM_CONFIG_VALUE      (SA11X0_DRAM_REFRESH_INTERVAL(312)              | \
 225                                 SA11X0_DATA_INPUT_LATCH_CAS_PLUS_THREE         | \
 226                                 SA11X0_DRAM_CAS_BEFORE_RAS(5)                  | \
 227                                 SA11X0_DRAM_RAS_PRECHARGE(4)                   | \
 228                                 SA11X0_DRAM_CLOCK_CPU_CLOCK                    | \
 229                                 SA11X0_DRAM_ROW_ADDRESS_BITS_11                | \
 230                                 SA11X0_DRAM_BANK_0_ENABLED                     | \
 231                                 SA11X0_DRAM_BANK_1_DISABLED                    | \
 232                                 SA11X0_DRAM_BANK_2_DISABLED                    | \
 233                                 SA11X0_DRAM_BANK_3_DISABLED)
 234
 235 #define DRAM_CAS0_WAVEFORM     0xF0F0F00F
 236 #define DRAM_CAS1_WAVEFORM     0XF0F0F0F0
 237 #define DRAM_CAS2_WAVEFORM     0xFFFFFFF0
 238
 239 #define BANK_0_CONTROL_VALUE   SA11X0_STATIC_ROM_TYPE_FLASH                    | \
 240                                SA11X0_STATIC_ROM_BUS_WIDTH_16_BITS             | \
 241                                SA11X0_STATIC_ROM_DELAY_FIRST_ACCESS(0x1F)      | \
 242                                SA11X0_STATIC_ROM_DELAY_NEXT_ACCESS(0x1F)       | \
 243                                SA11X0_STATIC_ROM_RECOVERY(0x7)
 244 #define BANK_1_CONTROL_VALUE   SA11X0_STATIC_ROM_TYPE_FLASH                    | \
 245                                SA11X0_STATIC_ROM_BUS_WIDTH_32_BITS             | \
 246                                SA11X0_STATIC_ROM_DELAY_FIRST_ACCESS(0x1F)      | \
 247                                SA11X0_STATIC_ROM_DELAY_NEXT_ACCESS(0x1F)       | \
 248                                SA11X0_STATIC_ROM_RECOVERY(0x7)
 249 #define STATIC_CONTROL_0_VALUE (SA11X0_STATIC_ROM_BANK_0(BANK_0_CONTROL_VALUE) | \
 250                                 SA11X0_STATIC_ROM_BANK_1(BANK_1_CONTROL_VALUE))
 251
 252 #define BANK_2_CONTROL_VALUE   SA11X0_STATIC_ROM_TYPE_FLASH                    | \
 253                                SA11X0_STATIC_ROM_BUS_WIDTH_16_BITS             | \
 254                                SA11X0_STATIC_ROM_DELAY_FIRST_ACCESS(0x1F)      | \
 255                                SA11X0_STATIC_ROM_DELAY_NEXT_ACCESS(0x1F)       | \
 256                                SA11X0_STATIC_ROM_RECOVERY(0x7)
 257 #define BANK_3_CONTROL_VALUE   SA11X0_STATIC_ROM_TYPE_FLASH                    | \
 258                                SA11X0_STATIC_ROM_BUS_WIDTH_32_BITS             | \
 259                                SA11X0_STATIC_ROM_DELAY_FIRST_ACCESS(0x1F)      | \
 260                                SA11X0_STATIC_ROM_DELAY_NEXT_ACCESS(0x1F)       | \
 261                                SA11X0_STATIC_ROM_RECOVERY(0x7)
 262 #define STATIC_CONTROL_1_VALUE (SA11X0_STATIC_ROM_BANK_2(BANK_2_CONTROL_VALUE) | \
 263                                 SA11X0_STATIC_ROM_BANK_3(BANK_3_CONTROL_VALUE))
 264
 265         .macro  _init_MEM_INTERFACES
 266         /*
 267          * Initialize the DRAM Controller
 268          */
 269         ldr     r0, =SA11X0_DRAM_CONFIGURATION
 270         ldr     r1, =DRAM_CONFIG_VALUE
 271         str     r1, [r0]
 272
 273         ldr     r0, =SA11X0_DRAM0_CAS_0
 274         ldr     r1, =DRAM_CAS0_WAVEFORM
 275         str     r1, [r0]
 276
 277         ldr     r0, =SA11X0_DRAM0_CAS_1
 278         ldr     r1, =DRAM_CAS1_WAVEFORM
 279         str     r1, [r0]
 280
 281         ldr     r0, =SA11X0_DRAM0_CAS_2
 282         ldr     r1, =DRAM_CAS2_WAVEFORM
 283         str     r1, [r0]
 284
 285         ldr     r0, =SA11X0_STATIC_CONTROL_0
 286
 287         /*
 288          * Get the reset ROM setup
 289          */
 290         ldr     r1, [r0]
 291
 292         /*
 293          * Get the 16/32 bit setting to merge into the appropriate
 294          * register values later on.
 295          */
 296         and     r1, r1, #SA11X0_STATIC_ROM_BUS_WIDTH_MASK
 297
 298         /*
 299          * MSC0 - bank 0 ROM, bank 1 FLASH
 300          */
 301         ldr     r2, =STATIC_CONTROL_0_VALUE
 302         orr     r1, r1, r2
 303
 304         str     r1, [r0]
 305
 306         /*
 307          * MSC1 - bank 2 SRAM, bank 3 REG
 308          */
 309         ldr     r0, =SA11X0_STATIC_CONTROL_1
 310         ldr     r1, =STATIC_CONTROL_1_VALUE
 311         str     r1, [r0]
 312
 313         /*
 314          * Delay to let the DRAM warm up
 315          */
 316         ldr     r0, =0x200
 317 0:      subs    r0, r0, #1
 318         bne     0b
 319
 320         .endm
 321
 322
 323         .macro  _platform_setup1
 324         nop
 325         nop
 326         nop
 327         nop
 328         nop
 329         nop
 330         nop
 331         nop
 332         nop
 333
 334         _init_GPIO
 335         _init_HEX_DISPLAY               /* this is flaky sometimes */
 336         _init_HEX_DISPLAY               /* so do it twice just in case */
 337
 338         _set_LEDS 0x15
 339
 340         _init_PERIPHERAL_PINS
 341         _set_LEDS 0x13
 342
 343         _set_CLOCK_FREQUENCY
 344         _enable_CLOCK_SWITCHING
 345         _set_LEDS 0x12
 346
 347         _init_MEM_INTERFACES
 348         _set_LEDS 0x11
 349
 350         // Set up a stack [for calling C code]
 351         ldr     r1,=__startup_stack
 352         ldr     r2,=SA11X0_RAM_BANK0_BASE
 353         orr     sp,r1,r2
 354
 355         // Create MMU tables
 356         bl      hal_mmu_init
 357
 358         _set_LEDS 0x09
 359         // Enable MMU
 360         ldr     r2,=10f
 361         ldr     r1,=MMU_Control_Init|MMU_Control_M
 362         mcr     MMU_CP,0,r1,MMU_Control,c0
 363         mov     pc,r2    /* Change address spaces */
 364
 365         nop
 366         nop
 367         nop
 368 10:
 369         _set_LEDS 0x08
 370
 371         .endm
 372
 373 #else // STARTUP_ROM
 374 #define PLATFORM_SETUP1
 375 #endif
 376
 377 /*---------------------------------------------------------------------------*/
 378 /* end of hal_platform_setup.h                                               */
 379 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */