1 /*=============================================================================
5 // Verde I/O Coprocessor support (register layout, etc)
7 //=============================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
15 // Software Foundation; either version 2 or (at your option) any later version.
17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 // You should have received a copy of the GNU General Public License along
23 // with eCos; if not, write to the Free Software Foundation, Inc.,
24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 // As a special exception, if other files instantiate templates or use macros
27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
29 // by itself cause the resulting work to be covered by the GNU General Public
30 // License. However the source code for this file must still be made available
31 // in accordance with section (3) of the GNU General Public License.
33 // This exception does not invalidate any other reasons why a work based on
34 // this file might be covered by the GNU General Public License.
36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37 // at http://sources.redhat.com/ecos/ecos-license/
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //=============================================================================
41 //#####DESCRIPTIONBEGIN####
44 // Contributors: msalter
47 // Description: Verde I/O Processor support.
48 // Usage: #include <cyg/hal/hal_verde.h>
50 //####DESCRIPTIONEND####
52 //===========================================================================*/
53 #ifndef CYGONCE_HAL_ARM_XSCALE_HAL_VERDE_H
54 #define CYGONCE_HAL_ARM_XSCALE_HAL_VERDE_H
56 #include <pkgconf/system.h>
57 #include <cyg/hal/hal_xscale.h>
60 // --------------------------------------------------------------------------
61 // Address Translation Unit (Chapter 3)
62 #define ATU_ATUVID REG16(0,0xffffe100)
63 #define ATU_ATUDID REG16(0,0xffffe102)
64 #define ATU_ATUCMD REG16(0,0xffffe104)
65 #define ATU_ATUSR REG16(0,0xffffe106)
66 #define ATU_ATURID REG8(0,0xffffe108)
67 #define ATU_ATUCCR REG8(0,0xffffe109)
68 #define ATU_ATUCLSR REG8(0,0xffffe10c)
69 #define ATU_ATULT REG8(0,0xffffe10d)
70 #define ATU_ATUHTR REG8(0,0xffffe10e)
71 #define ATU_ATUBIST REG8(0,0xffffe10f)
72 #define ATU_IABAR0 REG32(0,0xffffe110)
73 #define ATU_IAUBAR0 REG32(0,0xffffe114)
74 #define ATU_IABAR1 REG32(0,0xffffe118)
75 #define ATU_IAUBAR1 REG32(0,0xffffe11c)
76 #define ATU_IABAR2 REG32(0,0xffffe120)
77 #define ATU_IAUBAR2 REG32(0,0xffffe124)
78 #define ATU_ASVIR REG16(0,0xffffe12c)
79 #define ATU_ASIR REG16(0,0xffffe12e)
80 #define ATU_ERBAR REG32(0,0xffffe130)
81 #define ATU_ATUILR REG8(0,0xffffe13c)
82 #define ATU_ATUIPR REG8(0,0xffffe13d)
83 #define ATU_ATUMGNT REG8(0,0xffffe13e)
84 #define ATU_ATUMLAT REG8(0,0xffffe13f)
85 #define ATU_IALR0 REG32(0,0xffffe140)
86 #define ATU_IATVR0 REG32(0,0xffffe144)
87 #define ATU_ERLR REG32(0,0xffffe148)
88 #define ATU_ERTVR REG32(0,0xffffe14c)
89 #define ATU_IALR1 REG32(0,0xffffe150)
90 #define ATU_IALR2 REG32(0,0xffffe154)
91 #define ATU_IATVR2 REG32(0,0xffffe158)
92 #define ATU_OIOWTVR REG32(0,0xffffe15c)
93 #define ATU_OMWTVR0 REG32(0,0xffffe160)
94 #define ATU_OUMWTVR0 REG32(0,0xffffe164)
95 #define ATU_OMWTVR1 REG32(0,0xffffe168)
96 #define ATU_OUMWTVR1 REG32(0,0xffffe16c)
97 #define ATU_OUDWTVR REG32(0,0xffffe178)
98 #define ATU_ATUCR REG32(0,0xffffe180)
99 #define ATU_PCSR REG32(0,0xffffe184)
100 #define ATU_ATUISR REG32(0,0xffffe188)
101 #define ATU_ATUIMR REG32(0,0xffffe18c)
102 #define ATU_IABAR3 REG32(0,0xffffe190)
103 #define ATU_IAUBAR3 REG32(0,0xffffe194)
104 #define ATU_IALR3 REG32(0,0xffffe198)
105 #define ATU_IATVR3 REG32(0,0xffffe19c)
106 #define ATU_OCCAR REG32(0,0xffffe1a4)
107 #define ATU_OCCDR REG32(0,0xffffe1ac)
108 #define ATU_PDSCR REG32(0,0xffffe1bc)
109 #define ATU_PMCAPID REG8(0,0xffffe1c0)
110 #define ATU_PMNEXT REG8(0,0xffffe1c1)
111 #define ATU_APMCR REG16(0,0xffffe1c2)
112 #define ATU_APMCSR REG16(0,0xffffe1c4)
113 #define ATU_PCIXCAPID REG8(0,0xffffe1e0)
114 #define ATU_PCIXNEXT REG8(0,0xffffe1e1)
115 #define ATU_PCIXCMD REG16(0,0xffffe1e2)
116 #define ATU_PCIXSR REG32(0,0xffffe1e4)
118 #define PCSR_RESET_I_BUS 0x20
119 #define PCSR_RESET_P_BUS 0x10
120 #define PCSR_CFG_RETRY 0x04
123 // --------------------------------------------------------------------------
124 // Application Accelerator Unit (Chapter 6)
125 #define AAU_ACR REG32(0,0xffffe800)
126 #define AAU_ASR REG32(0,0xffffe804)
127 #define AAU_ADAR REG32(0,0xffffe808)
128 #define AAU_ANDAR REG32(0,0xffffe80c)
129 #define AAU_SAR1 REG32(0,0xffffe810)
130 #define AAU_SAR2 REG32(0,0xffffe814)
131 #define AAU_SAR3 REG32(0,0xffffe818)
132 #define AAU_SAR4 REG32(0,0xffffe81c)
133 #define AAU_DAR REG32(0,0xffffe820)
134 #define AAU_ABCR REG32(0,0xffffe824)
135 #define AAU_ADCR REG32(0,0xffffe828)
136 #define AAU_SAR5 REG32(0,0xffffe82c)
137 #define AAU_SAR6 REG32(0,0xffffe830)
138 #define AAU_SAR7 REG32(0,0xffffe834)
139 #define AAU_SAR8 REG32(0,0xffffe838)
140 #define AAU_EDCR0 REG32(0,0xffffe83c)
141 #define AAU_SAR9 REG32(0,0xffffe840)
142 #define AAU_SAR10 REG32(0,0xffffe844)
143 #define AAU_SAR11 REG32(0,0xffffe848)
144 #define AAU_SAR12 REG32(0,0xffffe84c)
145 #define AAU_SAR13 REG32(0,0xffffe850)
146 #define AAU_SAR14 REG32(0,0xffffe854)
147 #define AAU_SAR15 REG32(0,0xffffe858)
148 #define AAU_SAR16 REG32(0,0xffffe85c)
149 #define AAU_EDCR1 REG32(0,0xffffe860)
150 #define AAU_SAR17 REG32(0,0xffffe864)
151 #define AAU_SAR18 REG32(0,0xffffe868)
152 #define AAU_SAR19 REG32(0,0xffffe86c)
153 #define AAU_SAR20 REG32(0,0xffffe870)
154 #define AAU_SAR21 REG32(0,0xffffe874)
155 #define AAU_SAR22 REG32(0,0xffffe878)
156 #define AAU_SAR23 REG32(0,0xffffe87c)
157 #define AAU_SAR24 REG32(0,0xffffe880)
158 #define AAU_EDCR2 REG32(0,0xffffe884)
159 #define AAU_SAR25 REG32(0,0xffffe888)
160 #define AAU_SAR26 REG32(0,0xffffe88c)
161 #define AAU_SAR27 REG32(0,0xffffe890)
162 #define AAU_SAR28 REG32(0,0xffffe894)
163 #define AAU_SAR29 REG32(0,0xffffe898)
164 #define AAU_SAR30 REG32(0,0xffffe89c)
165 #define AAU_SAR31 REG32(0,0xffffe8a0)
166 #define AAU_SAR32 REG32(0,0xffffe8a4)
167 #define AAU_RES0 REG32(0,0xffffe8a8)
168 #define AAU_RES1 REG32(0,0xffffe900)
169 #define AAU_RES2 REG32(0,0xfffff000)
174 #define ASR_ACTIVE 0x400
177 // --------------------------------------------------------------------------
178 // Memory Controller (Chapter 7)
179 #define MCU_SDIR REG32(0,0xffffe500)
180 #define MCU_SDCR REG32(0,0xffffe504)
181 #define MCU_SDBR REG32(0,0xffffe508)
182 #define MCU_SBR0 REG32(0,0xffffe50c)
183 #define MCU_SBR1 REG32(0,0xffffe510)
184 #define MCU_ECCR REG32(0,0xffffe534)
185 #define MCU_ELOG0 REG32(0,0xffffe538)
186 #define MCU_ELOG1 REG32(0,0xffffe53c)
187 #define MCU_ECAR0 REG32(0,0xffffe540)
188 #define MCU_ECAR1 REG32(0,0xffffe544)
189 #define MCU_ECTST REG32(0,0xffffe548)
190 #define MCU_MCISR REG32(0,0xffffe54c)
191 #define MCU_RFR REG32(0,0xffffe550)
192 #define MCU_DBUDSR REG32(0,0xffffe554)
193 #define MCU_DBDDSR REG32(0,0xffffe558)
194 #define MCU_CUDSR REG32(0,0xffffe55c)
195 #define MCU_CDDSR REG32(0,0xffffe560)
196 #define MCU_CEUDSR REG32(0,0xffffe564)
197 #define MCU_CEDDSR REG32(0,0xffffe568)
198 #define MCU_CSUDSR REG32(0,0xffffe56c)
199 #define MCU_CSDDSR REG32(0,0xffffe570)
200 #define MCU_REUDSR REG32(0,0xffffe574)
201 #define MCU_REDDSR REG32(0,0xffffe578)
202 #define MCU_ABUDSR REG32(0,0xffffe57c)
203 #define MCU_ABDDSR REG32(0,0xffffe580)
204 #define MCU_DSDR REG32(0,0xffffe584)
205 #define MCU_REDR REG32(0,0xffffe588)
206 #define MCU_RES10 REG32(0,0xffffe58c)
208 // Banksize specific component of SBRx register bits
213 #define SBR_512MEG 16
215 // Refresh rates for 200MHz
216 #define RFR_3_9us 0x300
217 #define RFR_7_8us 0x600
218 #define RFR_15_6us 0xC00
220 #define DSDR_REC_VAL 0x00000231
221 #define REDR_REC_VAL 0x00000000
222 #define SDCR_INIT_VAL 0x00000018 // 64-bit - unbuffered DIMM & turn off compensations (SECRET BITS!!!)
224 // SDRAM MODE COMMANDS
225 #define SDIR_CMD_NOP 0x00000005
226 #define SDIR_CMD_PRECHARGE_ALL 0x00000004
227 #define SDIR_CMD_ENABLE_DLL 0x00000006
228 #define SDIR_CMD_CAS_LAT_2_A 0x00000002
229 #define SDIR_CMD_CAS_LAT_2_B 0x00000000
230 #define SDIR_CMD_AUTO_REFRESH 0x00000007
233 // --------------------------------------------------------------------------
234 // Peripheral Bus Interface Unit (Chapter 8)
235 #define PBIU_PBCR REG32(0,0xffffe680)
236 #define PBIU_PBSR REG32(0,0xffffe684)
237 #define PBIU_PBAR0 REG32(0,0xffffe688)
238 #define PBIU_PBLR0 REG32(0,0xffffe68c)
239 #define PBIU_PBAR1 REG32(0,0xffffe690)
240 #define PBIU_PBLR1 REG32(0,0xffffe694)
241 #define PBIU_PBAR2 REG32(0,0xffffe698)
242 #define PBIU_PBLR2 REG32(0,0xffffe69c)
243 #define PBIU_PBAR3 REG32(0,0xffffe6a0)
244 #define PBIU_PBLR3 REG32(0,0xffffe6a4)
245 #define PBIU_PBAR4 REG32(0,0xffffe6a8)
246 #define PBIU_PBLR4 REG32(0,0xffffe6ac)
247 #define PBIU_PBAR5 REG32(0,0xffffe6b0)
248 #define PBIU_PBLR5 REG32(0,0xffffe6b4)
249 #define PBIU_PBVR0 REG32(0,0xffffe6c0)
250 #define PBIU_PBVR1 REG32(0,0xffffe6c4)
251 #define PBIU_PBVR2 REG32(0,0xffffe6c8)
252 #define PBIU_PBVR3 REG32(0,0xffffe6cc)
253 #define PBIU_PBVR4 REG32(0,0xffffe6d0)
254 #define PBIU_PBVR5 REG32(0,0xffffe6d8)
255 #define PBIU_PBVR6 REG32(0,0xffffe6dc)
257 #define PBCR_ENABLE 1
259 #define PBCR_ERR_VALID 0x01
260 #define PBCR_ERR_WRITE 0x02
261 #define PBCR_ERR_TYPEMASK 0x0C
263 #define PBAR_FLASH 0x200
264 #define PBAR_RCWAIT_1 0x000
265 #define PBAR_RCWAIT_4 0x040
266 #define PBAR_RCWAIT_8 0x080
267 #define PBAR_RCWAIT_12 0x0C0
268 #define PBAR_RCWAIT_16 0x100
269 #define PBAR_RCWAIT_20 0x1C0
270 #define PBAR_ADWAIT_4 0x000
271 #define PBAR_ADWAIT_8 0x004
272 #define PBAR_ADWAIT_12 0x008
273 #define PBAR_ADWAIT_16 0x00C
274 #define PBAR_ADWAIT_20 0x01C
275 #define PBAR_BUS_8 0x000
276 #define PBAR_BUS_16 0x001
277 #define PBAR_BUS_32 0x002
279 #define PBLR_SZ_4K 0xfffff000
280 #define PBLR_SZ_8K 0xffffe000
281 #define PBLR_SZ_16K 0xffffc000
282 #define PBLR_SZ_32K 0xffff8000
283 #define PBLR_SZ_64K 0xffff0000
284 #define PBLR_SZ_128K 0xfffe0000
285 #define PBLR_SZ_256K 0xfffc0000
286 #define PBLR_SZ_512K 0xfff80000
287 #define PBLR_SZ_1M 0xfff00000
288 #define PBLR_SZ_2M 0xffe00000
289 #define PBLR_SZ_4M 0xffc00000
290 #define PBLR_SZ_8M 0xff800000
291 #define PBLR_SZ_16M 0xff000000
292 #define PBLR_SZ_32M 0xfe000000
293 #define PBLR_SZ_64M 0xfc000000
294 #define PBLR_SZ_128M 0xf8000000
295 #define PBLR_SZ_256M 0xf0000000
296 #define PBLR_SZ_512M 0xe0000000
297 #define PBLR_SZ_1G 0xc0000000
298 #define PBLR_SZ_2G 0x80000000
299 #define PBLR_SZ_DISABLE 0x00000000
301 // --------------------------------------------------------------------------
303 #define I2C_BASE0 0xfffff680
304 #define I2C_BASE1 0xfffff6A0
308 #define I2C_ISAR 0x08
309 #define I2C_IDBR 0x0c
310 #define I2C_IBMR 0x14
312 #define I2C_ICR0 REG32(I2C_BASE0,I2C_ICR)
313 #define I2C_ICR1 REG32(I2C_BASE1,I2C_ICR)
314 #define I2C_ISR0 REG32(I2C_BASE0,I2C_ISR)
315 #define I2C_ISR1 REG32(I2C_BASE1,I2C_ISR)
316 #define I2C_ISAR0 REG32(I2C_BASE0,I2C_ISAR)
317 #define I2C_ISAR1 REG32(I2C_BASE1,I2C_ISAR)
318 #define I2C_IDBR0 REG32(I2C_BASE0,I2C_IDBR)
319 #define I2C_IDBR1 REG32(I2C_BASE1,I2C_IDBR)
320 #define I2C_IBMR0 REG32(I2C_BASE0,I2C_IBMR)
321 #define I2C_IBMR1 REG32(I2C_BASE1,I2C_IBMR)
323 // Control Register bits
324 #define ICR_START 0x0001 /* 1:send a Start condition to the I2C when in master mode */
325 #define ICR_STOP 0x0002 /* 1:send a Stop condition after next byte transferred in master mode */
326 #define ICR_ACK 0x0004 /* Ack/Nack control: 1:Nack, 0:Ack (negative or positive pulse) */
327 #define ICR_TRANSFER 0x0008 /* 1:send/receive byte, 0:cleared by I2C unit when done */
328 #define ICR_ABORT 0x0010 /* 1:I2C sends STOP w/out data permission, 0:ICR bit used only */
329 #define ICR_SCLENB 0x0020 /* I2C clock output: 1:Enabled, 0:Disabled. ICCR configured before ! */
330 #define ICR_ENB 0x0040 /* I2C unit: 1:Enabled, 0:Disabled */
331 #define ICR_GCALL 0x0080 /* General Call: 1:Disabled, 0:Enabled */
332 #define ICR_IEMPTY 0x0100 /* 1: IDBR Transmit Empty Interrupt Enable */
333 #define ICR_IFULL 0x0200 /* 1: IDBR Receive Full Interrupt Enable */
334 #define ICR_IERR 0x0400 /* 1: Bus Error Interrupt Enable */
335 #define ICR_ISTOP 0x0800 /* 1: Slave Stop Detected Interrupt Enable */
336 #define ICR_IARB 0x1000 /* 1: Arbitration Loss Detected Interrupt Enable */
337 #define ICR_ISADDR 0x2000 /* 1: Slave Address Detected Interrupt Enable */
338 #define ICR_RESET 0x4000 /* 1: I2C unit reset */
340 // Status Register bits
341 #define ISR_RWMODE 0x0001 /* 1: I2C in master receive = slave transmit mode */
342 #define ISR_ACK 0x0002 /* 1: I2C received/sent a Nack, 0: Ack */
343 #define ISR_BUSY 0x0004 /* 1: Processor's I2C unit busy */
344 #define ISR_BUSBUSY 0x0008 /* 1: I2C bus busy. Processor's I2C unit not involved */
345 #define ISR_STOP 0x0010 /* 1: Slave Stop detected (when in slave mode: receive or transmit) */
346 #define ISR_ARB 0x0020 /* 1: Arbitration Loss Detected */
347 #define ISR_EMPTY 0x0040 /* 1: Transfer finished on I2C bus. If enabled in ICR, interrupt signaled */
348 #define ISR_FULL 0x0080 /* 1: IDBR received new byte from I2C bus. If ICR, interrupt signaled */
349 #define ISR_GCALL 0x0100 /* 1: I2C unit received a General Call address */
350 #define ISR_SADDR 0x0200 /* 1: I2C unit detected a 7-bit address matching the general call or ISAR */
351 #define ISR_ERROR 0x0400 /* Bit set by unit when a Bus Error detected */
353 #define IDBR_MASK 0x000000ff
354 #define IDBR_MODE 0x01
356 // --------------------------------------------------------------------------
357 // Arbitration (Chapter 11)
358 #define ARB_IACR REG32(0,0xffffe780)
359 #define ARB_MTTR1 REG32(0,0xffffe784)
360 #define ARB_MTTR2 REG32(0,0xffffe788)
362 #define IACR_PRI_HIGH 0
363 #define IACR_PRI_MED 1
364 #define IACR_PRI_LOW 2
365 #define IACR_PRI_OFF 3
367 // macros to set priority for various units
368 #define IACR_ATU(x) ((x) << 0)
369 #define IACR_DMA0(x) ((x) << 4)
370 #define IACR_DMA1(x) ((x) << 6)
371 #define IACR_CORE(x) ((x) << 10)
372 #define IACR_AAU(x) ((x) << 12)
373 #define IACR_PBI(x) ((x) << 14)
376 // --------------------------------------------------------------------------
377 // Timers (Chapter 14)
378 #define TU_TMR0 REG32(0,0xffffe7e0)
379 #define TU_TMR1 REG32(0,0xffffe7e4)
380 #define TU_TCR0 REG32(0,0xffffe7e8)
381 #define TU_TCR1 REG32(0,0xffffe7ec)
382 #define TU_TRR0 REG32(0,0xffffe7f0)
383 #define TU_TRR1 REG32(0,0xffffe7f4)
384 #define TU_TISR REG32(0,0xffffe7f8)
385 #define TU_WDTCR REG32(0,0xffffe7fc)
387 #define TMR_TC 0x01 // terminal count
388 #define TMR_ENABLE 0x02 // timer enable
389 #define TMR_RELOAD 0x04 // auto reload enable
390 #define TMR_CLK_1 0x00 // CCLK (core clock)
391 #define TMR_CLK_4 0x10 // CCLK/4
392 #define TMR_CLK_8 0x20 // CCLK/8
393 #define TMR_CLK_16 0x30 // CCLK/16
395 #ifndef __ASSEMBLER__
396 // For full read/write access, you have to use coprocessor insns.
397 #define TMR0_READ(val) asm volatile ("mrc p6, 0, %0, c0, c1, 0" : "=r" (val))
398 #define _TMR0_WRITE(val) asm volatile ("mcr p6, 0, %0, c0, c1, 0" : : "r" (val))
399 #define TMR1_READ(val) asm volatile ("mrc p6, 0, %0, c1, c1, 0" : "=r" (val))
400 #define _TMR1_WRITE(val) asm volatile ("mcr p6, 0, %0, c1, c1, 0" : : "r" (val))
401 #define TCR0_READ(val) asm volatile ("mrc p6, 0, %0, c2, c1, 0" : "=r" (val))
402 #define _TCR0_WRITE(val) asm volatile ("mcr p6, 0, %0, c2, c1, 0" : : "r" (val))
403 #define TCR1_READ(val) asm volatile ("mrc p6, 0, %0, c3, c1, 0" : "=r" (val))
404 #define _TCR1_WRITE(val) asm volatile ("mcr p6, 0, %0, c3, c1, 0" : : "r" (val))
405 #define TRR0_READ(val) asm volatile ("mrc p6, 0, %0, c4, c1, 0" : "=r" (val))
406 #define _TRR0_WRITE(val) asm volatile ("mcr p6, 0, %0, c4, c1, 0" : : "r" (val))
407 #define TRR1_READ(val) asm volatile ("mrc p6, 0, %0, c5, c1, 0" : "=r" (val))
408 #define _TRR1_WRITE(val) asm volatile ("mcr p6, 0, %0, c5, c1, 0" : : "r" (val))
409 #define TISR_READ(val) asm volatile ("mrc p6, 0, %0, c6, c1, 0" : "=r" (val))
410 #define _TISR_WRITE(val) asm volatile ("mcr p6, 0, %0, c6, c1, 0" : : "r" (val))
411 #define _WDTCR_READ(val) asm volatile ("mrc p6, 0, %0, c7, c1, 0" : "=r" (val))
412 #define _WDTCR_WRITE(val) asm volatile ("mcr p6, 0, %0, c7, c1, 0" : : "r" (val))
414 static inline void TMR0_WRITE(cyg_uint32 val) { _TMR0_WRITE(val); }
415 static inline void TMR1_WRITE(cyg_uint32 val) { _TMR1_WRITE(val); }
416 static inline void TCR0_WRITE(cyg_uint32 val) { _TCR0_WRITE(val); }
417 static inline void TCR1_WRITE(cyg_uint32 val) { _TCR1_WRITE(val); }
418 static inline void TRR0_WRITE(cyg_uint32 val) { _TRR0_WRITE(val); }
419 static inline void TRR1_WRITE(cyg_uint32 val) { _TRR1_WRITE(val); }
420 static inline void TISR_WRITE(cyg_uint32 val) { _TISR_WRITE(val); }
423 // --------------------------------------------------------------------------
424 // Interrupts (Chapter 15)
425 #define INTCTL REG32(0,0xffffe7d0)
426 #define INTSTR REG32(0,0xffffe7d4)
427 #define IINTSRC REG32(0,0xffffe7d8)
428 #define FINTSRC REG32(0,0xffffe7dc)
429 #define PIRSR REG32(0,0xffffe1ec)
431 #ifndef __ASSEMBLER__
432 #define INTCTL_READ(val) asm volatile ("mrc p6, 0, %0, c0, c0, 0" : "=r" (val))
433 #define _INTCTL_WRITE(val) asm volatile ("mcr p6, 0, %0, c0, c0, 0" : : "r" (val))
434 #define INTSTR_READ(val) asm volatile ("mrc p6, 0, %0, c4, c0, 0" : "=r" (val))
435 #define _INTSTR_WRITE(val) asm volatile ("mcr p6, 0, %0, c4, c0, 0" : : "r" (val))
436 #define IINTSRC_READ(val) asm volatile ("mrc p6, 0, %0, c8, c0, 0" : "=r" (val))
437 #define FINTSRC_READ(val) asm volatile ("mrc p6, 0, %0, c9, c0, 0" : "=r" (val))
439 static inline void INTCTL_WRITE(cyg_uint32 val) { _INTCTL_WRITE(val); }
440 static inline void INTSTR_WRITE(cyg_uint32 val) { _INTSTR_WRITE(val); }
443 // --------------------------------------------------------------------------
445 #define GPIO_GPOE REG8(0,0xffffe7c4)
446 #define GPIO_GPID REG8(0,0xffffe7c8)
447 #define GPIO_GPOD REG8(0,0xffffe7cc)
449 #endif // CYGONCE_HAL_ARM_XSCALE_HAL_VERDE_H
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