1 #ifndef CYGONCE_MCF5272_DEVS_H
2 #define CYGONCE_MCF5272_DEVS_H
4 //=============================================================================
8 // Definitions for the MCF5272 on-chip peripherals
10 //==========================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15 // Copyright (C) 2006 eCosCentric Ltd.
17 // eCos is free software; you can redistribute it and/or modify it under
18 // the terms of the GNU General Public License as published by the Free
19 // Software Foundation; either version 2 or (at your option) any later version.
21 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
22 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
23 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
26 // You should have received a copy of the GNU General Public License along
27 // with eCos; if not, write to the Free Software Foundation, Inc.,
28 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
30 // As a special exception, if other files instantiate templates or use macros
31 // or inline functions from this file, or you compile this file and link it
32 // with other works to produce a work based on this file, this file does not
33 // by itself cause the resulting work to be covered by the GNU General Public
34 // License. However the source code for this file must still be made available
35 // in accordance with section (3) of the GNU General Public License.
37 // This exception does not invalidate any other reasons why a work based on
38 // this file might be covered by the GNU General Public License.
39 // -------------------------------------------
40 //####ECOSGPLCOPYRIGHTEND####
41 //==========================================================================
42 //#####DESCRIPTIONBEGIN####
44 // Author(s): Enrico Piria, Wade Jensen
47 // Purpose: Definitions for the MCF5272 on-chip peripherals.
48 // Usage: #include <cyg/hal/mcf5272_devs.h>
50 //####DESCRIPTIONEND####
51 //========================================================================
53 #include <pkgconf/hal.h>
54 #include <cyg/infra/cyg_type.h>
56 // General configuration registers
60 // Module base address register
63 // System configuration register
66 // System protection register
69 // Power management register
75 // Active low power register
78 // Device identification register
84 } __attribute__ ((aligned (4), packed)) mcf5272_sim_cfg_t;
86 // Configuration registers macros
88 #define MCF5272_SIM_SCR_HWWD_1024 0x0003
90 #define MCF5272_SIM_SPR_ADC 0x8000
91 #define MCF5272_SIM_SPR_ADCEN 0x0080
92 #define MCF5272_SIM_SPR_WPV 0x4000
93 #define MCF5272_SIM_SPR_WPVEN 0x0040
94 #define MCF5272_SIM_SPR_SMV 0x2000
95 #define MCF5272_SIM_SPR_SMVEN 0x0020
96 #define MCF5272_SIM_SPR_SBE 0x1000
97 #define MCF5272_SIM_SPR_SBEEN 0x0010
98 #define MCF5272_SIM_SPR_HWT 0x0800
99 #define MCF5272_SIM_SPR_HWTEN 0x0008
100 #define MCF5272_SIM_SPR_RPV 0x0400
101 #define MCF5272_SIM_SPR_RPVEN 0x0004
102 #define MCF5272_SIM_SPR_EXT 0x0200
103 #define MCF5272_SIM_SPR_EXTEN 0x0002
104 #define MCF5272_SIM_SPR_SUV 0x0100
105 #define MCF5272_SIM_SPR_SUVEN 0x0001
107 // ---------------------------------------------------------------------------
109 // Interrupt controller registers
113 // Interrupt control register 1-4
116 // Interrupt source register
119 // Programmable interrupt transition register
122 // Programmable interrupt wakeup register
128 // Programmable interrupt vector register
131 } __attribute__ ((aligned (4), packed)) mcf5272_sim_int_t;
133 // Interrupt controller related macros
135 #define MCF5272_SIM_PITR_INT1_POS_EDGE (0x80000000)
136 #define MCF5272_SIM_PITR_INT2_POS_EDGE (0x40000000)
137 #define MCF5272_SIM_PITR_INT3_POS_EDGE (0x20000000)
138 #define MCF5272_SIM_PITR_INT4_POS_EDGE (0x10000000)
139 #define MCF5272_SIM_PITR_INT5_POS_EDGE (0x00000040)
140 #define MCF5272_SIM_PITR_INT6_POS_EDGE (0x00000020)
142 #define MCF5272_SIM_PIWR_INT1_WAKE (0x80000000)
143 #define MCF5272_SIM_PIWR_INT2_WAKE (0x40000000)
144 #define MCF5272_SIM_PIWR_INT3_WAKE (0x20000000)
145 #define MCF5272_SIM_PIWR_INT4_WAKE (0x10000000)
146 #define MCF5272_SIM_PIWR_TMR0_WAKE (0x08000000)
147 #define MCF5272_SIM_PIWR_TMR1_WAKE (0x04000000)
148 #define MCF5272_SIM_PIWR_TMR2_WAKE (0x02000000)
149 #define MCF5272_SIM_PIWR_TMR3_WAKE (0x01000000)
150 #define MCF5272_SIM_PIWR_UART1_WAKE (0x00800000)
151 #define MCF5272_SIM_PIWR_UART2_WAKE (0x00400000)
152 #define MCF5272_SIM_PIWR_PLIP_WAKE (0x00200000)
153 #define MCF5272_SIM_PIWR_PLIA_WAKE (0x00100000)
154 #define MCF5272_SIM_PIWR_USB0_WAKE (0x00080000)
155 #define MCF5272_SIM_PIWR_USB1_WAKE (0x00040000)
156 #define MCF5272_SIM_PIWR_USB2_WAKE (0x00020000)
157 #define MCF5272_SIM_PIWR_USB3_WAKE (0x00010000)
158 #define MCF5272_SIM_PIWR_USB4_WAKE (0x00008000)
159 #define MCF5272_SIM_PIWR_USB5_WAKE (0x00004000)
160 #define MCF5272_SIM_PIWR_USB6_WAKE (0x00002000)
161 #define MCF5272_SIM_PIWR_USB7_WAKE (0x00001000)
162 #define MCF5272_SIM_PIWR_DMA_WAKE (0x00000800)
163 #define MCF5272_SIM_PIWR_ERX_WAKE (0x00000400)
164 #define MCF5272_SIM_PIWR_ETX_WAKE (0x00000200)
165 #define MCF5272_SIM_PIWR_ENTC_WAKE (0x00000100)
166 #define MCF5272_SIM_PIWR_QSPI_WAKE (0x00000080)
167 #define MCF5272_SIM_PIWR_INT5_WAKE (0x00000040)
168 #define MCF5272_SIM_PIWR_INT6_WAKE (0x00000020)
169 #define MCF5272_SIM_PIWR_SWTO_WAKE (0x00000010)
171 // ---------------------------------------------------------------------------
173 // Chip-select module
180 // CS option register
183 } __attribute__ ((aligned (4), packed)) mcf5272_sim_cs_t;
185 // Chip-select modules related macros
187 #define MCF5272_CS_BR_BASE(a) ((a) & 0xFFFFF000)
189 #define MCF5272_CS_OR_MASK_128M (0xF8000000)
190 #define MCF5272_CS_OR_MASK_64M (0xFC000000)
191 #define MCF5272_CS_OR_MASK_32M (0xFE000000)
192 #define MCF5272_CS_OR_MASK_16M (0xFF000000)
193 #define MCF5272_CS_OR_MASK_8M (0xFF800000)
194 #define MCF5272_CS_OR_MASK_4M (0xFFC00000)
195 #define MCF5272_CS_OR_MASK_2M (0xFFE00000)
196 #define MCF5272_CS_OR_MASK_1M (0xFFF00000)
197 #define MCF5272_CS_OR_MASK_512K (0xFFF80000)
198 #define MCF5272_CS_OR_MASK_256K (0xFFFC0000)
199 #define MCF5272_CS_OR_MASK_128K (0xFFFE0000)
200 #define MCF5272_CS_OR_MASK_64K (0xFFFF0000)
201 #define MCF5272_CS_OR_MASK_32K (0xFFFF8000)
202 #define MCF5272_CS_OR_MASK_16K (0xFFFFC000)
203 #define MCF5272_CS_OR_MASK_8K (0xFFFFE000)
204 #define MCF5272_CS_OR_MASK_4K (0xFFFFF000)
205 #define MCF5272_CS_OR_WS_MASK (0x007C)
206 #define MCF5272_CS_OR_WS(a) (((a) & 0x1F) << 2)
207 #define MCF5272_CS_OR_BRST (0x0100)
208 #define MCF5272_CS_OR_WR_ONLY (0x0003)
209 #define MCF5272_CS_OR_RD_ONLY (0x0001)
211 #define MCF5272_CS_BR_PS_8 (0x0100)
212 #define MCF5272_CS_BR_PS_16 (0x0200)
213 #define MCF5272_CS_BR_PS_32 (0x0000)
214 #define MCF5272_CS_BR_PS_LINE (0x0300)
215 #define MCF5272_CS_BR_ROM (0x0000)
216 #define MCF5272_CS_BR_SRAM (0x0000)
217 #define MCF5272_CS_BR_SRAM_8 (0x0C00)
218 #define MCF5272_CS_BR_SDRAM (0x0400)
219 #define MCF5272_CS_BR_ISA (0x0800)
220 #define MCF5272_CS_BR_SV (0x0080)
221 #define MCF5272_CS_BR_EN (0x0001)
223 // ---------------------------------------------------------------------------
225 // General purpose I/O module
229 // Port A control register
232 // Port A data direction register
235 // Port A data register
238 // Port B control register
241 // Port B data direction register
244 // Port B data register
250 // Port C data direction register
253 // Port C data register
256 // Port D control register
263 } __attribute__ ((aligned (4), packed)) mcf5272_sim_gpio_t;
265 // GPIO ports related macros
267 #define MCF5272_GPIO_DDR_IN (0)
268 #define MCF5272_GPIO_DDR_OUT (1)
270 #define MCF5272_GPIO_PBCNT_ETH_EN (0x55550000)
271 #define MCF5272_GPIO_PBCNT_ETH_DE (0x00000000)
272 #define MCF5272_GPIO_PBCNT_ETH_MSK (0xFFFF0000)
274 #define MCF5272_GPIO_PBCNT_TA_EN (0x00000400)
275 #define MCF5272_GPIO_PBCNT_TA_DE (0x00000000)
276 #define MCF5272_GPIO_PBCNT_TA_MSK (0x00000C00)
278 #define MCF5272_GPIO_PBCNT_URT0_EN (0x00000155)
279 #define MCF5272_GPIO_PBCNT_URT0_DE (0x00000000)
280 #define MCF5272_GPIO_PBCNT_URT0_MSK (0x000003FF)
282 #define MCF5272_GPIO_PDCNT_INT4_EN (0x00000C00)
283 #define MCF5272_GPIO_PDCNT_INT4_DE (0x00000000)
284 #define MCF5272_GPIO_PDCNT_INT4_MSK (0x00000C00)
286 #define MCF5272_GPIO_PDCNT_URT1_EN (0x000002AA)
287 #define MCF5272_GPIO_PDCNT_URT1_DE (0x00000000)
288 #define MCF5272_GPIO_PDCNT_URT1_MSK (0x000003FF)
290 // ---------------------------------------------------------------------------
296 // UART mode register
302 // UART status register (R) and clock-select register (W)
308 // UART command register
314 // UART receiver buffers (R) and transmitter buffers (W)
320 // UART input port change register (R) and auxiliary control register (W)
321 cyg_uint8 uipcr_uacr;
326 // UART interrupt status register (R) and interrupt mask register (W)
332 // UART divider upper register
338 // UART divider lower register
344 // UART autobaud register MSB
350 // UART autobaud register LSB
356 // UART transmitter FIFO register
362 // UART receiver FIFO register
368 // UART fractional precision divider register
374 // UART input port register
380 // UART output port register 1
386 // UART output port register 0
392 } __attribute__ ((aligned (4), packed)) mcf5272_uart_t;
394 // ---------------------------------------------------------------------------
403 // SDRAM configuration register
409 // SDRAM timing register
413 cyg_uint8 _res3[120];
415 } __attribute__ ((aligned (4), packed)) mcf5272_sim_sdramctrl_t;
417 // SDRAM controller related macros
419 #define MCF5272_SDRAMC_SDCCR_MCAS_A7 (0x0 << 13)
420 #define MCF5272_SDRAMC_SDCCR_MCAS_A8 (0x1 << 13)
421 #define MCF5272_SDRAMC_SDCCR_MCAS_A9 (0x2 << 13)
422 #define MCF5272_SDRAMC_SDCCR_MCAS_A10 (0x3 << 13)
423 #define MCF5272_SDRAMC_SDCCR_BALOC_A19 (0x0 << 8)
424 #define MCF5272_SDRAMC_SDCCR_BALOC_A20 (0x1 << 8)
425 #define MCF5272_SDRAMC_SDCCR_BALOC_A21 (0x2 << 8)
426 #define MCF5272_SDRAMC_SDCCR_BALOC_A22 (0x3 << 8)
427 #define MCF5272_SDRAMC_SDCCR_BALOC_A23 (0x4 << 8)
428 #define MCF5272_SDRAMC_SDCCR_BALOC_A24 (0x5 << 8)
429 #define MCF5272_SDRAMC_SDCCR_BALOC_A25 (0x6 << 8)
430 #define MCF5272_SDRAMC_SDCCR_BALOC_A26 (0x7 << 8)
431 #define MCF5272_SDRAMC_SDCCR_GSL (0x00000080)
432 #define MCF5272_SDRAMC_SDCCR_REG (0x00000010)
433 #define MCF5272_SDRAMC_SDCCR_INV (0x00000008)
434 #define MCF5272_SDRAMC_SDCCR_SLEEP (0x00000004)
435 #define MCF5272_SDRAMC_SDCCR_ACT (0x00000002)
436 #define MCF5272_SDRAMC_SDCCR_INIT (0x00000001)
438 #define MCF5272_SDRAMC_SDCTR_RTP_66MHz (0x3D << 10)
439 #define MCF5272_SDRAMC_SDCTR_RTP_48MHz (0x2B << 10)
440 #define MCF5272_SDRAMC_SDCTR_RTP_33MHz (0x1D << 10)
441 #define MCF5272_SDRAMC_SDCTR_RTP_25MHz (0x16 << 10)
442 #define MCF5272_SDRAMC_SDCTR_RC(x) ((x & 0x3) << 8)
443 #define MCF5272_SDRAMC_SDCTR_RP(x) ((x & 0x3) << 4)
444 #define MCF5272_SDRAMC_SDCTR_RCD(x) ((x & 0x3) << 2)
445 #define MCF5272_SDRAMC_SDCTR_CLT_2 (0x00000001)
446 #define MCF5272_SDRAMC_SDCTR_CLT_3 (0x00000002)
447 #define MCF5272_SDRAMC_SDCTR_CLT_4 (0x00000003)
449 // ---------------------------------------------------------------------------
455 // Timer mode register
461 // Timer reference register
467 // Timer capture register
473 // Timer counter register
479 // Timer event register
488 } __attribute__ ((aligned (4), packed)) mcf5272_timer_t;
492 #define MCF5272_TIMER_TMR_PS (0xFF00)
493 #define MCF5272_TIMER_TMR_PS_BIT (8)
494 #define MCF5272_TIMER_TMR_CE (0x00C0)
495 #define MCF5272_TIMER_TMR_CE_BIT (6)
496 #define MCF5272_TIMER_TMR_OM (0x0020)
497 #define MCF5272_TIMER_TMR_OM_BIT (5)
498 #define MCF5272_TIMER_TMR_ORI (0x0010)
499 #define MCF5272_TIMER_TMR_ORI_BIT (4)
500 #define MCF5272_TIMER_TMR_FRR (0x0008)
501 #define MCF5272_TIMER_TMR_FRR_BIT (3)
502 #define MCF5272_TIMER_TMR_CLK (0x0006)
503 #define MCF5272_TIMER_TMR_CLK_BIT (1)
504 #define MCF5272_TIMER_TMR_RST (0x0001)
505 #define MCF5272_TIMER_TMR_RST_BIT (0)
506 #define MCF5272_TIMER_TER_REF (0x0002)
507 #define MCF5272_TIMER_TER_REF_BIT (1)
508 #define MCF5272_TIMER_TER_CAP (0x0001)
509 #define MCF5272_TIMER_TER_CAP_BIT (0)
511 // ---------------------------------------------------------------------------
517 // Watchdog reset reference register
523 // Watchdog interrupt reference register
529 // Watchdog counter register
535 // Watchdog event register
542 cyg_uint32 _res5[28];
544 } __attribute__ ((aligned (4), packed)) mcf5272_sim_wdtmr_t;
546 // ---------------------------------------------------------------------------
548 // Fast Ethernet Controller module
552 // Ethernet control register
555 // Ethernet interrupt event register
558 // Ethernet interrupt mask register
561 // Interrupt vector status register
564 // Receive descriptor active register
567 // Transmit descriptor active register
571 cyg_uint8 _res2[0x0880 - 0x0858];
573 // MII management frame register
576 // MII speed control register
580 cyg_uint8 _res3[0x08cc - 0x0888];
582 // FIFO receive bound register
585 // FIFO receive start register
589 cyg_uint8 _res4[0x08e4 - 0x08d4];
591 // Transmit FIFO watermark
595 cyg_uint8 _res5[0x08ec - 0x08e8];
597 // Transmit FIFO start register
601 cyg_uint8 _res6[0x0944 - 0x08f0];
603 // Receive control register
606 // Maximum frame length register
610 cyg_uint8 _res7[0x0984 - 0x094c];
612 // Transmit control register
616 cyg_uint8 _res8[0x0c00 - 0x0988];
618 // RAM perfect match address low register
621 // RAM perfect match address high register
624 // Hash table high register
627 // Hash table low register
630 // Pointer to receive descriptor ring
633 // Pointer to transmit descriptor ring
636 // Maximum receive buffer size
640 cyg_uint8 _res9[0x0c40 - 0x0c1c];
643 cyg_uint8 efifo[0x0e00 - 0x0c40];
646 cyg_uint8 _res10[0x1000 - 0x0e00];
648 } __attribute__ ((aligned (4), packed)) mcf5272_fec_t;
650 // ---------------------------------------------------------------------------
652 // On-chip peripherals: this structure defines each register's offset from the
653 // current value of the MBAR register.
657 // 0x0000: System Integration Module (SIM) general configuration registers
658 mcf5272_sim_cfg_t cfg;
660 // 0x0020: SIM interrupt controller registers
661 mcf5272_sim_int_t intc;
663 // 0x0040: SIM chip-select modules
664 mcf5272_sim_cs_t cs[8];
666 // 0x0080: SIM general purpose I/O control registers
667 mcf5272_sim_gpio_t gpio;
669 // 0x00a0: QSPI module
670 // TODO: a specific data structure is needed
673 // 0x00c0: PWM module
674 // TODO: a specific data structure is needed
677 // 0x00e0: DMA controller
678 // TODO: a specific data structure is needed
681 // 0x0100: UART modules
682 mcf5272_uart_t uart[2];
684 // 0x0180: SIM SDRAM controller
685 mcf5272_sim_sdramctrl_t sdramc;
687 // 0x0200: timer module
688 mcf5272_timer_t timer[4];
690 // 0x0280: SIM watchdog timer module
691 mcf5272_sim_wdtmr_t wdtimer;
693 // 0x0300: physical layer interface controller
694 // TODO: a specific data structure is needed
695 cyg_uint32 plic[336];
697 // 0x0840: ethernet module
700 // 0x1000: USB module
701 // TODO: a specific data structure is needed
704 } __attribute__ ((aligned (4), packed)) mcf5272_devs_t;
706 // ---------------------------------------------------------------------------
707 // End of mcf5272_devs.h
708 #endif // CYGONCE_MCF5272_DEVS_H