1 # ====================================================================
3 # hal_h8300_h8300h_sim.cdl
5 # AKI3068NET board HAL package configuration data
7 # ====================================================================
8 #####ECOSGPLCOPYRIGHTBEGIN####
9 ## -------------------------------------------
10 ## This file is part of eCos, the Embedded Configurable Operating System.
11 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 ## eCos is free software; you can redistribute it and/or modify it under
14 ## the terms of the GNU General Public License as published by the Free
15 ## Software Foundation; either version 2 or (at your option) any later version.
17 ## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18 ## WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 ## You should have received a copy of the GNU General Public License along
23 ## with eCos; if not, write to the Free Software Foundation, Inc.,
24 ## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 ## As a special exception, if other files instantiate templates or use macros
27 ## or inline functions from this file, or you compile this file and link it
28 ## with other works to produce a work based on this file, this file does not
29 ## by itself cause the resulting work to be covered by the GNU General Public
30 ## License. However the source code for this file must still be made available
31 ## in accordance with section (3) of the GNU General Public License.
33 ## This exception does not invalidate any other reasons why a work based on
34 ## this file might be covered by the GNU General Public License.
36 ## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37 ## at http://sources.redhat.com/ecos/ecos-license/
38 ## -------------------------------------------
39 #####ECOSGPLCOPYRIGHTEND####
40 # ====================================================================
41 ######DESCRIPTIONBEGIN####
43 # Author(s): yoshinori sato
44 # Original data: bartv
45 # Contributors: yoshinori sato
48 #####DESCRIPTIONEND####
50 # ====================================================================
52 cdl_package CYGPKG_HAL_H8300_H8300H_AKI3068NET {
54 parent CYGPKG_HAL_H8300
55 requires CYGPKG_HAL_H8300_H8300H
56 implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
57 implements CYGINT_HAL_DEBUG_GDB_STUBS
58 implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
59 define_header hal_h8300_h8300h_aki3068net.h
62 The aki HAL package provides the support needed to run
63 eCos on a Akizuki H8/3068 Network micom board."
65 compile hal_diag.c plf_misc.c delay_us.S plf_ide.c
68 puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_h8300_h8300h.h>"
69 puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_h8300_h8300h_aki3068net.h>"
70 puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_IO_H <cyg/hal/plf_io.h>"
72 puts $::cdl_header "#define CYG_HAL_H8300"
73 puts $::cdl_header "#define CYGNUM_HAL_H8300_SCI_PORTS 1"
74 puts $::cdl_header "#define CYGHWR_HAL_VECTOR_TABLE 0xfffe20"
75 puts $::cdl_header "#define HAL_PLATFORM_CPU \"H8/300H\""
76 puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Akizuki H8/3068 Network micom\""
77 puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\""
80 cdl_component CYG_HAL_STARTUP {
81 display "Startup type"
83 legal_values {"ROM" "RAM"}
86 define -file system.h CYG_HAL_STARTUP
88 When targetting the AKI3068NET board it is possible to
89 build the system for either RAM bootstrap or ROM bootstrap.
90 RAM bootstrap generally requires that the board
91 is equipped with ROMs containing a suitable ROM monitor or
92 equivalent software that allows GDB to download the eCos
93 application and extend Memory on to the board.
94 The ROM bootstrap typically
95 requires that the eCos application be blown into EPROMs or
96 equivalent technology."
99 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
100 display "Number of communication channels on the board"
105 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
106 display "Debug serial port"
108 legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
111 The AKI3068NET board has only one serial port. This option
112 chooses which port will be used to connect to a host
116 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
117 display "Diagnostic serial port"
119 legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
122 The CQ/7708 board has only one serial port. This option
123 chooses which port will be used for diagnostic output."
126 # Real-time clock/counter specifics
127 cdl_component CYGNUM_HAL_RTC_CONSTANTS {
128 display "Real-time clock constants."
131 cdl_option CYGNUM_HAL_RTC_NUMERATOR {
132 display "Real-time clock numerator"
134 default_value 1000000000
136 cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
137 display "Real-time clock denominator"
141 cdl_option CYGNUM_HAL_H8300_RTC_PRESCALE {
142 display "Real-time clock base prescale"
146 # Isn't a nice way to handle freq requirement!
147 cdl_option CYGNUM_HAL_RTC_PERIOD {
148 display "Real-time clock period"
154 cdl_option CYGHWR_HAL_H8300_CPG_INPUT {
155 display "OSC/Clock Freqency"
157 default_value 20000000
160 cdl_option CYGHWR_HAL_AKI3068NET_EXTRAM {
161 display "Extend DRAM Using"
166 cdl_option CYGHWR_HAL_AKI3068NET_IDE {
167 display "IDE I/F expand"
172 cdl_component CYGBLD_GLOBAL_OPTIONS {
173 display "Global build options"
177 Global build options including control over
178 compiler flags, linker flags and choice of toolchain."
181 cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
182 display "Global command prefix"
185 default_value { "h8300-elf" }
187 This option specifies the command prefix used when
188 invoking the build tools."
191 cdl_option CYGBLD_GLOBAL_CFLAGS {
192 display "Global compiler flags"
195 default_value { "-Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -mh -mint32 -fsigned-char -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
197 This option controls the global compiler flags which
198 are used to compile all packages by
199 default. Individual packages may define
200 options which override these global flags."
203 cdl_option CYGBLD_GLOBAL_LDFLAGS {
204 display "Global linker flags"
207 default_value { "-g -nostdlib -Wl,--gc-sections -Wl,-static -mrelax -mh -mint32" }
209 This option controls the global linker flags. Individual
210 packages may define options which override these global flags."
212 cdl_option CYGBLD_BUILD_GDB_STUBS {
213 display "Build GDB stub ROM image"
215 requires CYGSEM_HAL_ROM_MONITOR
216 requires CYGBLD_BUILD_COMMON_GDB_STUBS
217 requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
218 requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
219 requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
222 This option enables the building of the GDB stubs for the
223 board. The common HAL controls takes care of most of the
224 build process, but the final conversion from ELF image to
225 binary data is handled by the platform CDL, allowing
226 relocation of the data if necessary."
229 <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img
230 $(OBJCOPY) -O binary $< $@
235 cdl_component CYGHWR_MEMORY_LAYOUT {
236 display "Memory layout"
239 calculated { CYG_HAL_STARTUP == "RAM" ? "h8300_h8300h_aki3068net_ram" : \
240 "h8300_h8300h_aki3068net_rom" }
242 cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
243 display "Memory layout linker script fragment"
246 define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
247 calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_h8300_h8300h_aki3068net_ram.ldi>" : \
248 "<pkgconf/mlt_h8300_h8300h_aki3068net_rom.ldi>" }
251 cdl_option CYGHWR_MEMORY_LAYOUT_H {
252 display "Memory layout header file"
255 define -file system.h CYGHWR_MEMORY_LAYOUT_H
256 calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_h8300_h8300h_aki3068net_ram.h>" : \
257 "<pkgconf/mlt_h8300_h8300h_aki3068net_rom.h>" }
261 cdl_component CYGHWR_AKI3068NET_IDE_OPTIONS {
262 display "IDE Expand Setting"
265 active_if CYGHWR_HAL_AKI3068NET_IDE
266 implements CYGINT_HAL_PLF_IF_IDE
268 IDE Expand Hardware Setting."
270 cdl_option CYGHWR_HAL_IDE_REGISTER {
271 display "IDE Register base address"
273 default_value 0x600000
276 cdl_option CYGHWR_HAL_IDE_ALT_REGS {
277 display "IDE AlternateRegister base address"
279 default_value 0x600020
282 cdl_option CYGHWR_HAL_IDE_BUSWIDTH {
283 display "IDE bus width"
290 cdl_option CYGSEM_HAL_ROM_MONITOR {
291 display "Behave as a ROM monitor"
294 parent CYGPKG_HAL_ROM_MONITOR
295 requires { CYG_HAL_STARTUP == "ROM" }
297 Enable this option if this program is to be used as a ROM monitor,
298 i.e. applications will be loaded into RAM on the board, and this
299 ROM monitor may process exceptions or interrupts generated from the
300 application. This enables features such as utilizing a separate
301 interrupt stack when exceptions are generated."
303 cdl_option CYGHWR_HAL_H8300_VECTOR_ADDRESS {
304 display "Hook Vector Address"
306 default_value 0xfffd20
307 active_if CYGSEM_HAL_H8300_VECTOR_HOOK
308 parent CYGPKG_HAL_ROM_MONITOR
310 Hooking Vector Table Address"
312 cdl_option CYGHAL_PLF_SCI_BASE {
313 display "SCI Base address"
315 default_value 0xffffb8
317 Used SCI Channel base address."
319 cdl_option CYGDAT_REDBOOT_H8300_LINUX_COMMAND_START {
320 display "Default kernel command line start address"
322 default_value 0x5ffe00
324 This option uClinux kernel command line start address of default."
327 cdl_option CYGDAT_REDBOOT_H8300_LINUX_BOOT_COMMAND_LINE {
328 display "Default command line"
330 default_value { "console=/dev/ttySC1" }
332 This option uClinux kernel startup command line of default."