1 #ifndef CYGONCE_HAL_IDT79RC233X_H
2 #define CYGONCE_HAL_IDT79RC233X_H
3 //==========================================================================
7 // IDT 79RC233x platform definitions
9 //==========================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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21 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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40 // -------------------------------------------
41 //####ECOSGPLCOPYRIGHTEND####
42 //==========================================================================
43 //#####DESCRIPTIONBEGIN####
45 // Author(s): Tim Michals
46 // Contributors: nickg
48 // Purpose: IDT 79RC233x platform definitions
51 //####DESCRIPTIONEND####
52 //==========================================================================
54 #define K0BASE 0x80000000
55 #define K0SIZE 0x20000000
56 #define K1BASE 0xA0000000
57 #define K1SIZE 0x20000000
58 #define K2BASE 0xC0000000
59 #define K2SIZE 0x40000000
65 #define T_VEC K0BASE /* tlbmiss vector */
66 #define C_VEC (K1BASE+0x100) /* cache exception vector */
67 #define E_VEC (K0BASE+0x180) /* exception vector */
68 #define R_VEC (K1BASE+0x1fc00000) /* reset vector */
71 * Address conversion macros
74 #define K0_TO_K1(x) ((unsigned)(x)|0xA0000000) /* kseg0 to kseg1 */
75 #define K1_TO_K0(x) ((unsigned)(x)&0x9FFFFFFF) /* kseg1 to kseg0 */
76 #define K0_TO_PHYS(x) ((unsigned)(x)&0x1FFFFFFF) /* kseg0 to physical */
77 #define K1_TO_PHYS(x) ((unsigned)(x)&0x1FFFFFFF) /* kseg1 to physical */
78 #define PHYS_TO_K0(x) ((unsigned)(x)|0x80000000) /* physical to kseg0 */
79 #define PHYS_TO_K1(x) ((unsigned)(x)|0xA0000000) /* physical to kseg1 */
85 #define IS_KSEG0(x) ((unsigned)(x) >= K0BASE && (unsigned)(x) < K1BASE)
86 #define IS_KSEG1(x) ((unsigned)(x) >= K1BASE && (unsigned)(x) < K2BASE)
87 #define IS_KUSEG(x) ((unsigned)(x) < K0BASE)
90 * Cache size constants
93 #define MINCACHE +(1*1024) /* leading plus for mas's benefit */
94 #define MAXCACHE +(256*1024) /* leading plus for mas's benefit */
97 * Cache alignment macros
99 * NOTE: These definitions may migrate to vxWorks.h in a future release.
102 #define CACHE_ROUND_UP(x) ROUND_UP(x, _CACHE_ALIGN_SIZE)
103 #define CACHE_ROUND_DOWN(x) ROUND_DOWN(x, _CACHE_ALIGN_SIZE)
106 * Cause bit definitions
109 #define CAUSE_BD 0x80000000 /* Branch delay slot */
110 #define CAUSE_CEMASK 0x30000000 /* coprocessor error */
111 #define CAUSE_CESHIFT 28
113 #define CAUSE_IP8 0x00008000 /* External level 8 pending */
114 #define CAUSE_IP7 0x00004000 /* External level 7 pending */
115 #define CAUSE_IP6 0x00002000 /* External level 6 pending */
116 #define CAUSE_IP5 0x00001000 /* External level 5 pending */
117 #define CAUSE_IP4 0x00000800 /* External level 4 pending */
118 #define CAUSE_IP3 0x00000400 /* External level 3 pending */
119 #define CAUSE_SW2 0x00000200 /* Software level 2 pending */
120 #define CAUSE_SW1 0x00000100 /* Software level 1 pending */
122 #define CAUSE_IPMASK 0x0000FF00 /* Pending interrupt mask */
123 #define CAUSE_IPSHIFT 8
125 #define CAUSE_EXCMASK 0x0000007C /* Cause code bits */
126 #define CAUSE_EXCSHIFT 2
129 * Status definition bits
132 #define SR_CUMASK 0xf0000000 /* coproc usable bits */
133 #define SR_CU3 0x80000000 /* Coprocessor 3 usable */
134 #define SR_CU2 0x40000000 /* Coprocessor 2 usable */
135 #define SR_CU1 0x20000000 /* Coprocessor 1 usable */
136 #define SR_CU0 0x10000000 /* Coprocessor 0 usable */
137 #define SR_NBL 0x08000000 /* Enables Non Blocking Load */
138 #define SR_RE 0x02000000 /* Reverse endian in user mode */
139 #define SR_DL 0x01000000 /* Data Cache Lock Enable */
140 #define SR_IL 0x00800000 /* Instruction Cache Lock Enable */
142 #define SR_BEV 0x00400000 /* use boot exception vectors */
143 #define SR_SR 0x00100000 /* soft reset occurred */
144 #define SR_CE 0x00020000 /* use ECC reg */
145 #define SR_DE 0x00010000 /* disable cache errors */
146 #define SR_IMASK 0x0000ff00 /* Interrupt mask */
147 #define SR_IMASK8 0x00000000 /* mask level 8 */
148 #define SR_IMASK7 0x00008000 /* mask level 7 */
149 #define SR_IMASK6 0x0000c000 /* mask level 6 */
150 #define SR_IMASK5 0x0000e000 /* mask level 5 */
151 #define SR_IMASK4 0x0000f000 /* mask level 4 */
152 #define SR_IMASK3 0x0000f800 /* mask level 3 */
153 #define SR_IMASK2 0x0000fc00 /* mask level 2 */
154 #define SR_IMASK1 0x0000fe00 /* mask level 1 */
155 #define SR_IMASK0 0x0000ff00 /* mask level 0 */
157 #define SR_IBIT8 0x00008000 /* bit level 8 */
158 #define SR_IBIT7 0x00004000 /* bit level 7 */
159 #define SR_IBIT6 0x00002000 /* bit level 6 */
160 #define SR_IBIT5 0x00001000 /* bit level 5 */
161 #define SR_IBIT4 0x00000800 /* bit level 4 */
162 #define SR_IBIT3 0x00000400 /* bit level 3 */
163 #define SR_IBIT2 0x00000200 /* bit level 2 */
164 #define SR_IBIT1 0x00000100 /* bit level 1 */
166 #define SR_KSU_K 0x00000000 /* kernel mode */
167 #define SR_KSU_U 0x00000010 /* user mode */
168 #define SR_ERL 0x00000004 /* Error Level */
169 #define SR_EXL 0x00000002 /* Exception Level */
170 #define SR_IE 0x00000001 /* interrupt enable, 1 => enable */
172 #define SR_IMASKSHIFT 8
178 #define TLB_ENTRIES 16
179 #define TLBLO_PFNMASK 0x03ffffc0
180 #define TLBLO_PFNSHIFT 6
181 #define TLBLO_CMASK 0x00000038
182 #define TLBLO_NC 0x00000010 /* uncached */
183 #define TLBLO_NONC 0x00000018 /* cacheable non-coherent */
184 #define TLBLO_D 0x4 /* writeable */
185 #define TLBLO_V 0x2 /* valid bit */
186 #define TLBLO_G 0x1 /* global bit */
188 #define TLBHI_VPN2MASK 0xffffe000
189 #define TLBHI_VPN2SHIFT 13
190 #define TLBHI_PIDMASK 0xff
191 #define TLBHI_PIDSHIFT 0
192 #define TLBHI_NPID 256
193 #define TLBINX_PROBE 0x80000000
194 #define TLBINX_INXMASK 0x0000003f
195 #define TLBINX_INXSHIFT 0
196 #define TLBRAND_RANDMASK 0x0000000f
197 #define TLBRAND_RANDSHIFT 0
198 #define TLBCTXT_BASEMASK 0xff800000
199 #define TLBCTXT_BASESHIFT 23
200 #define TLBCTXT_VPN2MASK 0x007ffff0
201 #define TLBCTXT_VPN2SHIFT 4
204 * RC32364 Config Register
206 #define CFG_ICE 0x80000000 /* In Circuit Emulator existence */
207 #define CFG_ECMASK 0x70000000 /* System Clock Ratio */
208 #define CFG_ECBY2 0x00000000 /* divide by 2 */
209 #define CFG_ECBY3 0x10000000 /* divide by 3 */
210 #define CFG_ECBY4 0x20000000 /* divide by 4 */
211 #define CFG_NBL 0x00800000 /* Non Blocking load */
212 #define CFG_BE 0x00008000 /* Big Endian */
213 #define CFG_ICMASK 0x00000e00 /* Instruction cache size */
214 #define CFG_ICSHIFT 9
215 #define CFG_DCMASK 0x000001c0 /* Data cache size */
216 #define CFG_DCSHIFT 6
217 #define CFG_IB 0x00000020 /* Instruction cache block size */
218 #define CFG_DB 0x00000010 /* Data cache block size */
219 #define CFG_K0MASK 0x00000007 /* KSEG0 coherency algorithm */
224 #define CFG_C_UNCACHED 2
225 #define CFG_C_NONCOHERENT 3
228 * Primary Cache TagLo
230 #define TAG_PTAG_MASK 0x7fffff00 /* Primary Tag */
231 #define TAG_PTAG_SHIFT 0x00000008
232 #define TAG_PSTATE_MASK 0x000000c0 /* Primary Cache State */
233 #define TAG_PSTATE_SHIFT 0x00000006
234 #define TAG_LOCK_BIT 0x00000004 /* Cache line lock bit */
235 #define TAG_LOCK_BIT_SHIFT 0x00000002
236 #define TAG_FIFO_REFILL 0x00000002 /* Fifo refill */
237 #define TAG_FIFO_REFILL_SHIFT 0x00000001
238 #define TAG_PARITY_MASK 0x00000001 /* Primary Tag Parity */
239 #define TAG_PARITY_SHIFT 0x00000000
246 #define CACHEERR_TYPE 0x80000000 /* reference type:
248 #define CACHEERR_LEVEL 0x40000000 /* cache level:
249 0=Primary, 1=reserved */
250 #define CACHEERR_DATA 0x20000000 /* data field:
251 0=No error, 1=Error */
252 #define CACHEERR_TAG 0x10000000 /* tag field:
253 0=No error, 1=Error */
254 #define CACHEERR_BOTH 0x02000000 /* Data & Instruction error:
256 #define CACHEERR_SIDX_MASK 0x003ffff8 /* PADDR(21..3) */
257 #define CACHEERR_SIDX_SHIFT 3
258 #define CACHEERR_PIDX_MASK 0x00000003 /* VADDR(13..12) */
259 #define CACHEERR_PIDX_SHIFT 12
265 #define Index_Invalidate_I 0x0 /* 0 0 */
266 #define Index_Writeback_Inv_D 0x1 /* 0 1 */
267 #define Index_Load_Tag_I 0x4 /* 1 0 */
268 #define Index_Load_Tag_D 0x5 /* 1 1 */
269 #define Index_Store_Tag_I 0x8 /* 2 0 */
270 #define Index_Store_Tag_D 0x9 /* 2 1 */
271 #define Create_Dirty_Exc_D 0xD /* 3 1 */
272 #define Hit_Invalidate_I 0x10 /* 4 0 */
273 #define Hit_Invalidate_D 0x11 /* 4 1 */
274 #define Hit_Writeback_Inv_D 0x15 /* 5 1 */
275 #define Fill_I 0x14 /* 5 0 */
276 #define Hit_Writeback_D 0x19 /* 6 1 */
277 #define Hit_Writeback_I 0x18 /* 6 0 */
280 * Coprocessor 0 operations
283 #define C0_READI 0x1 /* read ITLB entry addressed by C0_INDEX */
284 #define C0_WRITEI 0x2 /* write ITLB entry addressed by C0_INDEX */
285 #define C0_WRITER 0x6 /* write ITLB entry addressed by C0_RAND */
286 #define C0_PROBE 0x8 /* probe for ITLB entry addressed by TLBHI */
287 #define C0_ERET 0x18 /* restore for exception */
288 #define FP_EXC_MASK (FP_EXC_I|FP_EXC_U|FP_EXC_O|FP_EXC_Z|FP_EXC_V|FP_EXC_E)
289 #define FP_EXC_I 0x1000 /* inexact operation */
290 #define FP_EXC_U 0x2000 /* underflow */
291 #define FP_EXC_O 0x4000 /* overflow */
292 #define FP_EXC_Z 0x8000 /* divide by zero */
293 #define FP_EXC_V 0x10000 /* invalid operation */
294 #define FP_EXC_E 0x20000 /* unimplemented operation */
297 #define C0_INX $0 /* Index into TLB Array - 4Kc core */
298 #define C0_RANDOM $1 /* Randomly generated index into TLB Array - 4Kc core */
299 #define C0_TLBLO0 $2 /* Low-order portion of the TLB entry for even-numbered virtual pages - 4Kc core */
300 #define C0_TLBLO1 $3 /* Low-order portion of the TLB entry for odd-numbered virtual pages - 4Kc core */
301 #define C0_PAGEMASK $5 /* Pointer to page table entry in memory - 4Kc core */
302 #define C0_WIRED $6 /* Number of fixed TLB entries - 4Kc core */
303 #define C0_TLBHI $10 /* High-order portion of the TLB entry - 4Kc core */
304 #define C0_PRId $15 /* Processor Identification and Revision */
305 #define C0_CONFIG $16 /* Configuration Register */
306 #define C0_LLADDR $17 /* Load linked address */
307 #define C0_LLADDR $17 /* Load linked address */
308 #define C0_DEBUG $23 /* Debug control and exception status */
309 #define C0_DEPC $24 /* Program counter at last debug exception */
310 #define C0_TAGLO $28 /* Low-order portion of cache tag interface */
311 #define C0_TAGHI $29 /* High-order portion of cache tag interface (not implemented in 4K cores */
312 #define C0_DESAVE $31 /* Debug handler scratch pad register */
320 #define PORT_WIDTH_CNTL_REG 0xffffe200
321 #define BUS_TURN_AROUND_REG 0xffffe204
322 #define BUS_TURN_AROUND_CNTRL_REG 0xb8000000
323 #define BUS_TURN_AROUND_VAL 0x00000000
325 #define ADDRESS_LATCH_TIMING_REG 0xB8000004
326 #define ADDRESS_LATCH_TIMING_VAL 0x00000007
328 #define PORT_WIDTH_CNTL_VAL 0xaa822aaa
329 #define SDRAM_TEST_PATTERN 0xaa55aa55
331 /* RC32134 Register Settings */
332 #define MEM_BASE_BASE 0xb8000080
333 #define MBA_REG0 0x1fc00000
334 #define MBM_REG0 0xffC00000
337 #define MEM_CTL_BASE 0xb8000200
338 #define MCR_CS0_BS 0x23ef23ef
339 #define MCR_CS1_BS 0x28632863
340 #define MCR_CS2_BS 0x60e760e7
341 #define MCR_CS3_BS 0x60e760e7 /* NVRAM */
342 #define MCR_CS4_BS 0x60e760e7 /* S334 LED */
343 #define MCR_CS5_BS 0x60e760e7
346 #define RHEA_IREG_BASE 0xb8000000
349 #define DRAM_BNK0_BASE 0x00000000
350 #define DRAM_BNK1_BASE 0x01000000
351 #define DRAM_BNK2_BASE 0x02000000
352 #define DRAM_BNK3_BASE 0x03000000
353 #define DRAM_BNK0_MASK 0xff000000
354 #define DRAM_BNK1_MASK 0xff000000
355 #define DRAM_BNK2_MASK 0xff000000
356 #define DRAM_BNK3_MASK 0xff000000
357 #define MBA_REG1 0x04000000
358 #define MBM_REG1 0xffff0000
359 #define SDRAM_CR_BS 0x8955c0ff
360 #define SDRAM_PC_VAL 0x8955c0a0
361 #define SDRAM_RFRSH_CMD 0x8955c090
362 #define SDRAM_MODE_REG 0x8955c080
363 #define SDRAM_CSEL_PARK 0x8955c0ff
364 #define TIMER_BASE 0xb8000700
365 #define DRAM_RF_CMPR_BS 0x00000040
366 #define DRAM_RF_CMPR_SE_BS 0x00000200
367 #define CPU_BERR_BS 0xff
368 #define IP_BERR_BS 0xff
369 #define DISABLE_TIMER 0x0
370 #define ENABLE_TIMER 0x1
372 #define CPU_CLOCK_RATE 75000000
375 /* define macro so drivers will call sysWbFlush() */
379 /* task default status register */
381 #define INT_LVL_PCI INT_LVL_IORQ1
382 #define INT_LVL_SR_IMASK (INT_LVL_PCI | INT_LVL_IORQ3 |\
383 INT_LVL_SW0 | INT_LVL_SW1 )
385 #define RC32364_SR (SR_CU0| INT_LVL_SR_IMASK |\
386 INT_LVL_TIMER | SR_IE)
388 /* interrupt priority */
390 #define INT_PRIO_MSB TRUE /* interrupt priority msb highest */
397 #define PIO_DATA_REG0 0xb8000600
398 #define PIO_FUNC_SELECT_REG0 0xb8000608
399 #define PIO_DATA_REG1 0xb8000610
400 #define PIO_DIRCNTL_REG1 0xb8000614
401 #define PIO_FUNC_SELECT_REG1 0xb8000618
402 #define CYG_MGMT_LED_MASK 0x00000008
403 #define CYG_STATUS_LED_MASK 0x00000003
404 #define CYG_TEST_LED1_MASK 0x00000002
405 #define CYG_TEST_LED2_MASK 0x00000004
406 #define CYG_STATUS_LED_GREEN 0x00000001
407 #define CYG_STATUS_LED_ORANGE 0x00000002
412 /* PIO definition for Internal Uart */
414 #define PIO_DIRCNTL_REG 0xb8000604
415 #define PIO_FUNCSEL_MASK 0xf0
416 #define PIO_DIRCNTL_MASK 0xffffff0f
417 #define PIO_DIRCNTL_VAL 0x50
420 /* Serial grouping */
422 #define SERIAL_PORT0_GROUP 5
423 #define SERIAL_PORT1_GROUP 6
425 /* Rc32134 Interrupt controller settings for Uart */
426 #define INTR_STATUS_PTR 0xb8000500
427 #define INTR_MASK_REG 0xb8000504
428 #define INTR_CLEAR_REG 0xb8000508
430 #define INTR_COM0_REG 0xb8000554
431 #define INTR_COM1_REG 0xb8000564
433 #define INTR_CLEAR_COM0 0xb8000558
434 #define INTR_PEND_COM0 0xb8000550
435 #define INTR_CLEAR_COM1 0xb8000568
436 #define INTR_PEND_COM1 0xb8000560
438 #define INTR_CLEAR_MASTER 0xb8000508
439 #define INTR_PEND_MASTER 0xb8000500
441 #define INTR_MASTERMASK_COM1 0x0020
442 #define INTR_MASTERMASK_COM2 0x0040
443 #define INTR_MASTERMASK_UART ( INTR_MASTERMASK_COM1 | INTR_MASTERMASK_COM2 )
445 /* Rc32134 Timer0(used as Auxiliary clock)interrupts */
446 #define AUX_TIMER_INTR_PEND 0xb8000540
447 #define AUX_TIMER_INTR_MASK 0xb8000544
448 #define AUX_TIMER_INTR_CLEAR 0xb8000548
449 #define INTR_MASTERMASK_TIMER0 0x0010
450 #define AUX_TIMER_CNTL_REG 0xb8000700
451 #define AUX_TIMER_CNT_REG 0xb8000704
452 #define AUX_TIMER_CMP_REG 0xb8000708
454 #define AUX_CLOCK_FREQ (2 * NS16550_XTAL_FREQ)
456 /* Rc32364 Tlb attributes for PCI transactions */
457 #define PCI_MMU_PAGEMASK 0x00000fff
458 #define MMU_PAGE_UNCACHED 0x00000010
459 #define MMU_PAGE_DIRTY 0x00000004
460 #define MMU_PAGE_VALID 0x00000002
461 #define MMU_PAGE_GLOBAL 0x00000001
462 #define PCI_MMU_PAGEATTRIB (MMU_PAGE_UNCACHED|MMU_PAGE_DIRTY|\
463 MMU_PAGE_VALID|MMU_PAGE_GLOBAL)
464 #define PCI_MEMORY_SPACE1 0x40000000
465 #define PCI_MEMORY_SPACE2 0x60000000
466 #define PCI_IO_SPACE 0x18000000
467 #define PCI_PAGE_SIZE 0x01000000
468 #define TLB_HI_MASK 0xffffe000
469 #define TLB_LO_MASK 0x3fffffff
470 #define PAGEMASK_SHIFT 13
471 #define TLB_LO_SHIFT 6
474 /* RC32134 PCI definitions */
475 #define PCI_CONFIG_ADDR_REG 0xb8002cf8
476 #define PCI_CONFIG_DATA_REG 0xb8002cfc
478 /* Rhea's Configuration Address*/
480 #define RHEA_CONFIG0_ADDR 0x80000000
481 #define RHEA_CONFIG1_ADDR 0x80000004
482 #define RHEA_CONFIG2_ADDR 0x80000008
483 #define RHEA_CONFIG3_ADDR 0x8000000c
484 #define RHEA_CONFIG4_ADDR 0x80000010
485 #define RHEA_CONFIG5_ADDR 0x80000014
486 #define RHEA_CONFIG6_ADDR 0x80000018
487 #define RHEA_CONFIG7_ADDR 0x8000001c
488 #define RHEA_CONFIG8_ADDR 0x80000020
489 #define RHEA_CONFIG9_ADDR 0x80000024
490 #define RHEA_CONFIG10_ADDR 0x80000028
491 #define RHEA_CONFIG11_ADDR 0x8000002c
492 #define RHEA_CONFIG12_ADDR 0x80000030
493 #define RHEA_CONFIG13_ADDR 0x80000034
494 #define RHEA_CONFIG14_ADDR 0x80000038
495 #define RHEA_CONFIG15_ADDR 0x8000003c
496 #define RHEA_CONFIG16_ADDR 0x80000040
498 /* Rhea's configuration Header */
500 #define RHEA_PCI_CONFIG0 0x032410b5 /* Device ID & Vendor ID */
501 #define RHEA_PCI_CONFIG1 0x02a00157 /* Status & Command */
502 #define RHEA_PCI_CONFIG2 0x06800001 /* Class Code & Revision ID */
503 #define RHEA_PCI_CONFIG3 0x0000ff04 /* BIST, Header Type, Latency, & Cacheline Size */
504 #define RHEA_PCI_CONFIG4 0xa0000000 /* PCI Memory Address that Rhea responds to. */
505 #define RHEA_PCI_CONFIG5 0x60000000 /* PCI Dual Cycle Address that Rhea responds to.*/
506 #define RHEA_PCI_CONFIG6 0x00800001 /* PCI I/O Address that Rhea responds to. */
507 #define RHEA_PCI_CONFIG7 0x00000000
508 #define RHEA_PCI_CONFIG8 0x00000000
509 #define RHEA_PCI_CONFIG9 0x00000000
510 #define RHEA_PCI_CONFIG10 0x00000000
511 #define RHEA_PCI_CONFIG11 0x013410b5
512 #define RHEA_PCI_CONFIG12 0x00000000
513 #define RHEA_PCI_CONFIG13 0x00000000
514 #define RHEA_PCI_CONFIG14 0x00000000
515 #define RHEA_PCI_CONFIG15 0x38080101
517 /* Because of an errata in Rc32134 Pci Bridge, Scanning does not work properly.
518 The device number is selected based on which pci slot on S134 board is being
522 #define PCI_DEVICE_U28 2 /* PCI Slot U28 */
523 #define PCI_DEVICE_U29 3 /* PCI Slot U29 */
524 #define PCI_DEVICE_U20 4 /* PCI Slot U20 */
527 /* Latency for the Pci/Ethernet Card */
529 #define PCI_DEVICE_MAX_LATENCY 0x0000ff00
530 /* BusErrCntReg is used to disable/Enable BusError thrown on PCI
532 #define BUS_ERR_CNTL_REG_ADDR 0xb8000010
537 /* FEI PCI bus resources */
539 #define FEI_IO_MAP_USE
540 #define FEI_OFFSET_ADD
541 #define FEI0_MEMBASE0 0x40800000 /* memory base for CSR */
542 #define FEI0_MEMSIZE0 0x00001000 /* memory size for CSR, 4KB */
543 #define FEI0_MEMBASE1 0x40a00000 /* memory base for Flash */
544 #define FEI0_MEMSIZE1 0x00100000 /* memory size for Flash, 1MB */
545 #define FEI0_IOBASE0 0x18800000 /* IO base for CSR, 32Bytes */
546 #define FEI0_INT_LVL 0x1 /* IRQ 1 */
548 #define PCI_CFG_TYPE PCI_CFG_FORCE
550 /* Redefine PCI_CONFIG_ADDR & PCI_CONFIG_DATA */
552 #define CPU_TO_PCI_MEM_BASE 0x40000001
553 #define CPU_TO_PCI_IO_BASE 0x18800001
554 #define PCI_TO_CPU_MEM_BASE 0x00000000
555 #define PCI_TO_CPU_IO_BASE 0x00800001
557 #define IDT134_PCI_BASE 0xb8000000
559 #define IDT134_PCI_MEM_BAR1 (IDT134_PCI_BASE + 0x20B0)
560 #define IDT134_PCI_MEM_BAR2 (IDT134_PCI_BASE + 0x20B8)
561 #define IDT134_PCI_MEM_BAR3 (IDT134_PCI_BASE + 0x20C0)
562 #define IDT134_PCI_IO_BAR (IDT134_PCI_BASE + 0x20C8)
563 #define IDT134_PCI_ARB_REG (IDT134_PCI_BASE + 0x20E0)
564 #define IDT134_PCI_CPU_BAR1 (IDT134_PCI_BASE + 0x20E8)
565 #define IDT134_PCI_CPU_IO_BAR (IDT134_PCI_BASE + 0x2100)
566 #define IDT134_PCI_CONFIG_ADDR (IDT134_PCI_BASE + 0x2CF8)
567 #define IDT134_PCI_CONFIG_DATA (IDT134_PCI_BASE + 0x2CFC)
569 #define IDT134_BAR_MEM_SWAP 0x00000001
572 #endif /* CYGONCE_HAL_IDT79RC233X_H */
573 /*---------------------------------------------------------------------------*/
574 /* end of idt79rc233x.h */
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