packages/hal/powerpc/mpc8260/v2_0/include/var_cache.h

   1 #ifndef CYGONCE_VAR_CACHE_H
   2 #define CYGONCE_VAR_CACHE_H
   3 //=============================================================================
   4 //
   5 //      var_cache.h
   6 //
   7 //      Variant HAL cache control API
   8 //
   9 //=============================================================================
  10 //####ECOSGPLCOPYRIGHTBEGIN####
  11 // -------------------------------------------
  12 // This file is part of eCos, the Embedded Configurable Operating System.
  13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  14 // Copyright (C) 2002 Gary Thomas
  15 //
  16 // eCos is free software; you can redistribute it and/or modify it under
  17 // the terms of the GNU General Public License as published by the Free
  18 // Software Foundation; either version 2 or (at your option) any later version.
  19 //
  20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  22 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  23 // for more details.
  24 //
  25 // You should have received a copy of the GNU General Public License along
  26 // with eCos; if not, write to the Free Software Foundation, Inc.,
  27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  28 //
  29 // As a special exception, if other files instantiate templates or use macros
  30 // or inline functions from this file, or you compile this file and link it
  31 // with other works to produce a work based on this file, this file does not
  32 // by itself cause the resulting work to be covered by the GNU General Public
  33 // License. However the source code for this file must still be made available
  34 // in accordance with section (3) of the GNU General Public License.
  35 //
  36 // This exception does not invalidate any other reasons why a work based on
  37 // this file might be covered by the GNU General Public License.
  38 //
  39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  40 // at http://sources.redhat.com/ecos/ecos-license/
  41 // -------------------------------------------
  42 //####ECOSGPLCOPYRIGHTEND####
  43 //=============================================================================
  44 //#####DESCRIPTIONBEGIN####
  45 //
  46 // Author(s):   pfine
  47 // Contributors:nickg, jskov
  48 // Date:        2001-12-12
  49 // Purpose:     Variant cache control API
  50 // Description: The macros defined here provide the HAL APIs for handling
  51 //              cache control operations on the MPC8260 variant CPU.
  52 // Usage:       Is included via the architecture cache header:
  53 //              #include <cyg/hal/hal_cache.h>
  54 //              ...
  55 //
  56 //####DESCRIPTIONEND####
  57 //
  58 //=============================================================================
  59
  60 #include <pkgconf/hal.h>
  61 #include <cyg/infra/cyg_type.h>
  62
  63 #include <cyg/hal/ppc_regs.h>
  64 #include <cyg/hal/var_regs.h>
  65
  66 #include <cyg/hal/plf_cache.h>
  67
  68 //-----------------------------------------------------------------------------
  69 // Cache dimensions
  70
  71 // Data cache
  72 #define HAL_DCACHE_SIZE                 16384    // Size of data cache in bytes
  73 #define HAL_DCACHE_LINE_SIZE            32       // Size of a data cache line
  74 #define HAL_DCACHE_WAYS                 4        // Associativity of the cache
  75
  76 // Instruction cache
  77 #define HAL_ICACHE_SIZE                 16384    // Size of cache in bytes
  78 #define HAL_ICACHE_LINE_SIZE            32       // Size of a cache line
  79 #define HAL_ICACHE_WAYS                 4        // Associativity of the cache
  80
  81 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
  82 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
  83
  84 //-----------------------------------------------------------------------------
  85 // Global control of data cache
  86
  87 // Enable the data cache
  88 #define HAL_DCACHE_ENABLE()                 \
  89     CYG_MACRO_START                         \
  90     cyg_uint32 tmp1, tmp2;                  \
  91     asm volatile (                          \
  92         "mfspr %1, %2;"                     \
  93         "li %0, 0x4000;"                     \
  94         "rlwimi %1,%0,0,17,17;"             \
  95         "sync;"                             \
  96         "mtspr %2,%1;"                      \
  97         "isync;"                            \
  98         "sync;"                             \
  99         : "=r" (tmp1), "=r" (tmp2)          \
 100         : "I" (CYGARC_REG_HID0) /* %2 ==> HID0 */); \
 101     CYG_MACRO_END
 102
 103 // Disable the data cache
 104 #define HAL_DCACHE_DISABLE()                \
 105     CYG_MACRO_START                         \
 106     register cyg_uint32 tmp1;               \
 107     register cyg_uint32 tmp2;               \
 108     for (tmp1 = 0; tmp1 < HAL_DCACHE_SIZE; tmp1 += HAL_DCACHE_LINE_SIZE) \
 109         tmp2 = *((cyg_uint32 *) tmp1);      \
 110     asm volatile (                          \
 111         "mfspr %1, %2;"                     \
 112         "li %0, 0x0;"                       \
 113         "rlwimi %1,%0,0,17,17;"             \
 114         "sync;"                             \
 115         "mtspr %2,%1;"                      \
 116         "isync;"                            \
 117         "sync;"                             \
 118         : "=r" (tmp1), "=r" (tmp2)          \
 119         : "I" (CYGARC_REG_HID0) /* %2 ==> HID0 */); \
 120     CYG_MACRO_END
 121
 122 // Invalidate the entire cache
 123 #define HAL_DCACHE_INVALIDATE_ALL()                   \
 124     CYG_MACRO_START                                   \
 125     cyg_uint32 tmp1, tmp2;                            \
 126     asm volatile ("sync;"                             \
 127                   "mfspr %0, %2;"                     \
 128                   "ori   %0, %0, 0x0400;"             \
 129                   "mtspr %2, %0;"                     \
 130                   "li    %1, 0;"                      \
 131                   "rlwimi %0,%1,0,21,21;"             \
 132                   "mtspr %2, %0;"                     \
 133                   "sync;"                             \
 134                   : "=r" (tmp1), "=r" (tmp2)          \
 135                   : "I" (CYGARC_REG_HID0) /* %3 ==> HID0 */);\
 136     CYG_MACRO_END
 137
 138
 139 // Synchronize the contents of the cache with memory.
 140 // Modifications to this macro should mirror modifications to the
 141 // identically named one in the ppc60x variant.
 142 // We step through twice the number of lines in the cache in order
 143 // to ensure that all dirty lines are flushed to main memory.
 144 // (Consider the case where one of the dirty lines is in the
 145 // first 16Kbytes of RAM -- it won't get flushed by loading
 146 // in words from the first 16Kbytes of RAM).
 147 #define HAL_DCACHE_SYNC()                                       \
 148     CYG_MACRO_START                                             \
 149     cyg_int32 i;                                                \
 150     cyg_uint32 *__base = (cyg_uint32 *) (0);                    \
 151     for(i=0;i< (2 * HAL_DCACHE_SIZE/HAL_DCACHE_LINE_SIZE);i++,__base += HAL_DCACHE_LINE_SIZE/4){                                                 \
 152         asm volatile ("lwz %%r0,0(%0);"::"r"(__base):"r0");     \
 153     }                                                           \
 154     CYG_MACRO_END
 155
 156 // Query the state of the data cache
 157 #define HAL_DCACHE_IS_ENABLED(_state_)                          \
 158     asm volatile ("mfspr  %0, %1;"                              \
 159                   "rlwinm %0,%0,18,31,31;"                      \
 160                   : "=r" (_state_) : "I" (CYGARC_REG_HID0))
 161
 162 // Set the data cache refill burst size
 163 //#define HAL_DCACHE_BURST_SIZE(_size_)
 164
 165 // Set the data cache write mode
 166 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
 167
 168 //#define HAL_DCACHE_WRITETHRU_MODE       0
 169 //#define HAL_DCACHE_WRITEBACK_MODE       1
 170
 171 // Load the contents of the given address range into the data cache
 172 // and then lock the cache so that it stays there.
 173 //#define HAL_DCACHE_LOCK(_base_, _size_)
 174
 175 // Undo a previous lock operation
 176 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
 177
 178 // Unlock entire cache
 179 #define HAL_DCACHE_UNLOCK_ALL()                       \
 180     asm volatile ("isync;"                            \
 181                   "mfspr %0, %2;"                     \
 182                   "oris  %1, 0,0xFFFF;"               \
 183                   "ori   %1,%1,0xEFFF;"               \
 184                   "and   %0,%0,%1;"                   \
 185                   "mtspr %2,%0;"                      \
 186                   "isync;"                            \
 187                   "sync;"                             \
 188                   : /* No output */                   \
 189                   : "I" (5) /* %0 ==> r5 */,          \
 190                     "I" (6) /* %1 ==> r6 */,          \
 191                     "I" (CYGARC_REG_HID0) /* %2 ==> HID0 */);
 192
 193 //-----------------------------------------------------------------------------
 194 // Data cache line control
 195
 196 // Allocate cache lines for the given address range without reading its
 197 // contents from memory.
 198 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
 199
 200 // Write dirty cache lines to memory and invalidate the cache entries
 201 // for the given address range.
 202 #define HAL_DCACHE_FLUSH( _base_ , _size_ )                     \
 203     CYG_MACRO_START                                             \
 204     cyg_uint32 __base = (cyg_uint32) (_base_);                  \
 205     cyg_int32 __size = (cyg_int32) (_size_);                    \
 206     while (__size > 0) {                                        \
 207         asm volatile ("dcbf 0,%0;sync;" : : "r" (__base));      \
 208         __base += HAL_DCACHE_LINE_SIZE;                         \
 209         __size -= HAL_DCACHE_LINE_SIZE;                         \
 210     }                                                           \
 211     CYG_MACRO_END
 212
 213
 214 // Invalidate cache lines in the given range without writing to memory.
 215 // NOTE: The errata for the 603e processor indicates use of the dcbf
 216 // command as the dcbi command will only invalidate modified blocks.
 217 #define HAL_DCACHE_INVALIDATE( _base_ , _size_ )                \
 218     CYG_MACRO_START                                             \
 219     cyg_uint32 __base = (cyg_uint32) (_base_);                  \
 220     cyg_int32 __size = (cyg_int32) (_size_);                    \
 221     while (__size > 0) {                                        \
 222         asm volatile ("dcbf 0,%0;sync;" : : "r" (__base));      \
 223         __base += HAL_DCACHE_LINE_SIZE;                         \
 224         __size -= HAL_DCACHE_LINE_SIZE;                         \
 225     }                                                           \
 226     CYG_MACRO_END
 227
 228 // Write dirty cache lines to memory for the given address range.
 229 #define HAL_DCACHE_STORE( _base_ , _size_ )                     \
 230     CYG_MACRO_START                                             \
 231     cyg_uint32 __base = (cyg_uint32) (_base_);                  \
 232     cyg_int32 __size = (cyg_int32) (_size_);                    \
 233     while (__size > 0) {                                        \
 234         asm volatile ("dcbst 0,%0;sync;" : : "r" (__base));     \
 235         __base += HAL_DCACHE_LINE_SIZE;                         \
 236         __size -= HAL_DCACHE_LINE_SIZE;                         \
 237     }                                                           \
 238     CYG_MACRO_END
 239
 240 // Preread the given range into the cache with the intention of reading
 241 // from it later.
 242 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
 243
 244 // Preread the given range into the cache with the intention of writing
 245 // to it later.
 246 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
 247
 248 // Allocate and zero the cache lines associated with the given range.
 249 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
 250
 251 //-----------------------------------------------------------------------------
 252 // Global control of Instruction cache
 253
 254 // Enable the instruction cache
 255 #define HAL_ICACHE_ENABLE()                 \
 256     CYG_MACRO_START                         \
 257     cyg_uint32 tmp1, tmp2;                  \
 258     asm volatile (                          \
 259         "mfspr %1, %2;"                     \
 260         "li %0, 0x4000;"                    \
 261         "rlwimi %1,%0,1,16,16;"             \
 262         "sync;"                             \
 263         "isync;"                            \
 264         "mtspr %2,%1;"                      \
 265         "isync;"                            \
 266         "sync;"                             \
 267         : "=r" (tmp1), "=r" (tmp2)          \
 268         : "I" (CYGARC_REG_HID0) /* %2 ==> HID0 */); \
 269     CYG_MACRO_END
 270
 271 // Disable the instruction cache
 272 #define HAL_ICACHE_DISABLE()                          \
 273     CYG_MACRO_START                         \
 274     cyg_uint32 tmp1, tmp2;                  \
 275     asm volatile (                          \
 276         "mfspr %1, %2;"                     \
 277         "li %0, 0x0;"                       \
 278         "rlwimi %1,%0,0,16,16;"             \
 279         "sync;"                             \
 280         "isync;"                            \
 281         "mtspr %2,%1;"                      \
 282         "isync;"                            \
 283         "sync;"                             \
 284         : "=r" (tmp1), "=r" (tmp2)          \
 285         : "I" (CYGARC_REG_HID0) /* %2 ==> HID0 */); \
 286     CYG_MACRO_END
 287
 288 // Invalidate the entire cache
 289 #if 1
 290 #define HAL_ICACHE_INVALIDATE_ALL()                   \
 291     CYG_MACRO_START                                   \
 292     cyg_uint32 tmp1, tmp2;                            \
 293     asm volatile ("sync;"                             \
 294                   "mfspr %0, %2;"                     \
 295                   "ori   %1, %0, 0x8000;"             \
 296                   "mtspr %2, %1;"                     \
 297                   "isync;"                            \
 298                   "sync;"                             \
 299                   "ori   %1, %1, 0x0800;"             \
 300                   "mtspr %2, %1;"                     \
 301                   "isync;"                            \
 302                   "sync;"                             \
 303                   "mtspr %2, %0;"                     \
 304                   "isync;"                            \
 305                   "sync;"                             \
 306                   : "=r" (tmp1), "=r" (tmp2)          \
 307                   : "I" (CYGARC_REG_HID0) /* %3 ==> HID0 */);\
 308     CYG_MACRO_END
 309 #else
 310 #define HAL_ICACHE_INVALIDATE_ALL()                   \
 311     CYG_MACRO_START                                   \
 312     cyg_uint32 tmp1, tmp2;                            \
 313     asm volatile ("sync;"                             \
 314                   "mfspr %0, %2;"                     \
 315                   "ori   %0, %0, 0x0800;"             \
 316                   "isync;"                            \
 317                   "mtspr %2, %0;"                     \
 318                   "li    %1, 0;"                      \
 319                   "rlwimi %0,%1,0,20,20;"             \
 320                   "isync;"                            \
 321                   "mtspr %2, %0;"                     \
 322                   "isync;"                            \
 323                   "sync;"                             \
 324                   : "=r" (tmp1), "=r" (tmp2)          \
 325                   : "I" (CYGARC_REG_HID0) /* %3 ==> HID0 */);\
 326     CYG_MACRO_END
 327 #endif
 328 // Synchronize the contents of the cache with memory.
 329 #define HAL_ICACHE_SYNC()                             \
 330     HAL_ICACHE_INVALIDATE_ALL()
 331
 332
 333 // Query the state of the instruction cache
 334 #define HAL_ICACHE_IS_ENABLED(_state_)                          \
 335     asm volatile ("mfspr  %0, %1;"                              \
 336                   "rlwinm %0,%0,17,31,31;"                      \
 337                   : "=r" (_state_) : "I" (CYGARC_REG_HID0))
 338
 339
 340 // Set the instruction cache refill burst size
 341 //#define HAL_ICACHE_BURST_SIZE(_size_)
 342
 343 // Load the contents of the given address range into the instruction cache
 344 // and then lock the cache so that it stays there.
 345 //#define HAL_ICACHE_LOCK(_base_, _size_)
 346
 347 // Undo a previous lock operation
 348 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
 349
 350 // Unlock entire cache
 351 #define HAL_ICACHE_UNLOCK_ALL()                       \
 352     asm volatile ("isync;"                            \
 353                   "mfspr %0, %2;"                     \
 354                   "oris  %1, 0,0xFFFF;"               \
 355                   "ori   %1,%1,0xDFFF;"               \
 356                   "and   %0,%0,%1;"                   \
 357                   "isync;"                            \
 358                   "mtspr %2,%0;"                      \
 359                   "isync;"                            \
 360                   "sync;"                             \
 361                   : /* No output */                   \
 362                   : "I" (5) /* %0 ==> r5 */,          \
 363                     "I" (6) /* %1 ==> r6 */,          \
 364                     "I" (CYGARC_REG_HID0) /* %2 ==> HID0 */);
 365
 366 //-----------------------------------------------------------------------------
 367 // Instruction cache line control
 368
 369 // Invalidate cache lines in the given range without writing to memory.
 370 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
 371
 372 //-----------------------------------------------------------------------------
 373 #endif // ifndef CYGONCE_VAR_CACHE_H
 374 // End of var_cache.h