packages/hal/sh/arch/v2_0/include/hal_intr_excevt.h

   1 #ifndef CYGONCE_HAL_INTR_EXCEVT_H
   2 #define CYGONCE_HAL_INTR_EXCEVT_H
   3
   4 //==========================================================================
   5 //
   6 //      hal_intr_excevt.h
   7 //
   8 //      HAL Interrupt and clock support for variants with EXCEVT style
   9 //      exception/interrupt mapping (SH3, SH4)
  10 //
  11 //==========================================================================
  12 //####ECOSGPLCOPYRIGHTBEGIN####
  13 // -------------------------------------------
  14 // This file is part of eCos, the Embedded Configurable Operating System.
  15 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  16 //
  17 // eCos is free software; you can redistribute it and/or modify it under
  18 // the terms of the GNU General Public License as published by the Free
  19 // Software Foundation; either version 2 or (at your option) any later version.
  20 //
  21 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  22 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  23 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  24 // for more details.
  25 //
  26 // You should have received a copy of the GNU General Public License along
  27 // with eCos; if not, write to the Free Software Foundation, Inc.,
  28 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  29 //
  30 // As a special exception, if other files instantiate templates or use macros
  31 // or inline functions from this file, or you compile this file and link it
  32 // with other works to produce a work based on this file, this file does not
  33 // by itself cause the resulting work to be covered by the GNU General Public
  34 // License. However the source code for this file must still be made available
  35 // in accordance with section (3) of the GNU General Public License.
  36 //
  37 // This exception does not invalidate any other reasons why a work based on
  38 // this file might be covered by the GNU General Public License.
  39 //
  40 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  41 // at http://sources.redhat.com/ecos/ecos-license/
  42 // -------------------------------------------
  43 //####ECOSGPLCOPYRIGHTEND####
  44 //==========================================================================
  45 //#####DESCRIPTIONBEGIN####
  46 //
  47 // Author(s):    jskov
  48 // Contributors: jskov,
  49 // Date:         1999-04-24
  50 // Purpose:      Define Interrupt support
  51 // Description:  The macros defined here provide the HAL APIs for handling
  52 //               interrupts and the clock.
  53 //
  54 // Usage:        Is included from <cyg/hal/hal_intr.h>
  55 //
  56 //####DESCRIPTIONEND####
  57 //
  58 //==========================================================================
  59
  60 //--------------------------------------------------------------------------
  61 // SH exception vectors. These correspond to VSRs and are the values
  62 // to use for HAL_VSR_GET/SET
  63 //
  64 // Note that exceptions are decoded - there is a VSR slot for each exception
  65 // source, while interrupts are handled via the same VSR.
  66
  67 #define CYGNUM_HAL_VECTOR_POWERON                0 // power-on
  68 #define CYGNUM_HAL_VECTOR_RESET                  1 // reset
  69 #define CYGNUM_HAL_VECTOR_TLBMISS_ACCESS         2 // TLB-miss/invalid load
  70 #define CYGNUM_HAL_VECTOR_TLBMISS_WRITE          3 // TLB-miss/invalid store
  71 #define CYGNUM_HAL_VECTOR_INITIAL_WRITE          4 // initial page write
  72 #define CYGNUM_HAL_VECTOR_TLBERROR_ACCESS        5 // TLB prot violation l
  73 #define CYGNUM_HAL_VECTOR_TLBERROR_WRITE         6 // TLB prot violation s
  74 #define CYGNUM_HAL_VECTOR_DATA_ACCESS            7 // address error (load)
  75 #define CYGNUM_HAL_VECTOR_DATA_WRITE             8 // address error (store)
  76 // RESERVED 9-10
  77 #define CYGNUM_HAL_VECTOR_TRAP                  11 // unconditional trap
  78 #define CYGNUM_HAL_VECTOR_ILLEGAL_INSTRUCTION   12 // reserved instruction
  79 #define CYGNUM_HAL_VECTOR_ILLEGAL_SLOT_INSTRUCTION  13
  80                                            // illegal instruction in delay slot
  81 #define CYGNUM_HAL_VECTOR_NMI                   14 // NMI
  82 #define CYGNUM_HAL_VECTOR_INSTRUCTION_BP        15 // user breakpoint
  83
  84 #define CYGNUM_HAL_VECTOR_INTERRUPT             16 // all interrupts
  85
  86 #ifndef CYG_VECTOR_IS_INTERRUPT
  87 # define CYG_VECTOR_IS_INTERRUPT(v) (CYGNUM_HAL_VECTOR_INSTRUCTION_BP < (v))
  88 #endif
  89
  90 #define CYGNUM_HAL_VSR_MIN                   CYGNUM_HAL_VECTOR_POWERON
  91 #ifndef CYGNUM_HAL_VSR_MAX
  92 # define CYGNUM_HAL_VSR_MAX                  CYGNUM_HAL_VECTOR_INTERRUPT
  93 #endif
  94 #define CYGNUM_HAL_VSR_COUNT                 ( CYGNUM_HAL_VSR_MAX + 1 )
  95
  96 #ifndef CYGNUM_HAL_VSR_EXCEPTION_COUNT
  97 # define CYGNUM_HAL_VSR_EXCEPTION_COUNT       (CYGNUM_HAL_VECTOR_INSTRUCTION_BP-CYGNUM_HAL_VECTOR_POWERON+1)
  98 #endif
  99
 100 // For the stub exception handling
 101 #define _CYGNUM_HAL_VECTOR_FIRST_MEM_FAULT       CYGNUM_HAL_EXCEPTION_TLBMISS_ACCESS
 102 #define _CYGNUM_HAL_VECTOR_LAST_MEM_FAULT        CYGNUM_HAL_EXCEPTION_DATA_WRITE
 103
 104 // The decoded interrupts.
 105 #define CYGNUM_HAL_INTERRUPT_NMI             0
 106 #define CYGNUM_HAL_INTERRUPT_RESERVED_1E0    1
 107 #define CYGNUM_HAL_INTERRUPT_LVL0            2
 108 #define CYGNUM_HAL_INTERRUPT_LVL1            3
 109 #define CYGNUM_HAL_INTERRUPT_LVL2            4
 110 #define CYGNUM_HAL_INTERRUPT_LVL3            5
 111 #define CYGNUM_HAL_INTERRUPT_LVL4            6
 112 #define CYGNUM_HAL_INTERRUPT_LVL5            7
 113 #define CYGNUM_HAL_INTERRUPT_LVL6            8
 114 #define CYGNUM_HAL_INTERRUPT_LVL7            9
 115 #define CYGNUM_HAL_INTERRUPT_LVL8            10
 116 #define CYGNUM_HAL_INTERRUPT_LVL9            11
 117 #define CYGNUM_HAL_INTERRUPT_LVL10           12
 118 #define CYGNUM_HAL_INTERRUPT_LVL11           13
 119 #define CYGNUM_HAL_INTERRUPT_LVL12           14
 120 #define CYGNUM_HAL_INTERRUPT_LVL13           15
 121 #define CYGNUM_HAL_INTERRUPT_LVL14           16
 122 #define CYGNUM_HAL_INTERRUPT_RESERVED_3E0    17
 123 #define CYGNUM_HAL_INTERRUPT_TMU0_TUNI0      18
 124 #define CYGNUM_HAL_INTERRUPT_TMU1_TUNI1      19
 125 #define CYGNUM_HAL_INTERRUPT_TMU2_TUNI2      20
 126 #define CYGNUM_HAL_INTERRUPT_TMU2_TICPI2     21
 127 #define CYGNUM_HAL_INTERRUPT_RTC_ATI         22
 128 #define CYGNUM_HAL_INTERRUPT_RTC_PRI         23
 129 #define CYGNUM_HAL_INTERRUPT_RTC_CUI         24
 130 #define CYGNUM_HAL_INTERRUPT_SCI_ERI         25
 131 #define CYGNUM_HAL_INTERRUPT_SCI_RXI         26
 132 #define CYGNUM_HAL_INTERRUPT_SCI_TXI         27
 133 #define CYGNUM_HAL_INTERRUPT_SCI_TEI         28
 134 #define CYGNUM_HAL_INTERRUPT_WDT_ITI         29
 135 #define CYGNUM_HAL_INTERRUPT_REF_RCMI        30
 136 #define CYGNUM_HAL_INTERRUPT_REF_ROVI        31
 137
 138 #ifndef CYGNUM_HAL_ISR_MAX
 139 # define CYGNUM_HAL_ISR_MAX                  CYGNUM_HAL_INTERRUPT_REF_ROVI
 140 #endif
 141
 142 #define CYGNUM_HAL_ISR_MIN                   CYGNUM_HAL_INTERRUPT_NMI
 143 #define CYGNUM_HAL_ISR_COUNT                 ( CYGNUM_HAL_ISR_MAX - CYGNUM_HAL_ISR_MIN + 1 )
 144
 145 // The vector used by the Real time clock
 146 #ifndef CYGNUM_HAL_INTERRUPT_RTC
 147 # define CYGNUM_HAL_INTERRUPT_RTC             CYGNUM_HAL_INTERRUPT_TMU0_TUNI0
 148 #endif
 149
 150 //--------------------------------------------------------------------------
 151 // Exception vectors. These are the values used when passed out to an
 152 // external exception handler using cyg_hal_deliver_exception()
 153
 154 // The exception indexes are EXPEVT/0x20. Variants may define additional
 155 // exception vectors.
 156
 157 #define CYGNUM_HAL_EXCEPTION_POWERON                0 // power-on
 158 #define CYGNUM_HAL_EXCEPTION_RESET                  1 // reset
 159 #define CYGNUM_HAL_EXCEPTION_TLBMISS_ACCESS         2 // TLB-miss/invalid load
 160 #define CYGNUM_HAL_EXCEPTION_TLBMISS_WRITE          3 // TLB-miss/invalid store
 161 #define CYGNUM_HAL_EXCEPTION_INITIAL_WRITE          4 // initial page write
 162 #define CYGNUM_HAL_EXCEPTION_TLBERROR_ACCESS        5 // TLB prot violation l
 163 #define CYGNUM_HAL_EXCEPTION_TLBERROR_WRITE         6 // TLB prot violation s
 164 #define CYGNUM_HAL_EXCEPTION_DATA_ACCESS            7 // address error (load)
 165 #define CYGNUM_HAL_EXCEPTION_DATA_WRITE             8 // address error (store)
 166 #define CYGNUM_HAL_EXCEPTION_TRAP                  11 // unconditional trap
 167 #define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION   12 // reserved instruction
 168 #define CYGNUM_HAL_EXCEPTION_ILLEGAL_SLOT_INSTRUCTION  13
 169                                            // illegal instruction in delay slot
 170 #define CYGNUM_HAL_EXCEPTION_INSTRUCTION_BP        15 // user breakpoint
 171
 172 #define CYGNUM_HAL_EXCEPTION_MIN          CYGNUM_HAL_EXCEPTION_POWERON
 173
 174 #ifndef CYGNUM_HAL_EXCEPTION_MAX
 175 # define CYGNUM_HAL_EXCEPTION_MAX         CYGNUM_HAL_EXCEPTION_INSTRUCTION_BP
 176 #endif
 177
 178 #define CYGNUM_HAL_EXCEPTION_COUNT           \
 179                  ( CYGNUM_HAL_EXCEPTION_MAX - CYGNUM_HAL_EXCEPTION_MIN + 1 )
 180
 181 #ifndef __ASSEMBLER__
 182
 183 #include <cyg/infra/cyg_type.h>
 184
 185 #include <cyg/hal/sh_regs.h>            // register definitions
 186 #include <cyg/hal/hal_io.h>             // io macros
 187 #include <cyg/infra/cyg_ass.h>          // CYG_FAIL
 188
 189 //--------------------------------------------------------------------------
 190 // Clock control, using TMU counter 0.
 191
 192 #define CYGHWR_SH_RTC_TIMER_IS_TMU
 193
 194 #define HAL_CLOCK_INITIALIZE( _period_ )                                    \
 195     CYG_MACRO_START                                                         \
 196     register cyg_uint8 _tstr_;                                              \
 197                                                                             \
 198     /* Disable timer while programming it. */                               \
 199     HAL_READ_UINT8(CYGARC_REG_TSTR, _tstr_);                                \
 200     _tstr_ &= ~CYGARC_REG_TSTR_STR0;                                        \
 201     HAL_WRITE_UINT8(CYGARC_REG_TSTR, _tstr_);                               \
 202                                                                             \
 203     /* Set counter registers. */                                            \
 204     HAL_WRITE_UINT32(CYGARC_REG_TCOR0, (_period_));                         \
 205     HAL_WRITE_UINT32(CYGARC_REG_TCNT0, (_period_));                         \
 206                                                                             \
 207     /* Set interrupt on underflow and decrement frequency */                \
 208     HAL_WRITE_UINT16(CYGARC_REG_TCR0, CYGARC_REG_TCR_UNIE |                 \
 209                      ((4==CYGHWR_HAL_SH_TMU_PRESCALE_0) ?                   \
 210                           CYGARC_REG_TCR_TPSC_4 :                           \
 211                       (16==CYGHWR_HAL_SH_TMU_PRESCALE_0) ?                  \
 212                           CYGARC_REG_TCR_TPSC_16:                           \
 213                       (64==CYGHWR_HAL_SH_TMU_PRESCALE_0) ?                  \
 214                           CYGARC_REG_TCR_TPSC_64:CYGARC_REG_TCR_TPSC_256)); \
 215                                                                             \
 216                                                                             \
 217     /* Enable timer. */                                                     \
 218     _tstr_ |= CYGARC_REG_TSTR_STR0;                                         \
 219     HAL_WRITE_UINT8(CYGARC_REG_TSTR, _tstr_);                               \
 220                                                                             \
 221     CYG_MACRO_END
 222
 223 #define HAL_CLOCK_RESET( _vector_, _period_ )           \
 224     CYG_MACRO_START                                     \
 225     register cyg_uint16 _tcr_;                          \
 226                                                         \
 227     /* Clear underflow flag. */                         \
 228     HAL_READ_UINT16(CYGARC_REG_TCR0, _tcr_);            \
 229     _tcr_ &= ~CYGARC_REG_TCR_UNF;                       \
 230     HAL_WRITE_UINT16(CYGARC_REG_TCR0, _tcr_);           \
 231     HAL_READ_UINT16(CYGARC_REG_TCR0, _tcr_);            \
 232                                                         \
 233     CYG_MACRO_END
 234
 235 #define HAL_CLOCK_READ( _pvalue_ )                              \
 236     CYG_MACRO_START                                             \
 237     register cyg_uint32 _result_;                               \
 238                                                                 \
 239     HAL_READ_UINT32(CYGARC_REG_TCNT0, _result_);                \
 240                                                                 \
 241     *(_pvalue_) = CYGNUM_KERNEL_COUNTERS_RTC_PERIOD-_result_;   \
 242     CYG_MACRO_END
 243
 244 #ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
 245 #define HAL_CLOCK_LATENCY( _pvalue_ ) HAL_CLOCK_READ(_pvalue_)
 246 #endif
 247
 248 externC void hal_delay_us(int);
 249 #define HAL_DELAY_US(n) hal_delay_us(n)
 250
 251 #endif // __ASSEMBLER__
 252
 253 //--------------------------------------------------------------------------
 254 #endif // ifndef CYGONCE_HAL_INTR_EXCEVT_H
 255 // End of hal_intr_excevt.h