1 #ifndef CYGONCE_HAL_PLATFORM_INC
2 #define CYGONCE_HAL_PLATFORM_INC
3 ##=============================================================================
7 ## Hitachi SE77x9 board assembler header file
9 ##=============================================================================
10 #####ECOSGPLCOPYRIGHTBEGIN####
11 ## -------------------------------------------
12 ## This file is part of eCos, the Embedded Configurable Operating System.
13 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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28 ## As a special exception, if other files instantiate templates or use macros
29 ## or inline functions from this file, or you compile this file and link it
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32 ## License. However the source code for this file must still be made available
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40 ## -------------------------------------------
41 #####ECOSGPLCOPYRIGHTEND####
42 ##=============================================================================
43 #######DESCRIPTIONBEGIN####
46 ## Contributors:jskov, gthomas
48 ## Purpose: Hitachi SE77x9 platform startup
49 ## Description: This file contains various definitions and macros that are
50 ## useful for writing assembly code for the Hitachi SE77x9
53 ## #include <cyg/hal/platform.inc>
57 ######DESCRIPTIONEND####
59 ##=============================================================================
61 #include <pkgconf/hal.h>
63 #include <cyg/hal/sh_offsets.inc>
64 #include <cyg/hal/sh_regs.h>
66 #------------------------------------------------------------------------------
67 # Hardware initialization.
69 .macro hal_hardware_init
70 #ifndef CYG_HAL_STARTUP_RAM
71 // Set up the Bus State Controller
72 mova BSC_settings_table,r0
74 1: mov.w @r3+,r0 // Address (or zero)
79 mov.w r1,@r0 // delay slot
83 .word CYGARC_REG_WTCSR, 0xA502
84 .word CYGARC_REG_WTCNT, 0x5A00
85 .word CYGARC_REG_FRQCR, CYGARC_REG_FRQCR_INIT
86 # Settings from Hitachi docs for SE7709A
87 #ifdef CYGNUM_HAL_SH_SE77X9_SDRAM_SETUP
88 .word CYGARC_REG_BCR1, 0x0008
90 .word CYGARC_REG_BCR1, 0x0810
92 .word CYGARC_REG_BCR2, 0x2ef0
93 .word CYGARC_REG_BCR3, 0x0000
94 .word CYGARC_REG_WCR1, 0x0c30
95 #ifdef CYGNUM_HAL_SH_SE77X9_SDRAM_SETUP
96 .word CYGARC_REG_WCR2, 0x7ddb
97 .word CYGARC_REG_MCR, 0x002c
99 .word CYGARC_REG_WCR2, 0x5d5a
100 .word CYGARC_REG_MCR, 0x0055
102 .word CYGARC_REG_DCR, 0x0000
103 .word CYGARC_REG_PCR, 0x0000
104 #ifdef CYGNUM_HAL_SH_SE77X9_SDRAM_SETUP
105 .word CYGARC_REG_RTCOR, 0xa580
107 .word CYGARC_REG_RTCOR, 0xa54e
109 .word CYGARC_REG_RFCR, 0xa400
110 .word CYGARC_REG_RTCNT, 0xa500
111 .word CYGARC_REG_RTCSR, 0xa508
115 #ifdef CYGNUM_HAL_SH_SE77X9_SDRAM_SETUP
116 mov.l $SDMR,r1 // Turns on SDRAM controller
120 mova Post_settings_table,r0
122 1: mov.l @r3+,r0 // Address (or zero)
125 mov.l @r3+,r1 // data
127 mov.w r1,@r0 // delay slot
130 #ifdef CYGNUM_HAL_SH_SE77X9_SDRAM_SETUP
131 $SDMR: .long 0xffffe088
137 .long CYGNUM_HAL_SH_SE77X9_LEDS_BASE,0x5555 // leds
140 #endif // CYG_HAL_STARTUP_RAM
143 #------------------------------------------------------------------------------
144 # Monitor initialization.
146 #ifndef CYGPKG_HAL_SH_MON_DEFINED
148 #if !defined(CYG_HAL_STARTUP_RAM) || \
149 ( defined(CYG_HAL_STARTUP_RAM) && \
150 !defined(CYGSEM_HAL_USE_ROM_MONITOR))
152 # If we are not starting up from RAM, or we are starting in
153 # RAM and NOT using a ROM monitor, initialize the VSR table.
156 mov.l $hal_vsr_table,r3
157 # Write exception vectors
158 mov.l $cyg_hal_default_exception_vsr,r4
159 mov #CYGNUM_HAL_VSR_EXCEPTION_COUNT,r5
164 # Write interrupt vector
165 mov.l $cyg_hal_default_interrupt_vsr,r4
166 mov.l $hal_vsr_table,r3
167 add #CYGNUM_HAL_VECTOR_INTERRUPT*4,r3
173 SYM_PTR_REF(cyg_hal_default_exception_vsr)
174 SYM_PTR_REF(cyg_hal_default_interrupt_vsr)
175 SYM_PTR_REF(hal_vsr_table)
179 #elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR)
181 # Initialize the VSR table entries
182 # We only take control of the interrupt vector,
183 # the rest are left to the ROM for now...
186 # Write interrupt vector
187 mov.l $hal_vsr_table,r3
188 mov.l $cyg_hal_default_interrupt_vsr,r4
189 add #CYGNUM_HAL_VECTOR_INTERRUPT*4,r3
195 SYM_PTR_REF(cyg_hal_default_interrupt_vsr)
196 SYM_PTR_REF(hal_vsr_table)
208 #define CYGPKG_HAL_SH_MON_DEFINED
210 #endif // CYGPKG_HAL_SH_MON_DEFINED
212 #endif // CYGONCE_HAL_PLATFORM_INC