packages/hal/sparclite/sleb/v2_0/include/hal_hwio.h

   1 #ifndef CYGONCE_HAL_HAL_HWIO_H
   2 #define CYGONCE_HAL_HAL_HWIO_H
   3
   4 /*=============================================================================
   5 //
   6 //      hal_hwio.h
   7 //
   8 //      HAL Support for IO to platform-specific devices
   9 //
  10 //=============================================================================
  11 //####ECOSGPLCOPYRIGHTBEGIN####
  12 // -------------------------------------------
  13 // This file is part of eCos, the Embedded Configurable Operating System.
  14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  15 //
  16 // eCos is free software; you can redistribute it and/or modify it under
  17 // the terms of the GNU General Public License as published by the Free
  18 // Software Foundation; either version 2 or (at your option) any later version.
  19 //
  20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  22 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  23 // for more details.
  24 //
  25 // You should have received a copy of the GNU General Public License along
  26 // with eCos; if not, write to the Free Software Foundation, Inc.,
  27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  28 //
  29 // As a special exception, if other files instantiate templates or use macros
  30 // or inline functions from this file, or you compile this file and link it
  31 // with other works to produce a work based on this file, this file does not
  32 // by itself cause the resulting work to be covered by the GNU General Public
  33 // License. However the source code for this file must still be made available
  34 // in accordance with section (3) of the GNU General Public License.
  35 //
  36 // This exception does not invalidate any other reasons why a work based on
  37 // this file might be covered by the GNU General Public License.
  38 //
  39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  40 // at http://sources.redhat.com/ecos/ecos-license/
  41 // -------------------------------------------
  42 //####ECOSGPLCOPYRIGHTEND####
  43 //=============================================================================
  44 //#####DESCRIPTIONBEGIN####
  45 //
  46 // Author(s):   hmt
  47 // Contributors:        hmt
  48 // Date:        1999-01-11
  49 // Purpose:     HAL Support for IO to platform-specific devices
  50 // Description: Macros to access the 86940 SPARClite companion chip
  51 // Usage:       #include <cyg/hal/hal_hwio.h>
  52 //
  53 //####DESCRIPTIONEND####
  54 //
  55 //===========================================================================*/
  56
  57 #include <pkgconf/system.h>
  58 #include <pkgconf/hal.h>
  59 #include <pkgconf/hal_sparclite.h>
  60 #include <pkgconf/hal_sparclite_sleb.h>
  61
  62 #include <cyg/infra/cyg_type.h>
  63
  64 /*---------------------------------------------------------------------------*/
  65 /* MB86940 flags and the like                                                */
  66
  67 /* Interrupt trigger modes. */
  68 #define HAL_SPARC_86940_TRIG_LEVEL_H   0   /* trigger on high level   */
  69 #define HAL_SPARC_86940_TRIG_LEVEL_L   1   /* trigger on low level    */
  70 #define HAL_SPARC_86940_TRIG_EDGE_H    2   /* trigger on rising edge  */
  71 #define HAL_SPARC_86940_TRIG_EDGE_L    3   /* trigger on falling edge */
  72
  73 /* Timer prescaler register values */
  74 #define HAL_SPARC_86940_PRS_EXTCLK    0x8000
  75 #define HAL_SPARC_86940_PRS_ODIV1     (0<<8)
  76 #define HAL_SPARC_86940_PRS_ODIV2     (1<<8)
  77 #define HAL_SPARC_86940_PRS_ODIV4     (2<<8)
  78 #define HAL_SPARC_86940_PRS_ODIV8     (3<<8)
  79 #define HAL_SPARC_86940_PRS_ODIV16    (4<<8)
  80 #define HAL_SPARC_86940_PRS_ODIV32    (5<<8)
  81 #define HAL_SPARC_86940_PRS_ODIV64    (6<<8)
  82 #define HAL_SPARC_86940_PRS_ODIV128   (7<<8)
  83
  84 /* Timer control register values */
  85 #define HAL_SPARC_86940_TCR_CE          (1<<11)
  86 #define HAL_SPARC_86940_TCR_CLKINT      (0<<9)
  87 #define HAL_SPARC_86940_TCR_CLKEXT      (1<<9)
  88 #define HAL_SPARC_86940_TCR_CLKPRS      (2<<9)
  89 #define HAL_SPARC_86940_TCR_CLKRSVD     (3<<9)
  90 #define HAL_SPARC_86940_TCR_OUTSAME     (0<<7)
  91 #define HAL_SPARC_86940_TCR_OUTHIGH     (1<<7)
  92 #define HAL_SPARC_86940_TCR_OUTLOW      (2<<7)
  93 #define HAL_SPARC_86940_TCR_OUTC3       (3<<7)
  94 #define HAL_SPARC_86940_TCR_INV         (1<<6)
  95 #define HAL_SPARC_86940_TCR_PER_INT     (0<<3)
  96 #define HAL_SPARC_86940_TCR_TO_INT      (1<<3)
  97 #define HAL_SPARC_86940_TCR_SQWAVE      (2<<3)
  98 #define HAL_SPARC_86940_TCR_SW_WATCH    (3<<3)
  99 #define HAL_SPARC_86940_TCR_HW_WATCH    (4<<3)
 100 #define HAL_SPARC_86940_TCR_LEVEL_L     0
 101 #define HAL_SPARC_86940_TCR_LEVEL_H     1
 102 #define HAL_SPARC_86940_TCR_EDGE_H      2
 103 #define HAL_SPARC_86940_TCR_EDGE_L      3
 104 #define HAL_SPARC_86940_TCR_EDGE        4
 105
 106 /* serial mode register values */
 107 #define HAL_SPARC_86940_SER_STOP0       (0<<6)
 108 #define HAL_SPARC_86940_SER_STOP1       (1<<6)
 109 #define HAL_SPARC_86940_SER_STOP1_5     (2<<6)
 110 #define HAL_SPARC_86940_SER_STOP2       (3<<6)
 111 #define HAL_SPARC_86940_SER_NO_PARITY   (0<<4)
 112 #define HAL_SPARC_86940_SER_ODD_PARITY  (1<<4)
 113 #define HAL_SPARC_86940_SER_EVEN_PARITY (3<<4)
 114 #define HAL_SPARC_86940_SER_5BITS       (0<<2)
 115 #define HAL_SPARC_86940_SER_6BITS       (1<<2)
 116 #define HAL_SPARC_86940_SER_7BITS       (2<<2)
 117 #define HAL_SPARC_86940_SER_8BITS       (3<<2)
 118 #define HAL_SPARC_86940_SER_MODE_SYNCH  0
 119 #define HAL_SPARC_86940_SER_DIV1_CLK    1
 120 #define HAL_SPARC_86940_SER_DIV16_CLK   2
 121 #define HAL_SPARC_86940_SER_DIV64_CLK   3
 122
 123 /* serial command register (asynch) */
 124 #define HAL_SPARC_86940_SER_CMD_EHM     (1<<7)
 125 #define HAL_SPARC_86940_SER_CMD_IRST    (1<<6)
 126 #define HAL_SPARC_86940_SER_CMD_RTS     (1<<5)
 127 #define HAL_SPARC_86940_SER_CMD_EFR     (1<<4)
 128 #define HAL_SPARC_86940_SER_CMD_BREAK   (1<<3)
 129 #define HAL_SPARC_86940_SER_CMD_RXEN    (1<<2)
 130 #define HAL_SPARC_86940_SER_CMD_DTR     (1<<1)
 131 #define HAL_SPARC_86940_SER_CMD_TXEN    (1<<0)
 132
 133 /* serial status register */
 134 #define HAL_SPARC_86940_SER_STAT_DSR    (1<<7)
 135 #define HAL_SPARC_86940_SER_STAT_BREAK  (1<<6)
 136 #define HAL_SPARC_86940_SER_STAT_FERR   (1<<5)
 137 #define HAL_SPARC_86940_SER_STAT_OERR   (1<<4)
 138 #define HAL_SPARC_86940_SER_STAT_PERR   (1<<3)
 139 #define HAL_SPARC_86940_SER_STAT_TXEMP  (1<<2)
 140 #define HAL_SPARC_86940_SER_STAT_RXRDY  (1<<1)
 141 #define HAL_SPARC_86940_SER_STAT_TXRDY  (1<<0)
 142
 143 #define HAL_SPARC_86940_CHIP_ASI        4
 144 #define HAL_SPARC_86940_CHIP_BASE       0x10000000
 145 #define HAL_SPARC_86940_REGADDR_SHIFT   2
 146 #define HAL_SPARC_86940_REGVAL_SHIFT    16
 147
 148 /*---------------------------------------------------------------------------*/
 149 /* Register addresses                                                        */
 150
 151 // The "interesting" IO parts are in Address Space Four:
 152 #define HAL_SPARC_ASI_4_READ( addr, res )                                   \
 153     asm volatile(                                                           \
 154         "lda [ %1 ] 4, %0"                                                  \
 155         : "=r"(res)                                                         \
 156         : "r"(addr)                                                         \
 157     );
 158
 159 #define HAL_SPARC_ASI_4_WRITE( addr, val )                                  \
 160     asm volatile(                                                           \
 161         "sta %0, [ %1 ] 4"                                                  \
 162         :                                                                   \
 163         : "r"(val),"r"(addr)                                                \
 164     );
 165
 166 #define HAL_SPARC_86940_BASE (0x10000000)  // in ASI 4
 167
 168 // The 86940 is connected to the upper 16 bits!
 169 #define HAL_SPARC_86940_READ( reg, result ) CYG_MACRO_START                 \
 170         cyg_uint32 hires;                                                   \
 171         HAL_SPARC_ASI_4_READ( reg + HAL_SPARC_86940_BASE, hires );          \
 172         hires >>= 16;                                                       \
 173         result = hires;                                                     \
 174 CYG_MACRO_END
 175
 176 // THIS IS ONLY HERE FOR DEBUGGING:
 177 // The 86940 is connected to the upper 16 bits!
 178 // And seems to be an unreliable deprecated thing...
 179 // so read it 3 times and believe the majority.
 180 #define HAL_SPARC_86940_READ3( reg, result ) CYG_MACRO_START                \
 181         cyg_uint32 hires1;                                                  \
 182         cyg_uint32 hires2;                                                  \
 183         cyg_uint32 hires3;                                                  \
 184         HAL_SPARC_ASI_4_READ( reg + HAL_SPARC_86940_BASE, hires1 );         \
 185         HAL_SPARC_ASI_4_READ( reg + HAL_SPARC_86940_BASE, hires2 );         \
 186         HAL_SPARC_ASI_4_READ( reg + HAL_SPARC_86940_BASE, hires3 );         \
 187         result = ((hires1&hires2)|(hires1&hires3)|(hires2&hires3)) >> 16;   \
 188 CYG_MACRO_END
 189
 190 #define HAL_SPARC_86940_WRITE( reg, value ) CYG_MACRO_START                 \
 191         cyg_uint32 hival = (value) << 16;                                   \
 192         HAL_SPARC_ASI_4_WRITE( reg + HAL_SPARC_86940_BASE, hival );         \
 193 CYG_MACRO_END
 194
 195 // Registers are at word offsets
 196 #define HAL_SPARC_86940_REG_SDTR0_TXDATA ( 0x08 * 4 )
 197 #define HAL_SPARC_86940_REG_SDTR0_RXDATA ( 0x08 * 4 )
 198 #define HAL_SPARC_86940_REG_SDTR0_STAT   ( 0x09 * 4 )
 199 #define HAL_SPARC_86940_REG_SDTR0_CTRL   ( 0x09 * 4 )
 200 #define HAL_SPARC_86940_REG_SDTR1_TXDATA ( 0x0c * 4 )
 201 #define HAL_SPARC_86940_REG_SDTR1_RXDATA ( 0x0c * 4 )
 202 #define HAL_SPARC_86940_REG_SDTR1_STAT   ( 0x0d * 4 )
 203 #define HAL_SPARC_86940_REG_SDTR1_CTRL   ( 0x0d * 4 )
 204
 205 #define HAL_SPARC_86940_REG_PRS0         ( 0x10 * 4 )
 206 #define HAL_SPARC_86940_REG_TCR0         ( 0x11 * 4 )
 207 #define HAL_SPARC_86940_REG_RELOAD0      ( 0x12 * 4 )
 208 #define HAL_SPARC_86940_REG_CNT0         ( 0x13 * 4 )
 209 #define HAL_SPARC_86940_REG_PRS1         ( 0x14 * 4 )
 210 #define HAL_SPARC_86940_REG_TCR1         ( 0x15 * 4 )
 211 #define HAL_SPARC_86940_REG_RELOAD1      ( 0x16 * 4 )
 212 #define HAL_SPARC_86940_REG_CNT1         ( 0x17 * 4 )
 213 #define HAL_SPARC_86940_REG_TCR2         ( 0x19 * 4 )
 214 #define HAL_SPARC_86940_REG_RELOAD2      ( 0x1A * 4 )
 215 #define HAL_SPARC_86940_REG_CNT2         ( 0x1B * 4 )
 216 #define HAL_SPARC_86940_REG_TCR3         ( 0x1D * 4 )
 217 #define HAL_SPARC_86940_REG_RELOAD3      ( 0x1E * 4 )
 218 #define HAL_SPARC_86940_REG_CNT3         ( 0x1F * 4 )
 219
 220 // Glue together to access them neatly
 221 #define HAL_SPARC_86940_SDTR0_TXDATA_WRITE( v ) \
 222             HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_SDTR0_TXDATA, v )
 223 #define HAL_SPARC_86940_SDTR0_RXDATA_READ( r ) \
 224             HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_SDTR0_RXDATA, r )
 225
 226 #define HAL_SPARC_86940_SDTR0_STAT_READ( r ) \
 227             HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_SDTR0_STAT, r )
 228 #define HAL_SPARC_86940_SDTR0_CTRL_WRITE( v ) \
 229             HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_SDTR0_CTRL, v )
 230
 231 #define HAL_SPARC_86940_SDTR1_TXDATA_WRITE( v ) \
 232             HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_SDTR1_TXDATA, v )
 233 #define HAL_SPARC_86940_SDTR1_RXDATA_READ( r ) \
 234             HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_SDTR1_RXDATA, r )
 235
 236 #define HAL_SPARC_86940_SDTR1_STAT_READ( r ) \
 237             HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_SDTR1_STAT, r )
 238 #define HAL_SPARC_86940_SDTR1_CTRL_WRITE( v ) \
 239             HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_SDTR1_CTRL, v )
 240
 241 #define HAL_SPARC_86940_PRS0_READ( r ) \
 242             HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_PRS0, r )
 243 #define HAL_SPARC_86940_PRS0_WRITE( v ) \
 244             HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_PRS0, v )
 245
 246 #define HAL_SPARC_86940_TCR0_READ( r ) \
 247             HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_TCR0, r )
 248 #define HAL_SPARC_86940_TCR0_WRITE( v ) \
 249             HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_TCR0, v )
 250
 251 #define HAL_SPARC_86940_RELOAD0_READ( r ) \
 252             HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_RELOAD0, r )
 253 #define HAL_SPARC_86940_RELOAD0_WRITE( v ) \
 254             HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_RELOAD0, v )
 255
 256 #define HAL_SPARC_86940_CNT0_READ( r ) \
 257             HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_CNT0, r )
 258 #define HAL_SPARC_86940_CNT0_WRITE( v ) \
 259             HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_CNT0, v )
 260
 261 #define HAL_SPARC_86940_PRS1_READ( r ) \
 262             HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_PRS1, r )
 263 #define HAL_SPARC_86940_PRS1_WRITE( v ) \
 264             HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_PRS1, v )
 265
 266 #define HAL_SPARC_86940_TCR1_READ( r ) \
 267             HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_TCR1, r )
 268 #define HAL_SPARC_86940_TCR1_WRITE( v ) \
 269             HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_TCR1, v )
 270
 271 #define HAL_SPARC_86940_RELOAD1_READ( r ) \
 272             HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_RELOAD1, r )
 273 #define HAL_SPARC_86940_RELOAD1_WRITE( v ) \
 274             HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_RELOAD1, v )
 275
 276 #define HAL_SPARC_86940_CNT1_READ( r ) \
 277             HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_CNT1, r )
 278 #define HAL_SPARC_86940_CNT1_WRITE( v ) \
 279             HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_CNT1, v )
 280
 281 #define HAL_SPARC_86940_TCR2_READ( r ) \
 282             HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_TCR2, r )
 283 #define HAL_SPARC_86940_TCR2_WRITE( v ) \
 284             HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_TCR2, v )
 285
 286 #define HAL_SPARC_86940_RELOAD2_READ( r ) \
 287             HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_RELOAD2, r )
 288 #define HAL_SPARC_86940_RELOAD2_WRITE( v ) \
 289             HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_RELOAD2, v )
 290
 291 #define HAL_SPARC_86940_CNT2_READ( r ) \
 292             HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_CNT2, r )
 293 #define HAL_SPARC_86940_CNT2_WRITE( v ) \
 294             HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_CNT2, v )
 295
 296 #define HAL_SPARC_86940_TCR3_READ( r ) \
 297             HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_TCR3, r )
 298 #define HAL_SPARC_86940_TCR3_WRITE( v ) \
 299             HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_TCR3, v )
 300
 301 #define HAL_SPARC_86940_RELOAD3_READ( r ) \
 302             HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_RELOAD3, r )
 303 #define HAL_SPARC_86940_RELOAD3_WRITE( v ) \
 304             HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_RELOAD3, v )
 305
 306 #define HAL_SPARC_86940_CNT3_READ( r ) \
 307             HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_CNT3, r )
 308 #define HAL_SPARC_86940_CNT3_WRITE( v ) \
 309             HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_CNT3, v )
 310
 311 /*---------------------------------------------------------------------------*/
 312 /* end of hal_hwio.h                                                         */
 313 #endif /* CYGONCE_HAL_HAL_HWIO_H */