1 /*=================================================================
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
15 // Software Foundation; either version 2 or (at your option) any later version.
17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 // You should have received a copy of the GNU General Public License along
23 // with eCos; if not, write to the Free Software Foundation, Inc.,
24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 // As a special exception, if other files instantiate templates or use macros
27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
29 // by itself cause the resulting work to be covered by the GNU General Public
30 // License. However the source code for this file must still be made available
31 // in accordance with section (3) of the GNU General Public License.
33 // This exception does not invalidate any other reasons why a work based on
34 // this file might be covered by the GNU General Public License.
36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37 // at http://sources.redhat.com/ecos/ecos-license/
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //==========================================================================
41 //#####DESCRIPTIONBEGIN####
44 // Contributors: dsm, nickg
46 //####DESCRIPTIONEND####
49 #include <cyg/hal/hal_arch.h> // CYGNUM_HAL_STACK_SIZE_TYPICAL
51 #include <cyg/kernel/kapi.h>
53 #include <cyg/infra/testcase.h>
55 #include <cyg/hal/hal_cache.h>
57 #if defined(HAL_DCACHE_SIZE) || defined(HAL_UCACHE_SIZE)
58 #ifdef CYGVAR_KERNEL_COUNTERS_CLOCK
59 #ifdef CYGFUN_KERNEL_API_C
61 #include <cyg/infra/diag.h>
62 #include <cyg/hal/hal_intr.h>
64 // -------------------------------------------------------------------------
65 // If the HAL does not supply this, we supply our own version
67 #ifndef HAL_DCACHE_PURGE_ALL
68 # ifdef HAL_DCACHE_SYNC
70 #define HAL_DCACHE_PURGE_ALL() HAL_DCACHE_SYNC()
74 static cyg_uint8 dca[HAL_DCACHE_SIZE + HAL_DCACHE_LINE_SIZE*2];
76 #define HAL_DCACHE_PURGE_ALL() \
78 volatile cyg_uint8 *addr = &dca[HAL_DCACHE_LINE_SIZE]; \
79 volatile cyg_uint8 tmp = 0; \
81 for( i = 0; i < HAL_DCACHE_SIZE; i += HAL_DCACHE_LINE_SIZE ) \
90 // -------------------------------------------------------------------------
93 #define STACKSIZE CYGNUM_HAL_STACK_SIZE_TYPICAL
95 static cyg_handle_t thread[NTHREADS];
97 static cyg_thread thread_obj[NTHREADS];
98 static char stack[NTHREADS][STACKSIZE];
101 #define MAX_STRIDE 64
104 volatile char m[(HAL_DCACHE_SIZE/HAL_DCACHE_LINE_SIZE)*MAX_STRIDE];
106 // -------------------------------------------------------------------------
108 static void time0(register cyg_uint32 stride)
110 register cyg_uint32 j,k;
111 cyg_tick_count_t count0, count1;
115 count0 = cyg_current_time();
118 if ( cyg_test_is_simulator )
122 for(j=0; j<(HAL_DCACHE_SIZE/HAL_DCACHE_LINE_SIZE); j++) {
127 count1 = cyg_current_time();
129 diag_printf("stride=%d, time=%d\n", stride, t);
132 // -------------------------------------------------------------------------
138 for(i=1; i<=MAX_STRIDE; i+=i) {
143 // -------------------------------------------------------------------------
144 // With an ICache invalidate in the middle:
145 #ifdef HAL_ICACHE_INVALIDATE_ALL
146 static void time0II(register cyg_uint32 stride)
148 register cyg_uint32 j,k;
149 cyg_tick_count_t count0, count1;
153 count0 = cyg_current_time();
156 if ( cyg_test_is_simulator )
160 for(j=0; j<(HAL_DCACHE_SIZE/HAL_DCACHE_LINE_SIZE); j++) {
161 HAL_ICACHE_INVALIDATE_ALL();
166 count1 = cyg_current_time();
168 diag_printf("stride=%d, time=%d\n", stride, t);
171 // -------------------------------------------------------------------------
177 for(i=1; i<=MAX_STRIDE; i+=i) {
182 // -------------------------------------------------------------------------
183 // With a DCache invalidate in the middle:
184 // This is guaranteed to produce bogus timing results since interrupts
185 // have to be disabled to prevent accidental loss of state.
186 #ifdef HAL_DCACHE_INVALIDATE_ALL
187 static void time0DI(register cyg_uint32 stride)
189 register cyg_uint32 j,k;
190 volatile cyg_tick_count_t count0;
191 cyg_tick_count_t count1;
194 register CYG_INTERRUPT_STATE oldints;
196 count0 = cyg_current_time();
198 HAL_DISABLE_INTERRUPTS(oldints);
202 if ( cyg_test_is_simulator )
206 for(j=0; j<(HAL_DCACHE_SIZE/HAL_DCACHE_LINE_SIZE); j++) {
207 HAL_DCACHE_INVALIDATE_ALL();
211 HAL_RESTORE_INTERRUPTS(oldints);
213 count1 = cyg_current_time();
215 diag_printf("stride=%d, time=%d\n", stride, t);
218 // -------------------------------------------------------------------------
224 for(i=1; i<=MAX_STRIDE; i+=i) {
229 // -------------------------------------------------------------------------
230 // This test could be improved by counting number of passes possible
231 // in a given number of ticks.
233 static void entry0( cyg_addrword_t data )
235 register CYG_INTERRUPT_STATE oldints;
237 #ifdef HAL_CACHE_UNIFIED
239 HAL_DISABLE_INTERRUPTS(oldints);
240 HAL_DCACHE_PURGE_ALL(); // rely on above definition
241 HAL_UCACHE_INVALIDATE_ALL();
242 HAL_UCACHE_DISABLE();
243 HAL_RESTORE_INTERRUPTS(oldints);
244 CYG_TEST_INFO("Cache off");
247 HAL_DISABLE_INTERRUPTS(oldints);
248 HAL_DCACHE_PURGE_ALL(); // rely on above definition
249 HAL_UCACHE_INVALIDATE_ALL();
251 HAL_RESTORE_INTERRUPTS(oldints);
252 CYG_TEST_INFO("Cache on");
255 #ifdef HAL_DCACHE_INVALIDATE_ALL
256 HAL_DISABLE_INTERRUPTS(oldints);
257 HAL_DCACHE_PURGE_ALL();
258 HAL_UCACHE_INVALIDATE_ALL();
260 HAL_RESTORE_INTERRUPTS(oldints);
261 CYG_TEST_INFO("Cache on: invalidate Cache (expect bogus timing)");
265 #else // HAL_CACHE_UNIFIED
267 HAL_DISABLE_INTERRUPTS(oldints);
268 HAL_DCACHE_PURGE_ALL();
269 HAL_ICACHE_INVALIDATE_ALL();
270 HAL_DCACHE_INVALIDATE_ALL();
271 HAL_ICACHE_DISABLE();
272 HAL_DCACHE_DISABLE();
273 HAL_RESTORE_INTERRUPTS(oldints);
274 CYG_TEST_INFO("Dcache off Icache off");
277 HAL_DISABLE_INTERRUPTS(oldints);
278 HAL_DCACHE_PURGE_ALL();
279 HAL_ICACHE_INVALIDATE_ALL();
280 HAL_DCACHE_INVALIDATE_ALL();
281 HAL_ICACHE_DISABLE();
283 HAL_RESTORE_INTERRUPTS(oldints);
284 CYG_TEST_INFO("Dcache on Icache off");
287 HAL_DISABLE_INTERRUPTS(oldints);
288 HAL_DCACHE_PURGE_ALL();
289 HAL_ICACHE_INVALIDATE_ALL();
290 HAL_DCACHE_INVALIDATE_ALL();
292 HAL_DCACHE_DISABLE();
293 HAL_RESTORE_INTERRUPTS(oldints);
294 CYG_TEST_INFO("Dcache off Icache on");
297 HAL_DISABLE_INTERRUPTS(oldints);
298 HAL_DCACHE_PURGE_ALL();
299 HAL_ICACHE_INVALIDATE_ALL();
300 HAL_DCACHE_INVALIDATE_ALL();
303 HAL_RESTORE_INTERRUPTS(oldints);
304 CYG_TEST_INFO("Dcache on Icache on");
308 HAL_DISABLE_INTERRUPTS(oldints);
309 HAL_DCACHE_PURGE_ALL();
310 HAL_ICACHE_INVALIDATE_ALL();
311 HAL_DCACHE_INVALIDATE_ALL();
312 HAL_ICACHE_DISABLE();
313 HAL_DCACHE_DISABLE();
314 HAL_RESTORE_INTERRUPTS(oldints);
315 CYG_TEST_INFO("Dcache off Icache off (again)");
318 #if defined(HAL_DCACHE_INVALIDATE_ALL) || defined(HAL_ICACHE_INVALIDATE_ALL)
319 HAL_DISABLE_INTERRUPTS(oldints);
320 HAL_DCACHE_PURGE_ALL();
321 HAL_ICACHE_INVALIDATE_ALL();
322 HAL_DCACHE_INVALIDATE_ALL();
325 HAL_RESTORE_INTERRUPTS(oldints);
326 CYG_TEST_INFO("Dcache on Icache on (again)");
329 #if defined(CYGPKG_HAL_MIPS)
330 // In some architectures, the time taken for the next two tests is
331 // very long, partly because HAL_XCACHE_INVALIDATE_ALL() is implemented
332 // with a loop over the cache. Hence these tests take longer than the
333 // testing infrastructure is prepared to wait. The simplest way to get
334 // these tests to run quickly is to make them think they are running
335 // under a simulator.
336 // If the target actually is a simulator, skip the below - it's very
337 // slow on the simulator, even with reduced loop counts.
338 if (cyg_test_is_simulator)
339 CYG_TEST_PASS_FINISH("End of test");
341 #if defined(CYGPKG_HAL_MIPS_TX49)
342 // The TX49 has a large cache, and even with reduced loop count,
343 // 90+ seconds elapses between each INFO output.
344 CYG_TEST_PASS_FINISH("End of test");
347 cyg_test_is_simulator = 1;
350 #ifdef HAL_ICACHE_INVALIDATE_ALL
351 HAL_DISABLE_INTERRUPTS(oldints);
352 HAL_DCACHE_PURGE_ALL();
353 HAL_ICACHE_INVALIDATE_ALL();
354 HAL_DCACHE_INVALIDATE_ALL();
357 HAL_RESTORE_INTERRUPTS(oldints);
358 CYG_TEST_INFO("Dcache on Icache on: invalidate ICache each time");
361 #ifdef HAL_DCACHE_INVALIDATE_ALL
362 HAL_DISABLE_INTERRUPTS(oldints);
363 HAL_DCACHE_PURGE_ALL();
364 HAL_ICACHE_INVALIDATE_ALL();
365 HAL_DCACHE_INVALIDATE_ALL();
368 HAL_RESTORE_INTERRUPTS(oldints);
369 CYG_TEST_INFO("Dcache on Icache on: invalidate DCache (expect bogus times)");
372 #endif // either INVALIDATE_ALL macro
374 #endif // HAL_CACHE_UNIFIED
376 CYG_TEST_PASS_FINISH("End of test");
379 // -------------------------------------------------------------------------
381 void kcache2_main( void )
385 cyg_thread_create(4, entry0 , (cyg_addrword_t)0, "kcache1",
386 (void *)stack[0], STACKSIZE, &thread[0], &thread_obj[0]);
387 cyg_thread_resume(thread[0]);
389 cyg_scheduler_start();
392 // -------------------------------------------------------------------------
400 // -------------------------------------------------------------------------
402 #else // def CYGFUN_KERNEL_API_C
403 #define N_A_MSG "Kernel C API layer disabled"
404 #endif // def CYGFUN_KERNEL_API_C
405 #else // def CYGVAR_KERNEL_COUNTERS_CLOCK
406 #define N_A_MSG "Kernel real-time clock disabled"
407 #endif // def CYGVAR_KERNEL_COUNTERS_CLOCK
408 #else // def HAL_DCACHE_SIZE
409 #define N_A_MSG "No caches defined"
410 #endif // def HAL_DCACHE_SIZE
417 CYG_TEST_NA( N_A_MSG );
421 // -------------------------------------------------------------------------