3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * Ternary instructions instr rD,rA,rB
30 * Arithmetic instructions: add, addc, adde, subf, subfc, subfe,
31 * mullw, mulhw, mulhwu, divw, divwu
33 * The test contains a pre-built table of instructions, operands and
34 * expected results. For each table entry, the test will cyclically use
35 * different sets of operand registers and result registers.
41 #if CONFIG_POST & CONFIG_SYS_POST_CPU
43 extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
45 extern ulong cpu_post_makecr (long v);
47 static struct cpu_post_three_s
53 } cpu_post_three_table[] =
158 static unsigned int cpu_post_three_size =
159 sizeof (cpu_post_three_table) / sizeof (struct cpu_post_three_s);
161 int cpu_post_test_three (void)
165 int flag = disable_interrupts();
167 for (i = 0; i < cpu_post_three_size && ret == 0; i++)
169 struct cpu_post_three_s *test = cpu_post_three_table + i;
171 for (reg = 0; reg < 32 && ret == 0; reg++)
173 unsigned int reg0 = (reg + 0) % 32;
174 unsigned int reg1 = (reg + 1) % 32;
175 unsigned int reg2 = (reg + 2) % 32;
176 unsigned int stk = reg < 16 ? 31 : 15;
177 unsigned long code[] =
180 ASM_ADDI(stk, 1, -24),
183 ASM_STW(reg0, stk, 8),
184 ASM_STW(reg1, stk, 4),
185 ASM_STW(reg2, stk, 0),
186 ASM_LWZ(reg1, stk, 12),
187 ASM_LWZ(reg0, stk, 16),
188 ASM_12(test->cmd, reg2, reg1, reg0),
189 ASM_STW(reg2, stk, 12),
190 ASM_LWZ(reg2, stk, 0),
191 ASM_LWZ(reg1, stk, 4),
192 ASM_LWZ(reg0, stk, 8),
194 ASM_ADDI(1, stk, 24),
198 unsigned long codecr[] =
201 ASM_ADDI(stk, 1, -24),
204 ASM_STW(reg0, stk, 8),
205 ASM_STW(reg1, stk, 4),
206 ASM_STW(reg2, stk, 0),
207 ASM_LWZ(reg1, stk, 12),
208 ASM_LWZ(reg0, stk, 16),
209 ASM_12(test->cmd, reg2, reg1, reg0) | BIT_C,
210 ASM_STW(reg2, stk, 12),
211 ASM_LWZ(reg2, stk, 0),
212 ASM_LWZ(reg1, stk, 4),
213 ASM_LWZ(reg0, stk, 8),
215 ASM_ADDI(1, stk, 24),
225 cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);
227 ret = res == test->res && cr == 0 ? 0 : -1;
231 post_log ("Error at three test %d !\n", i);
237 cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);
239 ret = res == test->res &&
240 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
244 post_log ("Error at three test %d !\n", i);