3 * hda_intel.c - Implementation of primary alsa driver code base
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
50 /* for snoop control */
51 #include <asm/pgtable.h>
52 #include <asm/cacheflush.h>
54 #include <sound/core.h>
55 #include <sound/initval.h>
56 #include "hda_codec.h"
59 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
60 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
61 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
62 static char *model[SNDRV_CARDS];
63 static int position_fix[SNDRV_CARDS];
64 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
65 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
66 static int probe_only[SNDRV_CARDS];
67 static bool single_cmd;
68 static int enable_msi = -1;
69 #ifdef CONFIG_SND_HDA_PATCH_LOADER
70 static char *patch[SNDRV_CARDS];
72 #ifdef CONFIG_SND_HDA_INPUT_BEEP
73 static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
74 CONFIG_SND_HDA_INPUT_BEEP_MODE};
77 module_param_array(index, int, NULL, 0444);
78 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
79 module_param_array(id, charp, NULL, 0444);
80 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
81 module_param_array(enable, bool, NULL, 0444);
82 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
83 module_param_array(model, charp, NULL, 0444);
84 MODULE_PARM_DESC(model, "Use the given board model.");
85 module_param_array(position_fix, int, NULL, 0444);
86 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
87 "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
88 module_param_array(bdl_pos_adj, int, NULL, 0644);
89 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
90 module_param_array(probe_mask, int, NULL, 0444);
91 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
92 module_param_array(probe_only, int, NULL, 0444);
93 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
94 module_param(single_cmd, bool, 0444);
95 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
96 "(for debugging only).");
97 module_param(enable_msi, bint, 0444);
98 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
99 #ifdef CONFIG_SND_HDA_PATCH_LOADER
100 module_param_array(patch, charp, NULL, 0444);
101 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
103 #ifdef CONFIG_SND_HDA_INPUT_BEEP
104 module_param_array(beep_mode, int, NULL, 0444);
105 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
106 "(0=off, 1=on, 2=mute switch on/off) (default=1).");
109 #ifdef CONFIG_SND_HDA_POWER_SAVE
110 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
111 module_param(power_save, int, 0644);
112 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
113 "(in second, 0 = disable).");
115 /* reset the HD-audio controller in power save mode.
116 * this may give more power-saving, but will take longer time to
119 static bool power_save_controller = 1;
120 module_param(power_save_controller, bool, 0644);
121 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
124 static int align_buffer_size = -1;
125 module_param(align_buffer_size, bint, 0644);
126 MODULE_PARM_DESC(align_buffer_size,
127 "Force buffer and period sizes to be multiple of 128 bytes.");
130 static bool hda_snoop = true;
131 module_param_named(snoop, hda_snoop, bool, 0444);
132 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
133 #define azx_snoop(chip) (chip)->snoop
135 #define hda_snoop true
136 #define azx_snoop(chip) true
140 MODULE_LICENSE("GPL");
141 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
170 MODULE_DESCRIPTION("Intel HDA driver");
172 #ifdef CONFIG_SND_VERBOSE_PRINTK
173 #define SFX /* nop */
175 #define SFX "hda-intel: "
181 #define ICH6_REG_GCAP 0x00
182 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
183 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
184 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
185 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
186 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
187 #define ICH6_REG_VMIN 0x02
188 #define ICH6_REG_VMAJ 0x03
189 #define ICH6_REG_OUTPAY 0x04
190 #define ICH6_REG_INPAY 0x06
191 #define ICH6_REG_GCTL 0x08
192 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
193 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
194 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
195 #define ICH6_REG_WAKEEN 0x0c
196 #define ICH6_REG_STATESTS 0x0e
197 #define ICH6_REG_GSTS 0x10
198 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
199 #define ICH6_REG_INTCTL 0x20
200 #define ICH6_REG_INTSTS 0x24
201 #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
202 #define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
203 #define ICH6_REG_SSYNC 0x38
204 #define ICH6_REG_CORBLBASE 0x40
205 #define ICH6_REG_CORBUBASE 0x44
206 #define ICH6_REG_CORBWP 0x48
207 #define ICH6_REG_CORBRP 0x4a
208 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
209 #define ICH6_REG_CORBCTL 0x4c
210 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
211 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
212 #define ICH6_REG_CORBSTS 0x4d
213 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
214 #define ICH6_REG_CORBSIZE 0x4e
216 #define ICH6_REG_RIRBLBASE 0x50
217 #define ICH6_REG_RIRBUBASE 0x54
218 #define ICH6_REG_RIRBWP 0x58
219 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
220 #define ICH6_REG_RINTCNT 0x5a
221 #define ICH6_REG_RIRBCTL 0x5c
222 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
223 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
224 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
225 #define ICH6_REG_RIRBSTS 0x5d
226 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
227 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
228 #define ICH6_REG_RIRBSIZE 0x5e
230 #define ICH6_REG_IC 0x60
231 #define ICH6_REG_IR 0x64
232 #define ICH6_REG_IRS 0x68
233 #define ICH6_IRS_VALID (1<<1)
234 #define ICH6_IRS_BUSY (1<<0)
236 #define ICH6_REG_DPLBASE 0x70
237 #define ICH6_REG_DPUBASE 0x74
238 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
240 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
241 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
243 /* stream register offsets from stream base */
244 #define ICH6_REG_SD_CTL 0x00
245 #define ICH6_REG_SD_STS 0x03
246 #define ICH6_REG_SD_LPIB 0x04
247 #define ICH6_REG_SD_CBL 0x08
248 #define ICH6_REG_SD_LVI 0x0c
249 #define ICH6_REG_SD_FIFOW 0x0e
250 #define ICH6_REG_SD_FIFOSIZE 0x10
251 #define ICH6_REG_SD_FORMAT 0x12
252 #define ICH6_REG_SD_BDLPL 0x18
253 #define ICH6_REG_SD_BDLPU 0x1c
256 #define ICH6_PCIREG_TCSEL 0x44
262 /* max number of SDs */
263 /* ICH, ATI and VIA have 4 playback and 4 capture */
264 #define ICH6_NUM_CAPTURE 4
265 #define ICH6_NUM_PLAYBACK 4
267 /* ULI has 6 playback and 5 capture */
268 #define ULI_NUM_CAPTURE 5
269 #define ULI_NUM_PLAYBACK 6
271 /* ATI HDMI has 1 playback and 0 capture */
272 #define ATIHDMI_NUM_CAPTURE 0
273 #define ATIHDMI_NUM_PLAYBACK 1
275 /* TERA has 4 playback and 3 capture */
276 #define TERA_NUM_CAPTURE 3
277 #define TERA_NUM_PLAYBACK 4
279 /* this number is statically defined for simplicity */
280 #define MAX_AZX_DEV 16
282 /* max number of fragments - we may use more if allocating more pages for BDL */
283 #define BDL_SIZE 4096
284 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
285 #define AZX_MAX_FRAG 32
286 /* max buffer size - no h/w limit, you can increase as you like */
287 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
289 /* RIRB int mask: overrun[2], response[0] */
290 #define RIRB_INT_RESPONSE 0x01
291 #define RIRB_INT_OVERRUN 0x04
292 #define RIRB_INT_MASK 0x05
294 /* STATESTS int mask: S3,SD2,SD1,SD0 */
295 #define AZX_MAX_CODECS 8
296 #define AZX_DEFAULT_CODECS 4
297 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
300 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
301 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
302 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
303 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
304 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
305 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
306 #define SD_CTL_STREAM_TAG_SHIFT 20
308 /* SD_CTL and SD_STS */
309 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
310 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
311 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
312 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
316 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
318 /* INTCTL and INTSTS */
319 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
320 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
321 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
323 /* below are so far hardcoded - should read registers in future */
324 #define ICH6_MAX_CORB_ENTRIES 256
325 #define ICH6_MAX_RIRB_ENTRIES 256
327 /* position fix mode */
336 /* Defines for ATI HD Audio support in SB450 south bridge */
337 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
338 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
340 /* Defines for Nvidia HDA support */
341 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
342 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
343 #define NVIDIA_HDA_ISTRM_COH 0x4d
344 #define NVIDIA_HDA_OSTRM_COH 0x4c
345 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
347 /* Defines for Intel SCH HDA snoop control */
348 #define INTEL_SCH_HDA_DEVC 0x78
349 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
351 /* Define IN stream 0 FIFO size offset in VIA controller */
352 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
353 /* Define VIA HD Audio Device ID*/
354 #define VIA_HDAC_DEVICE_ID 0x3288
356 /* HD Audio class code */
357 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
363 struct snd_dma_buffer bdl; /* BDL buffer */
364 u32 *posbuf; /* position buffer pointer */
366 unsigned int bufsize; /* size of the play buffer in bytes */
367 unsigned int period_bytes; /* size of the period in bytes */
368 unsigned int frags; /* number for period in the play buffer */
369 unsigned int fifo_size; /* FIFO size */
370 unsigned long start_wallclk; /* start + minimum wallclk */
371 unsigned long period_wallclk; /* wallclk for period */
373 void __iomem *sd_addr; /* stream descriptor pointer */
375 u32 sd_int_sta_mask; /* stream int status mask */
378 struct snd_pcm_substream *substream; /* assigned substream,
381 unsigned int format_val; /* format value to be set in the
382 * controller and the codec
384 unsigned char stream_tag; /* assigned stream */
385 unsigned char index; /* stream index */
386 int assigned_key; /* last device# key assigned to */
388 unsigned int opened :1;
389 unsigned int running :1;
390 unsigned int irq_pending :1;
393 * A flag to ensure DMA position is 0
394 * when link position is not greater than FIFO size
396 unsigned int insufficient :1;
397 unsigned int wc_marked:1;
402 u32 *buf; /* CORB/RIRB buffer
403 * Each CORB entry is 4byte, RIRB is 8byte
405 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
407 unsigned short rp, wp; /* read/write pointers */
408 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
409 u32 res[AZX_MAX_CODECS]; /* last read value */
415 struct hda_codec *codec;
416 struct hda_pcm_stream *hinfo[2];
417 struct list_head list;
421 struct snd_card *card;
425 /* chip type specific */
427 unsigned int driver_caps;
428 int playback_streams;
429 int playback_index_offset;
431 int capture_index_offset;
436 void __iomem *remap_addr;
441 struct mutex open_mutex;
443 /* streams (x num_streams) */
444 struct azx_dev *azx_dev;
447 struct list_head pcm_list; /* azx_pcm list */
450 unsigned short codec_mask;
451 int codec_probe_mask; /* copied from probe_mask option */
453 unsigned int beep_mode;
459 /* CORB/RIRB and position buffers */
460 struct snd_dma_buffer rb;
461 struct snd_dma_buffer posbuf;
464 int position_fix[2]; /* for both playback/capture streams */
466 unsigned int running :1;
467 unsigned int initialized :1;
468 unsigned int single_cmd :1;
469 unsigned int polling_mode :1;
471 unsigned int irq_pending_warned :1;
472 unsigned int probing :1; /* codec probing phase */
473 unsigned int snoop:1;
474 unsigned int align_buffer_size:1;
477 unsigned int last_cmd[AZX_MAX_CODECS];
479 /* for pending irqs */
480 struct work_struct irq_pending_work;
482 /* reboot notifier (for mysterious hangup problem at power-down) */
483 struct notifier_block reboot_notifier;
493 AZX_DRIVER_ATIHDMI_NS,
502 AZX_NUM_DRIVERS, /* keep this as last entry */
505 /* driver quirks (capabilities) */
506 /* bits 0-7 are used for indicating driver type */
507 #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
508 #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
509 #define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
510 #define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
511 #define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
512 #define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
513 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
514 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
515 #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
516 #define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
517 #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
518 #define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
519 #define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
520 #define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
521 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
522 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
524 /* quirks for ATI SB / AMD Hudson */
525 #define AZX_DCAPS_PRESET_ATI_SB \
526 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
527 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
529 /* quirks for ATI/AMD HDMI */
530 #define AZX_DCAPS_PRESET_ATI_HDMI \
531 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
533 /* quirks for Nvidia */
534 #define AZX_DCAPS_PRESET_NVIDIA \
535 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
536 AZX_DCAPS_ALIGN_BUFSIZE)
538 #define AZX_DCAPS_PRESET_CTHDA \
539 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
541 static char *driver_short_names[] __devinitdata = {
542 [AZX_DRIVER_ICH] = "HDA Intel",
543 [AZX_DRIVER_PCH] = "HDA Intel PCH",
544 [AZX_DRIVER_SCH] = "HDA Intel MID",
545 [AZX_DRIVER_ATI] = "HDA ATI SB",
546 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
547 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
548 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
549 [AZX_DRIVER_SIS] = "HDA SIS966",
550 [AZX_DRIVER_ULI] = "HDA ULI M5461",
551 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
552 [AZX_DRIVER_TERA] = "HDA Teradici",
553 [AZX_DRIVER_CTX] = "HDA Creative",
554 [AZX_DRIVER_CTHDA] = "HDA Creative",
555 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
559 * macros for easy use
561 #define azx_writel(chip,reg,value) \
562 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
563 #define azx_readl(chip,reg) \
564 readl((chip)->remap_addr + ICH6_REG_##reg)
565 #define azx_writew(chip,reg,value) \
566 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
567 #define azx_readw(chip,reg) \
568 readw((chip)->remap_addr + ICH6_REG_##reg)
569 #define azx_writeb(chip,reg,value) \
570 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
571 #define azx_readb(chip,reg) \
572 readb((chip)->remap_addr + ICH6_REG_##reg)
574 #define azx_sd_writel(dev,reg,value) \
575 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
576 #define azx_sd_readl(dev,reg) \
577 readl((dev)->sd_addr + ICH6_REG_##reg)
578 #define azx_sd_writew(dev,reg,value) \
579 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
580 #define azx_sd_readw(dev,reg) \
581 readw((dev)->sd_addr + ICH6_REG_##reg)
582 #define azx_sd_writeb(dev,reg,value) \
583 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
584 #define azx_sd_readb(dev,reg) \
585 readb((dev)->sd_addr + ICH6_REG_##reg)
587 /* for pcm support */
588 #define get_azx_dev(substream) (substream->runtime->private_data)
591 static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
596 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
598 set_memory_wc((unsigned long)addr, pages);
600 set_memory_wb((unsigned long)addr, pages);
604 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
607 __mark_pages_wc(chip, buf->area, buf->bytes, on);
609 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
610 struct snd_pcm_runtime *runtime, bool on)
612 if (azx_dev->wc_marked != on) {
613 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
614 azx_dev->wc_marked = on;
618 /* NOP for other archs */
619 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
623 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
624 struct snd_pcm_runtime *runtime, bool on)
629 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
630 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
632 * Interface for HD codec
636 * CORB / RIRB interface
638 static int azx_alloc_cmd_io(struct azx *chip)
642 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
643 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
644 snd_dma_pci_data(chip->pci),
645 PAGE_SIZE, &chip->rb);
647 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
650 mark_pages_wc(chip, &chip->rb, true);
654 static void azx_init_cmd_io(struct azx *chip)
656 spin_lock_irq(&chip->reg_lock);
658 chip->corb.addr = chip->rb.addr;
659 chip->corb.buf = (u32 *)chip->rb.area;
660 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
661 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
663 /* set the corb size to 256 entries (ULI requires explicitly) */
664 azx_writeb(chip, CORBSIZE, 0x02);
665 /* set the corb write pointer to 0 */
666 azx_writew(chip, CORBWP, 0);
667 /* reset the corb hw read pointer */
668 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
669 /* enable corb dma */
670 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
673 chip->rirb.addr = chip->rb.addr + 2048;
674 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
675 chip->rirb.wp = chip->rirb.rp = 0;
676 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
677 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
678 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
680 /* set the rirb size to 256 entries (ULI requires explicitly) */
681 azx_writeb(chip, RIRBSIZE, 0x02);
682 /* reset the rirb hw write pointer */
683 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
684 /* set N=1, get RIRB response interrupt for new entry */
685 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
686 azx_writew(chip, RINTCNT, 0xc0);
688 azx_writew(chip, RINTCNT, 1);
689 /* enable rirb dma and response irq */
690 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
691 spin_unlock_irq(&chip->reg_lock);
694 static void azx_free_cmd_io(struct azx *chip)
696 spin_lock_irq(&chip->reg_lock);
697 /* disable ringbuffer DMAs */
698 azx_writeb(chip, RIRBCTL, 0);
699 azx_writeb(chip, CORBCTL, 0);
700 spin_unlock_irq(&chip->reg_lock);
703 static unsigned int azx_command_addr(u32 cmd)
705 unsigned int addr = cmd >> 28;
707 if (addr >= AZX_MAX_CODECS) {
715 static unsigned int azx_response_addr(u32 res)
717 unsigned int addr = res & 0xf;
719 if (addr >= AZX_MAX_CODECS) {
728 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
730 struct azx *chip = bus->private_data;
731 unsigned int addr = azx_command_addr(val);
734 spin_lock_irq(&chip->reg_lock);
736 /* add command to corb */
737 wp = azx_readb(chip, CORBWP);
739 wp %= ICH6_MAX_CORB_ENTRIES;
741 chip->rirb.cmds[addr]++;
742 chip->corb.buf[wp] = cpu_to_le32(val);
743 azx_writel(chip, CORBWP, wp);
745 spin_unlock_irq(&chip->reg_lock);
750 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
752 /* retrieve RIRB entry - called from interrupt handler */
753 static void azx_update_rirb(struct azx *chip)
759 wp = azx_readb(chip, RIRBWP);
760 if (wp == chip->rirb.wp)
764 while (chip->rirb.rp != wp) {
766 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
768 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
769 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
770 res = le32_to_cpu(chip->rirb.buf[rp]);
771 addr = azx_response_addr(res_ex);
772 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
773 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
774 else if (chip->rirb.cmds[addr]) {
775 chip->rirb.res[addr] = res;
777 chip->rirb.cmds[addr]--;
779 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
782 chip->last_cmd[addr]);
786 /* receive a response */
787 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
790 struct azx *chip = bus->private_data;
791 unsigned long timeout;
792 unsigned long loopcounter;
796 timeout = jiffies + msecs_to_jiffies(1000);
798 for (loopcounter = 0;; loopcounter++) {
799 if (chip->polling_mode || do_poll) {
800 spin_lock_irq(&chip->reg_lock);
801 azx_update_rirb(chip);
802 spin_unlock_irq(&chip->reg_lock);
804 if (!chip->rirb.cmds[addr]) {
809 chip->poll_count = 0;
810 return chip->rirb.res[addr]; /* the last value */
812 if (time_after(jiffies, timeout))
814 if (bus->needs_damn_long_delay || loopcounter > 3000)
815 msleep(2); /* temporary workaround */
822 if (!chip->polling_mode && chip->poll_count < 2) {
823 snd_printdd(SFX "azx_get_response timeout, "
824 "polling the codec once: last cmd=0x%08x\n",
825 chip->last_cmd[addr]);
832 if (!chip->polling_mode) {
833 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
834 "switching to polling mode: last cmd=0x%08x\n",
835 chip->last_cmd[addr]);
836 chip->polling_mode = 1;
841 snd_printk(KERN_WARNING SFX "No response from codec, "
842 "disabling MSI: last cmd=0x%08x\n",
843 chip->last_cmd[addr]);
844 free_irq(chip->irq, chip);
846 pci_disable_msi(chip->pci);
848 if (azx_acquire_irq(chip, 1) < 0) {
856 /* If this critical timeout happens during the codec probing
857 * phase, this is likely an access to a non-existing codec
858 * slot. Better to return an error and reset the system.
863 /* a fatal communication error; need either to reset or to fallback
864 * to the single_cmd mode
867 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
868 bus->response_reset = 1;
869 return -1; /* give a chance to retry */
872 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
873 "switching to single_cmd mode: last cmd=0x%08x\n",
874 chip->last_cmd[addr]);
875 chip->single_cmd = 1;
876 bus->response_reset = 0;
877 /* release CORB/RIRB */
878 azx_free_cmd_io(chip);
879 /* disable unsolicited responses */
880 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
885 * Use the single immediate command instead of CORB/RIRB for simplicity
887 * Note: according to Intel, this is not preferred use. The command was
888 * intended for the BIOS only, and may get confused with unsolicited
889 * responses. So, we shouldn't use it for normal operation from the
891 * I left the codes, however, for debugging/testing purposes.
894 /* receive a response */
895 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
900 /* check IRV busy bit */
901 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
902 /* reuse rirb.res as the response return value */
903 chip->rirb.res[addr] = azx_readl(chip, IR);
908 if (printk_ratelimit())
909 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
910 azx_readw(chip, IRS));
911 chip->rirb.res[addr] = -1;
916 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
918 struct azx *chip = bus->private_data;
919 unsigned int addr = azx_command_addr(val);
924 /* check ICB busy bit */
925 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
926 /* Clear IRV valid bit */
927 azx_writew(chip, IRS, azx_readw(chip, IRS) |
929 azx_writel(chip, IC, val);
930 azx_writew(chip, IRS, azx_readw(chip, IRS) |
932 return azx_single_wait_for_response(chip, addr);
936 if (printk_ratelimit())
937 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
938 azx_readw(chip, IRS), val);
942 /* receive a response */
943 static unsigned int azx_single_get_response(struct hda_bus *bus,
946 struct azx *chip = bus->private_data;
947 return chip->rirb.res[addr];
951 * The below are the main callbacks from hda_codec.
953 * They are just the skeleton to call sub-callbacks according to the
954 * current setting of chip->single_cmd.
958 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
960 struct azx *chip = bus->private_data;
962 chip->last_cmd[azx_command_addr(val)] = val;
963 if (chip->single_cmd)
964 return azx_single_send_cmd(bus, val);
966 return azx_corb_send_cmd(bus, val);
970 static unsigned int azx_get_response(struct hda_bus *bus,
973 struct azx *chip = bus->private_data;
974 if (chip->single_cmd)
975 return azx_single_get_response(bus, addr);
977 return azx_rirb_get_response(bus, addr);
980 #ifdef CONFIG_SND_HDA_POWER_SAVE
981 static void azx_power_notify(struct hda_bus *bus);
984 /* reset codec link */
985 static int azx_reset(struct azx *chip, int full_reset)
993 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
995 /* reset controller */
996 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
999 while (azx_readb(chip, GCTL) && --count)
1002 /* delay for >= 100us for codec PLL to settle per spec
1003 * Rev 0.9 section 5.5.1
1007 /* Bring controller out of reset */
1008 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1011 while (!azx_readb(chip, GCTL) && --count)
1014 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1018 /* check to see if controller is ready */
1019 if (!azx_readb(chip, GCTL)) {
1020 snd_printd(SFX "azx_reset: controller not ready!\n");
1024 /* Accept unsolicited responses */
1025 if (!chip->single_cmd)
1026 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1030 if (!chip->codec_mask) {
1031 chip->codec_mask = azx_readw(chip, STATESTS);
1032 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1040 * Lowlevel interface
1043 /* enable interrupts */
1044 static void azx_int_enable(struct azx *chip)
1046 /* enable controller CIE and GIE */
1047 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1048 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1051 /* disable interrupts */
1052 static void azx_int_disable(struct azx *chip)
1056 /* disable interrupts in stream descriptor */
1057 for (i = 0; i < chip->num_streams; i++) {
1058 struct azx_dev *azx_dev = &chip->azx_dev[i];
1059 azx_sd_writeb(azx_dev, SD_CTL,
1060 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1063 /* disable SIE for all streams */
1064 azx_writeb(chip, INTCTL, 0);
1066 /* disable controller CIE and GIE */
1067 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1068 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1071 /* clear interrupts */
1072 static void azx_int_clear(struct azx *chip)
1076 /* clear stream status */
1077 for (i = 0; i < chip->num_streams; i++) {
1078 struct azx_dev *azx_dev = &chip->azx_dev[i];
1079 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1082 /* clear STATESTS */
1083 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1085 /* clear rirb status */
1086 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1088 /* clear int status */
1089 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1092 /* start a stream */
1093 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1096 * Before stream start, initialize parameter
1098 azx_dev->insufficient = 1;
1101 azx_writel(chip, INTCTL,
1102 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1103 /* set DMA start and interrupt mask */
1104 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1105 SD_CTL_DMA_START | SD_INT_MASK);
1109 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1111 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1112 ~(SD_CTL_DMA_START | SD_INT_MASK));
1113 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1117 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1119 azx_stream_clear(chip, azx_dev);
1121 azx_writel(chip, INTCTL,
1122 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1127 * reset and start the controller registers
1129 static void azx_init_chip(struct azx *chip, int full_reset)
1131 if (chip->initialized)
1134 /* reset controller */
1135 azx_reset(chip, full_reset);
1137 /* initialize interrupts */
1138 azx_int_clear(chip);
1139 azx_int_enable(chip);
1141 /* initialize the codec command I/O */
1142 if (!chip->single_cmd)
1143 azx_init_cmd_io(chip);
1145 /* program the position buffer */
1146 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1147 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1149 chip->initialized = 1;
1153 * initialize the PCI registers
1155 /* update bits in a PCI register byte */
1156 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1157 unsigned char mask, unsigned char val)
1161 pci_read_config_byte(pci, reg, &data);
1163 data |= (val & mask);
1164 pci_write_config_byte(pci, reg, data);
1167 static void azx_init_pci(struct azx *chip)
1169 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1170 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1171 * Ensuring these bits are 0 clears playback static on some HD Audio
1173 * The PCI register TCSEL is defined in the Intel manuals.
1175 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1176 snd_printdd(SFX "Clearing TCSEL\n");
1177 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1180 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1181 * we need to enable snoop.
1183 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1184 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
1185 update_pci_byte(chip->pci,
1186 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1187 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1190 /* For NVIDIA HDA, enable snoop */
1191 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1192 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
1193 update_pci_byte(chip->pci,
1194 NVIDIA_HDA_TRANSREG_ADDR,
1195 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1196 update_pci_byte(chip->pci,
1197 NVIDIA_HDA_ISTRM_COH,
1198 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1199 update_pci_byte(chip->pci,
1200 NVIDIA_HDA_OSTRM_COH,
1201 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1204 /* Enable SCH/PCH snoop if needed */
1205 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1206 unsigned short snoop;
1207 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1208 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1209 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1210 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1211 if (!azx_snoop(chip))
1212 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1213 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1214 pci_read_config_word(chip->pci,
1215 INTEL_SCH_HDA_DEVC, &snoop);
1217 snd_printdd(SFX "SCH snoop: %s\n",
1218 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1219 ? "Disabled" : "Enabled");
1224 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1229 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1231 struct azx *chip = dev_id;
1232 struct azx_dev *azx_dev;
1237 spin_lock(&chip->reg_lock);
1239 status = azx_readl(chip, INTSTS);
1241 spin_unlock(&chip->reg_lock);
1245 for (i = 0; i < chip->num_streams; i++) {
1246 azx_dev = &chip->azx_dev[i];
1247 if (status & azx_dev->sd_int_sta_mask) {
1248 sd_status = azx_sd_readb(azx_dev, SD_STS);
1249 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1250 if (!azx_dev->substream || !azx_dev->running ||
1251 !(sd_status & SD_INT_COMPLETE))
1253 /* check whether this IRQ is really acceptable */
1254 ok = azx_position_ok(chip, azx_dev);
1256 azx_dev->irq_pending = 0;
1257 spin_unlock(&chip->reg_lock);
1258 snd_pcm_period_elapsed(azx_dev->substream);
1259 spin_lock(&chip->reg_lock);
1260 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1261 /* bogus IRQ, process it later */
1262 azx_dev->irq_pending = 1;
1263 queue_work(chip->bus->workq,
1264 &chip->irq_pending_work);
1269 /* clear rirb int */
1270 status = azx_readb(chip, RIRBSTS);
1271 if (status & RIRB_INT_MASK) {
1272 if (status & RIRB_INT_RESPONSE) {
1273 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1275 azx_update_rirb(chip);
1277 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1281 /* clear state status int */
1282 if (azx_readb(chip, STATESTS) & 0x04)
1283 azx_writeb(chip, STATESTS, 0x04);
1285 spin_unlock(&chip->reg_lock);
1292 * set up a BDL entry
1294 static int setup_bdle(struct azx *chip,
1295 struct snd_pcm_substream *substream,
1296 struct azx_dev *azx_dev, u32 **bdlp,
1297 int ofs, int size, int with_ioc)
1305 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1308 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1309 /* program the address field of the BDL entry */
1310 bdl[0] = cpu_to_le32((u32)addr);
1311 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1312 /* program the size field of the BDL entry */
1313 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1314 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1315 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1316 u32 remain = 0x1000 - (ofs & 0xfff);
1320 bdl[2] = cpu_to_le32(chunk);
1321 /* program the IOC to enable interrupt
1322 * only when the whole fragment is processed
1325 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1335 * set up BDL entries
1337 static int azx_setup_periods(struct azx *chip,
1338 struct snd_pcm_substream *substream,
1339 struct azx_dev *azx_dev)
1342 int i, ofs, periods, period_bytes;
1345 /* reset BDL address */
1346 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1347 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1349 period_bytes = azx_dev->period_bytes;
1350 periods = azx_dev->bufsize / period_bytes;
1352 /* program the initial BDL entries */
1353 bdl = (u32 *)azx_dev->bdl.area;
1356 pos_adj = bdl_pos_adj[chip->dev_index];
1358 struct snd_pcm_runtime *runtime = substream->runtime;
1359 int pos_align = pos_adj;
1360 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1362 pos_adj = pos_align;
1364 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1366 pos_adj = frames_to_bytes(runtime, pos_adj);
1367 if (pos_adj >= period_bytes) {
1368 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1369 bdl_pos_adj[chip->dev_index]);
1372 ofs = setup_bdle(chip, substream, azx_dev,
1374 !substream->runtime->no_period_wakeup);
1380 for (i = 0; i < periods; i++) {
1381 if (i == periods - 1 && pos_adj)
1382 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1383 period_bytes - pos_adj, 0);
1385 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1387 !substream->runtime->no_period_wakeup);
1394 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1395 azx_dev->bufsize, period_bytes);
1400 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1405 azx_stream_clear(chip, azx_dev);
1407 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1408 SD_CTL_STREAM_RESET);
1411 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1414 val &= ~SD_CTL_STREAM_RESET;
1415 azx_sd_writeb(azx_dev, SD_CTL, val);
1419 /* waiting for hardware to report that the stream is out of reset */
1420 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1424 /* reset first position - may not be synced with hw at this time */
1425 *azx_dev->posbuf = 0;
1429 * set up the SD for streaming
1431 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1434 /* make sure the run bit is zero for SD */
1435 azx_stream_clear(chip, azx_dev);
1436 /* program the stream_tag */
1437 val = azx_sd_readl(azx_dev, SD_CTL);
1438 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1439 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1440 if (!azx_snoop(chip))
1441 val |= SD_CTL_TRAFFIC_PRIO;
1442 azx_sd_writel(azx_dev, SD_CTL, val);
1444 /* program the length of samples in cyclic buffer */
1445 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1447 /* program the stream format */
1448 /* this value needs to be the same as the one programmed */
1449 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1451 /* program the stream LVI (last valid index) of the BDL */
1452 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1454 /* program the BDL address */
1455 /* lower BDL address */
1456 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1457 /* upper BDL address */
1458 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1460 /* enable the position buffer */
1461 if (chip->position_fix[0] != POS_FIX_LPIB ||
1462 chip->position_fix[1] != POS_FIX_LPIB) {
1463 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1464 azx_writel(chip, DPLBASE,
1465 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1468 /* set the interrupt enable bits in the descriptor control register */
1469 azx_sd_writel(azx_dev, SD_CTL,
1470 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1476 * Probe the given codec address
1478 static int probe_codec(struct azx *chip, int addr)
1480 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1481 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1484 mutex_lock(&chip->bus->cmd_mutex);
1486 azx_send_cmd(chip->bus, cmd);
1487 res = azx_get_response(chip->bus, addr);
1489 mutex_unlock(&chip->bus->cmd_mutex);
1492 snd_printdd(SFX "codec #%d probed OK\n", addr);
1496 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1497 struct hda_pcm *cpcm);
1498 static void azx_stop_chip(struct azx *chip);
1500 static void azx_bus_reset(struct hda_bus *bus)
1502 struct azx *chip = bus->private_data;
1505 azx_stop_chip(chip);
1506 azx_init_chip(chip, 1);
1508 if (chip->initialized) {
1510 list_for_each_entry(p, &chip->pcm_list, list)
1511 snd_pcm_suspend_all(p->pcm);
1512 snd_hda_suspend(chip->bus);
1513 snd_hda_resume(chip->bus);
1520 * Codec initialization
1523 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1524 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1525 [AZX_DRIVER_NVIDIA] = 8,
1526 [AZX_DRIVER_TERA] = 1,
1529 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1531 struct hda_bus_template bus_temp;
1535 memset(&bus_temp, 0, sizeof(bus_temp));
1536 bus_temp.private_data = chip;
1537 bus_temp.modelname = model;
1538 bus_temp.pci = chip->pci;
1539 bus_temp.ops.command = azx_send_cmd;
1540 bus_temp.ops.get_response = azx_get_response;
1541 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1542 bus_temp.ops.bus_reset = azx_bus_reset;
1543 #ifdef CONFIG_SND_HDA_POWER_SAVE
1544 bus_temp.power_save = &power_save;
1545 bus_temp.ops.pm_notify = azx_power_notify;
1548 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1552 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1553 snd_printd(SFX "Enable delay in RIRB handling\n");
1554 chip->bus->needs_damn_long_delay = 1;
1558 max_slots = azx_max_codecs[chip->driver_type];
1560 max_slots = AZX_DEFAULT_CODECS;
1562 /* First try to probe all given codec slots */
1563 for (c = 0; c < max_slots; c++) {
1564 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1565 if (probe_codec(chip, c) < 0) {
1566 /* Some BIOSen give you wrong codec addresses
1569 snd_printk(KERN_WARNING SFX
1570 "Codec #%d probe error; "
1571 "disabling it...\n", c);
1572 chip->codec_mask &= ~(1 << c);
1573 /* More badly, accessing to a non-existing
1574 * codec often screws up the controller chip,
1575 * and disturbs the further communications.
1576 * Thus if an error occurs during probing,
1577 * better to reset the controller chip to
1578 * get back to the sanity state.
1580 azx_stop_chip(chip);
1581 azx_init_chip(chip, 1);
1586 /* AMD chipsets often cause the communication stalls upon certain
1587 * sequence like the pin-detection. It seems that forcing the synced
1588 * access works around the stall. Grrr...
1590 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1591 snd_printd(SFX "Enable sync_write for stable communication\n");
1592 chip->bus->sync_write = 1;
1593 chip->bus->allow_bus_reset = 1;
1596 /* Then create codec instances */
1597 for (c = 0; c < max_slots; c++) {
1598 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1599 struct hda_codec *codec;
1600 err = snd_hda_codec_new(chip->bus, c, &codec);
1603 codec->beep_mode = chip->beep_mode;
1608 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1614 /* configure each codec instance */
1615 static int __devinit azx_codec_configure(struct azx *chip)
1617 struct hda_codec *codec;
1618 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1619 snd_hda_codec_configure(codec);
1629 /* assign a stream for the PCM */
1630 static inline struct azx_dev *
1631 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1634 struct azx_dev *res = NULL;
1635 /* make a non-zero unique key for the substream */
1636 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1637 (substream->stream + 1);
1639 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1640 dev = chip->playback_index_offset;
1641 nums = chip->playback_streams;
1643 dev = chip->capture_index_offset;
1644 nums = chip->capture_streams;
1646 for (i = 0; i < nums; i++, dev++)
1647 if (!chip->azx_dev[dev].opened) {
1648 res = &chip->azx_dev[dev];
1649 if (res->assigned_key == key)
1654 res->assigned_key = key;
1659 /* release the assigned stream */
1660 static inline void azx_release_device(struct azx_dev *azx_dev)
1662 azx_dev->opened = 0;
1665 static struct snd_pcm_hardware azx_pcm_hw = {
1666 .info = (SNDRV_PCM_INFO_MMAP |
1667 SNDRV_PCM_INFO_INTERLEAVED |
1668 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1669 SNDRV_PCM_INFO_MMAP_VALID |
1670 /* No full-resume yet implemented */
1671 /* SNDRV_PCM_INFO_RESUME |*/
1672 SNDRV_PCM_INFO_PAUSE |
1673 SNDRV_PCM_INFO_SYNC_START |
1674 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1675 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1676 .rates = SNDRV_PCM_RATE_48000,
1681 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1682 .period_bytes_min = 128,
1683 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1685 .periods_max = AZX_MAX_FRAG,
1689 static int azx_pcm_open(struct snd_pcm_substream *substream)
1691 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1692 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1693 struct azx *chip = apcm->chip;
1694 struct azx_dev *azx_dev;
1695 struct snd_pcm_runtime *runtime = substream->runtime;
1696 unsigned long flags;
1700 mutex_lock(&chip->open_mutex);
1701 azx_dev = azx_assign_device(chip, substream);
1702 if (azx_dev == NULL) {
1703 mutex_unlock(&chip->open_mutex);
1706 runtime->hw = azx_pcm_hw;
1707 runtime->hw.channels_min = hinfo->channels_min;
1708 runtime->hw.channels_max = hinfo->channels_max;
1709 runtime->hw.formats = hinfo->formats;
1710 runtime->hw.rates = hinfo->rates;
1711 snd_pcm_limit_hw_rates(runtime);
1712 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1713 if (chip->align_buffer_size)
1714 /* constrain buffer sizes to be multiple of 128
1715 bytes. This is more efficient in terms of memory
1716 access but isn't required by the HDA spec and
1717 prevents users from specifying exact period/buffer
1718 sizes. For example for 44.1kHz, a period size set
1719 to 20ms will be rounded to 19.59ms. */
1722 /* Don't enforce steps on buffer sizes, still need to
1723 be multiple of 4 bytes (HDA spec). Tested on Intel
1724 HDA controllers, may not work on all devices where
1725 option needs to be disabled */
1728 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1730 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1732 snd_hda_power_up(apcm->codec);
1733 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1735 azx_release_device(azx_dev);
1736 snd_hda_power_down(apcm->codec);
1737 mutex_unlock(&chip->open_mutex);
1740 snd_pcm_limit_hw_rates(runtime);
1742 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1743 snd_BUG_ON(!runtime->hw.channels_max) ||
1744 snd_BUG_ON(!runtime->hw.formats) ||
1745 snd_BUG_ON(!runtime->hw.rates)) {
1746 azx_release_device(azx_dev);
1747 hinfo->ops.close(hinfo, apcm->codec, substream);
1748 snd_hda_power_down(apcm->codec);
1749 mutex_unlock(&chip->open_mutex);
1752 spin_lock_irqsave(&chip->reg_lock, flags);
1753 azx_dev->substream = substream;
1754 azx_dev->running = 0;
1755 spin_unlock_irqrestore(&chip->reg_lock, flags);
1757 runtime->private_data = azx_dev;
1758 snd_pcm_set_sync(substream);
1759 mutex_unlock(&chip->open_mutex);
1763 static int azx_pcm_close(struct snd_pcm_substream *substream)
1765 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1766 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1767 struct azx *chip = apcm->chip;
1768 struct azx_dev *azx_dev = get_azx_dev(substream);
1769 unsigned long flags;
1771 mutex_lock(&chip->open_mutex);
1772 spin_lock_irqsave(&chip->reg_lock, flags);
1773 azx_dev->substream = NULL;
1774 azx_dev->running = 0;
1775 spin_unlock_irqrestore(&chip->reg_lock, flags);
1776 azx_release_device(azx_dev);
1777 hinfo->ops.close(hinfo, apcm->codec, substream);
1778 snd_hda_power_down(apcm->codec);
1779 mutex_unlock(&chip->open_mutex);
1783 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1784 struct snd_pcm_hw_params *hw_params)
1786 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1787 struct azx *chip = apcm->chip;
1788 struct snd_pcm_runtime *runtime = substream->runtime;
1789 struct azx_dev *azx_dev = get_azx_dev(substream);
1792 mark_runtime_wc(chip, azx_dev, runtime, false);
1793 azx_dev->bufsize = 0;
1794 azx_dev->period_bytes = 0;
1795 azx_dev->format_val = 0;
1796 ret = snd_pcm_lib_malloc_pages(substream,
1797 params_buffer_bytes(hw_params));
1800 mark_runtime_wc(chip, azx_dev, runtime, true);
1804 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1806 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1807 struct azx_dev *azx_dev = get_azx_dev(substream);
1808 struct azx *chip = apcm->chip;
1809 struct snd_pcm_runtime *runtime = substream->runtime;
1810 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1812 /* reset BDL address */
1813 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1814 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1815 azx_sd_writel(azx_dev, SD_CTL, 0);
1816 azx_dev->bufsize = 0;
1817 azx_dev->period_bytes = 0;
1818 azx_dev->format_val = 0;
1820 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1822 mark_runtime_wc(chip, azx_dev, runtime, false);
1823 return snd_pcm_lib_free_pages(substream);
1826 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1828 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1829 struct azx *chip = apcm->chip;
1830 struct azx_dev *azx_dev = get_azx_dev(substream);
1831 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1832 struct snd_pcm_runtime *runtime = substream->runtime;
1833 unsigned int bufsize, period_bytes, format_val, stream_tag;
1835 struct hda_spdif_out *spdif =
1836 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1837 unsigned short ctls = spdif ? spdif->ctls : 0;
1839 azx_stream_reset(chip, azx_dev);
1840 format_val = snd_hda_calc_stream_format(runtime->rate,
1846 snd_printk(KERN_ERR SFX
1847 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1848 runtime->rate, runtime->channels, runtime->format);
1852 bufsize = snd_pcm_lib_buffer_bytes(substream);
1853 period_bytes = snd_pcm_lib_period_bytes(substream);
1855 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1856 bufsize, format_val);
1858 if (bufsize != azx_dev->bufsize ||
1859 period_bytes != azx_dev->period_bytes ||
1860 format_val != azx_dev->format_val) {
1861 azx_dev->bufsize = bufsize;
1862 azx_dev->period_bytes = period_bytes;
1863 azx_dev->format_val = format_val;
1864 err = azx_setup_periods(chip, substream, azx_dev);
1869 /* wallclk has 24Mhz clock source */
1870 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1871 runtime->rate) * 1000);
1872 azx_setup_controller(chip, azx_dev);
1873 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1874 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1876 azx_dev->fifo_size = 0;
1878 stream_tag = azx_dev->stream_tag;
1879 /* CA-IBG chips need the playback stream starting from 1 */
1880 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
1881 stream_tag > chip->capture_streams)
1882 stream_tag -= chip->capture_streams;
1883 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1884 azx_dev->format_val, substream);
1887 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1889 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1890 struct azx *chip = apcm->chip;
1891 struct azx_dev *azx_dev;
1892 struct snd_pcm_substream *s;
1893 int rstart = 0, start, nsync = 0, sbits = 0;
1897 case SNDRV_PCM_TRIGGER_START:
1899 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1900 case SNDRV_PCM_TRIGGER_RESUME:
1903 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1904 case SNDRV_PCM_TRIGGER_SUSPEND:
1905 case SNDRV_PCM_TRIGGER_STOP:
1912 snd_pcm_group_for_each_entry(s, substream) {
1913 if (s->pcm->card != substream->pcm->card)
1915 azx_dev = get_azx_dev(s);
1916 sbits |= 1 << azx_dev->index;
1918 snd_pcm_trigger_done(s, substream);
1921 spin_lock(&chip->reg_lock);
1923 /* first, set SYNC bits of corresponding streams */
1924 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1925 azx_writel(chip, OLD_SSYNC,
1926 azx_readl(chip, OLD_SSYNC) | sbits);
1928 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
1930 snd_pcm_group_for_each_entry(s, substream) {
1931 if (s->pcm->card != substream->pcm->card)
1933 azx_dev = get_azx_dev(s);
1935 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1937 azx_dev->start_wallclk -=
1938 azx_dev->period_wallclk;
1939 azx_stream_start(chip, azx_dev);
1941 azx_stream_stop(chip, azx_dev);
1943 azx_dev->running = start;
1945 spin_unlock(&chip->reg_lock);
1949 /* wait until all FIFOs get ready */
1950 for (timeout = 5000; timeout; timeout--) {
1952 snd_pcm_group_for_each_entry(s, substream) {
1953 if (s->pcm->card != substream->pcm->card)
1955 azx_dev = get_azx_dev(s);
1956 if (!(azx_sd_readb(azx_dev, SD_STS) &
1965 /* wait until all RUN bits are cleared */
1966 for (timeout = 5000; timeout; timeout--) {
1968 snd_pcm_group_for_each_entry(s, substream) {
1969 if (s->pcm->card != substream->pcm->card)
1971 azx_dev = get_azx_dev(s);
1972 if (azx_sd_readb(azx_dev, SD_CTL) &
1982 spin_lock(&chip->reg_lock);
1983 /* reset SYNC bits */
1984 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1985 azx_writel(chip, OLD_SSYNC,
1986 azx_readl(chip, OLD_SSYNC) & ~sbits);
1988 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
1989 spin_unlock(&chip->reg_lock);
1994 /* get the current DMA position with correction on VIA chips */
1995 static unsigned int azx_via_get_position(struct azx *chip,
1996 struct azx_dev *azx_dev)
1998 unsigned int link_pos, mini_pos, bound_pos;
1999 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2000 unsigned int fifo_size;
2002 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2003 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2004 /* Playback, no problem using link position */
2010 * use mod to get the DMA position just like old chipset
2012 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2013 mod_dma_pos %= azx_dev->period_bytes;
2015 /* azx_dev->fifo_size can't get FIFO size of in stream.
2016 * Get from base address + offset.
2018 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2020 if (azx_dev->insufficient) {
2021 /* Link position never gather than FIFO size */
2022 if (link_pos <= fifo_size)
2025 azx_dev->insufficient = 0;
2028 if (link_pos <= fifo_size)
2029 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2031 mini_pos = link_pos - fifo_size;
2033 /* Find nearest previous boudary */
2034 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2035 mod_link_pos = link_pos % azx_dev->period_bytes;
2036 if (mod_link_pos >= fifo_size)
2037 bound_pos = link_pos - mod_link_pos;
2038 else if (mod_dma_pos >= mod_mini_pos)
2039 bound_pos = mini_pos - mod_mini_pos;
2041 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2042 if (bound_pos >= azx_dev->bufsize)
2046 /* Calculate real DMA position we want */
2047 return bound_pos + mod_dma_pos;
2050 static unsigned int azx_get_position(struct azx *chip,
2051 struct azx_dev *azx_dev,
2055 int stream = azx_dev->substream->stream;
2057 switch (chip->position_fix[stream]) {
2060 pos = azx_sd_readl(azx_dev, SD_LPIB);
2062 case POS_FIX_VIACOMBO:
2063 pos = azx_via_get_position(chip, azx_dev);
2066 /* use the position buffer */
2067 pos = le32_to_cpu(*azx_dev->posbuf);
2068 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2069 if (!pos || pos == (u32)-1) {
2071 "hda-intel: Invalid position buffer, "
2072 "using LPIB read method instead.\n");
2073 chip->position_fix[stream] = POS_FIX_LPIB;
2074 pos = azx_sd_readl(azx_dev, SD_LPIB);
2076 chip->position_fix[stream] = POS_FIX_POSBUF;
2081 if (pos >= azx_dev->bufsize)
2086 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2088 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2089 struct azx *chip = apcm->chip;
2090 struct azx_dev *azx_dev = get_azx_dev(substream);
2091 return bytes_to_frames(substream->runtime,
2092 azx_get_position(chip, azx_dev, false));
2096 * Check whether the current DMA position is acceptable for updating
2097 * periods. Returns non-zero if it's OK.
2099 * Many HD-audio controllers appear pretty inaccurate about
2100 * the update-IRQ timing. The IRQ is issued before actually the
2101 * data is processed. So, we need to process it afterwords in a
2104 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2110 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2111 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2112 return -1; /* bogus (too early) interrupt */
2114 stream = azx_dev->substream->stream;
2115 pos = azx_get_position(chip, azx_dev, true);
2117 if (WARN_ONCE(!azx_dev->period_bytes,
2118 "hda-intel: zero azx_dev->period_bytes"))
2119 return -1; /* this shouldn't happen! */
2120 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2121 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2122 /* NG - it's below the first next period boundary */
2123 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2124 azx_dev->start_wallclk += wallclk;
2125 return 1; /* OK, it's fine */
2129 * The work for pending PCM period updates.
2131 static void azx_irq_pending_work(struct work_struct *work)
2133 struct azx *chip = container_of(work, struct azx, irq_pending_work);
2136 if (!chip->irq_pending_warned) {
2138 "hda-intel: IRQ timing workaround is activated "
2139 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2140 chip->card->number);
2141 chip->irq_pending_warned = 1;
2146 spin_lock_irq(&chip->reg_lock);
2147 for (i = 0; i < chip->num_streams; i++) {
2148 struct azx_dev *azx_dev = &chip->azx_dev[i];
2149 if (!azx_dev->irq_pending ||
2150 !azx_dev->substream ||
2153 ok = azx_position_ok(chip, azx_dev);
2155 azx_dev->irq_pending = 0;
2156 spin_unlock(&chip->reg_lock);
2157 snd_pcm_period_elapsed(azx_dev->substream);
2158 spin_lock(&chip->reg_lock);
2159 } else if (ok < 0) {
2160 pending = 0; /* too early */
2164 spin_unlock_irq(&chip->reg_lock);
2171 /* clear irq_pending flags and assure no on-going workq */
2172 static void azx_clear_irq_pending(struct azx *chip)
2176 spin_lock_irq(&chip->reg_lock);
2177 for (i = 0; i < chip->num_streams; i++)
2178 chip->azx_dev[i].irq_pending = 0;
2179 spin_unlock_irq(&chip->reg_lock);
2183 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2184 struct vm_area_struct *area)
2186 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2187 struct azx *chip = apcm->chip;
2188 if (!azx_snoop(chip))
2189 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2190 return snd_pcm_lib_default_mmap(substream, area);
2193 #define azx_pcm_mmap NULL
2196 static struct snd_pcm_ops azx_pcm_ops = {
2197 .open = azx_pcm_open,
2198 .close = azx_pcm_close,
2199 .ioctl = snd_pcm_lib_ioctl,
2200 .hw_params = azx_pcm_hw_params,
2201 .hw_free = azx_pcm_hw_free,
2202 .prepare = azx_pcm_prepare,
2203 .trigger = azx_pcm_trigger,
2204 .pointer = azx_pcm_pointer,
2205 .mmap = azx_pcm_mmap,
2206 .page = snd_pcm_sgbuf_ops_page,
2209 static void azx_pcm_free(struct snd_pcm *pcm)
2211 struct azx_pcm *apcm = pcm->private_data;
2213 list_del(&apcm->list);
2218 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2221 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2222 struct hda_pcm *cpcm)
2224 struct azx *chip = bus->private_data;
2225 struct snd_pcm *pcm;
2226 struct azx_pcm *apcm;
2227 int pcm_dev = cpcm->device;
2231 list_for_each_entry(apcm, &chip->pcm_list, list) {
2232 if (apcm->pcm->device == pcm_dev) {
2233 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2237 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2238 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2239 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2243 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2244 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2249 apcm->codec = codec;
2250 pcm->private_data = apcm;
2251 pcm->private_free = azx_pcm_free;
2252 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2253 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2254 list_add_tail(&apcm->list, &chip->pcm_list);
2256 for (s = 0; s < 2; s++) {
2257 apcm->hinfo[s] = &cpcm->stream[s];
2258 if (cpcm->stream[s].substreams)
2259 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2261 /* buffer pre-allocation */
2262 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2263 if (size > MAX_PREALLOC_SIZE)
2264 size = MAX_PREALLOC_SIZE;
2265 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2266 snd_dma_pci_data(chip->pci),
2267 size, MAX_PREALLOC_SIZE);
2272 * mixer creation - all stuff is implemented in hda module
2274 static int __devinit azx_mixer_create(struct azx *chip)
2276 return snd_hda_build_controls(chip->bus);
2281 * initialize SD streams
2283 static int __devinit azx_init_stream(struct azx *chip)
2287 /* initialize each stream (aka device)
2288 * assign the starting bdl address to each stream (device)
2291 for (i = 0; i < chip->num_streams; i++) {
2292 struct azx_dev *azx_dev = &chip->azx_dev[i];
2293 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2294 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2295 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2296 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2297 azx_dev->sd_int_sta_mask = 1 << i;
2298 /* stream tag: must be non-zero and unique */
2300 azx_dev->stream_tag = i + 1;
2306 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2308 if (request_irq(chip->pci->irq, azx_interrupt,
2309 chip->msi ? 0 : IRQF_SHARED,
2310 KBUILD_MODNAME, chip)) {
2311 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2312 "disabling device\n", chip->pci->irq);
2314 snd_card_disconnect(chip->card);
2317 chip->irq = chip->pci->irq;
2318 pci_intx(chip->pci, !chip->msi);
2323 static void azx_stop_chip(struct azx *chip)
2325 if (!chip->initialized)
2328 /* disable interrupts */
2329 azx_int_disable(chip);
2330 azx_int_clear(chip);
2332 /* disable CORB/RIRB */
2333 azx_free_cmd_io(chip);
2335 /* disable position buffer */
2336 azx_writel(chip, DPLBASE, 0);
2337 azx_writel(chip, DPUBASE, 0);
2339 chip->initialized = 0;
2342 #ifdef CONFIG_SND_HDA_POWER_SAVE
2343 /* power-up/down the controller */
2344 static void azx_power_notify(struct hda_bus *bus)
2346 struct azx *chip = bus->private_data;
2347 struct hda_codec *c;
2350 list_for_each_entry(c, &bus->codec_list, list) {
2357 azx_init_chip(chip, 1);
2358 else if (chip->running && power_save_controller &&
2359 !bus->power_keep_link_on)
2360 azx_stop_chip(chip);
2362 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2369 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2371 struct snd_card *card = pci_get_drvdata(pci);
2372 struct azx *chip = card->private_data;
2375 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2376 azx_clear_irq_pending(chip);
2377 list_for_each_entry(p, &chip->pcm_list, list)
2378 snd_pcm_suspend_all(p->pcm);
2379 if (chip->initialized)
2380 snd_hda_suspend(chip->bus);
2381 azx_stop_chip(chip);
2382 if (chip->irq >= 0) {
2383 free_irq(chip->irq, chip);
2387 pci_disable_msi(chip->pci);
2388 pci_disable_device(pci);
2389 pci_save_state(pci);
2390 pci_set_power_state(pci, pci_choose_state(pci, state));
2394 static int azx_resume(struct pci_dev *pci)
2396 struct snd_card *card = pci_get_drvdata(pci);
2397 struct azx *chip = card->private_data;
2399 pci_set_power_state(pci, PCI_D0);
2400 pci_restore_state(pci);
2401 if (pci_enable_device(pci) < 0) {
2402 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2403 "disabling device\n");
2404 snd_card_disconnect(card);
2407 pci_set_master(pci);
2409 if (pci_enable_msi(pci) < 0)
2411 if (azx_acquire_irq(chip, 1) < 0)
2415 azx_init_chip(chip, 1);
2417 snd_hda_resume(chip->bus);
2418 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2421 #endif /* CONFIG_PM */
2425 * reboot notifier for hang-up problem at power-down
2427 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2429 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2430 snd_hda_bus_reboot_notify(chip->bus);
2431 azx_stop_chip(chip);
2435 static void azx_notifier_register(struct azx *chip)
2437 chip->reboot_notifier.notifier_call = azx_halt;
2438 register_reboot_notifier(&chip->reboot_notifier);
2441 static void azx_notifier_unregister(struct azx *chip)
2443 if (chip->reboot_notifier.notifier_call)
2444 unregister_reboot_notifier(&chip->reboot_notifier);
2450 static int azx_free(struct azx *chip)
2454 azx_notifier_unregister(chip);
2456 if (chip->initialized) {
2457 azx_clear_irq_pending(chip);
2458 for (i = 0; i < chip->num_streams; i++)
2459 azx_stream_stop(chip, &chip->azx_dev[i]);
2460 azx_stop_chip(chip);
2464 free_irq(chip->irq, (void*)chip);
2466 pci_disable_msi(chip->pci);
2467 if (chip->remap_addr)
2468 iounmap(chip->remap_addr);
2470 if (chip->azx_dev) {
2471 for (i = 0; i < chip->num_streams; i++)
2472 if (chip->azx_dev[i].bdl.area) {
2473 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2474 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2477 if (chip->rb.area) {
2478 mark_pages_wc(chip, &chip->rb, false);
2479 snd_dma_free_pages(&chip->rb);
2481 if (chip->posbuf.area) {
2482 mark_pages_wc(chip, &chip->posbuf, false);
2483 snd_dma_free_pages(&chip->posbuf);
2485 pci_release_regions(chip->pci);
2486 pci_disable_device(chip->pci);
2487 kfree(chip->azx_dev);
2493 static int azx_dev_free(struct snd_device *device)
2495 return azx_free(device->device_data);
2499 * white/black-listing for position_fix
2501 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2502 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2503 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2504 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2505 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2506 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2507 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2508 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2509 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
2510 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2511 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2512 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2513 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2514 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2515 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2519 static int __devinit check_position_fix(struct azx *chip, int fix)
2521 const struct snd_pci_quirk *q;
2525 case POS_FIX_POSBUF:
2526 case POS_FIX_VIACOMBO:
2531 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2534 "hda_intel: position_fix set to %d "
2535 "for device %04x:%04x\n",
2536 q->value, q->subvendor, q->subdevice);
2540 /* Check VIA/ATI HD Audio Controller exist */
2541 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2542 snd_printd(SFX "Using VIACOMBO position fix\n");
2543 return POS_FIX_VIACOMBO;
2545 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2546 snd_printd(SFX "Using LPIB position fix\n");
2547 return POS_FIX_LPIB;
2549 return POS_FIX_AUTO;
2553 * black-lists for probe_mask
2555 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2556 /* Thinkpad often breaks the controller communication when accessing
2557 * to the non-working (or non-existing) modem codec slot.
2559 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2560 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2561 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2563 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2564 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2565 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2566 /* forced codec slots */
2567 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2568 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2569 /* WinFast VP200 H (Teradici) user reported broken communication */
2570 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
2574 #define AZX_FORCE_CODEC_MASK 0x100
2576 static void __devinit check_probe_mask(struct azx *chip, int dev)
2578 const struct snd_pci_quirk *q;
2580 chip->codec_probe_mask = probe_mask[dev];
2581 if (chip->codec_probe_mask == -1) {
2582 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2585 "hda_intel: probe_mask set to 0x%x "
2586 "for device %04x:%04x\n",
2587 q->value, q->subvendor, q->subdevice);
2588 chip->codec_probe_mask = q->value;
2592 /* check forced option */
2593 if (chip->codec_probe_mask != -1 &&
2594 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2595 chip->codec_mask = chip->codec_probe_mask & 0xff;
2596 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2602 * white/black-list for enable_msi
2604 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2605 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2606 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2607 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2608 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2609 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2613 static void __devinit check_msi(struct azx *chip)
2615 const struct snd_pci_quirk *q;
2617 if (enable_msi >= 0) {
2618 chip->msi = !!enable_msi;
2621 chip->msi = 1; /* enable MSI as default */
2622 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2625 "hda_intel: msi for device %04x:%04x set to %d\n",
2626 q->subvendor, q->subdevice, q->value);
2627 chip->msi = q->value;
2631 /* NVidia chipsets seem to cause troubles with MSI */
2632 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2633 printk(KERN_INFO "hda_intel: Disabling MSI\n");
2638 /* check the snoop mode availability */
2639 static void __devinit azx_check_snoop_available(struct azx *chip)
2641 bool snoop = chip->snoop;
2643 switch (chip->driver_type) {
2644 case AZX_DRIVER_VIA:
2645 /* force to non-snoop mode for a new VIA controller
2650 pci_read_config_byte(chip->pci, 0x42, &val);
2651 if (!(val & 0x80) && chip->pci->revision == 0x30)
2655 case AZX_DRIVER_ATIHDMI_NS:
2656 /* new ATI HDMI requires non-snoop */
2661 if (snoop != chip->snoop) {
2662 snd_printk(KERN_INFO SFX "Force to %s mode\n",
2663 snoop ? "snoop" : "non-snoop");
2664 chip->snoop = snoop;
2671 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2672 int dev, unsigned int driver_caps,
2677 unsigned short gcap;
2678 static struct snd_device_ops ops = {
2679 .dev_free = azx_dev_free,
2684 err = pci_enable_device(pci);
2688 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2690 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2691 pci_disable_device(pci);
2695 spin_lock_init(&chip->reg_lock);
2696 mutex_init(&chip->open_mutex);
2700 chip->driver_caps = driver_caps;
2701 chip->driver_type = driver_caps & 0xff;
2703 chip->dev_index = dev;
2704 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2705 INIT_LIST_HEAD(&chip->pcm_list);
2707 chip->position_fix[0] = chip->position_fix[1] =
2708 check_position_fix(chip, position_fix[dev]);
2709 /* combo mode uses LPIB for playback */
2710 if (chip->position_fix[0] == POS_FIX_COMBO) {
2711 chip->position_fix[0] = POS_FIX_LPIB;
2712 chip->position_fix[1] = POS_FIX_AUTO;
2715 check_probe_mask(chip, dev);
2717 chip->single_cmd = single_cmd;
2718 chip->snoop = hda_snoop;
2719 azx_check_snoop_available(chip);
2721 if (bdl_pos_adj[dev] < 0) {
2722 switch (chip->driver_type) {
2723 case AZX_DRIVER_ICH:
2724 case AZX_DRIVER_PCH:
2725 bdl_pos_adj[dev] = 1;
2728 bdl_pos_adj[dev] = 32;
2733 #if BITS_PER_LONG != 64
2734 /* Fix up base address on ULI M5461 */
2735 if (chip->driver_type == AZX_DRIVER_ULI) {
2737 pci_read_config_word(pci, 0x40, &tmp3);
2738 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2739 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2743 err = pci_request_regions(pci, "ICH HD audio");
2746 pci_disable_device(pci);
2750 chip->addr = pci_resource_start(pci, 0);
2751 chip->remap_addr = pci_ioremap_bar(pci, 0);
2752 if (chip->remap_addr == NULL) {
2753 snd_printk(KERN_ERR SFX "ioremap error\n");
2759 if (pci_enable_msi(pci) < 0)
2762 if (azx_acquire_irq(chip, 0) < 0) {
2767 pci_set_master(pci);
2768 synchronize_irq(chip->irq);
2770 gcap = azx_readw(chip, GCAP);
2771 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2773 /* disable SB600 64bit support for safety */
2774 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
2775 struct pci_dev *p_smbus;
2776 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2777 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2780 if (p_smbus->revision < 0x30)
2781 gcap &= ~ICH6_GCAP_64OK;
2782 pci_dev_put(p_smbus);
2786 /* disable 64bit DMA address on some devices */
2787 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
2788 snd_printd(SFX "Disabling 64bit DMA\n");
2789 gcap &= ~ICH6_GCAP_64OK;
2792 /* disable buffer size rounding to 128-byte multiples if supported */
2793 if (align_buffer_size >= 0)
2794 chip->align_buffer_size = !!align_buffer_size;
2796 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
2797 chip->align_buffer_size = 0;
2798 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
2799 chip->align_buffer_size = 1;
2801 chip->align_buffer_size = 1;
2804 /* allow 64bit DMA address if supported by H/W */
2805 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2806 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2808 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2809 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2812 /* read number of streams from GCAP register instead of using
2815 chip->capture_streams = (gcap >> 8) & 0x0f;
2816 chip->playback_streams = (gcap >> 12) & 0x0f;
2817 if (!chip->playback_streams && !chip->capture_streams) {
2818 /* gcap didn't give any info, switching to old method */
2820 switch (chip->driver_type) {
2821 case AZX_DRIVER_ULI:
2822 chip->playback_streams = ULI_NUM_PLAYBACK;
2823 chip->capture_streams = ULI_NUM_CAPTURE;
2825 case AZX_DRIVER_ATIHDMI:
2826 case AZX_DRIVER_ATIHDMI_NS:
2827 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2828 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2830 case AZX_DRIVER_GENERIC:
2832 chip->playback_streams = ICH6_NUM_PLAYBACK;
2833 chip->capture_streams = ICH6_NUM_CAPTURE;
2837 chip->capture_index_offset = 0;
2838 chip->playback_index_offset = chip->capture_streams;
2839 chip->num_streams = chip->playback_streams + chip->capture_streams;
2840 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2842 if (!chip->azx_dev) {
2843 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2847 for (i = 0; i < chip->num_streams; i++) {
2848 /* allocate memory for the BDL for each stream */
2849 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2850 snd_dma_pci_data(chip->pci),
2851 BDL_SIZE, &chip->azx_dev[i].bdl);
2853 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2856 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
2858 /* allocate memory for the position buffer */
2859 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2860 snd_dma_pci_data(chip->pci),
2861 chip->num_streams * 8, &chip->posbuf);
2863 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2866 mark_pages_wc(chip, &chip->posbuf, true);
2867 /* allocate CORB/RIRB */
2868 err = azx_alloc_cmd_io(chip);
2872 /* initialize streams */
2873 azx_init_stream(chip);
2875 /* initialize chip */
2877 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
2879 /* codec detection */
2880 if (!chip->codec_mask) {
2881 snd_printk(KERN_ERR SFX "no codecs found!\n");
2886 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2888 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2892 strcpy(card->driver, "HDA-Intel");
2893 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2894 sizeof(card->shortname));
2895 snprintf(card->longname, sizeof(card->longname),
2896 "%s at 0x%lx irq %i",
2897 card->shortname, chip->addr, chip->irq);
2907 static void power_down_all_codecs(struct azx *chip)
2909 #ifdef CONFIG_SND_HDA_POWER_SAVE
2910 /* The codecs were powered up in snd_hda_codec_new().
2911 * Now all initialization done, so turn them down if possible
2913 struct hda_codec *codec;
2914 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2915 snd_hda_power_down(codec);
2920 static int __devinit azx_probe(struct pci_dev *pci,
2921 const struct pci_device_id *pci_id)
2924 struct snd_card *card;
2928 if (dev >= SNDRV_CARDS)
2935 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2937 snd_printk(KERN_ERR SFX "Error creating card!\n");
2941 /* set this here since it's referred in snd_hda_load_patch() */
2942 snd_card_set_dev(card, &pci->dev);
2944 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2947 card->private_data = chip;
2949 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2950 chip->beep_mode = beep_mode[dev];
2953 /* create codec instances */
2954 err = azx_codec_create(chip, model[dev]);
2957 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2958 if (patch[dev] && *patch[dev]) {
2959 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2961 err = snd_hda_load_patch(chip->bus, patch[dev]);
2966 if ((probe_only[dev] & 1) == 0) {
2967 err = azx_codec_configure(chip);
2972 /* create PCM streams */
2973 err = snd_hda_build_pcms(chip->bus);
2977 /* create mixer controls */
2978 err = azx_mixer_create(chip);
2982 err = snd_card_register(card);
2986 pci_set_drvdata(pci, card);
2988 power_down_all_codecs(chip);
2989 azx_notifier_register(chip);
2994 snd_card_free(card);
2998 static void __devexit azx_remove(struct pci_dev *pci)
3000 snd_card_free(pci_get_drvdata(pci));
3001 pci_set_drvdata(pci, NULL);
3005 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
3007 { PCI_DEVICE(0x8086, 0x1c20),
3008 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3009 AZX_DCAPS_BUFSIZE },
3011 { PCI_DEVICE(0x8086, 0x1d20),
3012 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3015 { PCI_DEVICE(0x8086, 0x1e20),
3016 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3019 { PCI_DEVICE(0x8086, 0x8c20),
3020 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3023 { PCI_DEVICE(0x8086, 0x811b),
3024 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3025 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
3026 { PCI_DEVICE(0x8086, 0x080a),
3027 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3028 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
3030 { PCI_DEVICE(0x8086, 0x2668),
3031 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3032 AZX_DCAPS_BUFSIZE }, /* ICH6 */
3033 { PCI_DEVICE(0x8086, 0x27d8),
3034 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3035 AZX_DCAPS_BUFSIZE }, /* ICH7 */
3036 { PCI_DEVICE(0x8086, 0x269a),
3037 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3038 AZX_DCAPS_BUFSIZE }, /* ESB2 */
3039 { PCI_DEVICE(0x8086, 0x284b),
3040 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3041 AZX_DCAPS_BUFSIZE }, /* ICH8 */
3042 { PCI_DEVICE(0x8086, 0x293e),
3043 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3044 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3045 { PCI_DEVICE(0x8086, 0x293f),
3046 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3047 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3048 { PCI_DEVICE(0x8086, 0x3a3e),
3049 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3050 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3051 { PCI_DEVICE(0x8086, 0x3a6e),
3052 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3053 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3055 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3056 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3057 .class_mask = 0xffffff,
3058 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3059 /* ATI SB 450/600/700/800/900 */
3060 { PCI_DEVICE(0x1002, 0x437b),
3061 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3062 { PCI_DEVICE(0x1002, 0x4383),
3063 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3065 { PCI_DEVICE(0x1022, 0x780d),
3066 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3068 { PCI_DEVICE(0x1002, 0x793b),
3069 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3070 { PCI_DEVICE(0x1002, 0x7919),
3071 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3072 { PCI_DEVICE(0x1002, 0x960f),
3073 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3074 { PCI_DEVICE(0x1002, 0x970f),
3075 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3076 { PCI_DEVICE(0x1002, 0xaa00),
3077 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3078 { PCI_DEVICE(0x1002, 0xaa08),
3079 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3080 { PCI_DEVICE(0x1002, 0xaa10),
3081 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3082 { PCI_DEVICE(0x1002, 0xaa18),
3083 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3084 { PCI_DEVICE(0x1002, 0xaa20),
3085 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3086 { PCI_DEVICE(0x1002, 0xaa28),
3087 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3088 { PCI_DEVICE(0x1002, 0xaa30),
3089 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3090 { PCI_DEVICE(0x1002, 0xaa38),
3091 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3092 { PCI_DEVICE(0x1002, 0xaa40),
3093 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3094 { PCI_DEVICE(0x1002, 0xaa48),
3095 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3096 { PCI_DEVICE(0x1002, 0x9902),
3097 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3098 { PCI_DEVICE(0x1002, 0xaaa0),
3099 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3100 { PCI_DEVICE(0x1002, 0xaaa8),
3101 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3102 { PCI_DEVICE(0x1002, 0xaab0),
3103 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3104 /* VIA VT8251/VT8237A */
3105 { PCI_DEVICE(0x1106, 0x3288),
3106 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3108 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3110 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3112 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3113 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3114 .class_mask = 0xffffff,
3115 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3117 { PCI_DEVICE(0x6549, 0x1200),
3118 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3119 /* Creative X-Fi (CA0110-IBG) */
3120 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3121 /* the following entry conflicts with snd-ctxfi driver,
3122 * as ctxfi driver mutates from HD-audio to native mode with
3123 * a special command sequence.
3125 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3126 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3127 .class_mask = 0xffffff,
3128 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3129 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3131 /* this entry seems still valid -- i.e. without emu20kx chip */
3132 { PCI_DEVICE(0x1102, 0x0009),
3133 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3134 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3137 { PCI_DEVICE(0x1102, 0x0010),
3138 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3139 { PCI_DEVICE(0x1102, 0x0012),
3140 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3142 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3143 /* VMware HDAudio */
3144 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3145 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3146 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3147 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3148 .class_mask = 0xffffff,
3149 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3150 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3151 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3152 .class_mask = 0xffffff,
3153 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3156 MODULE_DEVICE_TABLE(pci, azx_ids);
3158 /* pci_driver definition */
3159 static struct pci_driver azx_driver = {
3160 .name = KBUILD_MODNAME,
3161 .id_table = azx_ids,
3163 .remove = __devexit_p(azx_remove),
3165 .suspend = azx_suspend,
3166 .resume = azx_resume,
3170 module_pci_driver(azx_driver);