sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/reboot.h>
  48 #include <linux/io.h>
  49 #include <linux/pm_runtime.h>
  50 #include <linux/clocksource.h>
  51 #include <linux/time.h>
  52 #include <linux/completion.h>
  53
  54 #ifdef CONFIG_X86
  55 /* for snoop control */
  56 #include <asm/pgtable.h>
  57 #include <asm/cacheflush.h>
  58 #endif
  59 #include <sound/core.h>
  60 #include <sound/initval.h>
  61 #include <linux/vgaarb.h>
  62 #include <linux/vga_switcheroo.h>
  63 #include <linux/firmware.h>
  64 #include "hda_codec.h"
  65 #include "hda_i915.h"
  66
  67
  68 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  69 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  70 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  71 static char *model[SNDRV_CARDS];
  72 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  73 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  74 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  75 static int probe_only[SNDRV_CARDS];
  76 static int jackpoll_ms[SNDRV_CARDS];
  77 static bool single_cmd;
  78 static int enable_msi = -1;
  79 #ifdef CONFIG_SND_HDA_PATCH_LOADER
  80 static char *patch[SNDRV_CARDS];
  81 #endif
  82 #ifdef CONFIG_SND_HDA_INPUT_BEEP
  83 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
  84                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
  85 #endif
  86
  87 module_param_array(index, int, NULL, 0444);
  88 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  89 module_param_array(id, charp, NULL, 0444);
  90 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  91 module_param_array(enable, bool, NULL, 0444);
  92 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  93 module_param_array(model, charp, NULL, 0444);
  94 MODULE_PARM_DESC(model, "Use the given board model.");
  95 module_param_array(position_fix, int, NULL, 0444);
  96 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
  97                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
  98 module_param_array(bdl_pos_adj, int, NULL, 0644);
  99 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 100 module_param_array(probe_mask, int, NULL, 0444);
 101 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 102 module_param_array(probe_only, int, NULL, 0444);
 103 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 104 module_param_array(jackpoll_ms, int, NULL, 0444);
 105 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 106 module_param(single_cmd, bool, 0444);
 107 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 108                  "(for debugging only).");
 109 module_param(enable_msi, bint, 0444);
 110 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 111 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 112 module_param_array(patch, charp, NULL, 0444);
 113 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 114 #endif
 115 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 116 module_param_array(beep_mode, bool, NULL, 0444);
 117 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 118                             "(0=off, 1=on) (default=1).");
 119 #endif
 120
 121 #ifdef CONFIG_PM
 122 static int param_set_xint(const char *val, const struct kernel_param *kp);
 123 static struct kernel_param_ops param_ops_xint = {
 124         .set = param_set_xint,
 125         .get = param_get_int,
 126 };
 127 #define param_check_xint param_check_int
 128
 129 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 130 module_param(power_save, xint, 0644);
 131 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 132                  "(in second, 0 = disable).");
 133
 134 /* reset the HD-audio controller in power save mode.
 135  * this may give more power-saving, but will take longer time to
 136  * wake up.
 137  */
 138 static bool power_save_controller = 1;
 139 module_param(power_save_controller, bool, 0644);
 140 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 141 #endif /* CONFIG_PM */
 142
 143 static int align_buffer_size = -1;
 144 module_param(align_buffer_size, bint, 0644);
 145 MODULE_PARM_DESC(align_buffer_size,
 146                 "Force buffer and period sizes to be multiple of 128 bytes.");
 147
 148 #ifdef CONFIG_X86
 149 static bool hda_snoop = true;
 150 module_param_named(snoop, hda_snoop, bool, 0444);
 151 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 152 #define azx_snoop(chip)         (chip)->snoop
 153 #else
 154 #define hda_snoop               true
 155 #define azx_snoop(chip)         true
 156 #endif
 157
 158
 159 MODULE_LICENSE("GPL");
 160 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 161                          "{Intel, ICH6M},"
 162                          "{Intel, ICH7},"
 163                          "{Intel, ESB2},"
 164                          "{Intel, ICH8},"
 165                          "{Intel, ICH9},"
 166                          "{Intel, ICH10},"
 167                          "{Intel, PCH},"
 168                          "{Intel, CPT},"
 169                          "{Intel, PPT},"
 170                          "{Intel, LPT},"
 171                          "{Intel, LPT_LP},"
 172                          "{Intel, WPT_LP},"
 173                          "{Intel, HPT},"
 174                          "{Intel, PBG},"
 175                          "{Intel, SCH},"
 176                          "{ATI, SB450},"
 177                          "{ATI, SB600},"
 178                          "{ATI, RS600},"
 179                          "{ATI, RS690},"
 180                          "{ATI, RS780},"
 181                          "{ATI, R600},"
 182                          "{ATI, RV630},"
 183                          "{ATI, RV610},"
 184                          "{ATI, RV670},"
 185                          "{ATI, RV635},"
 186                          "{ATI, RV620},"
 187                          "{ATI, RV770},"
 188                          "{VIA, VT8251},"
 189                          "{VIA, VT8237A},"
 190                          "{SiS, SIS966},"
 191                          "{ULI, M5461}}");
 192 MODULE_DESCRIPTION("Intel HDA driver");
 193
 194 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 195 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 196 #define SUPPORT_VGA_SWITCHEROO
 197 #endif
 198 #endif
 199
 200
 201 /*
 202  * registers
 203  */
 204 #define ICH6_REG_GCAP                   0x00
 205 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
 206 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
 207 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
 208 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
 209 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
 210 #define ICH6_REG_VMIN                   0x02
 211 #define ICH6_REG_VMAJ                   0x03
 212 #define ICH6_REG_OUTPAY                 0x04
 213 #define ICH6_REG_INPAY                  0x06
 214 #define ICH6_REG_GCTL                   0x08
 215 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
 216 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
 217 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
 218 #define ICH6_REG_WAKEEN                 0x0c
 219 #define ICH6_REG_STATESTS               0x0e
 220 #define ICH6_REG_GSTS                   0x10
 221 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
 222 #define ICH6_REG_INTCTL                 0x20
 223 #define ICH6_REG_INTSTS                 0x24
 224 #define ICH6_REG_WALLCLK                0x30    /* 24Mhz source */
 225 #define ICH6_REG_OLD_SSYNC              0x34    /* SSYNC for old ICH */
 226 #define ICH6_REG_SSYNC                  0x38
 227 #define ICH6_REG_CORBLBASE              0x40
 228 #define ICH6_REG_CORBUBASE              0x44
 229 #define ICH6_REG_CORBWP                 0x48
 230 #define ICH6_REG_CORBRP                 0x4a
 231 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
 232 #define ICH6_REG_CORBCTL                0x4c
 233 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
 234 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
 235 #define ICH6_REG_CORBSTS                0x4d
 236 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
 237 #define ICH6_REG_CORBSIZE               0x4e
 238
 239 #define ICH6_REG_RIRBLBASE              0x50
 240 #define ICH6_REG_RIRBUBASE              0x54
 241 #define ICH6_REG_RIRBWP                 0x58
 242 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
 243 #define ICH6_REG_RINTCNT                0x5a
 244 #define ICH6_REG_RIRBCTL                0x5c
 245 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
 246 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
 247 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
 248 #define ICH6_REG_RIRBSTS                0x5d
 249 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
 250 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
 251 #define ICH6_REG_RIRBSIZE               0x5e
 252
 253 #define ICH6_REG_IC                     0x60
 254 #define ICH6_REG_IR                     0x64
 255 #define ICH6_REG_IRS                    0x68
 256 #define   ICH6_IRS_VALID        (1<<1)
 257 #define   ICH6_IRS_BUSY         (1<<0)
 258
 259 #define ICH6_REG_DPLBASE                0x70
 260 #define ICH6_REG_DPUBASE                0x74
 261 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 262
 263 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 264 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 265
 266 /* stream register offsets from stream base */
 267 #define ICH6_REG_SD_CTL                 0x00
 268 #define ICH6_REG_SD_STS                 0x03
 269 #define ICH6_REG_SD_LPIB                0x04
 270 #define ICH6_REG_SD_CBL                 0x08
 271 #define ICH6_REG_SD_LVI                 0x0c
 272 #define ICH6_REG_SD_FIFOW               0x0e
 273 #define ICH6_REG_SD_FIFOSIZE            0x10
 274 #define ICH6_REG_SD_FORMAT              0x12
 275 #define ICH6_REG_SD_BDLPL               0x18
 276 #define ICH6_REG_SD_BDLPU               0x1c
 277
 278 /* PCI space */
 279 #define ICH6_PCIREG_TCSEL       0x44
 280
 281 /*
 282  * other constants
 283  */
 284
 285 /* max number of SDs */
 286 /* ICH, ATI and VIA have 4 playback and 4 capture */
 287 #define ICH6_NUM_CAPTURE        4
 288 #define ICH6_NUM_PLAYBACK       4
 289
 290 /* ULI has 6 playback and 5 capture */
 291 #define ULI_NUM_CAPTURE         5
 292 #define ULI_NUM_PLAYBACK        6
 293
 294 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 295 #define ATIHDMI_NUM_CAPTURE     0
 296 #define ATIHDMI_NUM_PLAYBACK    8
 297
 298 /* TERA has 4 playback and 3 capture */
 299 #define TERA_NUM_CAPTURE        3
 300 #define TERA_NUM_PLAYBACK       4
 301
 302 /* this number is statically defined for simplicity */
 303 #define MAX_AZX_DEV             16
 304
 305 /* max number of fragments - we may use more if allocating more pages for BDL */
 306 #define BDL_SIZE                4096
 307 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 308 #define AZX_MAX_FRAG            32
 309 /* max buffer size - no h/w limit, you can increase as you like */
 310 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 311
 312 /* RIRB int mask: overrun[2], response[0] */
 313 #define RIRB_INT_RESPONSE       0x01
 314 #define RIRB_INT_OVERRUN        0x04
 315 #define RIRB_INT_MASK           0x05
 316
 317 /* STATESTS int mask: S3,SD2,SD1,SD0 */
 318 #define AZX_MAX_CODECS          8
 319 #define AZX_DEFAULT_CODECS      4
 320 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
 321
 322 /* SD_CTL bits */
 323 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 324 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 325 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 326 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 327 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 328 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 329 #define SD_CTL_STREAM_TAG_SHIFT 20
 330
 331 /* SD_CTL and SD_STS */
 332 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 333 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 334 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 335 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 336                                  SD_INT_COMPLETE)
 337
 338 /* SD_STS */
 339 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 340
 341 /* INTCTL and INTSTS */
 342 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 343 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 344 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 345
 346 /* below are so far hardcoded - should read registers in future */
 347 #define ICH6_MAX_CORB_ENTRIES   256
 348 #define ICH6_MAX_RIRB_ENTRIES   256
 349
 350 /* position fix mode */
 351 enum {
 352         POS_FIX_AUTO,
 353         POS_FIX_LPIB,
 354         POS_FIX_POSBUF,
 355         POS_FIX_VIACOMBO,
 356         POS_FIX_COMBO,
 357 };
 358
 359 /* Defines for ATI HD Audio support in SB450 south bridge */
 360 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 361 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 362
 363 /* Defines for Nvidia HDA support */
 364 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 365 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 366 #define NVIDIA_HDA_ISTRM_COH          0x4d
 367 #define NVIDIA_HDA_OSTRM_COH          0x4c
 368 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 369
 370 /* Defines for Intel SCH HDA snoop control */
 371 #define INTEL_SCH_HDA_DEVC      0x78
 372 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 373
 374 /* Define IN stream 0 FIFO size offset in VIA controller */
 375 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 376 /* Define VIA HD Audio Device ID*/
 377 #define VIA_HDAC_DEVICE_ID              0x3288
 378
 379 /* HD Audio class code */
 380 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
 381
 382 /*
 383  */
 384
 385 struct azx_dev {
 386         struct snd_dma_buffer bdl; /* BDL buffer */
 387         u32 *posbuf;            /* position buffer pointer */
 388
 389         unsigned int bufsize;   /* size of the play buffer in bytes */
 390         unsigned int period_bytes; /* size of the period in bytes */
 391         unsigned int frags;     /* number for period in the play buffer */
 392         unsigned int fifo_size; /* FIFO size */
 393         unsigned long start_wallclk;    /* start + minimum wallclk */
 394         unsigned long period_wallclk;   /* wallclk for period */
 395
 396         void __iomem *sd_addr;  /* stream descriptor pointer */
 397
 398         u32 sd_int_sta_mask;    /* stream int status mask */
 399
 400         /* pcm support */
 401         struct snd_pcm_substream *substream;    /* assigned substream,
 402                                                  * set in PCM open
 403                                                  */
 404         unsigned int format_val;        /* format value to be set in the
 405                                          * controller and the codec
 406                                          */
 407         unsigned char stream_tag;       /* assigned stream */
 408         unsigned char index;            /* stream index */
 409         int assigned_key;               /* last device# key assigned to */
 410
 411         unsigned int opened :1;
 412         unsigned int running :1;
 413         unsigned int irq_pending :1;
 414         unsigned int prepared:1;
 415         unsigned int locked:1;
 416         /*
 417          * For VIA:
 418          *  A flag to ensure DMA position is 0
 419          *  when link position is not greater than FIFO size
 420          */
 421         unsigned int insufficient :1;
 422         unsigned int wc_marked:1;
 423         unsigned int no_period_wakeup:1;
 424
 425         struct timecounter  azx_tc;
 426         struct cyclecounter azx_cc;
 427
 428         int delay_negative_threshold;
 429
 430 #ifdef CONFIG_SND_HDA_DSP_LOADER
 431         struct mutex dsp_mutex;
 432 #endif
 433 };
 434
 435 /* DSP lock helpers */
 436 #ifdef CONFIG_SND_HDA_DSP_LOADER
 437 #define dsp_lock_init(dev)      mutex_init(&(dev)->dsp_mutex)
 438 #define dsp_lock(dev)           mutex_lock(&(dev)->dsp_mutex)
 439 #define dsp_unlock(dev)         mutex_unlock(&(dev)->dsp_mutex)
 440 #define dsp_is_locked(dev)      ((dev)->locked)
 441 #else
 442 #define dsp_lock_init(dev)      do {} while (0)
 443 #define dsp_lock(dev)           do {} while (0)
 444 #define dsp_unlock(dev)         do {} while (0)
 445 #define dsp_is_locked(dev)      0
 446 #endif
 447
 448 /* CORB/RIRB */
 449 struct azx_rb {
 450         u32 *buf;               /* CORB/RIRB buffer
 451                                  * Each CORB entry is 4byte, RIRB is 8byte
 452                                  */
 453         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 454         /* for RIRB */
 455         unsigned short rp, wp;  /* read/write pointers */
 456         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
 457         u32 res[AZX_MAX_CODECS];        /* last read value */
 458 };
 459
 460 struct azx_pcm {
 461         struct azx *chip;
 462         struct snd_pcm *pcm;
 463         struct hda_codec *codec;
 464         struct hda_pcm_stream *hinfo[2];
 465         struct list_head list;
 466 };
 467
 468 struct azx {
 469         struct snd_card *card;
 470         struct pci_dev *pci;
 471         int dev_index;
 472
 473         /* chip type specific */
 474         int driver_type;
 475         unsigned int driver_caps;
 476         int playback_streams;
 477         int playback_index_offset;
 478         int capture_streams;
 479         int capture_index_offset;
 480         int num_streams;
 481
 482         /* pci resources */
 483         unsigned long addr;
 484         void __iomem *remap_addr;
 485         int irq;
 486
 487         /* locks */
 488         spinlock_t reg_lock;
 489         struct mutex open_mutex;
 490         struct completion probe_wait;
 491
 492         /* streams (x num_streams) */
 493         struct azx_dev *azx_dev;
 494
 495         /* PCM */
 496         struct list_head pcm_list; /* azx_pcm list */
 497
 498         /* HD codec */
 499         unsigned short codec_mask;
 500         int  codec_probe_mask; /* copied from probe_mask option */
 501         struct hda_bus *bus;
 502         unsigned int beep_mode;
 503
 504         /* CORB/RIRB */
 505         struct azx_rb corb;
 506         struct azx_rb rirb;
 507
 508         /* CORB/RIRB and position buffers */
 509         struct snd_dma_buffer rb;
 510         struct snd_dma_buffer posbuf;
 511
 512 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 513         const struct firmware *fw;
 514 #endif
 515
 516         /* flags */
 517         int position_fix[2]; /* for both playback/capture streams */
 518         int poll_count;
 519         unsigned int running :1;
 520         unsigned int initialized :1;
 521         unsigned int single_cmd :1;
 522         unsigned int polling_mode :1;
 523         unsigned int msi :1;
 524         unsigned int irq_pending_warned :1;
 525         unsigned int probing :1; /* codec probing phase */
 526         unsigned int snoop:1;
 527         unsigned int align_buffer_size:1;
 528         unsigned int region_requested:1;
 529
 530         /* VGA-switcheroo setup */
 531         unsigned int use_vga_switcheroo:1;
 532         unsigned int vga_switcheroo_registered:1;
 533         unsigned int init_failed:1; /* delayed init failed */
 534         unsigned int disabled:1; /* disabled by VGA-switcher */
 535
 536         /* for debugging */
 537         unsigned int last_cmd[AZX_MAX_CODECS];
 538
 539         /* for pending irqs */
 540         struct work_struct irq_pending_work;
 541
 542         struct work_struct probe_work;
 543
 544         /* reboot notifier (for mysterious hangup problem at power-down) */
 545         struct notifier_block reboot_notifier;
 546
 547         /* card list (for power_save trigger) */
 548         struct list_head list;
 549
 550 #ifdef CONFIG_SND_HDA_DSP_LOADER
 551         struct azx_dev saved_azx_dev;
 552 #endif
 553
 554         /* secondary power domain for hdmi audio under vga device */
 555         struct dev_pm_domain hdmi_pm_domain;
 556 };
 557
 558 #define CREATE_TRACE_POINTS
 559 #include "hda_intel_trace.h"
 560
 561 /* driver types */
 562 enum {
 563         AZX_DRIVER_ICH,
 564         AZX_DRIVER_PCH,
 565         AZX_DRIVER_SCH,
 566         AZX_DRIVER_HDMI,
 567         AZX_DRIVER_ATI,
 568         AZX_DRIVER_ATIHDMI,
 569         AZX_DRIVER_ATIHDMI_NS,
 570         AZX_DRIVER_VIA,
 571         AZX_DRIVER_SIS,
 572         AZX_DRIVER_ULI,
 573         AZX_DRIVER_NVIDIA,
 574         AZX_DRIVER_TERA,
 575         AZX_DRIVER_CTX,
 576         AZX_DRIVER_CTHDA,
 577         AZX_DRIVER_GENERIC,
 578         AZX_NUM_DRIVERS, /* keep this as last entry */
 579 };
 580
 581 /* driver quirks (capabilities) */
 582 /* bits 0-7 are used for indicating driver type */
 583 #define AZX_DCAPS_NO_TCSEL      (1 << 8)        /* No Intel TCSEL bit */
 584 #define AZX_DCAPS_NO_MSI        (1 << 9)        /* No MSI support */
 585 #define AZX_DCAPS_ATI_SNOOP     (1 << 10)       /* ATI snoop enable */
 586 #define AZX_DCAPS_NVIDIA_SNOOP  (1 << 11)       /* Nvidia snoop enable */
 587 #define AZX_DCAPS_SCH_SNOOP     (1 << 12)       /* SCH/PCH snoop enable */
 588 #define AZX_DCAPS_RIRB_DELAY    (1 << 13)       /* Long delay in read loop */
 589 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)      /* Put a delay before read */
 590 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15)      /* X-Fi workaround */
 591 #define AZX_DCAPS_POSFIX_LPIB   (1 << 16)       /* Use LPIB as default */
 592 #define AZX_DCAPS_POSFIX_VIA    (1 << 17)       /* Use VIACOMBO as default */
 593 #define AZX_DCAPS_NO_64BIT      (1 << 18)       /* No 64bit address */
 594 #define AZX_DCAPS_SYNC_WRITE    (1 << 19)       /* sync each cmd write */
 595 #define AZX_DCAPS_OLD_SSYNC     (1 << 20)       /* Old SSYNC reg for ICH */
 596 #define AZX_DCAPS_BUFSIZE       (1 << 21)       /* no buffer size alignment */
 597 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22)       /* buffer size alignment */
 598 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23)    /* BDLE in 4k boundary */
 599 #define AZX_DCAPS_COUNT_LPIB_DELAY  (1 << 25)   /* Take LPIB as delay */
 600 #define AZX_DCAPS_PM_RUNTIME    (1 << 26)       /* runtime PM support */
 601 #define AZX_DCAPS_I915_POWERWELL (1 << 27)      /* HSW i915 power well support */
 602
 603 /* quirks for Intel PCH */
 604 #define AZX_DCAPS_INTEL_PCH_NOPM \
 605         (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
 606          AZX_DCAPS_COUNT_LPIB_DELAY)
 607
 608 #define AZX_DCAPS_INTEL_PCH \
 609         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
 610
 611 #define AZX_DCAPS_INTEL_HASWELL \
 612         (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \
 613          AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME | \
 614          AZX_DCAPS_I915_POWERWELL)
 615
 616 /* quirks for ATI SB / AMD Hudson */
 617 #define AZX_DCAPS_PRESET_ATI_SB \
 618         (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
 619          AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
 620
 621 /* quirks for ATI/AMD HDMI */
 622 #define AZX_DCAPS_PRESET_ATI_HDMI \
 623         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
 624
 625 /* quirks for Nvidia */
 626 #define AZX_DCAPS_PRESET_NVIDIA \
 627         (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
 628          AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT)
 629
 630 #define AZX_DCAPS_PRESET_CTHDA \
 631         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
 632
 633 /*
 634  * VGA-switcher support
 635  */
 636 #ifdef SUPPORT_VGA_SWITCHEROO
 637 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 638 #else
 639 #define use_vga_switcheroo(chip)        0
 640 #endif
 641
 642 static char *driver_short_names[] = {
 643         [AZX_DRIVER_ICH] = "HDA Intel",
 644         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 645         [AZX_DRIVER_SCH] = "HDA Intel MID",
 646         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 647         [AZX_DRIVER_ATI] = "HDA ATI SB",
 648         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 649         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 650         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 651         [AZX_DRIVER_SIS] = "HDA SIS966",
 652         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 653         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 654         [AZX_DRIVER_TERA] = "HDA Teradici",
 655         [AZX_DRIVER_CTX] = "HDA Creative",
 656         [AZX_DRIVER_CTHDA] = "HDA Creative",
 657         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 658 };
 659
 660 /*
 661  * macros for easy use
 662  */
 663 #define azx_writel(chip,reg,value) \
 664         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 665 #define azx_readl(chip,reg) \
 666         readl((chip)->remap_addr + ICH6_REG_##reg)
 667 #define azx_writew(chip,reg,value) \
 668         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 669 #define azx_readw(chip,reg) \
 670         readw((chip)->remap_addr + ICH6_REG_##reg)
 671 #define azx_writeb(chip,reg,value) \
 672         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 673 #define azx_readb(chip,reg) \
 674         readb((chip)->remap_addr + ICH6_REG_##reg)
 675
 676 #define azx_sd_writel(dev,reg,value) \
 677         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 678 #define azx_sd_readl(dev,reg) \
 679         readl((dev)->sd_addr + ICH6_REG_##reg)
 680 #define azx_sd_writew(dev,reg,value) \
 681         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 682 #define azx_sd_readw(dev,reg) \
 683         readw((dev)->sd_addr + ICH6_REG_##reg)
 684 #define azx_sd_writeb(dev,reg,value) \
 685         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 686 #define azx_sd_readb(dev,reg) \
 687         readb((dev)->sd_addr + ICH6_REG_##reg)
 688
 689 /* for pcm support */
 690 #define get_azx_dev(substream) (substream->runtime->private_data)
 691
 692 #ifdef CONFIG_X86
 693 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
 694 {
 695         int pages;
 696
 697         if (azx_snoop(chip))
 698                 return;
 699         if (!dmab || !dmab->area || !dmab->bytes)
 700                 return;
 701
 702 #ifdef CONFIG_SND_DMA_SGBUF
 703         if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
 704                 struct snd_sg_buf *sgbuf = dmab->private_data;
 705                 if (on)
 706                         set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
 707                 else
 708                         set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
 709                 return;
 710         }
 711 #endif
 712
 713         pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
 714         if (on)
 715                 set_memory_wc((unsigned long)dmab->area, pages);
 716         else
 717                 set_memory_wb((unsigned long)dmab->area, pages);
 718 }
 719
 720 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 721                                  bool on)
 722 {
 723         __mark_pages_wc(chip, buf, on);
 724 }
 725 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 726                                    struct snd_pcm_substream *substream, bool on)
 727 {
 728         if (azx_dev->wc_marked != on) {
 729                 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
 730                 azx_dev->wc_marked = on;
 731         }
 732 }
 733 #else
 734 /* NOP for other archs */
 735 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 736                                  bool on)
 737 {
 738 }
 739 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 740                                    struct snd_pcm_substream *substream, bool on)
 741 {
 742 }
 743 #endif
 744
 745 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 746 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
 747 /*
 748  * Interface for HD codec
 749  */
 750
 751 /*
 752  * CORB / RIRB interface
 753  */
 754 static int azx_alloc_cmd_io(struct azx *chip)
 755 {
 756         int err;
 757
 758         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 759         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 760                                   snd_dma_pci_data(chip->pci),
 761                                   PAGE_SIZE, &chip->rb);
 762         if (err < 0) {
 763                 dev_err(chip->card->dev, "cannot allocate CORB/RIRB\n");
 764                 return err;
 765         }
 766         mark_pages_wc(chip, &chip->rb, true);
 767         return 0;
 768 }
 769
 770 static void azx_init_cmd_io(struct azx *chip)
 771 {
 772         spin_lock_irq(&chip->reg_lock);
 773         /* CORB set up */
 774         chip->corb.addr = chip->rb.addr;
 775         chip->corb.buf = (u32 *)chip->rb.area;
 776         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 777         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 778
 779         /* set the corb size to 256 entries (ULI requires explicitly) */
 780         azx_writeb(chip, CORBSIZE, 0x02);
 781         /* set the corb write pointer to 0 */
 782         azx_writew(chip, CORBWP, 0);
 783         /* reset the corb hw read pointer */
 784         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
 785         /* enable corb dma */
 786         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
 787
 788         /* RIRB set up */
 789         chip->rirb.addr = chip->rb.addr + 2048;
 790         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 791         chip->rirb.wp = chip->rirb.rp = 0;
 792         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
 793         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 794         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 795
 796         /* set the rirb size to 256 entries (ULI requires explicitly) */
 797         azx_writeb(chip, RIRBSIZE, 0x02);
 798         /* reset the rirb hw write pointer */
 799         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
 800         /* set N=1, get RIRB response interrupt for new entry */
 801         if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
 802                 azx_writew(chip, RINTCNT, 0xc0);
 803         else
 804                 azx_writew(chip, RINTCNT, 1);
 805         /* enable rirb dma and response irq */
 806         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 807         spin_unlock_irq(&chip->reg_lock);
 808 }
 809
 810 static void azx_free_cmd_io(struct azx *chip)
 811 {
 812         spin_lock_irq(&chip->reg_lock);
 813         /* disable ringbuffer DMAs */
 814         azx_writeb(chip, RIRBCTL, 0);
 815         azx_writeb(chip, CORBCTL, 0);
 816         spin_unlock_irq(&chip->reg_lock);
 817 }
 818
 819 static unsigned int azx_command_addr(u32 cmd)
 820 {
 821         unsigned int addr = cmd >> 28;
 822
 823         if (addr >= AZX_MAX_CODECS) {
 824                 snd_BUG();
 825                 addr = 0;
 826         }
 827
 828         return addr;
 829 }
 830
 831 /* send a command */
 832 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
 833 {
 834         struct azx *chip = bus->private_data;
 835         unsigned int addr = azx_command_addr(val);
 836         unsigned int wp, rp;
 837
 838         spin_lock_irq(&chip->reg_lock);
 839
 840         /* add command to corb */
 841         wp = azx_readw(chip, CORBWP);
 842         if (wp == 0xffff) {
 843                 /* something wrong, controller likely turned to D3 */
 844                 spin_unlock_irq(&chip->reg_lock);
 845                 return -EIO;
 846         }
 847         wp++;
 848         wp %= ICH6_MAX_CORB_ENTRIES;
 849
 850         rp = azx_readw(chip, CORBRP);
 851         if (wp == rp) {
 852                 /* oops, it's full */
 853                 spin_unlock_irq(&chip->reg_lock);
 854                 return -EAGAIN;
 855         }
 856
 857         chip->rirb.cmds[addr]++;
 858         chip->corb.buf[wp] = cpu_to_le32(val);
 859         azx_writel(chip, CORBWP, wp);
 860
 861         spin_unlock_irq(&chip->reg_lock);
 862
 863         return 0;
 864 }
 865
 866 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 867
 868 /* retrieve RIRB entry - called from interrupt handler */
 869 static void azx_update_rirb(struct azx *chip)
 870 {
 871         unsigned int rp, wp;
 872         unsigned int addr;
 873         u32 res, res_ex;
 874
 875         wp = azx_readw(chip, RIRBWP);
 876         if (wp == 0xffff) {
 877                 /* something wrong, controller likely turned to D3 */
 878                 return;
 879         }
 880
 881         if (wp == chip->rirb.wp)
 882                 return;
 883         chip->rirb.wp = wp;
 884
 885         while (chip->rirb.rp != wp) {
 886                 chip->rirb.rp++;
 887                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 888
 889                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 890                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 891                 res = le32_to_cpu(chip->rirb.buf[rp]);
 892                 addr = res_ex & 0xf;
 893                 if ((addr >= AZX_MAX_CODECS) || !(chip->codec_mask & (1 << addr))) {
 894                         dev_err(chip->card->dev, "spurious response %#x:%#x, rp = %d, wp = %d",
 895                                 res, res_ex,
 896                                 chip->rirb.rp, wp);
 897                         snd_BUG();
 898                 }
 899                 else if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 900                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 901                 else if (chip->rirb.cmds[addr]) {
 902                         chip->rirb.res[addr] = res;
 903                         smp_wmb();
 904                         chip->rirb.cmds[addr]--;
 905                 } else if (printk_ratelimit()) {
 906                         dev_err(chip->card->dev, "spurious response %#x:%#x, last cmd=%#08x\n",
 907                                 res, res_ex,
 908                                 chip->last_cmd[addr]);
 909                 }
 910         }
 911 }
 912
 913 /* receive a response */
 914 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
 915                                           unsigned int addr)
 916 {
 917         struct azx *chip = bus->private_data;
 918         unsigned long timeout;
 919         unsigned long loopcounter;
 920         int do_poll = 0;
 921
 922  again:
 923         timeout = jiffies + msecs_to_jiffies(1000);
 924
 925         for (loopcounter = 0;; loopcounter++) {
 926                 if (chip->polling_mode || do_poll) {
 927                         spin_lock_irq(&chip->reg_lock);
 928                         azx_update_rirb(chip);
 929                         spin_unlock_irq(&chip->reg_lock);
 930                 }
 931                 if (!chip->rirb.cmds[addr]) {
 932                         smp_rmb();
 933                         bus->rirb_error = 0;
 934
 935                         if (!do_poll)
 936                                 chip->poll_count = 0;
 937                         return chip->rirb.res[addr]; /* the last value */
 938                 }
 939                 if (time_after(jiffies, timeout))
 940                         break;
 941                 if (bus->needs_damn_long_delay || loopcounter > 3000)
 942                         msleep(2); /* temporary workaround */
 943                 else {
 944                         udelay(10);
 945                         cond_resched();
 946                 }
 947         }
 948
 949         if (!bus->no_response_fallback)
 950                 return -1;
 951
 952         if (!chip->polling_mode && chip->poll_count < 2) {
 953                 dev_dbg(chip->card->dev,
 954                         "azx_get_response timeout, polling the codec once: last cmd=0x%08x\n",
 955                         chip->last_cmd[addr]);
 956                 do_poll = 1;
 957                 chip->poll_count++;
 958                 goto again;
 959         }
 960
 961
 962         if (!chip->polling_mode) {
 963                 dev_warn(chip->card->dev,
 964                          "azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n",
 965                          chip->last_cmd[addr]);
 966                 chip->polling_mode = 1;
 967                 goto again;
 968         }
 969
 970         if (chip->msi) {
 971                 dev_warn(chip->card->dev,
 972                          "No response from codec, disabling MSI: last cmd=0x%08x\n",
 973                          chip->last_cmd[addr]);
 974                 free_irq(chip->irq, chip);
 975                 chip->irq = -1;
 976                 pci_disable_msi(chip->pci);
 977                 chip->msi = 0;
 978                 if (azx_acquire_irq(chip, 1) < 0) {
 979                         bus->rirb_error = 1;
 980                         return -1;
 981                 }
 982                 goto again;
 983         }
 984
 985         if (chip->probing) {
 986                 /* If this critical timeout happens during the codec probing
 987                  * phase, this is likely an access to a non-existing codec
 988                  * slot.  Better to return an error and reset the system.
 989                  */
 990                 return -1;
 991         }
 992
 993         /* a fatal communication error; need either to reset or to fallback
 994          * to the single_cmd mode
 995          */
 996         bus->rirb_error = 1;
 997         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
 998                 bus->response_reset = 1;
 999                 return -1; /* give a chance to retry */
1000         }
1001
1002         dev_err(chip->card->dev,
1003                 "azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n",
1004                 chip->last_cmd[addr]);
1005         chip->single_cmd = 1;
1006         bus->response_reset = 0;
1007         /* release CORB/RIRB */
1008         azx_free_cmd_io(chip);
1009         /* disable unsolicited responses */
1010         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
1011         return -1;
1012 }
1013
1014 /*
1015  * Use the single immediate command instead of CORB/RIRB for simplicity
1016  *
1017  * Note: according to Intel, this is not preferred use.  The command was
1018  *       intended for the BIOS only, and may get confused with unsolicited
1019  *       responses.  So, we shouldn't use it for normal operation from the
1020  *       driver.
1021  *       I left the codes, however, for debugging/testing purposes.
1022  */
1023
1024 /* receive a response */
1025 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
1026 {
1027         int timeout = 50;
1028
1029         while (timeout--) {
1030                 /* check IRV busy bit */
1031                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
1032                         /* reuse rirb.res as the response return value */
1033                         chip->rirb.res[addr] = azx_readl(chip, IR);
1034                         return 0;
1035                 }
1036                 udelay(1);
1037         }
1038         if (printk_ratelimit())
1039                 dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n",
1040                         azx_readw(chip, IRS));
1041         chip->rirb.res[addr] = -1;
1042         return -EIO;
1043 }
1044
1045 /* send a command */
1046 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1047 {
1048         struct azx *chip = bus->private_data;
1049         unsigned int addr = azx_command_addr(val);
1050         int timeout = 50;
1051
1052         bus->rirb_error = 0;
1053         while (timeout--) {
1054                 /* check ICB busy bit */
1055                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1056                         /* Clear IRV valid bit */
1057                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1058                                    ICH6_IRS_VALID);
1059                         azx_writel(chip, IC, val);
1060                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1061                                    ICH6_IRS_BUSY);
1062                         return azx_single_wait_for_response(chip, addr);
1063                 }
1064                 udelay(1);
1065         }
1066         if (printk_ratelimit())
1067                 dev_dbg(chip->card->dev,
1068                         "send_cmd timeout: IRS=0x%x, val=0x%x\n",
1069                         azx_readw(chip, IRS), val);
1070         return -EIO;
1071 }
1072
1073 /* receive a response */
1074 static unsigned int azx_single_get_response(struct hda_bus *bus,
1075                                             unsigned int addr)
1076 {
1077         struct azx *chip = bus->private_data;
1078         return chip->rirb.res[addr];
1079 }
1080
1081 /*
1082  * The below are the main callbacks from hda_codec.
1083  *
1084  * They are just the skeleton to call sub-callbacks according to the
1085  * current setting of chip->single_cmd.
1086  */
1087
1088 /* send a command */
1089 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1090 {
1091         struct azx *chip = bus->private_data;
1092
1093         if (chip->disabled)
1094                 return 0;
1095         chip->last_cmd[azx_command_addr(val)] = val;
1096         if (chip->single_cmd)
1097                 return azx_single_send_cmd(bus, val);
1098         else
1099                 return azx_corb_send_cmd(bus, val);
1100 }
1101
1102 /* get a response */
1103 static unsigned int azx_get_response(struct hda_bus *bus,
1104                                      unsigned int addr)
1105 {
1106         struct azx *chip = bus->private_data;
1107         if (chip->disabled)
1108                 return 0;
1109         if (chip->single_cmd)
1110                 return azx_single_get_response(bus, addr);
1111         else
1112                 return azx_rirb_get_response(bus, addr);
1113 }
1114
1115 #ifdef CONFIG_PM
1116 static void azx_power_notify(struct hda_bus *bus, bool power_up);
1117 #endif
1118
1119 #ifdef CONFIG_SND_HDA_DSP_LOADER
1120 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
1121                                 unsigned int byte_size,
1122                                 struct snd_dma_buffer *bufp);
1123 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start);
1124 static void azx_load_dsp_cleanup(struct hda_bus *bus,
1125                                  struct snd_dma_buffer *dmab);
1126 #endif
1127
1128 /* enter link reset */
1129 static void azx_enter_link_reset(struct azx *chip)
1130 {
1131         unsigned long timeout;
1132
1133         /* reset controller */
1134         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1135
1136         timeout = jiffies + msecs_to_jiffies(100);
1137         while ((azx_readb(chip, GCTL) & ICH6_GCTL_RESET) &&
1138                         time_before(jiffies, timeout))
1139                 usleep_range(500, 1000);
1140 }
1141
1142 /* exit link reset */
1143 static void azx_exit_link_reset(struct azx *chip)
1144 {
1145         unsigned long timeout;
1146
1147         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1148
1149         timeout = jiffies + msecs_to_jiffies(100);
1150         while (!azx_readb(chip, GCTL) &&
1151                         time_before(jiffies, timeout))
1152                 usleep_range(500, 1000);
1153 }
1154
1155 /* reset codec link */
1156 static int azx_reset(struct azx *chip, int full_reset)
1157 {
1158         if (!full_reset)
1159                 goto __skip;
1160
1161         /* clear STATESTS */
1162         azx_writew(chip, STATESTS, STATESTS_INT_MASK);
1163
1164         /* reset controller */
1165         azx_enter_link_reset(chip);
1166
1167         /* delay for >= 100us for codec PLL to settle per spec
1168          * Rev 0.9 section 5.5.1
1169          */
1170         usleep_range(500, 1000);
1171
1172         /* Bring controller out of reset */
1173         azx_exit_link_reset(chip);
1174
1175         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1176         usleep_range(1000, 1200);
1177
1178       __skip:
1179         /* check to see if controller is ready */
1180         if (!azx_readb(chip, GCTL)) {
1181                 dev_dbg(chip->card->dev, "azx_reset: controller not ready!\n");
1182                 return -EBUSY;
1183         }
1184
1185         /* Accept unsolicited responses */
1186         if (!chip->single_cmd)
1187                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1188                            ICH6_GCTL_UNSOL);
1189
1190         /* detect codecs */
1191         if (!chip->codec_mask) {
1192                 chip->codec_mask = azx_readw(chip, STATESTS);
1193                 dev_dbg(chip->card->dev, "codec_mask = 0x%x\n",
1194                         chip->codec_mask);
1195         }
1196
1197         return 0;
1198 }
1199
1200
1201 /*
1202  * Lowlevel interface
1203  */
1204
1205 /* enable interrupts */
1206 static void azx_int_enable(struct azx *chip)
1207 {
1208         /* enable controller CIE and GIE */
1209         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1210                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1211 }
1212
1213 /* disable interrupts */
1214 static void azx_int_disable(struct azx *chip)
1215 {
1216         int i;
1217
1218         /* disable interrupts in stream descriptor */
1219         for (i = 0; i < chip->num_streams; i++) {
1220                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1221                 azx_sd_writeb(azx_dev, SD_CTL,
1222                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1223         }
1224
1225         /* disable SIE for all streams */
1226         azx_writeb(chip, INTCTL, 0);
1227
1228         /* disable controller CIE and GIE */
1229         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1230                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1231 }
1232
1233 /* clear interrupts */
1234 static void azx_int_clear(struct azx *chip)
1235 {
1236         int i;
1237
1238         /* clear stream status */
1239         for (i = 0; i < chip->num_streams; i++) {
1240                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1241                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1242         }
1243
1244         /* clear STATESTS */
1245         azx_writew(chip, STATESTS, STATESTS_INT_MASK);
1246
1247         /* clear rirb status */
1248         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1249
1250         /* clear int status */
1251         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1252 }
1253
1254 /* start a stream */
1255 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1256 {
1257         /*
1258          * Before stream start, initialize parameter
1259          */
1260         azx_dev->insufficient = 1;
1261
1262         /* enable SIE */
1263         azx_writel(chip, INTCTL,
1264                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1265         /* set DMA start and interrupt mask */
1266         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1267                       SD_CTL_DMA_START | SD_INT_MASK);
1268 }
1269
1270 /* stop DMA */
1271 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1272 {
1273         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1274                       ~(SD_CTL_DMA_START | SD_INT_MASK));
1275         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1276 }
1277
1278 /* stop a stream */
1279 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1280 {
1281         azx_stream_clear(chip, azx_dev);
1282         /* disable SIE */
1283         azx_writel(chip, INTCTL,
1284                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1285 }
1286
1287
1288 /*
1289  * reset and start the controller registers
1290  */
1291 static void azx_init_chip(struct azx *chip, int full_reset)
1292 {
1293         if (chip->initialized)
1294                 return;
1295
1296         /* reset controller */
1297         azx_reset(chip, full_reset);
1298
1299         /* initialize interrupts */
1300         azx_int_clear(chip);
1301         azx_int_enable(chip);
1302
1303         /* initialize the codec command I/O */
1304         if (!chip->single_cmd)
1305                 azx_init_cmd_io(chip);
1306
1307         /* program the position buffer */
1308         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1309         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1310
1311         chip->initialized = 1;
1312 }
1313
1314 /*
1315  * initialize the PCI registers
1316  */
1317 /* update bits in a PCI register byte */
1318 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1319                             unsigned char mask, unsigned char val)
1320 {
1321         unsigned char data;
1322
1323         pci_read_config_byte(pci, reg, &data);
1324         data &= ~mask;
1325         data |= (val & mask);
1326         pci_write_config_byte(pci, reg, data);
1327 }
1328
1329 static void azx_init_pci(struct azx *chip)
1330 {
1331         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1332          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1333          * Ensuring these bits are 0 clears playback static on some HD Audio
1334          * codecs.
1335          * The PCI register TCSEL is defined in the Intel manuals.
1336          */
1337         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1338                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
1339                 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1340         }
1341
1342         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1343          * we need to enable snoop.
1344          */
1345         if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1346                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
1347                         azx_snoop(chip));
1348                 update_pci_byte(chip->pci,
1349                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1350                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1351         }
1352
1353         /* For NVIDIA HDA, enable snoop */
1354         if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1355                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
1356                         azx_snoop(chip));
1357                 update_pci_byte(chip->pci,
1358                                 NVIDIA_HDA_TRANSREG_ADDR,
1359                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1360                 update_pci_byte(chip->pci,
1361                                 NVIDIA_HDA_ISTRM_COH,
1362                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1363                 update_pci_byte(chip->pci,
1364                                 NVIDIA_HDA_OSTRM_COH,
1365                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1366         }
1367
1368         /* Enable SCH/PCH snoop if needed */
1369         if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1370                 unsigned short snoop;
1371                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1372                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1373                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1374                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1375                         if (!azx_snoop(chip))
1376                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1377                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1378                         pci_read_config_word(chip->pci,
1379                                 INTEL_SCH_HDA_DEVC, &snoop);
1380                 }
1381                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
1382                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
1383                         "Disabled" : "Enabled");
1384         }
1385 }
1386
1387
1388 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1389
1390 /*
1391  * interrupt handler
1392  */
1393 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1394 {
1395         struct azx *chip = dev_id;
1396         struct azx_dev *azx_dev;
1397         u32 status;
1398         u8 sd_status;
1399         int i, ok;
1400
1401 #ifdef CONFIG_PM_RUNTIME
1402         if (chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
1403                 if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1404                         return IRQ_NONE;
1405 #endif
1406
1407         spin_lock(&chip->reg_lock);
1408
1409         if (chip->disabled) {
1410                 spin_unlock(&chip->reg_lock);
1411                 return IRQ_NONE;
1412         }
1413
1414         status = azx_readl(chip, INTSTS);
1415         if (status == 0 || status == 0xffffffff) {
1416                 spin_unlock(&chip->reg_lock);
1417                 return IRQ_NONE;
1418         }
1419
1420         for (i = 0; i < chip->num_streams; i++) {
1421                 azx_dev = &chip->azx_dev[i];
1422                 if (status & azx_dev->sd_int_sta_mask) {
1423                         sd_status = azx_sd_readb(azx_dev, SD_STS);
1424                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1425                         if (!azx_dev->substream || !azx_dev->running ||
1426                             !(sd_status & SD_INT_COMPLETE))
1427                                 continue;
1428                         /* check whether this IRQ is really acceptable */
1429                         ok = azx_position_ok(chip, azx_dev);
1430                         if (ok == 1) {
1431                                 azx_dev->irq_pending = 0;
1432                                 spin_unlock(&chip->reg_lock);
1433                                 snd_pcm_period_elapsed(azx_dev->substream);
1434                                 spin_lock(&chip->reg_lock);
1435                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1436                                 /* bogus IRQ, process it later */
1437                                 azx_dev->irq_pending = 1;
1438                                 queue_work(chip->bus->workq,
1439                                            &chip->irq_pending_work);
1440                         }
1441                 }
1442         }
1443
1444         /* clear rirb int */
1445         status = azx_readb(chip, RIRBSTS);
1446         if (status & RIRB_INT_MASK) {
1447                 if (status & RIRB_INT_RESPONSE) {
1448                         if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1449                                 udelay(80);
1450                         azx_update_rirb(chip);
1451                 }
1452                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1453         }
1454
1455 #if 0
1456         /* clear state status int */
1457         if (azx_readw(chip, STATESTS) & 0x04)
1458                 azx_writew(chip, STATESTS, 0x04);
1459 #endif
1460         spin_unlock(&chip->reg_lock);
1461
1462         return IRQ_HANDLED;
1463 }
1464
1465
1466 /*
1467  * set up a BDL entry
1468  */
1469 static int setup_bdle(struct azx *chip,
1470                       struct snd_dma_buffer *dmab,
1471                       struct azx_dev *azx_dev, u32 **bdlp,
1472                       int ofs, int size, int with_ioc)
1473 {
1474         u32 *bdl = *bdlp;
1475
1476         while (size > 0) {
1477                 dma_addr_t addr;
1478                 int chunk;
1479
1480                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1481                         return -EINVAL;
1482
1483                 addr = snd_sgbuf_get_addr(dmab, ofs);
1484                 /* program the address field of the BDL entry */
1485                 bdl[0] = cpu_to_le32((u32)addr);
1486                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1487                 /* program the size field of the BDL entry */
1488                 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
1489                 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1490                 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1491                         u32 remain = 0x1000 - (ofs & 0xfff);
1492                         if (chunk > remain)
1493                                 chunk = remain;
1494                 }
1495                 bdl[2] = cpu_to_le32(chunk);
1496                 /* program the IOC to enable interrupt
1497                  * only when the whole fragment is processed
1498                  */
1499                 size -= chunk;
1500                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1501                 bdl += 4;
1502                 azx_dev->frags++;
1503                 ofs += chunk;
1504         }
1505         *bdlp = bdl;
1506         return ofs;
1507 }
1508
1509 /*
1510  * set up BDL entries
1511  */
1512 static int azx_setup_periods(struct azx *chip,
1513                              struct snd_pcm_substream *substream,
1514                              struct azx_dev *azx_dev)
1515 {
1516         u32 *bdl;
1517         int i, ofs, periods, period_bytes;
1518         int pos_adj;
1519
1520         /* reset BDL address */
1521         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1522         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1523
1524         period_bytes = azx_dev->period_bytes;
1525         periods = azx_dev->bufsize / period_bytes;
1526
1527         /* program the initial BDL entries */
1528         bdl = (u32 *)azx_dev->bdl.area;
1529         ofs = 0;
1530         azx_dev->frags = 0;
1531         pos_adj = bdl_pos_adj[chip->dev_index];
1532         if (!azx_dev->no_period_wakeup && pos_adj > 0) {
1533                 struct snd_pcm_runtime *runtime = substream->runtime;
1534                 int pos_align = pos_adj;
1535                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1536                 if (!pos_adj)
1537                         pos_adj = pos_align;
1538                 else
1539                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1540                                 pos_align;
1541                 pos_adj = frames_to_bytes(runtime, pos_adj);
1542                 if (pos_adj >= period_bytes) {
1543                         dev_warn(chip->card->dev,"Too big adjustment %d\n",
1544                                  bdl_pos_adj[chip->dev_index]);
1545                         pos_adj = 0;
1546                 } else {
1547                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1548                                          azx_dev,
1549                                          &bdl, ofs, pos_adj, true);
1550                         if (ofs < 0)
1551                                 goto error;
1552                 }
1553         } else
1554                 pos_adj = 0;
1555         for (i = 0; i < periods; i++) {
1556                 if (i == periods - 1 && pos_adj)
1557                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1558                                          azx_dev, &bdl, ofs,
1559                                          period_bytes - pos_adj, 0);
1560                 else
1561                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1562                                          azx_dev, &bdl, ofs,
1563                                          period_bytes,
1564                                          !azx_dev->no_period_wakeup);
1565                 if (ofs < 0)
1566                         goto error;
1567         }
1568         return 0;
1569
1570  error:
1571         dev_err(chip->card->dev, "Too many BDL entries: buffer=%d, period=%d\n",
1572                 azx_dev->bufsize, period_bytes);
1573         return -EINVAL;
1574 }
1575
1576 /* reset stream */
1577 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1578 {
1579         unsigned char val;
1580         int timeout;
1581
1582         azx_stream_clear(chip, azx_dev);
1583
1584         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1585                       SD_CTL_STREAM_RESET);
1586         udelay(3);
1587         timeout = 300;
1588         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1589                --timeout)
1590                 ;
1591         val &= ~SD_CTL_STREAM_RESET;
1592         azx_sd_writeb(azx_dev, SD_CTL, val);
1593         udelay(3);
1594
1595         timeout = 300;
1596         /* waiting for hardware to report that the stream is out of reset */
1597         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1598                --timeout)
1599                 ;
1600
1601         /* reset first position - may not be synced with hw at this time */
1602         *azx_dev->posbuf = 0;
1603 }
1604
1605 /*
1606  * set up the SD for streaming
1607  */
1608 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1609 {
1610         unsigned int val;
1611         /* make sure the run bit is zero for SD */
1612         azx_stream_clear(chip, azx_dev);
1613         /* program the stream_tag */
1614         val = azx_sd_readl(azx_dev, SD_CTL);
1615         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1616                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1617         if (!azx_snoop(chip))
1618                 val |= SD_CTL_TRAFFIC_PRIO;
1619         azx_sd_writel(azx_dev, SD_CTL, val);
1620
1621         /* program the length of samples in cyclic buffer */
1622         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1623
1624         /* program the stream format */
1625         /* this value needs to be the same as the one programmed */
1626         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1627
1628         /* program the stream LVI (last valid index) of the BDL */
1629         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1630
1631         /* program the BDL address */
1632         /* lower BDL address */
1633         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1634         /* upper BDL address */
1635         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1636
1637         /* enable the position buffer */
1638         if (chip->position_fix[0] != POS_FIX_LPIB ||
1639             chip->position_fix[1] != POS_FIX_LPIB) {
1640                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1641                         azx_writel(chip, DPLBASE,
1642                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1643         }
1644
1645         /* set the interrupt enable bits in the descriptor control register */
1646         azx_sd_writel(azx_dev, SD_CTL,
1647                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1648
1649         return 0;
1650 }
1651
1652 /*
1653  * Probe the given codec address
1654  */
1655 static int probe_codec(struct azx *chip, int addr)
1656 {
1657         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1658                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1659         unsigned int res;
1660
1661         mutex_lock(&chip->bus->cmd_mutex);
1662         chip->probing = 1;
1663         azx_send_cmd(chip->bus, cmd);
1664         res = azx_get_response(chip->bus, addr);
1665         chip->probing = 0;
1666         mutex_unlock(&chip->bus->cmd_mutex);
1667         if (res == -1)
1668                 return -EIO;
1669         dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr);
1670         return 0;
1671 }
1672
1673 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1674                                  struct hda_pcm *cpcm);
1675 static void azx_stop_chip(struct azx *chip);
1676
1677 static void azx_bus_reset(struct hda_bus *bus)
1678 {
1679         struct azx *chip = bus->private_data;
1680
1681         bus->in_reset = 1;
1682         azx_stop_chip(chip);
1683         azx_init_chip(chip, 1);
1684 #ifdef CONFIG_PM
1685         if (chip->initialized) {
1686                 struct azx_pcm *p;
1687                 list_for_each_entry(p, &chip->pcm_list, list)
1688                         snd_pcm_suspend_all(p->pcm);
1689                 snd_hda_suspend(chip->bus);
1690                 snd_hda_resume(chip->bus);
1691         }
1692 #endif
1693         bus->in_reset = 0;
1694 }
1695
1696 static int get_jackpoll_interval(struct azx *chip)
1697 {
1698         int i = jackpoll_ms[chip->dev_index];
1699         unsigned int j;
1700         if (i == 0)
1701                 return 0;
1702         if (i < 50 || i > 60000)
1703                 j = 0;
1704         else
1705                 j = msecs_to_jiffies(i);
1706         if (j == 0)
1707                 dev_warn(chip->card->dev,
1708                          "jackpoll_ms value out of range: %d\n", i);
1709         return j;
1710 }
1711
1712 /*
1713  * Codec initialization
1714  */
1715
1716 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1717 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1718         [AZX_DRIVER_NVIDIA] = 8,
1719         [AZX_DRIVER_TERA] = 1,
1720 };
1721
1722 static int azx_codec_create(struct azx *chip, const char *model)
1723 {
1724         struct hda_bus_template bus_temp;
1725         int c, codecs, err;
1726         int max_slots;
1727
1728         memset(&bus_temp, 0, sizeof(bus_temp));
1729         bus_temp.private_data = chip;
1730         bus_temp.modelname = model;
1731         bus_temp.pci = chip->pci;
1732         bus_temp.ops.command = azx_send_cmd;
1733         bus_temp.ops.get_response = azx_get_response;
1734         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1735         bus_temp.ops.bus_reset = azx_bus_reset;
1736 #ifdef CONFIG_PM
1737         bus_temp.power_save = &power_save;
1738         bus_temp.ops.pm_notify = azx_power_notify;
1739 #endif
1740 #ifdef CONFIG_SND_HDA_DSP_LOADER
1741         bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare;
1742         bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger;
1743         bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup;
1744 #endif
1745
1746         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1747         if (err < 0)
1748                 return err;
1749
1750         if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1751                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1752                 chip->bus->needs_damn_long_delay = 1;
1753         }
1754
1755         codecs = 0;
1756         max_slots = azx_max_codecs[chip->driver_type];
1757         if (!max_slots)
1758                 max_slots = AZX_DEFAULT_CODECS;
1759
1760         /* First try to probe all given codec slots */
1761         for (c = 0; c < max_slots; c++) {
1762                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1763                         if (probe_codec(chip, c) < 0) {
1764                                 /* Some BIOSen give you wrong codec addresses
1765                                  * that don't exist
1766                                  */
1767                                 dev_warn(chip->card->dev,
1768                                          "Codec #%d probe error; disabling it...\n", c);
1769                                 chip->codec_mask &= ~(1 << c);
1770                                 /* More badly, accessing to a non-existing
1771                                  * codec often screws up the controller chip,
1772                                  * and disturbs the further communications.
1773                                  * Thus if an error occurs during probing,
1774                                  * better to reset the controller chip to
1775                                  * get back to the sanity state.
1776                                  */
1777                                 azx_stop_chip(chip);
1778                                 azx_init_chip(chip, 1);
1779                         }
1780                 }
1781         }
1782
1783         /* AMD chipsets often cause the communication stalls upon certain
1784          * sequence like the pin-detection.  It seems that forcing the synced
1785          * access works around the stall.  Grrr...
1786          */
1787         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1788                 dev_dbg(chip->card->dev, "Enable sync_write for stable communication\n");
1789                 chip->bus->sync_write = 1;
1790                 chip->bus->allow_bus_reset = 1;
1791         }
1792
1793         /* Then create codec instances */
1794         for (c = 0; c < max_slots; c++) {
1795                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1796                         struct hda_codec *codec;
1797                         err = snd_hda_codec_new(chip->bus, c, &codec);
1798                         if (err < 0)
1799                                 continue;
1800                         codec->jackpoll_interval = get_jackpoll_interval(chip);
1801                         codec->beep_mode = chip->beep_mode;
1802                         codecs++;
1803                 }
1804         }
1805         if (!codecs) {
1806                 dev_err(chip->card->dev, "no codecs initialized\n");
1807                 return -ENXIO;
1808         }
1809         return 0;
1810 }
1811
1812 /* configure each codec instance */
1813 static int azx_codec_configure(struct azx *chip)
1814 {
1815         struct hda_codec *codec;
1816         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1817                 snd_hda_codec_configure(codec);
1818         }
1819         return 0;
1820 }
1821
1822
1823 /*
1824  * PCM support
1825  */
1826
1827 /* assign a stream for the PCM */
1828 static inline struct azx_dev *
1829 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1830 {
1831         int dev, i, nums;
1832         struct azx_dev *res = NULL;
1833         /* make a non-zero unique key for the substream */
1834         int key = (substream->pcm->device << 16) | (substream->number << 2) |
1835                 (substream->stream + 1);
1836
1837         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1838                 dev = chip->playback_index_offset;
1839                 nums = chip->playback_streams;
1840         } else {
1841                 dev = chip->capture_index_offset;
1842                 nums = chip->capture_streams;
1843         }
1844         for (i = 0; i < nums; i++, dev++) {
1845                 struct azx_dev *azx_dev = &chip->azx_dev[dev];
1846                 dsp_lock(azx_dev);
1847                 if (!azx_dev->opened && !dsp_is_locked(azx_dev)) {
1848                         res = azx_dev;
1849                         if (res->assigned_key == key) {
1850                                 res->opened = 1;
1851                                 res->assigned_key = key;
1852                                 dsp_unlock(azx_dev);
1853                                 return azx_dev;
1854                         }
1855                 }
1856                 dsp_unlock(azx_dev);
1857         }
1858         if (res) {
1859                 dsp_lock(res);
1860                 res->opened = 1;
1861                 res->assigned_key = key;
1862                 dsp_unlock(res);
1863         }
1864         return res;
1865 }
1866
1867 /* release the assigned stream */
1868 static inline void azx_release_device(struct azx_dev *azx_dev)
1869 {
1870         azx_dev->opened = 0;
1871 }
1872
1873 static cycle_t azx_cc_read(const struct cyclecounter *cc)
1874 {
1875         struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
1876         struct snd_pcm_substream *substream = azx_dev->substream;
1877         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1878         struct azx *chip = apcm->chip;
1879
1880         return azx_readl(chip, WALLCLK);
1881 }
1882
1883 static void azx_timecounter_init(struct snd_pcm_substream *substream,
1884                                 bool force, cycle_t last)
1885 {
1886         struct azx_dev *azx_dev = get_azx_dev(substream);
1887         struct timecounter *tc = &azx_dev->azx_tc;
1888         struct cyclecounter *cc = &azx_dev->azx_cc;
1889         u64 nsec;
1890
1891         cc->read = azx_cc_read;
1892         cc->mask = CLOCKSOURCE_MASK(32);
1893
1894         /*
1895          * Converting from 24 MHz to ns means applying a 125/3 factor.
1896          * To avoid any saturation issues in intermediate operations,
1897          * the 125 factor is applied first. The division is applied
1898          * last after reading the timecounter value.
1899          * Applying the 1/3 factor as part of the multiplication
1900          * requires at least 20 bits for a decent precision, however
1901          * overflows occur after about 4 hours or less, not a option.
1902          */
1903
1904         cc->mult = 125; /* saturation after 195 years */
1905         cc->shift = 0;
1906
1907         nsec = 0; /* audio time is elapsed time since trigger */
1908         timecounter_init(tc, cc, nsec);
1909         if (force)
1910                 /*
1911                  * force timecounter to use predefined value,
1912                  * used for synchronized starts
1913                  */
1914                 tc->cycle_last = last;
1915 }
1916
1917 static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
1918                                 u64 nsec)
1919 {
1920         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1921         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1922         u64 codec_frames, codec_nsecs;
1923
1924         if (!hinfo->ops.get_delay)
1925                 return nsec;
1926
1927         codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
1928         codec_nsecs = div_u64(codec_frames * 1000000000LL,
1929                               substream->runtime->rate);
1930
1931         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1932                 return nsec + codec_nsecs;
1933
1934         return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1935 }
1936
1937 static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
1938                                 struct timespec *ts)
1939 {
1940         struct azx_dev *azx_dev = get_azx_dev(substream);
1941         u64 nsec;
1942
1943         nsec = timecounter_read(&azx_dev->azx_tc);
1944         nsec = div_u64(nsec, 3); /* can be optimized */
1945         nsec = azx_adjust_codec_delay(substream, nsec);
1946
1947         *ts = ns_to_timespec(nsec);
1948
1949         return 0;
1950 }
1951
1952 static struct snd_pcm_hardware azx_pcm_hw = {
1953         .info =                 (SNDRV_PCM_INFO_MMAP |
1954                                  SNDRV_PCM_INFO_INTERLEAVED |
1955                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1956                                  SNDRV_PCM_INFO_MMAP_VALID |
1957                                  /* No full-resume yet implemented */
1958                                  /* SNDRV_PCM_INFO_RESUME |*/
1959                                  SNDRV_PCM_INFO_PAUSE |
1960                                  SNDRV_PCM_INFO_SYNC_START |
1961                                  SNDRV_PCM_INFO_HAS_WALL_CLOCK |
1962                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1963         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1964         .rates =                SNDRV_PCM_RATE_48000,
1965         .rate_min =             48000,
1966         .rate_max =             48000,
1967         .channels_min =         2,
1968         .channels_max =         2,
1969         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1970         .period_bytes_min =     128,
1971         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1972         .periods_min =          2,
1973         .periods_max =          AZX_MAX_FRAG,
1974         .fifo_size =            0,
1975 };
1976
1977 static int azx_pcm_open(struct snd_pcm_substream *substream)
1978 {
1979         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1980         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1981         struct azx *chip = apcm->chip;
1982         struct azx_dev *azx_dev;
1983         struct snd_pcm_runtime *runtime = substream->runtime;
1984         unsigned long flags;
1985         int err;
1986         int buff_step;
1987
1988         mutex_lock(&chip->open_mutex);
1989         azx_dev = azx_assign_device(chip, substream);
1990         if (azx_dev == NULL) {
1991                 mutex_unlock(&chip->open_mutex);
1992                 return -EBUSY;
1993         }
1994         runtime->hw = azx_pcm_hw;
1995         runtime->hw.channels_min = hinfo->channels_min;
1996         runtime->hw.channels_max = hinfo->channels_max;
1997         runtime->hw.formats = hinfo->formats;
1998         runtime->hw.rates = hinfo->rates;
1999         snd_pcm_limit_hw_rates(runtime);
2000         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
2001
2002         /* avoid wrap-around with wall-clock */
2003         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
2004                                 20,
2005                                 178000000);
2006
2007         if (chip->align_buffer_size)
2008                 /* constrain buffer sizes to be multiple of 128
2009                    bytes. This is more efficient in terms of memory
2010                    access but isn't required by the HDA spec and
2011                    prevents users from specifying exact period/buffer
2012                    sizes. For example for 44.1kHz, a period size set
2013                    to 20ms will be rounded to 19.59ms. */
2014                 buff_step = 128;
2015         else
2016                 /* Don't enforce steps on buffer sizes, still need to
2017                    be multiple of 4 bytes (HDA spec). Tested on Intel
2018                    HDA controllers, may not work on all devices where
2019                    option needs to be disabled */
2020                 buff_step = 4;
2021
2022         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
2023                                    buff_step);
2024         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
2025                                    buff_step);
2026         snd_hda_power_up_d3wait(apcm->codec);
2027         err = hinfo->ops.open(hinfo, apcm->codec, substream);
2028         if (err < 0) {
2029                 azx_release_device(azx_dev);
2030                 snd_hda_power_down(apcm->codec);
2031                 mutex_unlock(&chip->open_mutex);
2032                 return err;
2033         }
2034         snd_pcm_limit_hw_rates(runtime);
2035         /* sanity check */
2036         if (snd_BUG_ON(!runtime->hw.channels_min) ||
2037             snd_BUG_ON(!runtime->hw.channels_max) ||
2038             snd_BUG_ON(!runtime->hw.formats) ||
2039             snd_BUG_ON(!runtime->hw.rates)) {
2040                 azx_release_device(azx_dev);
2041                 hinfo->ops.close(hinfo, apcm->codec, substream);
2042                 snd_hda_power_down(apcm->codec);
2043                 mutex_unlock(&chip->open_mutex);
2044                 return -EINVAL;
2045         }
2046
2047         /* disable WALLCLOCK timestamps for capture streams
2048            until we figure out how to handle digital inputs */
2049         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2050                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
2051
2052         spin_lock_irqsave(&chip->reg_lock, flags);
2053         azx_dev->substream = substream;
2054         azx_dev->running = 0;
2055         spin_unlock_irqrestore(&chip->reg_lock, flags);
2056
2057         runtime->private_data = azx_dev;
2058         snd_pcm_set_sync(substream);
2059         mutex_unlock(&chip->open_mutex);
2060         return 0;
2061 }
2062
2063 static int azx_pcm_close(struct snd_pcm_substream *substream)
2064 {
2065         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2066         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2067         struct azx *chip = apcm->chip;
2068         struct azx_dev *azx_dev = get_azx_dev(substream);
2069         unsigned long flags;
2070
2071         mutex_lock(&chip->open_mutex);
2072         spin_lock_irqsave(&chip->reg_lock, flags);
2073         azx_dev->substream = NULL;
2074         azx_dev->running = 0;
2075         spin_unlock_irqrestore(&chip->reg_lock, flags);
2076         azx_release_device(azx_dev);
2077         hinfo->ops.close(hinfo, apcm->codec, substream);
2078         snd_hda_power_down(apcm->codec);
2079         mutex_unlock(&chip->open_mutex);
2080         return 0;
2081 }
2082
2083 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
2084                              struct snd_pcm_hw_params *hw_params)
2085 {
2086         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2087         struct azx *chip = apcm->chip;
2088         struct azx_dev *azx_dev = get_azx_dev(substream);
2089         int ret;
2090
2091         dsp_lock(azx_dev);
2092         if (dsp_is_locked(azx_dev)) {
2093                 ret = -EBUSY;
2094                 goto unlock;
2095         }
2096
2097         mark_runtime_wc(chip, azx_dev, substream, false);
2098         azx_dev->bufsize = 0;
2099         azx_dev->period_bytes = 0;
2100         azx_dev->format_val = 0;
2101         ret = snd_pcm_lib_malloc_pages(substream,
2102                                         params_buffer_bytes(hw_params));
2103         if (ret < 0)
2104                 goto unlock;
2105         mark_runtime_wc(chip, azx_dev, substream, true);
2106  unlock:
2107         dsp_unlock(azx_dev);
2108         return ret;
2109 }
2110
2111 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
2112 {
2113         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2114         struct azx_dev *azx_dev = get_azx_dev(substream);
2115         struct azx *chip = apcm->chip;
2116         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2117
2118         /* reset BDL address */
2119         dsp_lock(azx_dev);
2120         if (!dsp_is_locked(azx_dev)) {
2121                 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2122                 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2123                 azx_sd_writel(azx_dev, SD_CTL, 0);
2124                 azx_dev->bufsize = 0;
2125                 azx_dev->period_bytes = 0;
2126                 azx_dev->format_val = 0;
2127         }
2128
2129         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
2130
2131         mark_runtime_wc(chip, azx_dev, substream, false);
2132         azx_dev->prepared = 0;
2133         dsp_unlock(azx_dev);
2134         return snd_pcm_lib_free_pages(substream);
2135 }
2136
2137 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
2138 {
2139         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2140         struct azx *chip = apcm->chip;
2141         struct azx_dev *azx_dev = get_azx_dev(substream);
2142         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2143         struct snd_pcm_runtime *runtime = substream->runtime;
2144         unsigned int bufsize, period_bytes, format_val, stream_tag;
2145         int err;
2146         struct hda_spdif_out *spdif =
2147                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
2148         unsigned short ctls = spdif ? spdif->ctls : 0;
2149
2150         dsp_lock(azx_dev);
2151         if (dsp_is_locked(azx_dev)) {
2152                 err = -EBUSY;
2153                 goto unlock;
2154         }
2155
2156         azx_stream_reset(chip, azx_dev);
2157         format_val = snd_hda_calc_stream_format(runtime->rate,
2158                                                 runtime->channels,
2159                                                 runtime->format,
2160                                                 hinfo->maxbps,
2161                                                 ctls);
2162         if (!format_val) {
2163                 dev_err(chip->card->dev,
2164                         "invalid format_val, rate=%d, ch=%d, format=%d\n",
2165                         runtime->rate, runtime->channels, runtime->format);
2166                 err = -EINVAL;
2167                 goto unlock;
2168         }
2169
2170         bufsize = snd_pcm_lib_buffer_bytes(substream);
2171         period_bytes = snd_pcm_lib_period_bytes(substream);
2172
2173         dev_dbg(chip->card->dev, "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
2174                 bufsize, format_val);
2175
2176         if (bufsize != azx_dev->bufsize ||
2177             period_bytes != azx_dev->period_bytes ||
2178             format_val != azx_dev->format_val ||
2179             runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
2180                 azx_dev->bufsize = bufsize;
2181                 azx_dev->period_bytes = period_bytes;
2182                 azx_dev->format_val = format_val;
2183                 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
2184                 err = azx_setup_periods(chip, substream, azx_dev);
2185                 if (err < 0)
2186                         goto unlock;
2187         }
2188
2189         /* when LPIB delay correction gives a small negative value,
2190          * we ignore it; currently set the threshold statically to
2191          * 64 frames
2192          */
2193         if (runtime->period_size > 64)
2194                 azx_dev->delay_negative_threshold = -frames_to_bytes(runtime, 64);
2195         else
2196                 azx_dev->delay_negative_threshold = 0;
2197
2198         /* wallclk has 24Mhz clock source */
2199         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
2200                                                 runtime->rate) * 1000);
2201         azx_setup_controller(chip, azx_dev);
2202         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2203                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
2204         else
2205                 azx_dev->fifo_size = 0;
2206
2207         stream_tag = azx_dev->stream_tag;
2208         /* CA-IBG chips need the playback stream starting from 1 */
2209         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
2210             stream_tag > chip->capture_streams)
2211                 stream_tag -= chip->capture_streams;
2212         err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
2213                                      azx_dev->format_val, substream);
2214
2215  unlock:
2216         if (!err)
2217                 azx_dev->prepared = 1;
2218         dsp_unlock(azx_dev);
2219         return err;
2220 }
2221
2222 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
2223 {
2224         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2225         struct azx *chip = apcm->chip;
2226         struct azx_dev *azx_dev;
2227         struct snd_pcm_substream *s;
2228         int rstart = 0, start, nsync = 0, sbits = 0;
2229         int nwait, timeout;
2230
2231         azx_dev = get_azx_dev(substream);
2232         trace_azx_pcm_trigger(chip, azx_dev, cmd);
2233
2234         if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
2235                 return -EPIPE;
2236
2237         switch (cmd) {
2238         case SNDRV_PCM_TRIGGER_START:
2239                 rstart = 1;
2240         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2241         case SNDRV_PCM_TRIGGER_RESUME:
2242                 start = 1;
2243                 break;
2244         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2245         case SNDRV_PCM_TRIGGER_SUSPEND:
2246         case SNDRV_PCM_TRIGGER_STOP:
2247                 start = 0;
2248                 break;
2249         default:
2250                 return -EINVAL;
2251         }
2252
2253         snd_pcm_group_for_each_entry(s, substream) {
2254                 if (s->pcm->card != substream->pcm->card)
2255                         continue;
2256                 azx_dev = get_azx_dev(s);
2257                 sbits |= 1 << azx_dev->index;
2258                 nsync++;
2259                 snd_pcm_trigger_done(s, substream);
2260         }
2261
2262         spin_lock(&chip->reg_lock);
2263
2264         /* first, set SYNC bits of corresponding streams */
2265         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2266                 azx_writel(chip, OLD_SSYNC,
2267                         azx_readl(chip, OLD_SSYNC) | sbits);
2268         else
2269                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2270
2271         snd_pcm_group_for_each_entry(s, substream) {
2272                 if (s->pcm->card != substream->pcm->card)
2273                         continue;
2274                 azx_dev = get_azx_dev(s);
2275                 if (start) {
2276                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2277                         if (!rstart)
2278                                 azx_dev->start_wallclk -=
2279                                                 azx_dev->period_wallclk;
2280                         azx_stream_start(chip, azx_dev);
2281                 } else {
2282                         azx_stream_stop(chip, azx_dev);
2283                 }
2284                 azx_dev->running = start;
2285         }
2286         spin_unlock(&chip->reg_lock);
2287         if (start) {
2288                 /* wait until all FIFOs get ready */
2289                 for (timeout = 5000; timeout; timeout--) {
2290                         nwait = 0;
2291                         snd_pcm_group_for_each_entry(s, substream) {
2292                                 if (s->pcm->card != substream->pcm->card)
2293                                         continue;
2294                                 azx_dev = get_azx_dev(s);
2295                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
2296                                       SD_STS_FIFO_READY))
2297                                         nwait++;
2298                         }
2299                         if (!nwait)
2300                                 break;
2301                         cpu_relax();
2302                 }
2303         } else {
2304                 /* wait until all RUN bits are cleared */
2305                 for (timeout = 5000; timeout; timeout--) {
2306                         nwait = 0;
2307                         snd_pcm_group_for_each_entry(s, substream) {
2308                                 if (s->pcm->card != substream->pcm->card)
2309                                         continue;
2310                                 azx_dev = get_azx_dev(s);
2311                                 if (azx_sd_readb(azx_dev, SD_CTL) &
2312                                     SD_CTL_DMA_START)
2313                                         nwait++;
2314                         }
2315                         if (!nwait)
2316                                 break;
2317                         cpu_relax();
2318                 }
2319         }
2320         spin_lock(&chip->reg_lock);
2321         /* reset SYNC bits */
2322         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2323                 azx_writel(chip, OLD_SSYNC,
2324                         azx_readl(chip, OLD_SSYNC) & ~sbits);
2325         else
2326                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2327         if (start) {
2328                 azx_timecounter_init(substream, 0, 0);
2329                 if (nsync > 1) {
2330                         cycle_t cycle_last;
2331
2332                         /* same start cycle for master and group */
2333                         azx_dev = get_azx_dev(substream);
2334                         cycle_last = azx_dev->azx_tc.cycle_last;
2335
2336                         snd_pcm_group_for_each_entry(s, substream) {
2337                                 if (s->pcm->card != substream->pcm->card)
2338                                         continue;
2339                                 azx_timecounter_init(s, 1, cycle_last);
2340                         }
2341                 }
2342         }
2343         spin_unlock(&chip->reg_lock);
2344         return 0;
2345 }
2346
2347 /* get the current DMA position with correction on VIA chips */
2348 static unsigned int azx_via_get_position(struct azx *chip,
2349                                          struct azx_dev *azx_dev)
2350 {
2351         unsigned int link_pos, mini_pos, bound_pos;
2352         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2353         unsigned int fifo_size;
2354
2355         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2356         if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2357                 /* Playback, no problem using link position */
2358                 return link_pos;
2359         }
2360
2361         /* Capture */
2362         /* For new chipset,
2363          * use mod to get the DMA position just like old chipset
2364          */
2365         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2366         mod_dma_pos %= azx_dev->period_bytes;
2367
2368         /* azx_dev->fifo_size can't get FIFO size of in stream.
2369          * Get from base address + offset.
2370          */
2371         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2372
2373         if (azx_dev->insufficient) {
2374                 /* Link position never gather than FIFO size */
2375                 if (link_pos <= fifo_size)
2376                         return 0;
2377
2378                 azx_dev->insufficient = 0;
2379         }
2380
2381         if (link_pos <= fifo_size)
2382                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2383         else
2384                 mini_pos = link_pos - fifo_size;
2385
2386         /* Find nearest previous boudary */
2387         mod_mini_pos = mini_pos % azx_dev->period_bytes;
2388         mod_link_pos = link_pos % azx_dev->period_bytes;
2389         if (mod_link_pos >= fifo_size)
2390                 bound_pos = link_pos - mod_link_pos;
2391         else if (mod_dma_pos >= mod_mini_pos)
2392                 bound_pos = mini_pos - mod_mini_pos;
2393         else {
2394                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2395                 if (bound_pos >= azx_dev->bufsize)
2396                         bound_pos = 0;
2397         }
2398
2399         /* Calculate real DMA position we want */
2400         return bound_pos + mod_dma_pos;
2401 }
2402
2403 static unsigned int azx_get_position(struct azx *chip,
2404                                      struct azx_dev *azx_dev,
2405                                      bool with_check)
2406 {
2407         struct snd_pcm_substream *substream = azx_dev->substream;
2408         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2409         unsigned int pos;
2410         int stream = substream->stream;
2411         struct hda_pcm_stream *hinfo = apcm->hinfo[stream];
2412         int delay = 0;
2413
2414         switch (chip->position_fix[stream]) {
2415         case POS_FIX_LPIB:
2416                 /* read LPIB */
2417                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2418                 break;
2419         case POS_FIX_VIACOMBO:
2420                 pos = azx_via_get_position(chip, azx_dev);
2421                 break;
2422         default:
2423                 /* use the position buffer */
2424                 pos = le32_to_cpu(*azx_dev->posbuf);
2425                 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2426                         if (!pos || pos == (u32)-1) {
2427                                 dev_info(chip->card->dev,
2428                                          "Invalid position buffer, using LPIB read method instead.\n");
2429                                 chip->position_fix[stream] = POS_FIX_LPIB;
2430                                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2431                         } else
2432                                 chip->position_fix[stream] = POS_FIX_POSBUF;
2433                 }
2434                 break;
2435         }
2436
2437         if (pos >= azx_dev->bufsize)
2438                 pos = 0;
2439
2440         /* calculate runtime delay from LPIB */
2441         if (substream->runtime &&
2442             chip->position_fix[stream] == POS_FIX_POSBUF &&
2443             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2444                 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
2445                 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2446                         delay = pos - lpib_pos;
2447                 else
2448                         delay = lpib_pos - pos;
2449                 if (delay < 0) {
2450                         if (delay >= azx_dev->delay_negative_threshold)
2451                                 delay = 0;
2452                         else
2453                                 delay += azx_dev->bufsize;
2454                 }
2455                 if (delay >= azx_dev->period_bytes) {
2456                         dev_info(chip->card->dev,
2457                                  "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
2458                                  delay, azx_dev->period_bytes);
2459                         delay = 0;
2460                         chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
2461                 }
2462                 delay = bytes_to_frames(substream->runtime, delay);
2463         }
2464
2465         if (substream->runtime) {
2466                 if (hinfo->ops.get_delay)
2467                         delay += hinfo->ops.get_delay(hinfo, apcm->codec,
2468                                                       substream);
2469                 substream->runtime->delay = delay;
2470         }
2471
2472         trace_azx_get_position(chip, azx_dev, pos, delay);
2473         return pos;
2474 }
2475
2476 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2477 {
2478         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2479         struct azx *chip = apcm->chip;
2480         struct azx_dev *azx_dev = get_azx_dev(substream);
2481         return bytes_to_frames(substream->runtime,
2482                                azx_get_position(chip, azx_dev, false));
2483 }
2484
2485 /*
2486  * Check whether the current DMA position is acceptable for updating
2487  * periods.  Returns non-zero if it's OK.
2488  *
2489  * Many HD-audio controllers appear pretty inaccurate about
2490  * the update-IRQ timing.  The IRQ is issued before actually the
2491  * data is processed.  So, we need to process it afterwords in a
2492  * workqueue.
2493  */
2494 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2495 {
2496         u32 wallclk;
2497         unsigned int pos;
2498
2499         wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2500         if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2501                 return -1;      /* bogus (too early) interrupt */
2502
2503         pos = azx_get_position(chip, azx_dev, true);
2504
2505         if (WARN_ONCE(!azx_dev->period_bytes,
2506                       "hda-intel: zero azx_dev->period_bytes"))
2507                 return -1; /* this shouldn't happen! */
2508         if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2509             pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2510                 /* NG - it's below the first next period boundary */
2511                 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2512         azx_dev->start_wallclk += wallclk;
2513         return 1; /* OK, it's fine */
2514 }
2515
2516 /*
2517  * The work for pending PCM period updates.
2518  */
2519 static void azx_irq_pending_work(struct work_struct *work)
2520 {
2521         struct azx *chip = container_of(work, struct azx, irq_pending_work);
2522         int i, pending, ok;
2523
2524         if (!chip->irq_pending_warned) {
2525                 dev_info(chip->card->dev,
2526                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
2527                          chip->card->number);
2528                 chip->irq_pending_warned = 1;
2529         }
2530
2531         for (;;) {
2532                 pending = 0;
2533                 spin_lock_irq(&chip->reg_lock);
2534                 for (i = 0; i < chip->num_streams; i++) {
2535                         struct azx_dev *azx_dev = &chip->azx_dev[i];
2536                         if (!azx_dev->irq_pending ||
2537                             !azx_dev->substream ||
2538                             !azx_dev->running)
2539                                 continue;
2540                         ok = azx_position_ok(chip, azx_dev);
2541                         if (ok > 0) {
2542                                 azx_dev->irq_pending = 0;
2543                                 spin_unlock(&chip->reg_lock);
2544                                 snd_pcm_period_elapsed(azx_dev->substream);
2545                                 spin_lock(&chip->reg_lock);
2546                         } else if (ok < 0) {
2547                                 pending = 0;    /* too early */
2548                         } else
2549                                 pending++;
2550                 }
2551                 spin_unlock_irq(&chip->reg_lock);
2552                 if (!pending)
2553                         return;
2554                 msleep(1);
2555         }
2556 }
2557
2558 /* clear irq_pending flags and assure no on-going workq */
2559 static void azx_clear_irq_pending(struct azx *chip)
2560 {
2561         int i;
2562
2563         spin_lock_irq(&chip->reg_lock);
2564         for (i = 0; i < chip->num_streams; i++)
2565                 chip->azx_dev[i].irq_pending = 0;
2566         spin_unlock_irq(&chip->reg_lock);
2567 }
2568
2569 #ifdef CONFIG_X86
2570 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2571                         struct vm_area_struct *area)
2572 {
2573         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2574         struct azx *chip = apcm->chip;
2575         if (!azx_snoop(chip))
2576                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2577         return snd_pcm_lib_default_mmap(substream, area);
2578 }
2579 #else
2580 #define azx_pcm_mmap    NULL
2581 #endif
2582
2583 static struct snd_pcm_ops azx_pcm_ops = {
2584         .open = azx_pcm_open,
2585         .close = azx_pcm_close,
2586         .ioctl = snd_pcm_lib_ioctl,
2587         .hw_params = azx_pcm_hw_params,
2588         .hw_free = azx_pcm_hw_free,
2589         .prepare = azx_pcm_prepare,
2590         .trigger = azx_pcm_trigger,
2591         .pointer = azx_pcm_pointer,
2592         .wall_clock =  azx_get_wallclock_tstamp,
2593         .mmap = azx_pcm_mmap,
2594         .page = snd_pcm_sgbuf_ops_page,
2595 };
2596
2597 static void azx_pcm_free(struct snd_pcm *pcm)
2598 {
2599         struct azx_pcm *apcm = pcm->private_data;
2600         if (apcm) {
2601                 list_del(&apcm->list);
2602                 kfree(apcm);
2603         }
2604 }
2605
2606 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
2607
2608 static int
2609 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2610                       struct hda_pcm *cpcm)
2611 {
2612         struct azx *chip = bus->private_data;
2613         struct snd_pcm *pcm;
2614         struct azx_pcm *apcm;
2615         int pcm_dev = cpcm->device;
2616         unsigned int size;
2617         int s, err;
2618
2619         list_for_each_entry(apcm, &chip->pcm_list, list) {
2620                 if (apcm->pcm->device == pcm_dev) {
2621                         dev_err(chip->card->dev, "PCM %d already exists\n",
2622                                 pcm_dev);
2623                         return -EBUSY;
2624                 }
2625         }
2626         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2627                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2628                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2629                           &pcm);
2630         if (err < 0)
2631                 return err;
2632         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2633         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2634         if (apcm == NULL)
2635                 return -ENOMEM;
2636         apcm->chip = chip;
2637         apcm->pcm = pcm;
2638         apcm->codec = codec;
2639         pcm->private_data = apcm;
2640         pcm->private_free = azx_pcm_free;
2641         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2642                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2643         list_add_tail(&apcm->list, &chip->pcm_list);
2644         cpcm->pcm = pcm;
2645         for (s = 0; s < 2; s++) {
2646                 apcm->hinfo[s] = &cpcm->stream[s];
2647                 if (cpcm->stream[s].substreams)
2648                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2649         }
2650         /* buffer pre-allocation */
2651         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2652         if (size > MAX_PREALLOC_SIZE)
2653                 size = MAX_PREALLOC_SIZE;
2654         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2655                                               snd_dma_pci_data(chip->pci),
2656                                               size, MAX_PREALLOC_SIZE);
2657         /* link to codec */
2658         pcm->dev = &codec->dev;
2659         return 0;
2660 }
2661
2662 /*
2663  * mixer creation - all stuff is implemented in hda module
2664  */
2665 static int azx_mixer_create(struct azx *chip)
2666 {
2667         return snd_hda_build_controls(chip->bus);
2668 }
2669
2670
2671 /*
2672  * initialize SD streams
2673  */
2674 static int azx_init_stream(struct azx *chip)
2675 {
2676         int i;
2677
2678         /* initialize each stream (aka device)
2679          * assign the starting bdl address to each stream (device)
2680          * and initialize
2681          */
2682         for (i = 0; i < chip->num_streams; i++) {
2683                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2684                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2685                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2686                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2687                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2688                 azx_dev->sd_int_sta_mask = 1 << i;
2689                 /* stream tag: must be non-zero and unique */
2690                 azx_dev->index = i;
2691                 azx_dev->stream_tag = i + 1;
2692         }
2693
2694         return 0;
2695 }
2696
2697 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2698 {
2699         if (request_irq(chip->pci->irq, azx_interrupt,
2700                         chip->msi ? 0 : IRQF_SHARED,
2701                         KBUILD_MODNAME, chip)) {
2702                 dev_err(chip->card->dev,
2703                         "unable to grab IRQ %d, disabling device\n",
2704                         chip->pci->irq);
2705                 if (do_disconnect)
2706                         snd_card_disconnect(chip->card);
2707                 return -1;
2708         }
2709         chip->irq = chip->pci->irq;
2710         pci_intx(chip->pci, !chip->msi);
2711         return 0;
2712 }
2713
2714
2715 static void azx_stop_chip(struct azx *chip)
2716 {
2717         if (!chip->initialized)
2718                 return;
2719
2720         /* disable interrupts */
2721         azx_int_disable(chip);
2722         azx_int_clear(chip);
2723
2724         /* disable CORB/RIRB */
2725         azx_free_cmd_io(chip);
2726
2727         /* disable position buffer */
2728         azx_writel(chip, DPLBASE, 0);
2729         azx_writel(chip, DPUBASE, 0);
2730
2731         chip->initialized = 0;
2732 }
2733
2734 #ifdef CONFIG_SND_HDA_DSP_LOADER
2735 /*
2736  * DSP loading code (e.g. for CA0132)
2737  */
2738
2739 /* use the first stream for loading DSP */
2740 static struct azx_dev *
2741 azx_get_dsp_loader_dev(struct azx *chip)
2742 {
2743         return &chip->azx_dev[chip->playback_index_offset];
2744 }
2745
2746 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
2747                                 unsigned int byte_size,
2748                                 struct snd_dma_buffer *bufp)
2749 {
2750         u32 *bdl;
2751         struct azx *chip = bus->private_data;
2752         struct azx_dev *azx_dev;
2753         int err;
2754
2755         azx_dev = azx_get_dsp_loader_dev(chip);
2756
2757         dsp_lock(azx_dev);
2758         spin_lock_irq(&chip->reg_lock);
2759         if (azx_dev->running || azx_dev->locked) {
2760                 spin_unlock_irq(&chip->reg_lock);
2761                 err = -EBUSY;
2762                 goto unlock;
2763         }
2764         azx_dev->prepared = 0;
2765         chip->saved_azx_dev = *azx_dev;
2766         azx_dev->locked = 1;
2767         spin_unlock_irq(&chip->reg_lock);
2768
2769         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG,
2770                                   snd_dma_pci_data(chip->pci),
2771                                   byte_size, bufp);
2772         if (err < 0)
2773                 goto err_alloc;
2774
2775         mark_pages_wc(chip, bufp, true);
2776         azx_dev->bufsize = byte_size;
2777         azx_dev->period_bytes = byte_size;
2778         azx_dev->format_val = format;
2779
2780         azx_stream_reset(chip, azx_dev);
2781
2782         /* reset BDL address */
2783         azx_sd_writel(azx_dev, SD_BDLPL, 0);
2784         azx_sd_writel(azx_dev, SD_BDLPU, 0);
2785
2786         azx_dev->frags = 0;
2787         bdl = (u32 *)azx_dev->bdl.area;
2788         err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
2789         if (err < 0)
2790                 goto error;
2791
2792         azx_setup_controller(chip, azx_dev);
2793         dsp_unlock(azx_dev);
2794         return azx_dev->stream_tag;
2795
2796  error:
2797         mark_pages_wc(chip, bufp, false);
2798         snd_dma_free_pages(bufp);
2799  err_alloc:
2800         spin_lock_irq(&chip->reg_lock);
2801         if (azx_dev->opened)
2802                 *azx_dev = chip->saved_azx_dev;
2803         azx_dev->locked = 0;
2804         spin_unlock_irq(&chip->reg_lock);
2805  unlock:
2806         dsp_unlock(azx_dev);
2807         return err;
2808 }
2809
2810 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
2811 {
2812         struct azx *chip = bus->private_data;
2813         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2814
2815         if (start)
2816                 azx_stream_start(chip, azx_dev);
2817         else
2818                 azx_stream_stop(chip, azx_dev);
2819         azx_dev->running = start;
2820 }
2821
2822 static void azx_load_dsp_cleanup(struct hda_bus *bus,
2823                                  struct snd_dma_buffer *dmab)
2824 {
2825         struct azx *chip = bus->private_data;
2826         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2827
2828         if (!dmab->area || !azx_dev->locked)
2829                 return;
2830
2831         dsp_lock(azx_dev);
2832         /* reset BDL address */
2833         azx_sd_writel(azx_dev, SD_BDLPL, 0);
2834         azx_sd_writel(azx_dev, SD_BDLPU, 0);
2835         azx_sd_writel(azx_dev, SD_CTL, 0);
2836         azx_dev->bufsize = 0;
2837         azx_dev->period_bytes = 0;
2838         azx_dev->format_val = 0;
2839
2840         mark_pages_wc(chip, dmab, false);
2841         snd_dma_free_pages(dmab);
2842         dmab->area = NULL;
2843
2844         spin_lock_irq(&chip->reg_lock);
2845         if (azx_dev->opened)
2846                 *azx_dev = chip->saved_azx_dev;
2847         azx_dev->locked = 0;
2848         spin_unlock_irq(&chip->reg_lock);
2849         dsp_unlock(azx_dev);
2850 }
2851 #endif /* CONFIG_SND_HDA_DSP_LOADER */
2852
2853 #ifdef CONFIG_PM
2854 /* power-up/down the controller */
2855 static void azx_power_notify(struct hda_bus *bus, bool power_up)
2856 {
2857         struct azx *chip = bus->private_data;
2858
2859         if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2860                 return;
2861
2862         if (power_up)
2863                 pm_runtime_get_sync(&chip->pci->dev);
2864         else
2865                 pm_runtime_put_sync(&chip->pci->dev);
2866 }
2867
2868 static DEFINE_MUTEX(card_list_lock);
2869 static LIST_HEAD(card_list);
2870
2871 static void azx_add_card_list(struct azx *chip)
2872 {
2873         mutex_lock(&card_list_lock);
2874         list_add(&chip->list, &card_list);
2875         mutex_unlock(&card_list_lock);
2876 }
2877
2878 static void azx_del_card_list(struct azx *chip)
2879 {
2880         mutex_lock(&card_list_lock);
2881         list_del_init(&chip->list);
2882         mutex_unlock(&card_list_lock);
2883 }
2884
2885 /* trigger power-save check at writing parameter */
2886 static int param_set_xint(const char *val, const struct kernel_param *kp)
2887 {
2888         struct azx *chip;
2889         struct hda_codec *c;
2890         int prev = power_save;
2891         int ret = param_set_int(val, kp);
2892
2893         if (ret || prev == power_save)
2894                 return ret;
2895
2896         mutex_lock(&card_list_lock);
2897         list_for_each_entry(chip, &card_list, list) {
2898                 if (!chip->bus || chip->disabled)
2899                         continue;
2900                 list_for_each_entry(c, &chip->bus->codec_list, list)
2901                         snd_hda_power_sync(c);
2902         }
2903         mutex_unlock(&card_list_lock);
2904         return 0;
2905 }
2906 #else
2907 #define azx_add_card_list(chip) /* NOP */
2908 #define azx_del_card_list(chip) /* NOP */
2909 #endif /* CONFIG_PM */
2910
2911 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
2912 /*
2913  * power management
2914  */
2915 static int azx_suspend(struct device *dev)
2916 {
2917         struct pci_dev *pci = to_pci_dev(dev);
2918         struct snd_card *card = dev_get_drvdata(dev);
2919         struct azx *chip = card->private_data;
2920         struct azx_pcm *p;
2921
2922         if (chip->disabled)
2923                 return 0;
2924
2925         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2926         azx_clear_irq_pending(chip);
2927         list_for_each_entry(p, &chip->pcm_list, list)
2928                 snd_pcm_suspend_all(p->pcm);
2929         if (chip->initialized)
2930                 snd_hda_suspend(chip->bus);
2931         azx_stop_chip(chip);
2932         azx_enter_link_reset(chip);
2933         if (chip->irq >= 0) {
2934                 free_irq(chip->irq, chip);
2935                 chip->irq = -1;
2936         }
2937         if (chip->msi)
2938                 pci_disable_msi(chip->pci);
2939         pci_disable_device(pci);
2940         pci_save_state(pci);
2941         pci_set_power_state(pci, PCI_D3hot);
2942         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2943                 hda_display_power(false);
2944         return 0;
2945 }
2946
2947 static int azx_resume(struct device *dev)
2948 {
2949         struct pci_dev *pci = to_pci_dev(dev);
2950         struct snd_card *card = dev_get_drvdata(dev);
2951         struct azx *chip = card->private_data;
2952
2953         if (chip->disabled)
2954                 return 0;
2955
2956         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2957                 hda_display_power(true);
2958         pci_set_power_state(pci, PCI_D0);
2959         pci_restore_state(pci);
2960         if (pci_enable_device(pci) < 0) {
2961                 dev_err(chip->card->dev,
2962                         "pci_enable_device failed, disabling device\n");
2963                 snd_card_disconnect(card);
2964                 return -EIO;
2965         }
2966         pci_set_master(pci);
2967         if (chip->msi)
2968                 if (pci_enable_msi(pci) < 0)
2969                         chip->msi = 0;
2970         if (azx_acquire_irq(chip, 1) < 0)
2971                 return -EIO;
2972         azx_init_pci(chip);
2973
2974         azx_init_chip(chip, 1);
2975
2976         snd_hda_resume(chip->bus);
2977         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2978         return 0;
2979 }
2980 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2981
2982 #ifdef CONFIG_PM_RUNTIME
2983 static int azx_runtime_suspend(struct device *dev)
2984 {
2985         struct snd_card *card = dev_get_drvdata(dev);
2986         struct azx *chip = card->private_data;
2987
2988         if (chip->disabled)
2989                 return 0;
2990
2991         if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2992                 return 0;
2993
2994         /* enable controller wake up event */
2995         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
2996                   STATESTS_INT_MASK);
2997
2998         azx_stop_chip(chip);
2999         azx_enter_link_reset(chip);
3000         azx_clear_irq_pending(chip);
3001         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
3002                 hda_display_power(false);
3003         return 0;
3004 }
3005
3006 static int azx_runtime_resume(struct device *dev)
3007 {
3008         struct snd_card *card = dev_get_drvdata(dev);
3009         struct azx *chip = card->private_data;
3010         struct hda_bus *bus;
3011         struct hda_codec *codec;
3012         int status;
3013
3014         if (chip->disabled)
3015                 return 0;
3016
3017         if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
3018                 return 0;
3019
3020         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
3021                 hda_display_power(true);
3022
3023         /* Read STATESTS before controller reset */
3024         status = azx_readw(chip, STATESTS);
3025
3026         azx_init_pci(chip);
3027         azx_init_chip(chip, 1);
3028
3029         bus = chip->bus;
3030         if (status && bus) {
3031                 list_for_each_entry(codec, &bus->codec_list, list)
3032                         if (status & (1 << codec->addr))
3033                                 queue_delayed_work(codec->bus->workq,
3034                                                    &codec->jackpoll_work, codec->jackpoll_interval);
3035         }
3036
3037         /* disable controller Wake Up event*/
3038         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
3039                         ~STATESTS_INT_MASK);
3040
3041         return 0;
3042 }
3043
3044 static int azx_runtime_idle(struct device *dev)
3045 {
3046         struct snd_card *card = dev_get_drvdata(dev);
3047         struct azx *chip = card->private_data;
3048
3049         if (chip->disabled)
3050                 return 0;
3051
3052         if (!power_save_controller ||
3053             !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
3054                 return -EBUSY;
3055
3056         return 0;
3057 }
3058
3059 #endif /* CONFIG_PM_RUNTIME */
3060
3061 #ifdef CONFIG_PM
3062 static const struct dev_pm_ops azx_pm = {
3063         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
3064         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
3065 };
3066
3067 #define AZX_PM_OPS      &azx_pm
3068 #else
3069 #define AZX_PM_OPS      NULL
3070 #endif /* CONFIG_PM */
3071
3072
3073 /*
3074  * reboot notifier for hang-up problem at power-down
3075  */
3076 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
3077 {
3078         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
3079         snd_hda_bus_reboot_notify(chip->bus);
3080         azx_stop_chip(chip);
3081         return NOTIFY_OK;
3082 }
3083
3084 static void azx_notifier_register(struct azx *chip)
3085 {
3086         chip->reboot_notifier.notifier_call = azx_halt;
3087         register_reboot_notifier(&chip->reboot_notifier);
3088 }
3089
3090 static void azx_notifier_unregister(struct azx *chip)
3091 {
3092         if (chip->reboot_notifier.notifier_call)
3093                 unregister_reboot_notifier(&chip->reboot_notifier);
3094 }
3095
3096 static int azx_probe_continue(struct azx *chip);
3097
3098 #ifdef SUPPORT_VGA_SWITCHEROO
3099 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
3100
3101 static void azx_vs_set_state(struct pci_dev *pci,
3102                              enum vga_switcheroo_state state)
3103 {
3104         struct snd_card *card = pci_get_drvdata(pci);
3105         struct azx *chip = card->private_data;
3106         bool disabled;
3107
3108         wait_for_completion(&chip->probe_wait);
3109         if (chip->init_failed)
3110                 return;
3111
3112         disabled = (state == VGA_SWITCHEROO_OFF);
3113         if (chip->disabled == disabled)
3114                 return;
3115
3116         if (!chip->bus) {
3117                 chip->disabled = disabled;
3118                 if (!disabled) {
3119                         dev_info(chip->card->dev,
3120                                  "Start delayed initialization\n");
3121                         if (azx_probe_continue(chip) < 0) {
3122                                 dev_err(chip->card->dev, "initialization error\n");
3123                                 chip->init_failed = true;
3124                         }
3125                 }
3126         } else {
3127                 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
3128                          disabled ? "Disabling" : "Enabling");
3129                 if (disabled) {
3130                         pm_runtime_put_sync_suspend(&pci->dev);
3131                         azx_suspend(&pci->dev);
3132                         /* when we get suspended by vga switcheroo we end up in D3cold,
3133                          * however we have no ACPI handle, so pci/acpi can't put us there,
3134                          * put ourselves there */
3135                         pci->current_state = PCI_D3cold;
3136                         chip->disabled = true;
3137                         if (snd_hda_lock_devices(chip->bus))
3138                                 dev_warn(chip->card->dev,
3139                                          "Cannot lock devices!\n");
3140                 } else {
3141                         snd_hda_unlock_devices(chip->bus);
3142                         pm_runtime_get_noresume(&pci->dev);
3143                         chip->disabled = false;
3144                         azx_resume(&pci->dev);
3145                 }
3146         }
3147 }
3148
3149 static bool azx_vs_can_switch(struct pci_dev *pci)
3150 {
3151         struct snd_card *card = pci_get_drvdata(pci);
3152         struct azx *chip = card->private_data;
3153
3154         wait_for_completion(&chip->probe_wait);
3155         if (chip->init_failed)
3156                 return false;
3157         if (chip->disabled || !chip->bus)
3158                 return true;
3159         if (snd_hda_lock_devices(chip->bus))
3160                 return false;
3161         snd_hda_unlock_devices(chip->bus);
3162         return true;
3163 }
3164
3165 static void init_vga_switcheroo(struct azx *chip)
3166 {
3167         struct pci_dev *p = get_bound_vga(chip->pci);
3168         if (p) {
3169                 dev_info(chip->card->dev,
3170                          "Handle VGA-switcheroo audio client\n");
3171                 chip->use_vga_switcheroo = 1;
3172                 pci_dev_put(p);
3173         }
3174 }
3175
3176 static const struct vga_switcheroo_client_ops azx_vs_ops = {
3177         .set_gpu_state = azx_vs_set_state,
3178         .can_switch = azx_vs_can_switch,
3179 };
3180
3181 static int register_vga_switcheroo(struct azx *chip)
3182 {
3183         int err;
3184
3185         if (!chip->use_vga_switcheroo)
3186                 return 0;
3187         /* FIXME: currently only handling DIS controller
3188          * is there any machine with two switchable HDMI audio controllers?
3189          */
3190         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
3191                                                     VGA_SWITCHEROO_DIS,
3192                                                     chip->bus != NULL);
3193         if (err < 0)
3194                 return err;
3195         chip->vga_switcheroo_registered = 1;
3196
3197         /* register as an optimus hdmi audio power domain */
3198         vga_switcheroo_init_domain_pm_optimus_hdmi_audio(&chip->pci->dev, &chip->hdmi_pm_domain);
3199         return 0;
3200 }
3201 #else
3202 #define init_vga_switcheroo(chip)               /* NOP */
3203 #define register_vga_switcheroo(chip)           0
3204 #define check_hdmi_disabled(pci)        false
3205 #endif /* SUPPORT_VGA_SWITCHER */
3206
3207 /*
3208  * destructor
3209  */
3210 static int azx_free(struct azx *chip)
3211 {
3212         struct pci_dev *pci = chip->pci;
3213         int i;
3214
3215         if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
3216                         && chip->running)
3217                 pm_runtime_get_noresume(&pci->dev);
3218
3219         azx_del_card_list(chip);
3220
3221         azx_notifier_unregister(chip);
3222
3223         chip->init_failed = 1; /* to be sure */
3224         complete_all(&chip->probe_wait);
3225
3226         if (use_vga_switcheroo(chip)) {
3227                 if (chip->disabled && chip->bus)
3228                         snd_hda_unlock_devices(chip->bus);
3229                 if (chip->vga_switcheroo_registered)
3230                         vga_switcheroo_unregister_client(chip->pci);
3231         }
3232
3233         if (chip->initialized) {
3234                 azx_clear_irq_pending(chip);
3235                 for (i = 0; i < chip->num_streams; i++)
3236                         azx_stream_stop(chip, &chip->azx_dev[i]);
3237                 azx_stop_chip(chip);
3238         }
3239
3240         if (chip->irq >= 0)
3241                 free_irq(chip->irq, (void*)chip);
3242         if (chip->msi)
3243                 pci_disable_msi(chip->pci);
3244         if (chip->remap_addr)
3245                 iounmap(chip->remap_addr);
3246
3247         if (chip->azx_dev) {
3248                 for (i = 0; i < chip->num_streams; i++)
3249                         if (chip->azx_dev[i].bdl.area) {
3250                                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
3251                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
3252                         }
3253         }
3254         if (chip->rb.area) {
3255                 mark_pages_wc(chip, &chip->rb, false);
3256                 snd_dma_free_pages(&chip->rb);
3257         }
3258         if (chip->posbuf.area) {
3259                 mark_pages_wc(chip, &chip->posbuf, false);
3260                 snd_dma_free_pages(&chip->posbuf);
3261         }
3262         if (chip->region_requested)
3263                 pci_release_regions(chip->pci);
3264         pci_disable_device(chip->pci);
3265         kfree(chip->azx_dev);
3266 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3267         if (chip->fw)
3268                 release_firmware(chip->fw);
3269 #endif
3270         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
3271                 hda_display_power(false);
3272                 hda_i915_exit();
3273         }
3274         kfree(chip);
3275
3276         return 0;
3277 }
3278
3279 static int azx_dev_free(struct snd_device *device)
3280 {
3281         return azx_free(device->device_data);
3282 }
3283
3284 #ifdef SUPPORT_VGA_SWITCHEROO
3285 /*
3286  * Check of disabled HDMI controller by vga-switcheroo
3287  */
3288 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
3289 {
3290         struct pci_dev *p;
3291
3292         /* check only discrete GPU */
3293         switch (pci->vendor) {
3294         case PCI_VENDOR_ID_ATI:
3295         case PCI_VENDOR_ID_AMD:
3296         case PCI_VENDOR_ID_NVIDIA:
3297                 if (pci->devfn == 1) {
3298                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
3299                                                         pci->bus->number, 0);
3300                         if (p) {
3301                                 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3302                                         return p;
3303                                 pci_dev_put(p);
3304                         }
3305                 }
3306                 break;
3307         }
3308         return NULL;
3309 }
3310
3311 static bool check_hdmi_disabled(struct pci_dev *pci)
3312 {
3313         bool vga_inactive = false;
3314         struct pci_dev *p = get_bound_vga(pci);
3315
3316         if (p) {
3317                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
3318                         vga_inactive = true;
3319                 pci_dev_put(p);
3320         }
3321         return vga_inactive;
3322 }
3323 #endif /* SUPPORT_VGA_SWITCHEROO */
3324
3325 /*
3326  * white/black-listing for position_fix
3327  */
3328 static struct snd_pci_quirk position_fix_list[] = {
3329         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
3330         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
3331         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
3332         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
3333         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
3334         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
3335         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
3336         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
3337         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
3338         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
3339         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
3340         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
3341         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
3342         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3343         {}
3344 };
3345
3346 static int check_position_fix(struct azx *chip, int fix)
3347 {
3348         const struct snd_pci_quirk *q;
3349
3350         switch (fix) {
3351         case POS_FIX_AUTO:
3352         case POS_FIX_LPIB:
3353         case POS_FIX_POSBUF:
3354         case POS_FIX_VIACOMBO:
3355         case POS_FIX_COMBO:
3356                 return fix;
3357         }
3358
3359         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
3360         if (q) {
3361                 dev_info(chip->card->dev,
3362                          "position_fix set to %d for device %04x:%04x\n",
3363                          q->value, q->subvendor, q->subdevice);
3364                 return q->value;
3365         }
3366
3367         /* Check VIA/ATI HD Audio Controller exist */
3368         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
3369                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
3370                 return POS_FIX_VIACOMBO;
3371         }
3372         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
3373                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
3374                 return POS_FIX_LPIB;
3375         }
3376         return POS_FIX_AUTO;
3377 }
3378
3379 /*
3380  * black-lists for probe_mask
3381  */
3382 static struct snd_pci_quirk probe_mask_list[] = {
3383         /* Thinkpad often breaks the controller communication when accessing
3384          * to the non-working (or non-existing) modem codec slot.
3385          */
3386         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
3387         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3388         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
3389         /* broken BIOS */
3390         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
3391         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3392         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
3393         /* forced codec slots */
3394         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
3395         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
3396         /* WinFast VP200 H (Teradici) user reported broken communication */
3397         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
3398         {}
3399 };
3400
3401 #define AZX_FORCE_CODEC_MASK    0x100
3402
3403 static void check_probe_mask(struct azx *chip, int dev)
3404 {
3405         const struct snd_pci_quirk *q;
3406
3407         chip->codec_probe_mask = probe_mask[dev];
3408         if (chip->codec_probe_mask == -1) {
3409                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3410                 if (q) {
3411                         dev_info(chip->card->dev,
3412                                  "probe_mask set to 0x%x for device %04x:%04x\n",
3413                                  q->value, q->subvendor, q->subdevice);
3414                         chip->codec_probe_mask = q->value;
3415                 }
3416         }
3417
3418         /* check forced option */
3419         if (chip->codec_probe_mask != -1 &&
3420             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3421                 chip->codec_mask = chip->codec_probe_mask & 0xff;
3422                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
3423                          chip->codec_mask);
3424         }
3425 }
3426
3427 /*
3428  * white/black-list for enable_msi
3429  */
3430 static struct snd_pci_quirk msi_black_list[] = {
3431         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
3432         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
3433         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
3434         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
3435         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
3436         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
3437         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
3438         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
3439         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3440         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
3441         {}
3442 };
3443
3444 static void check_msi(struct azx *chip)
3445 {
3446         const struct snd_pci_quirk *q;
3447
3448         if (enable_msi >= 0) {
3449                 chip->msi = !!enable_msi;
3450                 return;
3451         }
3452         chip->msi = 1;  /* enable MSI as default */
3453         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
3454         if (q) {
3455                 dev_info(chip->card->dev,
3456                          "msi for device %04x:%04x set to %d\n",
3457                          q->subvendor, q->subdevice, q->value);
3458                 chip->msi = q->value;
3459                 return;
3460         }
3461
3462         /* NVidia chipsets seem to cause troubles with MSI */
3463         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3464                 dev_info(chip->card->dev, "Disabling MSI\n");
3465                 chip->msi = 0;
3466         }
3467 }
3468
3469 /* check the snoop mode availability */
3470 static void azx_check_snoop_available(struct azx *chip)
3471 {
3472         bool snoop = chip->snoop;
3473
3474         switch (chip->driver_type) {
3475         case AZX_DRIVER_VIA:
3476                 /* force to non-snoop mode for a new VIA controller
3477                  * when BIOS is set
3478                  */
3479                 if (snoop) {
3480                         u8 val;
3481                         pci_read_config_byte(chip->pci, 0x42, &val);
3482                         if (!(val & 0x80) && chip->pci->revision == 0x30)
3483                                 snoop = false;
3484                 }
3485                 break;
3486         case AZX_DRIVER_ATIHDMI_NS:
3487                 /* new ATI HDMI requires non-snoop */
3488                 snoop = false;
3489                 break;
3490         case AZX_DRIVER_CTHDA:
3491                 snoop = false;
3492                 break;
3493         }
3494
3495         if (snoop != chip->snoop) {
3496                 dev_info(chip->card->dev, "Force to %s mode\n",
3497                          snoop ? "snoop" : "non-snoop");
3498                 chip->snoop = snoop;
3499         }
3500 }
3501
3502 static void azx_probe_work(struct work_struct *work)
3503 {
3504         azx_probe_continue(container_of(work, struct azx, probe_work));
3505 }
3506
3507 /*
3508  * constructor
3509  */
3510 static int azx_create(struct snd_card *card, struct pci_dev *pci,
3511                       int dev, unsigned int driver_caps,
3512                       struct azx **rchip)
3513 {
3514         static struct snd_device_ops ops = {
3515                 .dev_free = azx_dev_free,
3516         };
3517         struct azx *chip;
3518         int err;
3519
3520         *rchip = NULL;
3521
3522         err = pci_enable_device(pci);
3523         if (err < 0)
3524                 return err;
3525
3526         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3527         if (!chip) {
3528                 dev_err(card->dev, "Cannot allocate chip\n");
3529                 pci_disable_device(pci);
3530                 return -ENOMEM;
3531         }
3532
3533         spin_lock_init(&chip->reg_lock);
3534         mutex_init(&chip->open_mutex);
3535         chip->card = card;
3536         chip->pci = pci;
3537         chip->irq = -1;
3538         chip->driver_caps = driver_caps;
3539         chip->driver_type = driver_caps & 0xff;
3540         check_msi(chip);
3541         chip->dev_index = dev;
3542         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
3543         INIT_LIST_HEAD(&chip->pcm_list);
3544         INIT_LIST_HEAD(&chip->list);
3545         init_vga_switcheroo(chip);
3546         init_completion(&chip->probe_wait);
3547
3548         chip->position_fix[0] = chip->position_fix[1] =
3549                 check_position_fix(chip, position_fix[dev]);
3550         /* combo mode uses LPIB for playback */
3551         if (chip->position_fix[0] == POS_FIX_COMBO) {
3552                 chip->position_fix[0] = POS_FIX_LPIB;
3553                 chip->position_fix[1] = POS_FIX_AUTO;
3554         }
3555
3556         check_probe_mask(chip, dev);
3557
3558         chip->single_cmd = single_cmd;
3559         chip->snoop = hda_snoop;
3560         azx_check_snoop_available(chip);
3561
3562         if (bdl_pos_adj[dev] < 0) {
3563                 switch (chip->driver_type) {
3564                 case AZX_DRIVER_ICH:
3565                 case AZX_DRIVER_PCH:
3566                         bdl_pos_adj[dev] = 1;
3567                         break;
3568                 default:
3569                         bdl_pos_adj[dev] = 32;
3570                         break;
3571                 }
3572         }
3573
3574         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3575         if (err < 0) {
3576                 dev_err(card->dev, "Error creating device [card]!\n");
3577                 azx_free(chip);
3578                 return err;
3579         }
3580
3581         /* continue probing in work context as may trigger request module */
3582         INIT_WORK(&chip->probe_work, azx_probe_work);
3583
3584         *rchip = chip;
3585
3586         return 0;
3587 }
3588
3589 static int azx_first_init(struct azx *chip)
3590 {
3591         int dev = chip->dev_index;
3592         struct pci_dev *pci = chip->pci;
3593         struct snd_card *card = chip->card;
3594         int i, err;
3595         unsigned short gcap;
3596
3597 #if BITS_PER_LONG != 64
3598         /* Fix up base address on ULI M5461 */
3599         if (chip->driver_type == AZX_DRIVER_ULI) {
3600                 u16 tmp3;
3601                 pci_read_config_word(pci, 0x40, &tmp3);
3602                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3603                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3604         }
3605 #endif
3606
3607         err = pci_request_regions(pci, "ICH HD audio");
3608         if (err < 0)
3609                 return err;
3610         chip->region_requested = 1;
3611
3612         chip->addr = pci_resource_start(pci, 0);
3613         chip->remap_addr = pci_ioremap_bar(pci, 0);
3614         if (chip->remap_addr == NULL) {
3615                 dev_err(card->dev, "ioremap error\n");
3616                 return -ENXIO;
3617         }
3618
3619         if (chip->msi)
3620                 if (pci_enable_msi(pci) < 0)
3621                         chip->msi = 0;
3622
3623         if (azx_acquire_irq(chip, 0) < 0)
3624                 return -EBUSY;
3625
3626         pci_set_master(pci);
3627         synchronize_irq(chip->irq);
3628
3629         gcap = azx_readw(chip, GCAP);
3630         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
3631
3632         /* disable SB600 64bit support for safety */
3633         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
3634                 struct pci_dev *p_smbus;
3635                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3636                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3637                                          NULL);
3638                 if (p_smbus) {
3639                         if (p_smbus->revision < 0x30)
3640                                 gcap &= ~ICH6_GCAP_64OK;
3641                         pci_dev_put(p_smbus);
3642                 }
3643         }
3644
3645         /* disable 64bit DMA address on some devices */
3646         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3647                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
3648                 gcap &= ~ICH6_GCAP_64OK;
3649         }
3650
3651         /* disable buffer size rounding to 128-byte multiples if supported */
3652         if (align_buffer_size >= 0)
3653                 chip->align_buffer_size = !!align_buffer_size;
3654         else {
3655                 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3656                         chip->align_buffer_size = 0;
3657                 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3658                         chip->align_buffer_size = 1;
3659                 else
3660                         chip->align_buffer_size = 1;
3661         }
3662
3663         /* allow 64bit DMA address if supported by H/W */
3664         if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
3665                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
3666         else {
3667                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3668                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
3669         }
3670
3671         /* read number of streams from GCAP register instead of using
3672          * hardcoded value
3673          */
3674         chip->capture_streams = (gcap >> 8) & 0x0f;
3675         chip->playback_streams = (gcap >> 12) & 0x0f;
3676         if (!chip->playback_streams && !chip->capture_streams) {
3677                 /* gcap didn't give any info, switching to old method */
3678
3679                 switch (chip->driver_type) {
3680                 case AZX_DRIVER_ULI:
3681                         chip->playback_streams = ULI_NUM_PLAYBACK;
3682                         chip->capture_streams = ULI_NUM_CAPTURE;
3683                         break;
3684                 case AZX_DRIVER_ATIHDMI:
3685                 case AZX_DRIVER_ATIHDMI_NS:
3686                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3687                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
3688                         break;
3689                 case AZX_DRIVER_GENERIC:
3690                 default:
3691                         chip->playback_streams = ICH6_NUM_PLAYBACK;
3692                         chip->capture_streams = ICH6_NUM_CAPTURE;
3693                         break;
3694                 }
3695         }
3696         chip->capture_index_offset = 0;
3697         chip->playback_index_offset = chip->capture_streams;
3698         chip->num_streams = chip->playback_streams + chip->capture_streams;
3699         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3700                                 GFP_KERNEL);
3701         if (!chip->azx_dev) {
3702                 dev_err(card->dev, "cannot malloc azx_dev\n");
3703                 return -ENOMEM;
3704         }
3705
3706         for (i = 0; i < chip->num_streams; i++) {
3707                 dsp_lock_init(&chip->azx_dev[i]);
3708                 /* allocate memory for the BDL for each stream */
3709                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3710                                           snd_dma_pci_data(chip->pci),
3711                                           BDL_SIZE, &chip->azx_dev[i].bdl);
3712                 if (err < 0) {
3713                         dev_err(card->dev, "cannot allocate BDL\n");
3714                         return -ENOMEM;
3715                 }
3716                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
3717         }
3718         /* allocate memory for the position buffer */
3719         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3720                                   snd_dma_pci_data(chip->pci),
3721                                   chip->num_streams * 8, &chip->posbuf);
3722         if (err < 0) {
3723                 dev_err(card->dev, "cannot allocate posbuf\n");
3724                 return -ENOMEM;
3725         }
3726         mark_pages_wc(chip, &chip->posbuf, true);
3727         /* allocate CORB/RIRB */
3728         err = azx_alloc_cmd_io(chip);
3729         if (err < 0)
3730                 return err;
3731
3732         /* initialize streams */
3733         azx_init_stream(chip);
3734
3735         /* initialize chip */
3736         azx_init_pci(chip);
3737         azx_init_chip(chip, (probe_only[dev] & 2) == 0);
3738
3739         /* codec detection */
3740         if (!chip->codec_mask) {
3741                 dev_err(card->dev, "no codecs found!\n");
3742                 return -ENODEV;
3743         }
3744
3745         strcpy(card->driver, "HDA-Intel");
3746         strlcpy(card->shortname, driver_short_names[chip->driver_type],
3747                 sizeof(card->shortname));
3748         snprintf(card->longname, sizeof(card->longname),
3749                  "%s at 0x%lx irq %i",
3750                  card->shortname, chip->addr, chip->irq);
3751
3752         return 0;
3753 }
3754
3755 static void power_down_all_codecs(struct azx *chip)
3756 {
3757 #ifdef CONFIG_PM
3758         /* The codecs were powered up in snd_hda_codec_new().
3759          * Now all initialization done, so turn them down if possible
3760          */
3761         struct hda_codec *codec;
3762         list_for_each_entry(codec, &chip->bus->codec_list, list) {
3763                 snd_hda_power_down(codec);
3764         }
3765 #endif
3766 }
3767
3768 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3769 /* callback from request_firmware_nowait() */
3770 static void azx_firmware_cb(const struct firmware *fw, void *context)
3771 {
3772         struct snd_card *card = context;
3773         struct azx *chip = card->private_data;
3774         struct pci_dev *pci = chip->pci;
3775
3776         if (!fw) {
3777                 dev_err(card->dev, "Cannot load firmware, aborting\n");
3778                 goto error;
3779         }
3780
3781         chip->fw = fw;
3782         if (!chip->disabled) {
3783                 /* continue probing */
3784                 if (azx_probe_continue(chip))
3785                         goto error;
3786         }
3787         return; /* OK */
3788
3789  error:
3790         snd_card_free(card);
3791         pci_set_drvdata(pci, NULL);
3792 }
3793 #endif
3794
3795 static int azx_probe(struct pci_dev *pci,
3796                      const struct pci_device_id *pci_id)
3797 {
3798         static int dev;
3799         struct snd_card *card;
3800         struct azx *chip;
3801         bool schedule_probe;
3802         int err;
3803
3804         if (dev >= SNDRV_CARDS)
3805                 return -ENODEV;
3806         if (!enable[dev]) {
3807                 dev++;
3808                 return -ENOENT;
3809         }
3810
3811         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
3812                            0, &card);
3813         if (err < 0) {
3814                 dev_err(&pci->dev, "Error creating card!\n");
3815                 return err;
3816         }
3817
3818         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
3819         if (err < 0)
3820                 goto out_free;
3821         card->private_data = chip;
3822
3823         pci_set_drvdata(pci, card);
3824
3825         err = register_vga_switcheroo(chip);
3826         if (err < 0) {
3827                 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
3828                 goto out_free;
3829         }
3830
3831         if (check_hdmi_disabled(pci)) {
3832                 dev_info(card->dev, "VGA controller is disabled\n");
3833                 dev_info(card->dev, "Delaying initialization\n");
3834                 chip->disabled = true;
3835         }
3836
3837         schedule_probe = !chip->disabled;
3838
3839 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3840         if (patch[dev] && *patch[dev]) {
3841                 dev_info(card->dev, "Applying patch firmware '%s'\n",
3842                          patch[dev]);
3843                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3844                                               &pci->dev, GFP_KERNEL, card,
3845                                               azx_firmware_cb);
3846                 if (err < 0)
3847                         goto out_free;
3848                 schedule_probe = false; /* continued in azx_firmware_cb() */
3849         }
3850 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
3851
3852 #ifndef CONFIG_SND_HDA_I915
3853         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
3854                 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
3855 #endif
3856
3857         if (schedule_probe)
3858                 schedule_work(&chip->probe_work);
3859
3860         dev++;
3861         if (chip->disabled)
3862                 complete_all(&chip->probe_wait);
3863         return 0;
3864
3865 out_free:
3866         snd_card_free(card);
3867         return err;
3868 }
3869
3870 static int azx_probe_continue(struct azx *chip)
3871 {
3872         struct pci_dev *pci = chip->pci;
3873         int dev = chip->dev_index;
3874         int err;
3875
3876         /* Request power well for Haswell HDA controller and codec */
3877         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
3878 #ifdef CONFIG_SND_HDA_I915
3879                 err = hda_i915_init();
3880                 if (err < 0) {
3881                         dev_err(chip->card->dev,
3882                                 "Error request power-well from i915\n");
3883                         goto out_free;
3884                 }
3885 #endif
3886                 hda_display_power(true);
3887         }
3888
3889         err = azx_first_init(chip);
3890         if (err < 0)
3891                 goto out_free;
3892
3893 #ifdef CONFIG_SND_HDA_INPUT_BEEP
3894         chip->beep_mode = beep_mode[dev];
3895 #endif
3896
3897         /* create codec instances */
3898         err = azx_codec_create(chip, model[dev]);
3899         if (err < 0)
3900                 goto out_free;
3901 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3902         if (chip->fw) {
3903                 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3904                                          chip->fw->data);
3905                 if (err < 0)
3906                         goto out_free;
3907 #ifndef CONFIG_PM
3908                 release_firmware(chip->fw); /* no longer needed */
3909                 chip->fw = NULL;
3910 #endif
3911         }
3912 #endif
3913         if ((probe_only[dev] & 1) == 0) {
3914                 err = azx_codec_configure(chip);
3915                 if (err < 0)
3916                         goto out_free;
3917         }
3918
3919         /* create PCM streams */
3920         err = snd_hda_build_pcms(chip->bus);
3921         if (err < 0)
3922                 goto out_free;
3923
3924         /* create mixer controls */
3925         err = azx_mixer_create(chip);
3926         if (err < 0)
3927                 goto out_free;
3928
3929         err = snd_card_register(chip->card);
3930         if (err < 0)
3931                 goto out_free;
3932
3933         chip->running = 1;
3934         power_down_all_codecs(chip);
3935         azx_notifier_register(chip);
3936         azx_add_card_list(chip);
3937         if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || chip->use_vga_switcheroo)
3938                 pm_runtime_put_noidle(&pci->dev);
3939
3940 out_free:
3941         if (err < 0)
3942                 chip->init_failed = 1;
3943         complete_all(&chip->probe_wait);
3944         return err;
3945 }
3946
3947 static void azx_remove(struct pci_dev *pci)
3948 {
3949         struct snd_card *card = pci_get_drvdata(pci);
3950
3951         if (card)
3952                 snd_card_free(card);
3953 }
3954
3955 /* PCI IDs */
3956 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
3957         /* CPT */
3958         { PCI_DEVICE(0x8086, 0x1c20),
3959           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3960         /* PBG */
3961         { PCI_DEVICE(0x8086, 0x1d20),
3962           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3963         /* Panther Point */
3964         { PCI_DEVICE(0x8086, 0x1e20),
3965           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3966         /* Lynx Point */
3967         { PCI_DEVICE(0x8086, 0x8c20),
3968           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3969         /* Wellsburg */
3970         { PCI_DEVICE(0x8086, 0x8d20),
3971           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3972         { PCI_DEVICE(0x8086, 0x8d21),
3973           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3974         /* Lynx Point-LP */
3975         { PCI_DEVICE(0x8086, 0x9c20),
3976           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3977         /* Lynx Point-LP */
3978         { PCI_DEVICE(0x8086, 0x9c21),
3979           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3980         /* Wildcat Point-LP */
3981         { PCI_DEVICE(0x8086, 0x9ca0),
3982           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3983         /* Haswell */
3984         { PCI_DEVICE(0x8086, 0x0a0c),
3985           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
3986         { PCI_DEVICE(0x8086, 0x0c0c),
3987           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
3988         { PCI_DEVICE(0x8086, 0x0d0c),
3989           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
3990         /* Broadwell */
3991         { PCI_DEVICE(0x8086, 0x160c),
3992           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
3993         /* 5 Series/3400 */
3994         { PCI_DEVICE(0x8086, 0x3b56),
3995           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
3996         /* Poulsbo */
3997         { PCI_DEVICE(0x8086, 0x811b),
3998           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
3999         /* Oaktrail */
4000         { PCI_DEVICE(0x8086, 0x080a),
4001           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
4002         /* BayTrail */
4003         { PCI_DEVICE(0x8086, 0x0f04),
4004           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
4005         /* ICH */
4006         { PCI_DEVICE(0x8086, 0x2668),
4007           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4008           AZX_DCAPS_BUFSIZE },  /* ICH6 */
4009         { PCI_DEVICE(0x8086, 0x27d8),
4010           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4011           AZX_DCAPS_BUFSIZE },  /* ICH7 */
4012         { PCI_DEVICE(0x8086, 0x269a),
4013           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4014           AZX_DCAPS_BUFSIZE },  /* ESB2 */
4015         { PCI_DEVICE(0x8086, 0x284b),
4016           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4017           AZX_DCAPS_BUFSIZE },  /* ICH8 */
4018         { PCI_DEVICE(0x8086, 0x293e),
4019           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4020           AZX_DCAPS_BUFSIZE },  /* ICH9 */
4021         { PCI_DEVICE(0x8086, 0x293f),
4022           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4023           AZX_DCAPS_BUFSIZE },  /* ICH9 */
4024         { PCI_DEVICE(0x8086, 0x3a3e),
4025           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4026           AZX_DCAPS_BUFSIZE },  /* ICH10 */
4027         { PCI_DEVICE(0x8086, 0x3a6e),
4028           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4029           AZX_DCAPS_BUFSIZE },  /* ICH10 */
4030         /* Generic Intel */
4031         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
4032           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4033           .class_mask = 0xffffff,
4034           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
4035         /* ATI SB 450/600/700/800/900 */
4036         { PCI_DEVICE(0x1002, 0x437b),
4037           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
4038         { PCI_DEVICE(0x1002, 0x4383),
4039           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
4040         /* AMD Hudson */
4041         { PCI_DEVICE(0x1022, 0x780d),
4042           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
4043         /* ATI HDMI */
4044         { PCI_DEVICE(0x1002, 0x793b),
4045           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4046         { PCI_DEVICE(0x1002, 0x7919),
4047           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4048         { PCI_DEVICE(0x1002, 0x960f),
4049           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4050         { PCI_DEVICE(0x1002, 0x970f),
4051           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4052         { PCI_DEVICE(0x1002, 0xaa00),
4053           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4054         { PCI_DEVICE(0x1002, 0xaa08),
4055           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4056         { PCI_DEVICE(0x1002, 0xaa10),
4057           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4058         { PCI_DEVICE(0x1002, 0xaa18),
4059           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4060         { PCI_DEVICE(0x1002, 0xaa20),
4061           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4062         { PCI_DEVICE(0x1002, 0xaa28),
4063           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4064         { PCI_DEVICE(0x1002, 0xaa30),
4065           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4066         { PCI_DEVICE(0x1002, 0xaa38),
4067           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4068         { PCI_DEVICE(0x1002, 0xaa40),
4069           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4070         { PCI_DEVICE(0x1002, 0xaa48),
4071           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4072         { PCI_DEVICE(0x1002, 0xaa50),
4073           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4074         { PCI_DEVICE(0x1002, 0xaa58),
4075           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4076         { PCI_DEVICE(0x1002, 0xaa60),
4077           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4078         { PCI_DEVICE(0x1002, 0xaa68),
4079           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4080         { PCI_DEVICE(0x1002, 0xaa80),
4081           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4082         { PCI_DEVICE(0x1002, 0xaa88),
4083           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4084         { PCI_DEVICE(0x1002, 0xaa90),
4085           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4086         { PCI_DEVICE(0x1002, 0xaa98),
4087           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4088         { PCI_DEVICE(0x1002, 0x9902),
4089           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4090         { PCI_DEVICE(0x1002, 0xaaa0),
4091           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4092         { PCI_DEVICE(0x1002, 0xaaa8),
4093           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4094         { PCI_DEVICE(0x1002, 0xaab0),
4095           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4096         /* VIA VT8251/VT8237A */
4097         { PCI_DEVICE(0x1106, 0x3288),
4098           .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
4099         /* VIA GFX VT7122/VX900 */
4100         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
4101         /* VIA GFX VT6122/VX11 */
4102         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
4103         /* SIS966 */
4104         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
4105         /* ULI M5461 */
4106         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
4107         /* NVIDIA MCP */
4108         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
4109           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4110           .class_mask = 0xffffff,
4111           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
4112         /* Teradici */
4113         { PCI_DEVICE(0x6549, 0x1200),
4114           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4115         { PCI_DEVICE(0x6549, 0x2200),
4116           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4117         /* Creative X-Fi (CA0110-IBG) */
4118         /* CTHDA chips */
4119         { PCI_DEVICE(0x1102, 0x0010),
4120           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
4121         { PCI_DEVICE(0x1102, 0x0012),
4122           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
4123 #if !IS_ENABLED(CONFIG_SND_CTXFI)
4124         /* the following entry conflicts with snd-ctxfi driver,
4125          * as ctxfi driver mutates from HD-audio to native mode with
4126          * a special command sequence.
4127          */
4128         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
4129           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4130           .class_mask = 0xffffff,
4131           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
4132           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
4133 #else
4134         /* this entry seems still valid -- i.e. without emu20kx chip */
4135         { PCI_DEVICE(0x1102, 0x0009),
4136           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
4137           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
4138 #endif
4139         /* Vortex86MX */
4140         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
4141         /* VMware HDAudio */
4142         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
4143         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
4144         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
4145           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4146           .class_mask = 0xffffff,
4147           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
4148         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
4149           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4150           .class_mask = 0xffffff,
4151           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
4152         { 0, }
4153 };
4154 MODULE_DEVICE_TABLE(pci, azx_ids);
4155
4156 /* pci_driver definition */
4157 static struct pci_driver azx_driver = {
4158         .name = KBUILD_MODNAME,
4159         .id_table = azx_ids,
4160         .probe = azx_probe,
4161         .remove = azx_remove,
4162         .driver = {
4163                 .pm = AZX_PM_OPS,
4164         },
4165 };
4166
4167 module_pci_driver(azx_driver);