sound/pci/hda/patch_hdmi.c

   1 /*
   2  *
   3  *  patch_hdmi.c - routines for HDMI/DisplayPort codecs
   4  *
   5  *  Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
   6  *  Copyright (c) 2006 ATI Technologies Inc.
   7  *  Copyright (c) 2008 NVIDIA Corp.  All rights reserved.
   8  *  Copyright (c) 2008 Wei Ni <wni@nvidia.com>
   9  *  Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
  10  *
  11  *  Authors:
  12  *                      Wu Fengguang <wfg@linux.intel.com>
  13  *
  14  *  Maintained by:
  15  *                      Wu Fengguang <wfg@linux.intel.com>
  16  *
  17  *  This program is free software; you can redistribute it and/or modify it
  18  *  under the terms of the GNU General Public License as published by the Free
  19  *  Software Foundation; either version 2 of the License, or (at your option)
  20  *  any later version.
  21  *
  22  *  This program is distributed in the hope that it will be useful, but
  23  *  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  24  *  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  25  *  for more details.
  26  *
  27  *  You should have received a copy of the GNU General Public License
  28  *  along with this program; if not, write to the Free Software Foundation,
  29  *  Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  30  */
  31
  32 #include <linux/init.h>
  33 #include <linux/delay.h>
  34 #include <linux/slab.h>
  35 #include <linux/module.h>
  36 #include <sound/core.h>
  37 #include <sound/jack.h>
  38 #include <sound/asoundef.h>
  39 #include <sound/tlv.h>
  40 #include <sound/hdaudio.h>
  41 #include <sound/hda_i915.h>
  42 #include "hda_codec.h"
  43 #include "hda_local.h"
  44 #include "hda_jack.h"
  45
  46 static bool static_hdmi_pcm;
  47 module_param(static_hdmi_pcm, bool, 0644);
  48 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
  49
  50 #define is_haswell(codec)  ((codec)->core.vendor_id == 0x80862807)
  51 #define is_broadwell(codec)    ((codec)->core.vendor_id == 0x80862808)
  52 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
  53 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
  54                                         || is_skylake(codec))
  55
  56 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
  57 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
  58 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
  59
  60 struct hdmi_spec_per_cvt {
  61         hda_nid_t cvt_nid;
  62         int assigned;
  63         unsigned int channels_min;
  64         unsigned int channels_max;
  65         u32 rates;
  66         u64 formats;
  67         unsigned int maxbps;
  68 };
  69
  70 /* max. connections to a widget */
  71 #define HDA_MAX_CONNECTIONS     32
  72
  73 struct hdmi_spec_per_pin {
  74         hda_nid_t pin_nid;
  75         int num_mux_nids;
  76         hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
  77         int mux_idx;
  78         hda_nid_t cvt_nid;
  79
  80         struct hda_codec *codec;
  81         struct hdmi_eld sink_eld;
  82         struct mutex lock;
  83         struct delayed_work work;
  84         struct snd_kcontrol *eld_ctl;
  85         int repoll_count;
  86         bool setup; /* the stream has been set up by prepare callback */
  87         int channels; /* current number of channels */
  88         bool non_pcm;
  89         bool chmap_set;         /* channel-map override by ALSA API? */
  90         unsigned char chmap[8]; /* ALSA API channel-map */
  91 #ifdef CONFIG_SND_PROC_FS
  92         struct snd_info_entry *proc_entry;
  93 #endif
  94 };
  95
  96 struct cea_channel_speaker_allocation;
  97
  98 /* operations used by generic code that can be overridden by patches */
  99 struct hdmi_ops {
 100         int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
 101                            unsigned char *buf, int *eld_size);
 102
 103         /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */
 104         int (*pin_get_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
 105                                     int asp_slot);
 106         int (*pin_set_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
 107                                     int asp_slot, int channel);
 108
 109         void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
 110                                     int ca, int active_channels, int conn_type);
 111
 112         /* enable/disable HBR (HD passthrough) */
 113         int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
 114
 115         int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
 116                             hda_nid_t pin_nid, u32 stream_tag, int format);
 117
 118         /* Helpers for producing the channel map TLVs. These can be overridden
 119          * for devices that have non-standard mapping requirements. */
 120         int (*chmap_cea_alloc_validate_get_type)(struct cea_channel_speaker_allocation *cap,
 121                                                  int channels);
 122         void (*cea_alloc_to_tlv_chmap)(struct cea_channel_speaker_allocation *cap,
 123                                        unsigned int *chmap, int channels);
 124
 125         /* check that the user-given chmap is supported */
 126         int (*chmap_validate)(int ca, int channels, unsigned char *chmap);
 127 };
 128
 129 struct hdmi_spec {
 130         int num_cvts;
 131         struct snd_array cvts; /* struct hdmi_spec_per_cvt */
 132         hda_nid_t cvt_nids[4]; /* only for haswell fix */
 133
 134         int num_pins;
 135         struct snd_array pins; /* struct hdmi_spec_per_pin */
 136         struct hda_pcm *pcm_rec[16];
 137         unsigned int channels_max; /* max over all cvts */
 138
 139         struct hdmi_eld temp_eld;
 140         struct hdmi_ops ops;
 141
 142         bool dyn_pin_out;
 143
 144         /*
 145          * Non-generic VIA/NVIDIA specific
 146          */
 147         struct hda_multi_out multiout;
 148         struct hda_pcm_stream pcm_playback;
 149
 150         /* i915/powerwell (Haswell+/Valleyview+) specific */
 151         struct i915_audio_component_audio_ops i915_audio_ops;
 152 };
 153
 154
 155 struct hdmi_audio_infoframe {
 156         u8 type; /* 0x84 */
 157         u8 ver;  /* 0x01 */
 158         u8 len;  /* 0x0a */
 159
 160         u8 checksum;
 161
 162         u8 CC02_CT47;   /* CC in bits 0:2, CT in 4:7 */
 163         u8 SS01_SF24;
 164         u8 CXT04;
 165         u8 CA;
 166         u8 LFEPBL01_LSV36_DM_INH7;
 167 };
 168
 169 struct dp_audio_infoframe {
 170         u8 type; /* 0x84 */
 171         u8 len;  /* 0x1b */
 172         u8 ver;  /* 0x11 << 2 */
 173
 174         u8 CC02_CT47;   /* match with HDMI infoframe from this on */
 175         u8 SS01_SF24;
 176         u8 CXT04;
 177         u8 CA;
 178         u8 LFEPBL01_LSV36_DM_INH7;
 179 };
 180
 181 union audio_infoframe {
 182         struct hdmi_audio_infoframe hdmi;
 183         struct dp_audio_infoframe dp;
 184         u8 bytes[0];
 185 };
 186
 187 /*
 188  * CEA speaker placement:
 189  *
 190  *        FLH       FCH        FRH
 191  *  FLW    FL  FLC   FC   FRC   FR   FRW
 192  *
 193  *                                  LFE
 194  *                     TC
 195  *
 196  *          RL  RLC   RC   RRC   RR
 197  *
 198  * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
 199  * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
 200  */
 201 enum cea_speaker_placement {
 202         FL  = (1 <<  0),        /* Front Left           */
 203         FC  = (1 <<  1),        /* Front Center         */
 204         FR  = (1 <<  2),        /* Front Right          */
 205         FLC = (1 <<  3),        /* Front Left Center    */
 206         FRC = (1 <<  4),        /* Front Right Center   */
 207         RL  = (1 <<  5),        /* Rear Left            */
 208         RC  = (1 <<  6),        /* Rear Center          */
 209         RR  = (1 <<  7),        /* Rear Right           */
 210         RLC = (1 <<  8),        /* Rear Left Center     */
 211         RRC = (1 <<  9),        /* Rear Right Center    */
 212         LFE = (1 << 10),        /* Low Frequency Effect */
 213         FLW = (1 << 11),        /* Front Left Wide      */
 214         FRW = (1 << 12),        /* Front Right Wide     */
 215         FLH = (1 << 13),        /* Front Left High      */
 216         FCH = (1 << 14),        /* Front Center High    */
 217         FRH = (1 << 15),        /* Front Right High     */
 218         TC  = (1 << 16),        /* Top Center           */
 219 };
 220
 221 /*
 222  * ELD SA bits in the CEA Speaker Allocation data block
 223  */
 224 static int eld_speaker_allocation_bits[] = {
 225         [0] = FL | FR,
 226         [1] = LFE,
 227         [2] = FC,
 228         [3] = RL | RR,
 229         [4] = RC,
 230         [5] = FLC | FRC,
 231         [6] = RLC | RRC,
 232         /* the following are not defined in ELD yet */
 233         [7] = FLW | FRW,
 234         [8] = FLH | FRH,
 235         [9] = TC,
 236         [10] = FCH,
 237 };
 238
 239 struct cea_channel_speaker_allocation {
 240         int ca_index;
 241         int speakers[8];
 242
 243         /* derived values, just for convenience */
 244         int channels;
 245         int spk_mask;
 246 };
 247
 248 /*
 249  * ALSA sequence is:
 250  *
 251  *       surround40   surround41   surround50   surround51   surround71
 252  * ch0   front left   =            =            =            =
 253  * ch1   front right  =            =            =            =
 254  * ch2   rear left    =            =            =            =
 255  * ch3   rear right   =            =            =            =
 256  * ch4                LFE          center       center       center
 257  * ch5                                          LFE          LFE
 258  * ch6                                                       side left
 259  * ch7                                                       side right
 260  *
 261  * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
 262  */
 263 static int hdmi_channel_mapping[0x32][8] = {
 264         /* stereo */
 265         [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
 266         /* 2.1 */
 267         [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
 268         /* Dolby Surround */
 269         [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
 270         /* surround40 */
 271         [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
 272         /* 4ch */
 273         [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
 274         /* surround41 */
 275         [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
 276         /* surround50 */
 277         [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
 278         /* surround51 */
 279         [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
 280         /* 7.1 */
 281         [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
 282 };
 283
 284 /*
 285  * This is an ordered list!
 286  *
 287  * The preceding ones have better chances to be selected by
 288  * hdmi_channel_allocation().
 289  */
 290 static struct cea_channel_speaker_allocation channel_allocations[] = {
 291 /*                        channel:   7     6    5    4    3     2    1    0  */
 292 { .ca_index = 0x00,  .speakers = {   0,    0,   0,   0,   0,    0,  FR,  FL } },
 293                                  /* 2.1 */
 294 { .ca_index = 0x01,  .speakers = {   0,    0,   0,   0,   0,  LFE,  FR,  FL } },
 295                                  /* Dolby Surround */
 296 { .ca_index = 0x02,  .speakers = {   0,    0,   0,   0,  FC,    0,  FR,  FL } },
 297                                  /* surround40 */
 298 { .ca_index = 0x08,  .speakers = {   0,    0,  RR,  RL,   0,    0,  FR,  FL } },
 299                                  /* surround41 */
 300 { .ca_index = 0x09,  .speakers = {   0,    0,  RR,  RL,   0,  LFE,  FR,  FL } },
 301                                  /* surround50 */
 302 { .ca_index = 0x0a,  .speakers = {   0,    0,  RR,  RL,  FC,    0,  FR,  FL } },
 303                                  /* surround51 */
 304 { .ca_index = 0x0b,  .speakers = {   0,    0,  RR,  RL,  FC,  LFE,  FR,  FL } },
 305                                  /* 6.1 */
 306 { .ca_index = 0x0f,  .speakers = {   0,   RC,  RR,  RL,  FC,  LFE,  FR,  FL } },
 307                                  /* surround71 */
 308 { .ca_index = 0x13,  .speakers = { RRC,  RLC,  RR,  RL,  FC,  LFE,  FR,  FL } },
 309
 310 { .ca_index = 0x03,  .speakers = {   0,    0,   0,   0,  FC,  LFE,  FR,  FL } },
 311 { .ca_index = 0x04,  .speakers = {   0,    0,   0,  RC,   0,    0,  FR,  FL } },
 312 { .ca_index = 0x05,  .speakers = {   0,    0,   0,  RC,   0,  LFE,  FR,  FL } },
 313 { .ca_index = 0x06,  .speakers = {   0,    0,   0,  RC,  FC,    0,  FR,  FL } },
 314 { .ca_index = 0x07,  .speakers = {   0,    0,   0,  RC,  FC,  LFE,  FR,  FL } },
 315 { .ca_index = 0x0c,  .speakers = {   0,   RC,  RR,  RL,   0,    0,  FR,  FL } },
 316 { .ca_index = 0x0d,  .speakers = {   0,   RC,  RR,  RL,   0,  LFE,  FR,  FL } },
 317 { .ca_index = 0x0e,  .speakers = {   0,   RC,  RR,  RL,  FC,    0,  FR,  FL } },
 318 { .ca_index = 0x10,  .speakers = { RRC,  RLC,  RR,  RL,   0,    0,  FR,  FL } },
 319 { .ca_index = 0x11,  .speakers = { RRC,  RLC,  RR,  RL,   0,  LFE,  FR,  FL } },
 320 { .ca_index = 0x12,  .speakers = { RRC,  RLC,  RR,  RL,  FC,    0,  FR,  FL } },
 321 { .ca_index = 0x14,  .speakers = { FRC,  FLC,   0,   0,   0,    0,  FR,  FL } },
 322 { .ca_index = 0x15,  .speakers = { FRC,  FLC,   0,   0,   0,  LFE,  FR,  FL } },
 323 { .ca_index = 0x16,  .speakers = { FRC,  FLC,   0,   0,  FC,    0,  FR,  FL } },
 324 { .ca_index = 0x17,  .speakers = { FRC,  FLC,   0,   0,  FC,  LFE,  FR,  FL } },
 325 { .ca_index = 0x18,  .speakers = { FRC,  FLC,   0,  RC,   0,    0,  FR,  FL } },
 326 { .ca_index = 0x19,  .speakers = { FRC,  FLC,   0,  RC,   0,  LFE,  FR,  FL } },
 327 { .ca_index = 0x1a,  .speakers = { FRC,  FLC,   0,  RC,  FC,    0,  FR,  FL } },
 328 { .ca_index = 0x1b,  .speakers = { FRC,  FLC,   0,  RC,  FC,  LFE,  FR,  FL } },
 329 { .ca_index = 0x1c,  .speakers = { FRC,  FLC,  RR,  RL,   0,    0,  FR,  FL } },
 330 { .ca_index = 0x1d,  .speakers = { FRC,  FLC,  RR,  RL,   0,  LFE,  FR,  FL } },
 331 { .ca_index = 0x1e,  .speakers = { FRC,  FLC,  RR,  RL,  FC,    0,  FR,  FL } },
 332 { .ca_index = 0x1f,  .speakers = { FRC,  FLC,  RR,  RL,  FC,  LFE,  FR,  FL } },
 333 { .ca_index = 0x20,  .speakers = {   0,  FCH,  RR,  RL,  FC,    0,  FR,  FL } },
 334 { .ca_index = 0x21,  .speakers = {   0,  FCH,  RR,  RL,  FC,  LFE,  FR,  FL } },
 335 { .ca_index = 0x22,  .speakers = {  TC,    0,  RR,  RL,  FC,    0,  FR,  FL } },
 336 { .ca_index = 0x23,  .speakers = {  TC,    0,  RR,  RL,  FC,  LFE,  FR,  FL } },
 337 { .ca_index = 0x24,  .speakers = { FRH,  FLH,  RR,  RL,   0,    0,  FR,  FL } },
 338 { .ca_index = 0x25,  .speakers = { FRH,  FLH,  RR,  RL,   0,  LFE,  FR,  FL } },
 339 { .ca_index = 0x26,  .speakers = { FRW,  FLW,  RR,  RL,   0,    0,  FR,  FL } },
 340 { .ca_index = 0x27,  .speakers = { FRW,  FLW,  RR,  RL,   0,  LFE,  FR,  FL } },
 341 { .ca_index = 0x28,  .speakers = {  TC,   RC,  RR,  RL,  FC,    0,  FR,  FL } },
 342 { .ca_index = 0x29,  .speakers = {  TC,   RC,  RR,  RL,  FC,  LFE,  FR,  FL } },
 343 { .ca_index = 0x2a,  .speakers = { FCH,   RC,  RR,  RL,  FC,    0,  FR,  FL } },
 344 { .ca_index = 0x2b,  .speakers = { FCH,   RC,  RR,  RL,  FC,  LFE,  FR,  FL } },
 345 { .ca_index = 0x2c,  .speakers = {  TC,  FCH,  RR,  RL,  FC,    0,  FR,  FL } },
 346 { .ca_index = 0x2d,  .speakers = {  TC,  FCH,  RR,  RL,  FC,  LFE,  FR,  FL } },
 347 { .ca_index = 0x2e,  .speakers = { FRH,  FLH,  RR,  RL,  FC,    0,  FR,  FL } },
 348 { .ca_index = 0x2f,  .speakers = { FRH,  FLH,  RR,  RL,  FC,  LFE,  FR,  FL } },
 349 { .ca_index = 0x30,  .speakers = { FRW,  FLW,  RR,  RL,  FC,    0,  FR,  FL } },
 350 { .ca_index = 0x31,  .speakers = { FRW,  FLW,  RR,  RL,  FC,  LFE,  FR,  FL } },
 351 };
 352
 353
 354 /*
 355  * HDMI routines
 356  */
 357
 358 #define get_pin(spec, idx) \
 359         ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
 360 #define get_cvt(spec, idx) \
 361         ((struct hdmi_spec_per_cvt  *)snd_array_elem(&spec->cvts, idx))
 362 #define get_pcm_rec(spec, idx)  ((spec)->pcm_rec[idx])
 363
 364 static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid)
 365 {
 366         struct hdmi_spec *spec = codec->spec;
 367         int pin_idx;
 368
 369         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
 370                 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
 371                         return pin_idx;
 372
 373         codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
 374         return -EINVAL;
 375 }
 376
 377 static int hinfo_to_pin_index(struct hda_codec *codec,
 378                               struct hda_pcm_stream *hinfo)
 379 {
 380         struct hdmi_spec *spec = codec->spec;
 381         int pin_idx;
 382
 383         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
 384                 if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
 385                         return pin_idx;
 386
 387         codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
 388         return -EINVAL;
 389 }
 390
 391 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
 392 {
 393         struct hdmi_spec *spec = codec->spec;
 394         int cvt_idx;
 395
 396         for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
 397                 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
 398                         return cvt_idx;
 399
 400         codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
 401         return -EINVAL;
 402 }
 403
 404 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
 405                         struct snd_ctl_elem_info *uinfo)
 406 {
 407         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
 408         struct hdmi_spec *spec = codec->spec;
 409         struct hdmi_spec_per_pin *per_pin;
 410         struct hdmi_eld *eld;
 411         int pin_idx;
 412
 413         uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
 414
 415         pin_idx = kcontrol->private_value;
 416         per_pin = get_pin(spec, pin_idx);
 417         eld = &per_pin->sink_eld;
 418
 419         mutex_lock(&per_pin->lock);
 420         uinfo->count = eld->eld_valid ? eld->eld_size : 0;
 421         mutex_unlock(&per_pin->lock);
 422
 423         return 0;
 424 }
 425
 426 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
 427                         struct snd_ctl_elem_value *ucontrol)
 428 {
 429         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
 430         struct hdmi_spec *spec = codec->spec;
 431         struct hdmi_spec_per_pin *per_pin;
 432         struct hdmi_eld *eld;
 433         int pin_idx;
 434
 435         pin_idx = kcontrol->private_value;
 436         per_pin = get_pin(spec, pin_idx);
 437         eld = &per_pin->sink_eld;
 438
 439         mutex_lock(&per_pin->lock);
 440         if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) {
 441                 mutex_unlock(&per_pin->lock);
 442                 snd_BUG();
 443                 return -EINVAL;
 444         }
 445
 446         memset(ucontrol->value.bytes.data, 0,
 447                ARRAY_SIZE(ucontrol->value.bytes.data));
 448         if (eld->eld_valid)
 449                 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
 450                        eld->eld_size);
 451         mutex_unlock(&per_pin->lock);
 452
 453         return 0;
 454 }
 455
 456 static struct snd_kcontrol_new eld_bytes_ctl = {
 457         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
 458         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
 459         .name = "ELD",
 460         .info = hdmi_eld_ctl_info,
 461         .get = hdmi_eld_ctl_get,
 462 };
 463
 464 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
 465                         int device)
 466 {
 467         struct snd_kcontrol *kctl;
 468         struct hdmi_spec *spec = codec->spec;
 469         int err;
 470
 471         kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
 472         if (!kctl)
 473                 return -ENOMEM;
 474         kctl->private_value = pin_idx;
 475         kctl->id.device = device;
 476
 477         err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
 478         if (err < 0)
 479                 return err;
 480
 481         get_pin(spec, pin_idx)->eld_ctl = kctl;
 482         return 0;
 483 }
 484
 485 #ifdef BE_PARANOID
 486 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
 487                                 int *packet_index, int *byte_index)
 488 {
 489         int val;
 490
 491         val = snd_hda_codec_read(codec, pin_nid, 0,
 492                                  AC_VERB_GET_HDMI_DIP_INDEX, 0);
 493
 494         *packet_index = val >> 5;
 495         *byte_index = val & 0x1f;
 496 }
 497 #endif
 498
 499 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
 500                                 int packet_index, int byte_index)
 501 {
 502         int val;
 503
 504         val = (packet_index << 5) | (byte_index & 0x1f);
 505
 506         snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
 507 }
 508
 509 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
 510                                 unsigned char val)
 511 {
 512         snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
 513 }
 514
 515 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
 516 {
 517         struct hdmi_spec *spec = codec->spec;
 518         int pin_out;
 519
 520         /* Unmute */
 521         if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
 522                 snd_hda_codec_write(codec, pin_nid, 0,
 523                                 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
 524
 525         if (spec->dyn_pin_out)
 526                 /* Disable pin out until stream is active */
 527                 pin_out = 0;
 528         else
 529                 /* Enable pin out: some machines with GM965 gets broken output
 530                  * when the pin is disabled or changed while using with HDMI
 531                  */
 532                 pin_out = PIN_OUT;
 533
 534         snd_hda_codec_write(codec, pin_nid, 0,
 535                             AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
 536 }
 537
 538 static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
 539 {
 540         return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
 541                                         AC_VERB_GET_CVT_CHAN_COUNT, 0);
 542 }
 543
 544 static void hdmi_set_channel_count(struct hda_codec *codec,
 545                                    hda_nid_t cvt_nid, int chs)
 546 {
 547         if (chs != hdmi_get_channel_count(codec, cvt_nid))
 548                 snd_hda_codec_write(codec, cvt_nid, 0,
 549                                     AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
 550 }
 551
 552 /*
 553  * ELD proc files
 554  */
 555
 556 #ifdef CONFIG_SND_PROC_FS
 557 static void print_eld_info(struct snd_info_entry *entry,
 558                            struct snd_info_buffer *buffer)
 559 {
 560         struct hdmi_spec_per_pin *per_pin = entry->private_data;
 561
 562         mutex_lock(&per_pin->lock);
 563         snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
 564         mutex_unlock(&per_pin->lock);
 565 }
 566
 567 static void write_eld_info(struct snd_info_entry *entry,
 568                            struct snd_info_buffer *buffer)
 569 {
 570         struct hdmi_spec_per_pin *per_pin = entry->private_data;
 571
 572         mutex_lock(&per_pin->lock);
 573         snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
 574         mutex_unlock(&per_pin->lock);
 575 }
 576
 577 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
 578 {
 579         char name[32];
 580         struct hda_codec *codec = per_pin->codec;
 581         struct snd_info_entry *entry;
 582         int err;
 583
 584         snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
 585         err = snd_card_proc_new(codec->card, name, &entry);
 586         if (err < 0)
 587                 return err;
 588
 589         snd_info_set_text_ops(entry, per_pin, print_eld_info);
 590         entry->c.text.write = write_eld_info;
 591         entry->mode |= S_IWUSR;
 592         per_pin->proc_entry = entry;
 593
 594         return 0;
 595 }
 596
 597 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
 598 {
 599         if (!per_pin->codec->bus->shutdown) {
 600                 snd_info_free_entry(per_pin->proc_entry);
 601                 per_pin->proc_entry = NULL;
 602         }
 603 }
 604 #else
 605 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
 606                                int index)
 607 {
 608         return 0;
 609 }
 610 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
 611 {
 612 }
 613 #endif
 614
 615 /*
 616  * Channel mapping routines
 617  */
 618
 619 /*
 620  * Compute derived values in channel_allocations[].
 621  */
 622 static void init_channel_allocations(void)
 623 {
 624         int i, j;
 625         struct cea_channel_speaker_allocation *p;
 626
 627         for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
 628                 p = channel_allocations + i;
 629                 p->channels = 0;
 630                 p->spk_mask = 0;
 631                 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
 632                         if (p->speakers[j]) {
 633                                 p->channels++;
 634                                 p->spk_mask |= p->speakers[j];
 635                         }
 636         }
 637 }
 638
 639 static int get_channel_allocation_order(int ca)
 640 {
 641         int i;
 642
 643         for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
 644                 if (channel_allocations[i].ca_index == ca)
 645                         break;
 646         }
 647         return i;
 648 }
 649
 650 /*
 651  * The transformation takes two steps:
 652  *
 653  *      eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
 654  *            spk_mask => (channel_allocations[])         => ai->CA
 655  *
 656  * TODO: it could select the wrong CA from multiple candidates.
 657 */
 658 static int hdmi_channel_allocation(struct hda_codec *codec,
 659                                    struct hdmi_eld *eld, int channels)
 660 {
 661         int i;
 662         int ca = 0;
 663         int spk_mask = 0;
 664         char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
 665
 666         /*
 667          * CA defaults to 0 for basic stereo audio
 668          */
 669         if (channels <= 2)
 670                 return 0;
 671
 672         /*
 673          * expand ELD's speaker allocation mask
 674          *
 675          * ELD tells the speaker mask in a compact(paired) form,
 676          * expand ELD's notions to match the ones used by Audio InfoFrame.
 677          */
 678         for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
 679                 if (eld->info.spk_alloc & (1 << i))
 680                         spk_mask |= eld_speaker_allocation_bits[i];
 681         }
 682
 683         /* search for the first working match in the CA table */
 684         for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
 685                 if (channels == channel_allocations[i].channels &&
 686                     (spk_mask & channel_allocations[i].spk_mask) ==
 687                                 channel_allocations[i].spk_mask) {
 688                         ca = channel_allocations[i].ca_index;
 689                         break;
 690                 }
 691         }
 692
 693         if (!ca) {
 694                 /* if there was no match, select the regular ALSA channel
 695                  * allocation with the matching number of channels */
 696                 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
 697                         if (channels == channel_allocations[i].channels) {
 698                                 ca = channel_allocations[i].ca_index;
 699                                 break;
 700                         }
 701                 }
 702         }
 703
 704         snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
 705         codec_dbg(codec, "HDMI: select CA 0x%x for %d-channel allocation: %s\n",
 706                     ca, channels, buf);
 707
 708         return ca;
 709 }
 710
 711 static void hdmi_debug_channel_mapping(struct hda_codec *codec,
 712                                        hda_nid_t pin_nid)
 713 {
 714 #ifdef CONFIG_SND_DEBUG_VERBOSE
 715         struct hdmi_spec *spec = codec->spec;
 716         int i;
 717         int channel;
 718
 719         for (i = 0; i < 8; i++) {
 720                 channel = spec->ops.pin_get_slot_channel(codec, pin_nid, i);
 721                 codec_dbg(codec, "HDMI: ASP channel %d => slot %d\n",
 722                                                 channel, i);
 723         }
 724 #endif
 725 }
 726
 727 static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
 728                                        hda_nid_t pin_nid,
 729                                        bool non_pcm,
 730                                        int ca)
 731 {
 732         struct hdmi_spec *spec = codec->spec;
 733         struct cea_channel_speaker_allocation *ch_alloc;
 734         int i;
 735         int err;
 736         int order;
 737         int non_pcm_mapping[8];
 738
 739         order = get_channel_allocation_order(ca);
 740         ch_alloc = &channel_allocations[order];
 741
 742         if (hdmi_channel_mapping[ca][1] == 0) {
 743                 int hdmi_slot = 0;
 744                 /* fill actual channel mappings in ALSA channel (i) order */
 745                 for (i = 0; i < ch_alloc->channels; i++) {
 746                         while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
 747                                 hdmi_slot++; /* skip zero slots */
 748
 749                         hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
 750                 }
 751                 /* fill the rest of the slots with ALSA channel 0xf */
 752                 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
 753                         if (!ch_alloc->speakers[7 - hdmi_slot])
 754                                 hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
 755         }
 756
 757         if (non_pcm) {
 758                 for (i = 0; i < ch_alloc->channels; i++)
 759                         non_pcm_mapping[i] = (i << 4) | i;
 760                 for (; i < 8; i++)
 761                         non_pcm_mapping[i] = (0xf << 4) | i;
 762         }
 763
 764         for (i = 0; i < 8; i++) {
 765                 int slotsetup = non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i];
 766                 int hdmi_slot = slotsetup & 0x0f;
 767                 int channel = (slotsetup & 0xf0) >> 4;
 768                 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, channel);
 769                 if (err) {
 770                         codec_dbg(codec, "HDMI: channel mapping failed\n");
 771                         break;
 772                 }
 773         }
 774 }
 775
 776 struct channel_map_table {
 777         unsigned char map;              /* ALSA API channel map position */
 778         int spk_mask;                   /* speaker position bit mask */
 779 };
 780
 781 static struct channel_map_table map_tables[] = {
 782         { SNDRV_CHMAP_FL,       FL },
 783         { SNDRV_CHMAP_FR,       FR },
 784         { SNDRV_CHMAP_RL,       RL },
 785         { SNDRV_CHMAP_RR,       RR },
 786         { SNDRV_CHMAP_LFE,      LFE },
 787         { SNDRV_CHMAP_FC,       FC },
 788         { SNDRV_CHMAP_RLC,      RLC },
 789         { SNDRV_CHMAP_RRC,      RRC },
 790         { SNDRV_CHMAP_RC,       RC },
 791         { SNDRV_CHMAP_FLC,      FLC },
 792         { SNDRV_CHMAP_FRC,      FRC },
 793         { SNDRV_CHMAP_TFL,      FLH },
 794         { SNDRV_CHMAP_TFR,      FRH },
 795         { SNDRV_CHMAP_FLW,      FLW },
 796         { SNDRV_CHMAP_FRW,      FRW },
 797         { SNDRV_CHMAP_TC,       TC },
 798         { SNDRV_CHMAP_TFC,      FCH },
 799         {} /* terminator */
 800 };
 801
 802 /* from ALSA API channel position to speaker bit mask */
 803 static int to_spk_mask(unsigned char c)
 804 {
 805         struct channel_map_table *t = map_tables;
 806         for (; t->map; t++) {
 807                 if (t->map == c)
 808                         return t->spk_mask;
 809         }
 810         return 0;
 811 }
 812
 813 /* from ALSA API channel position to CEA slot */
 814 static int to_cea_slot(int ordered_ca, unsigned char pos)
 815 {
 816         int mask = to_spk_mask(pos);
 817         int i;
 818
 819         if (mask) {
 820                 for (i = 0; i < 8; i++) {
 821                         if (channel_allocations[ordered_ca].speakers[7 - i] == mask)
 822                                 return i;
 823                 }
 824         }
 825
 826         return -1;
 827 }
 828
 829 /* from speaker bit mask to ALSA API channel position */
 830 static int spk_to_chmap(int spk)
 831 {
 832         struct channel_map_table *t = map_tables;
 833         for (; t->map; t++) {
 834                 if (t->spk_mask == spk)
 835                         return t->map;
 836         }
 837         return 0;
 838 }
 839
 840 /* from CEA slot to ALSA API channel position */
 841 static int from_cea_slot(int ordered_ca, unsigned char slot)
 842 {
 843         int mask = channel_allocations[ordered_ca].speakers[7 - slot];
 844
 845         return spk_to_chmap(mask);
 846 }
 847
 848 /* get the CA index corresponding to the given ALSA API channel map */
 849 static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
 850 {
 851         int i, spks = 0, spk_mask = 0;
 852
 853         for (i = 0; i < chs; i++) {
 854                 int mask = to_spk_mask(map[i]);
 855                 if (mask) {
 856                         spk_mask |= mask;
 857                         spks++;
 858                 }
 859         }
 860
 861         for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
 862                 if ((chs == channel_allocations[i].channels ||
 863                      spks == channel_allocations[i].channels) &&
 864                     (spk_mask & channel_allocations[i].spk_mask) ==
 865                                 channel_allocations[i].spk_mask)
 866                         return channel_allocations[i].ca_index;
 867         }
 868         return -1;
 869 }
 870
 871 /* set up the channel slots for the given ALSA API channel map */
 872 static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
 873                                              hda_nid_t pin_nid,
 874                                              int chs, unsigned char *map,
 875                                              int ca)
 876 {
 877         struct hdmi_spec *spec = codec->spec;
 878         int ordered_ca = get_channel_allocation_order(ca);
 879         int alsa_pos, hdmi_slot;
 880         int assignments[8] = {[0 ... 7] = 0xf};
 881
 882         for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) {
 883
 884                 hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]);
 885
 886                 if (hdmi_slot < 0)
 887                         continue; /* unassigned channel */
 888
 889                 assignments[hdmi_slot] = alsa_pos;
 890         }
 891
 892         for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) {
 893                 int err;
 894
 895                 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot,
 896                                                      assignments[hdmi_slot]);
 897                 if (err)
 898                         return -EINVAL;
 899         }
 900         return 0;
 901 }
 902
 903 /* store ALSA API channel map from the current default map */
 904 static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
 905 {
 906         int i;
 907         int ordered_ca = get_channel_allocation_order(ca);
 908         for (i = 0; i < 8; i++) {
 909                 if (i < channel_allocations[ordered_ca].channels)
 910                         map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f);
 911                 else
 912                         map[i] = 0;
 913         }
 914 }
 915
 916 static void hdmi_setup_channel_mapping(struct hda_codec *codec,
 917                                        hda_nid_t pin_nid, bool non_pcm, int ca,
 918                                        int channels, unsigned char *map,
 919                                        bool chmap_set)
 920 {
 921         if (!non_pcm && chmap_set) {
 922                 hdmi_manual_setup_channel_mapping(codec, pin_nid,
 923                                                   channels, map, ca);
 924         } else {
 925                 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
 926                 hdmi_setup_fake_chmap(map, ca);
 927         }
 928
 929         hdmi_debug_channel_mapping(codec, pin_nid);
 930 }
 931
 932 static int hdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
 933                                      int asp_slot, int channel)
 934 {
 935         return snd_hda_codec_write(codec, pin_nid, 0,
 936                                    AC_VERB_SET_HDMI_CHAN_SLOT,
 937                                    (channel << 4) | asp_slot);
 938 }
 939
 940 static int hdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
 941                                      int asp_slot)
 942 {
 943         return (snd_hda_codec_read(codec, pin_nid, 0,
 944                                    AC_VERB_GET_HDMI_CHAN_SLOT,
 945                                    asp_slot) & 0xf0) >> 4;
 946 }
 947
 948 /*
 949  * Audio InfoFrame routines
 950  */
 951
 952 /*
 953  * Enable Audio InfoFrame Transmission
 954  */
 955 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
 956                                        hda_nid_t pin_nid)
 957 {
 958         hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
 959         snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
 960                                                 AC_DIPXMIT_BEST);
 961 }
 962
 963 /*
 964  * Disable Audio InfoFrame Transmission
 965  */
 966 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
 967                                       hda_nid_t pin_nid)
 968 {
 969         hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
 970         snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
 971                                                 AC_DIPXMIT_DISABLE);
 972 }
 973
 974 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
 975 {
 976 #ifdef CONFIG_SND_DEBUG_VERBOSE
 977         int i;
 978         int size;
 979
 980         size = snd_hdmi_get_eld_size(codec, pin_nid);
 981         codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
 982
 983         for (i = 0; i < 8; i++) {
 984                 size = snd_hda_codec_read(codec, pin_nid, 0,
 985                                                 AC_VERB_GET_HDMI_DIP_SIZE, i);
 986                 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
 987         }
 988 #endif
 989 }
 990
 991 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
 992 {
 993 #ifdef BE_PARANOID
 994         int i, j;
 995         int size;
 996         int pi, bi;
 997         for (i = 0; i < 8; i++) {
 998                 size = snd_hda_codec_read(codec, pin_nid, 0,
 999                                                 AC_VERB_GET_HDMI_DIP_SIZE, i);
1000                 if (size == 0)
1001                         continue;
1002
1003                 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
1004                 for (j = 1; j < 1000; j++) {
1005                         hdmi_write_dip_byte(codec, pin_nid, 0x0);
1006                         hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
1007                         if (pi != i)
1008                                 codec_dbg(codec, "dip index %d: %d != %d\n",
1009                                                 bi, pi, i);
1010                         if (bi == 0) /* byte index wrapped around */
1011                                 break;
1012                 }
1013                 codec_dbg(codec,
1014                         "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
1015                         i, size, j);
1016         }
1017 #endif
1018 }
1019
1020 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
1021 {
1022         u8 *bytes = (u8 *)hdmi_ai;
1023         u8 sum = 0;
1024         int i;
1025
1026         hdmi_ai->checksum = 0;
1027
1028         for (i = 0; i < sizeof(*hdmi_ai); i++)
1029                 sum += bytes[i];
1030
1031         hdmi_ai->checksum = -sum;
1032 }
1033
1034 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
1035                                       hda_nid_t pin_nid,
1036                                       u8 *dip, int size)
1037 {
1038         int i;
1039
1040         hdmi_debug_dip_size(codec, pin_nid);
1041         hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
1042
1043         hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
1044         for (i = 0; i < size; i++)
1045                 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
1046 }
1047
1048 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
1049                                     u8 *dip, int size)
1050 {
1051         u8 val;
1052         int i;
1053
1054         if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
1055                                                             != AC_DIPXMIT_BEST)
1056                 return false;
1057
1058         hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
1059         for (i = 0; i < size; i++) {
1060                 val = snd_hda_codec_read(codec, pin_nid, 0,
1061                                          AC_VERB_GET_HDMI_DIP_DATA, 0);
1062                 if (val != dip[i])
1063                         return false;
1064         }
1065
1066         return true;
1067 }
1068
1069 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
1070                                      hda_nid_t pin_nid,
1071                                      int ca, int active_channels,
1072                                      int conn_type)
1073 {
1074         union audio_infoframe ai;
1075
1076         memset(&ai, 0, sizeof(ai));
1077         if (conn_type == 0) { /* HDMI */
1078                 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
1079
1080                 hdmi_ai->type           = 0x84;
1081                 hdmi_ai->ver            = 0x01;
1082                 hdmi_ai->len            = 0x0a;
1083                 hdmi_ai->CC02_CT47      = active_channels - 1;
1084                 hdmi_ai->CA             = ca;
1085                 hdmi_checksum_audio_infoframe(hdmi_ai);
1086         } else if (conn_type == 1) { /* DisplayPort */
1087                 struct dp_audio_infoframe *dp_ai = &ai.dp;
1088
1089                 dp_ai->type             = 0x84;
1090                 dp_ai->len              = 0x1b;
1091                 dp_ai->ver              = 0x11 << 2;
1092                 dp_ai->CC02_CT47        = active_channels - 1;
1093                 dp_ai->CA               = ca;
1094         } else {
1095                 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
1096                             pin_nid);
1097                 return;
1098         }
1099
1100         /*
1101          * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
1102          * sizeof(*dp_ai) to avoid partial match/update problems when
1103          * the user switches between HDMI/DP monitors.
1104          */
1105         if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
1106                                         sizeof(ai))) {
1107                 codec_dbg(codec,
1108                           "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
1109                             pin_nid,
1110                             active_channels, ca);
1111                 hdmi_stop_infoframe_trans(codec, pin_nid);
1112                 hdmi_fill_audio_infoframe(codec, pin_nid,
1113                                             ai.bytes, sizeof(ai));
1114                 hdmi_start_infoframe_trans(codec, pin_nid);
1115         }
1116 }
1117
1118 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
1119                                        struct hdmi_spec_per_pin *per_pin,
1120                                        bool non_pcm)
1121 {
1122         struct hdmi_spec *spec = codec->spec;
1123         hda_nid_t pin_nid = per_pin->pin_nid;
1124         int channels = per_pin->channels;
1125         int active_channels;
1126         struct hdmi_eld *eld;
1127         int ca, ordered_ca;
1128
1129         if (!channels)
1130                 return;
1131
1132         if (is_haswell_plus(codec))
1133                 snd_hda_codec_write(codec, pin_nid, 0,
1134                                             AC_VERB_SET_AMP_GAIN_MUTE,
1135                                             AMP_OUT_UNMUTE);
1136
1137         eld = &per_pin->sink_eld;
1138
1139         if (!non_pcm && per_pin->chmap_set)
1140                 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
1141         else
1142                 ca = hdmi_channel_allocation(codec, eld, channels);
1143         if (ca < 0)
1144                 ca = 0;
1145
1146         ordered_ca = get_channel_allocation_order(ca);
1147         active_channels = channel_allocations[ordered_ca].channels;
1148
1149         hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels);
1150
1151         /*
1152          * always configure channel mapping, it may have been changed by the
1153          * user in the meantime
1154          */
1155         hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
1156                                    channels, per_pin->chmap,
1157                                    per_pin->chmap_set);
1158
1159         spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
1160                                       eld->info.conn_type);
1161
1162         per_pin->non_pcm = non_pcm;
1163 }
1164
1165 /*
1166  * Unsolicited events
1167  */
1168
1169 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
1170
1171 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid)
1172 {
1173         struct hdmi_spec *spec = codec->spec;
1174         int pin_idx = pin_nid_to_pin_index(codec, nid);
1175
1176         if (pin_idx < 0)
1177                 return;
1178         if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
1179                 snd_hda_jack_report_sync(codec);
1180 }
1181
1182 static void jack_callback(struct hda_codec *codec,
1183                           struct hda_jack_callback *jack)
1184 {
1185         check_presence_and_report(codec, jack->tbl->nid);
1186 }
1187
1188 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
1189 {
1190         int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1191         struct hda_jack_tbl *jack;
1192         int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
1193
1194         jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
1195         if (!jack)
1196                 return;
1197         jack->jack_dirty = 1;
1198
1199         codec_dbg(codec,
1200                 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
1201                 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
1202                 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
1203
1204         check_presence_and_report(codec, jack->nid);
1205 }
1206
1207 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
1208 {
1209         int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1210         int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1211         int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
1212         int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
1213
1214         codec_info(codec,
1215                 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
1216                 codec->addr,
1217                 tag,
1218                 subtag,
1219                 cp_state,
1220                 cp_ready);
1221
1222         /* TODO */
1223         if (cp_state)
1224                 ;
1225         if (cp_ready)
1226                 ;
1227 }
1228
1229
1230 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1231 {
1232         int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1233         int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1234
1235         if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
1236                 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
1237                 return;
1238         }
1239
1240         if (subtag == 0)
1241                 hdmi_intrinsic_event(codec, res);
1242         else
1243                 hdmi_non_intrinsic_event(codec, res);
1244 }
1245
1246 static void haswell_verify_D0(struct hda_codec *codec,
1247                 hda_nid_t cvt_nid, hda_nid_t nid)
1248 {
1249         int pwr;
1250
1251         /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1252          * thus pins could only choose converter 0 for use. Make sure the
1253          * converters are in correct power state */
1254         if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
1255                 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1256
1257         if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
1258                 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1259                                     AC_PWRST_D0);
1260                 msleep(40);
1261                 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1262                 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
1263                 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
1264         }
1265 }
1266
1267 /*
1268  * Callbacks
1269  */
1270
1271 /* HBR should be Non-PCM, 8 channels */
1272 #define is_hbr_format(format) \
1273         ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1274
1275 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
1276                               bool hbr)
1277 {
1278         int pinctl, new_pinctl;
1279
1280         if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1281                 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1282                                             AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1283
1284                 if (pinctl < 0)
1285                         return hbr ? -EINVAL : 0;
1286
1287                 new_pinctl = pinctl & ~AC_PINCTL_EPT;
1288                 if (hbr)
1289                         new_pinctl |= AC_PINCTL_EPT_HBR;
1290                 else
1291                         new_pinctl |= AC_PINCTL_EPT_NATIVE;
1292
1293                 codec_dbg(codec,
1294                           "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
1295                             pin_nid,
1296                             pinctl == new_pinctl ? "" : "new-",
1297                             new_pinctl);
1298
1299                 if (pinctl != new_pinctl)
1300                         snd_hda_codec_write(codec, pin_nid, 0,
1301                                             AC_VERB_SET_PIN_WIDGET_CONTROL,
1302                                             new_pinctl);
1303         } else if (hbr)
1304                 return -EINVAL;
1305
1306         return 0;
1307 }
1308
1309 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1310                               hda_nid_t pin_nid, u32 stream_tag, int format)
1311 {
1312         struct hdmi_spec *spec = codec->spec;
1313         int err;
1314
1315         if (is_haswell_plus(codec))
1316                 haswell_verify_D0(codec, cvt_nid, pin_nid);
1317
1318         err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
1319
1320         if (err) {
1321                 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
1322                 return err;
1323         }
1324
1325         snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
1326         return 0;
1327 }
1328
1329 static int hdmi_choose_cvt(struct hda_codec *codec,
1330                         int pin_idx, int *cvt_id, int *mux_id)
1331 {
1332         struct hdmi_spec *spec = codec->spec;
1333         struct hdmi_spec_per_pin *per_pin;
1334         struct hdmi_spec_per_cvt *per_cvt = NULL;
1335         int cvt_idx, mux_idx = 0;
1336
1337         per_pin = get_pin(spec, pin_idx);
1338
1339         /* Dynamically assign converter to stream */
1340         for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1341                 per_cvt = get_cvt(spec, cvt_idx);
1342
1343                 /* Must not already be assigned */
1344                 if (per_cvt->assigned)
1345                         continue;
1346                 /* Must be in pin's mux's list of converters */
1347                 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1348                         if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1349                                 break;
1350                 /* Not in mux list */
1351                 if (mux_idx == per_pin->num_mux_nids)
1352                         continue;
1353                 break;
1354         }
1355
1356         /* No free converters */
1357         if (cvt_idx == spec->num_cvts)
1358                 return -ENODEV;
1359
1360         per_pin->mux_idx = mux_idx;
1361
1362         if (cvt_id)
1363                 *cvt_id = cvt_idx;
1364         if (mux_id)
1365                 *mux_id = mux_idx;
1366
1367         return 0;
1368 }
1369
1370 /* Assure the pin select the right convetor */
1371 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1372                         struct hdmi_spec_per_pin *per_pin)
1373 {
1374         hda_nid_t pin_nid = per_pin->pin_nid;
1375         int mux_idx, curr;
1376
1377         mux_idx = per_pin->mux_idx;
1378         curr = snd_hda_codec_read(codec, pin_nid, 0,
1379                                           AC_VERB_GET_CONNECT_SEL, 0);
1380         if (curr != mux_idx)
1381                 snd_hda_codec_write_cache(codec, pin_nid, 0,
1382                                             AC_VERB_SET_CONNECT_SEL,
1383                                             mux_idx);
1384 }
1385
1386 /* Intel HDMI workaround to fix audio routing issue:
1387  * For some Intel display codecs, pins share the same connection list.
1388  * So a conveter can be selected by multiple pins and playback on any of these
1389  * pins will generate sound on the external display, because audio flows from
1390  * the same converter to the display pipeline. Also muting one pin may make
1391  * other pins have no sound output.
1392  * So this function assures that an assigned converter for a pin is not selected
1393  * by any other pins.
1394  */
1395 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1396                         hda_nid_t pin_nid, int mux_idx)
1397 {
1398         struct hdmi_spec *spec = codec->spec;
1399         hda_nid_t nid;
1400         int cvt_idx, curr;
1401         struct hdmi_spec_per_cvt *per_cvt;
1402
1403         /* configure all pins, including "no physical connection" ones */
1404         for_each_hda_codec_node(nid, codec) {
1405                 unsigned int wid_caps = get_wcaps(codec, nid);
1406                 unsigned int wid_type = get_wcaps_type(wid_caps);
1407
1408                 if (wid_type != AC_WID_PIN)
1409                         continue;
1410
1411                 if (nid == pin_nid)
1412                         continue;
1413
1414                 curr = snd_hda_codec_read(codec, nid, 0,
1415                                           AC_VERB_GET_CONNECT_SEL, 0);
1416                 if (curr != mux_idx)
1417                         continue;
1418
1419                 /* choose an unassigned converter. The conveters in the
1420                  * connection list are in the same order as in the codec.
1421                  */
1422                 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1423                         per_cvt = get_cvt(spec, cvt_idx);
1424                         if (!per_cvt->assigned) {
1425                                 codec_dbg(codec,
1426                                           "choose cvt %d for pin nid %d\n",
1427                                         cvt_idx, nid);
1428                                 snd_hda_codec_write_cache(codec, nid, 0,
1429                                             AC_VERB_SET_CONNECT_SEL,
1430                                             cvt_idx);
1431                                 break;
1432                         }
1433                 }
1434         }
1435 }
1436
1437 /*
1438  * HDA PCM callbacks
1439  */
1440 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1441                          struct hda_codec *codec,
1442                          struct snd_pcm_substream *substream)
1443 {
1444         struct hdmi_spec *spec = codec->spec;
1445         struct snd_pcm_runtime *runtime = substream->runtime;
1446         int pin_idx, cvt_idx, mux_idx = 0;
1447         struct hdmi_spec_per_pin *per_pin;
1448         struct hdmi_eld *eld;
1449         struct hdmi_spec_per_cvt *per_cvt = NULL;
1450         int err;
1451
1452         /* Validate hinfo */
1453         pin_idx = hinfo_to_pin_index(codec, hinfo);
1454         if (snd_BUG_ON(pin_idx < 0))
1455                 return -EINVAL;
1456         per_pin = get_pin(spec, pin_idx);
1457         eld = &per_pin->sink_eld;
1458
1459         err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1460         if (err < 0)
1461                 return err;
1462
1463         per_cvt = get_cvt(spec, cvt_idx);
1464         /* Claim converter */
1465         per_cvt->assigned = 1;
1466         per_pin->cvt_nid = per_cvt->cvt_nid;
1467         hinfo->nid = per_cvt->cvt_nid;
1468
1469         snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1470                             AC_VERB_SET_CONNECT_SEL,
1471                             mux_idx);
1472
1473         /* configure unused pins to choose other converters */
1474         if (is_haswell_plus(codec) || is_valleyview_plus(codec))
1475                 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx);
1476
1477         snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
1478
1479         /* Initially set the converter's capabilities */
1480         hinfo->channels_min = per_cvt->channels_min;
1481         hinfo->channels_max = per_cvt->channels_max;
1482         hinfo->rates = per_cvt->rates;
1483         hinfo->formats = per_cvt->formats;
1484         hinfo->maxbps = per_cvt->maxbps;
1485
1486         /* Restrict capabilities by ELD if this isn't disabled */
1487         if (!static_hdmi_pcm && eld->eld_valid) {
1488                 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1489                 if (hinfo->channels_min > hinfo->channels_max ||
1490                     !hinfo->rates || !hinfo->formats) {
1491                         per_cvt->assigned = 0;
1492                         hinfo->nid = 0;
1493                         snd_hda_spdif_ctls_unassign(codec, pin_idx);
1494                         return -ENODEV;
1495                 }
1496         }
1497
1498         /* Store the updated parameters */
1499         runtime->hw.channels_min = hinfo->channels_min;
1500         runtime->hw.channels_max = hinfo->channels_max;
1501         runtime->hw.formats = hinfo->formats;
1502         runtime->hw.rates = hinfo->rates;
1503
1504         snd_pcm_hw_constraint_step(substream->runtime, 0,
1505                                    SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1506         return 0;
1507 }
1508
1509 /*
1510  * HDA/HDMI auto parsing
1511  */
1512 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1513 {
1514         struct hdmi_spec *spec = codec->spec;
1515         struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1516         hda_nid_t pin_nid = per_pin->pin_nid;
1517
1518         if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1519                 codec_warn(codec,
1520                            "HDMI: pin %d wcaps %#x does not support connection list\n",
1521                            pin_nid, get_wcaps(codec, pin_nid));
1522                 return -EINVAL;
1523         }
1524
1525         per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1526                                                         per_pin->mux_nids,
1527                                                         HDA_MAX_CONNECTIONS);
1528
1529         return 0;
1530 }
1531
1532 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1533 {
1534         struct hda_jack_tbl *jack;
1535         struct hda_codec *codec = per_pin->codec;
1536         struct hdmi_spec *spec = codec->spec;
1537         struct hdmi_eld *eld = &spec->temp_eld;
1538         struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1539         hda_nid_t pin_nid = per_pin->pin_nid;
1540         /*
1541          * Always execute a GetPinSense verb here, even when called from
1542          * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1543          * response's PD bit is not the real PD value, but indicates that
1544          * the real PD value changed. An older version of the HD-audio
1545          * specification worked this way. Hence, we just ignore the data in
1546          * the unsolicited response to avoid custom WARs.
1547          */
1548         int present;
1549         bool update_eld = false;
1550         bool eld_changed = false;
1551         bool ret;
1552
1553         snd_hda_power_up_pm(codec);
1554         present = snd_hda_pin_sense(codec, pin_nid);
1555
1556         mutex_lock(&per_pin->lock);
1557         pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1558         if (pin_eld->monitor_present)
1559                 eld->eld_valid  = !!(present & AC_PINSENSE_ELDV);
1560         else
1561                 eld->eld_valid = false;
1562
1563         codec_dbg(codec,
1564                 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1565                 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
1566
1567         if (eld->eld_valid) {
1568                 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1569                                                      &eld->eld_size) < 0)
1570                         eld->eld_valid = false;
1571                 else {
1572                         memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
1573                         if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1574                                                     eld->eld_size) < 0)
1575                                 eld->eld_valid = false;
1576                 }
1577
1578                 if (eld->eld_valid) {
1579                         snd_hdmi_show_eld(codec, &eld->info);
1580                         update_eld = true;
1581                 }
1582                 else if (repoll) {
1583                         schedule_delayed_work(&per_pin->work,
1584                                               msecs_to_jiffies(300));
1585                         goto unlock;
1586                 }
1587         }
1588
1589         if (pin_eld->eld_valid != eld->eld_valid)
1590                 eld_changed = true;
1591
1592         if (pin_eld->eld_valid && !eld->eld_valid)
1593                 update_eld = true;
1594
1595         if (update_eld) {
1596                 bool old_eld_valid = pin_eld->eld_valid;
1597                 pin_eld->eld_valid = eld->eld_valid;
1598                 if (pin_eld->eld_size != eld->eld_size ||
1599                               memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1600                                      eld->eld_size) != 0) {
1601                         memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1602                                eld->eld_size);
1603                         eld_changed = true;
1604                 }
1605                 pin_eld->eld_size = eld->eld_size;
1606                 pin_eld->info = eld->info;
1607
1608                 /*
1609                  * Re-setup pin and infoframe. This is needed e.g. when
1610                  * - sink is first plugged-in (infoframe is not set up if !monitor_present)
1611                  * - transcoder can change during stream playback on Haswell
1612                  *   and this can make HW reset converter selection on a pin.
1613                  */
1614                 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1615                         if (is_haswell_plus(codec) ||
1616                                 is_valleyview_plus(codec)) {
1617                                 intel_verify_pin_cvt_connect(codec, per_pin);
1618                                 intel_not_share_assigned_cvt(codec, pin_nid,
1619                                                         per_pin->mux_idx);
1620                         }
1621
1622                         hdmi_setup_audio_infoframe(codec, per_pin,
1623                                                    per_pin->non_pcm);
1624                 }
1625         }
1626
1627         if (eld_changed)
1628                 snd_ctl_notify(codec->card,
1629                                SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO,
1630                                &per_pin->eld_ctl->id);
1631  unlock:
1632         ret = !repoll || !pin_eld->monitor_present || pin_eld->eld_valid;
1633
1634         jack = snd_hda_jack_tbl_get(codec, pin_nid);
1635         if (jack)
1636                 jack->block_report = !ret;
1637
1638         mutex_unlock(&per_pin->lock);
1639         snd_hda_power_down_pm(codec);
1640         return ret;
1641 }
1642
1643 static void hdmi_repoll_eld(struct work_struct *work)
1644 {
1645         struct hdmi_spec_per_pin *per_pin =
1646         container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1647
1648         if (per_pin->repoll_count++ > 6)
1649                 per_pin->repoll_count = 0;
1650
1651         if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1652                 snd_hda_jack_report_sync(per_pin->codec);
1653 }
1654
1655 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1656                                              hda_nid_t nid);
1657
1658 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1659 {
1660         struct hdmi_spec *spec = codec->spec;
1661         unsigned int caps, config;
1662         int pin_idx;
1663         struct hdmi_spec_per_pin *per_pin;
1664         int err;
1665
1666         caps = snd_hda_query_pin_caps(codec, pin_nid);
1667         if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1668                 return 0;
1669
1670         config = snd_hda_codec_get_pincfg(codec, pin_nid);
1671         if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1672                 return 0;
1673
1674         if (is_haswell_plus(codec))
1675                 intel_haswell_fixup_connect_list(codec, pin_nid);
1676
1677         pin_idx = spec->num_pins;
1678         per_pin = snd_array_new(&spec->pins);
1679         if (!per_pin)
1680                 return -ENOMEM;
1681
1682         per_pin->pin_nid = pin_nid;
1683         per_pin->non_pcm = false;
1684
1685         err = hdmi_read_pin_conn(codec, pin_idx);
1686         if (err < 0)
1687                 return err;
1688
1689         spec->num_pins++;
1690
1691         return 0;
1692 }
1693
1694 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1695 {
1696         struct hdmi_spec *spec = codec->spec;
1697         struct hdmi_spec_per_cvt *per_cvt;
1698         unsigned int chans;
1699         int err;
1700
1701         chans = get_wcaps(codec, cvt_nid);
1702         chans = get_wcaps_channels(chans);
1703
1704         per_cvt = snd_array_new(&spec->cvts);
1705         if (!per_cvt)
1706                 return -ENOMEM;
1707
1708         per_cvt->cvt_nid = cvt_nid;
1709         per_cvt->channels_min = 2;
1710         if (chans <= 16) {
1711                 per_cvt->channels_max = chans;
1712                 if (chans > spec->channels_max)
1713                         spec->channels_max = chans;
1714         }
1715
1716         err = snd_hda_query_supported_pcm(codec, cvt_nid,
1717                                           &per_cvt->rates,
1718                                           &per_cvt->formats,
1719                                           &per_cvt->maxbps);
1720         if (err < 0)
1721                 return err;
1722
1723         if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1724                 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1725         spec->num_cvts++;
1726
1727         return 0;
1728 }
1729
1730 static int hdmi_parse_codec(struct hda_codec *codec)
1731 {
1732         hda_nid_t nid;
1733         int i, nodes;
1734
1735         nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
1736         if (!nid || nodes < 0) {
1737                 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1738                 return -EINVAL;
1739         }
1740
1741         for (i = 0; i < nodes; i++, nid++) {
1742                 unsigned int caps;
1743                 unsigned int type;
1744
1745                 caps = get_wcaps(codec, nid);
1746                 type = get_wcaps_type(caps);
1747
1748                 if (!(caps & AC_WCAP_DIGITAL))
1749                         continue;
1750
1751                 switch (type) {
1752                 case AC_WID_AUD_OUT:
1753                         hdmi_add_cvt(codec, nid);
1754                         break;
1755                 case AC_WID_PIN:
1756                         hdmi_add_pin(codec, nid);
1757                         break;
1758                 }
1759         }
1760
1761         return 0;
1762 }
1763
1764 /*
1765  */
1766 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1767 {
1768         struct hda_spdif_out *spdif;
1769         bool non_pcm;
1770
1771         mutex_lock(&codec->spdif_mutex);
1772         spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1773         non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1774         mutex_unlock(&codec->spdif_mutex);
1775         return non_pcm;
1776 }
1777
1778
1779 /*
1780  * HDMI callbacks
1781  */
1782
1783 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1784                                            struct hda_codec *codec,
1785                                            unsigned int stream_tag,
1786                                            unsigned int format,
1787                                            struct snd_pcm_substream *substream)
1788 {
1789         hda_nid_t cvt_nid = hinfo->nid;
1790         struct hdmi_spec *spec = codec->spec;
1791         int pin_idx = hinfo_to_pin_index(codec, hinfo);
1792         struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1793         hda_nid_t pin_nid = per_pin->pin_nid;
1794         bool non_pcm;
1795         int pinctl;
1796
1797         if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
1798                 /* Verify pin:cvt selections to avoid silent audio after S3.
1799                  * After S3, the audio driver restores pin:cvt selections
1800                  * but this can happen before gfx is ready and such selection
1801                  * is overlooked by HW. Thus multiple pins can share a same
1802                  * default convertor and mute control will affect each other,
1803                  * which can cause a resumed audio playback become silent
1804                  * after S3.
1805                  */
1806                 intel_verify_pin_cvt_connect(codec, per_pin);
1807                 intel_not_share_assigned_cvt(codec, pin_nid, per_pin->mux_idx);
1808         }
1809
1810         non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1811         mutex_lock(&per_pin->lock);
1812         per_pin->channels = substream->runtime->channels;
1813         per_pin->setup = true;
1814
1815         hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1816         mutex_unlock(&per_pin->lock);
1817
1818         if (spec->dyn_pin_out) {
1819                 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1820                                             AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1821                 snd_hda_codec_write(codec, pin_nid, 0,
1822                                     AC_VERB_SET_PIN_WIDGET_CONTROL,
1823                                     pinctl | PIN_OUT);
1824         }
1825
1826         return spec->ops.setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
1827 }
1828
1829 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1830                                              struct hda_codec *codec,
1831                                              struct snd_pcm_substream *substream)
1832 {
1833         snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1834         return 0;
1835 }
1836
1837 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1838                           struct hda_codec *codec,
1839                           struct snd_pcm_substream *substream)
1840 {
1841         struct hdmi_spec *spec = codec->spec;
1842         int cvt_idx, pin_idx;
1843         struct hdmi_spec_per_cvt *per_cvt;
1844         struct hdmi_spec_per_pin *per_pin;
1845         int pinctl;
1846
1847         if (hinfo->nid) {
1848                 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1849                 if (snd_BUG_ON(cvt_idx < 0))
1850                         return -EINVAL;
1851                 per_cvt = get_cvt(spec, cvt_idx);
1852
1853                 snd_BUG_ON(!per_cvt->assigned);
1854                 per_cvt->assigned = 0;
1855                 hinfo->nid = 0;
1856
1857                 pin_idx = hinfo_to_pin_index(codec, hinfo);
1858                 if (snd_BUG_ON(pin_idx < 0))
1859                         return -EINVAL;
1860                 per_pin = get_pin(spec, pin_idx);
1861
1862                 if (spec->dyn_pin_out) {
1863                         pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1864                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1865                         snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1866                                             AC_VERB_SET_PIN_WIDGET_CONTROL,
1867                                             pinctl & ~PIN_OUT);
1868                 }
1869
1870                 snd_hda_spdif_ctls_unassign(codec, pin_idx);
1871
1872                 mutex_lock(&per_pin->lock);
1873                 per_pin->chmap_set = false;
1874                 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1875
1876                 per_pin->setup = false;
1877                 per_pin->channels = 0;
1878                 mutex_unlock(&per_pin->lock);
1879         }
1880
1881         return 0;
1882 }
1883
1884 static const struct hda_pcm_ops generic_ops = {
1885         .open = hdmi_pcm_open,
1886         .close = hdmi_pcm_close,
1887         .prepare = generic_hdmi_playback_pcm_prepare,
1888         .cleanup = generic_hdmi_playback_pcm_cleanup,
1889 };
1890
1891 /*
1892  * ALSA API channel-map control callbacks
1893  */
1894 static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1895                                struct snd_ctl_elem_info *uinfo)
1896 {
1897         struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1898         struct hda_codec *codec = info->private_data;
1899         struct hdmi_spec *spec = codec->spec;
1900         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1901         uinfo->count = spec->channels_max;
1902         uinfo->value.integer.min = 0;
1903         uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1904         return 0;
1905 }
1906
1907 static int hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
1908                                                   int channels)
1909 {
1910         /* If the speaker allocation matches the channel count, it is OK.*/
1911         if (cap->channels != channels)
1912                 return -1;
1913
1914         /* all channels are remappable freely */
1915         return SNDRV_CTL_TLVT_CHMAP_VAR;
1916 }
1917
1918 static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
1919                                         unsigned int *chmap, int channels)
1920 {
1921         int count = 0;
1922         int c;
1923
1924         for (c = 7; c >= 0; c--) {
1925                 int spk = cap->speakers[c];
1926                 if (!spk)
1927                         continue;
1928
1929                 chmap[count++] = spk_to_chmap(spk);
1930         }
1931
1932         WARN_ON(count != channels);
1933 }
1934
1935 static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
1936                               unsigned int size, unsigned int __user *tlv)
1937 {
1938         struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1939         struct hda_codec *codec = info->private_data;
1940         struct hdmi_spec *spec = codec->spec;
1941         unsigned int __user *dst;
1942         int chs, count = 0;
1943
1944         if (size < 8)
1945                 return -ENOMEM;
1946         if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
1947                 return -EFAULT;
1948         size -= 8;
1949         dst = tlv + 2;
1950         for (chs = 2; chs <= spec->channels_max; chs++) {
1951                 int i;
1952                 struct cea_channel_speaker_allocation *cap;
1953                 cap = channel_allocations;
1954                 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
1955                         int chs_bytes = chs * 4;
1956                         int type = spec->ops.chmap_cea_alloc_validate_get_type(cap, chs);
1957                         unsigned int tlv_chmap[8];
1958
1959                         if (type < 0)
1960                                 continue;
1961                         if (size < 8)
1962                                 return -ENOMEM;
1963                         if (put_user(type, dst) ||
1964                             put_user(chs_bytes, dst + 1))
1965                                 return -EFAULT;
1966                         dst += 2;
1967                         size -= 8;
1968                         count += 8;
1969                         if (size < chs_bytes)
1970                                 return -ENOMEM;
1971                         size -= chs_bytes;
1972                         count += chs_bytes;
1973                         spec->ops.cea_alloc_to_tlv_chmap(cap, tlv_chmap, chs);
1974                         if (copy_to_user(dst, tlv_chmap, chs_bytes))
1975                                 return -EFAULT;
1976                         dst += chs;
1977                 }
1978         }
1979         if (put_user(count, tlv + 1))
1980                 return -EFAULT;
1981         return 0;
1982 }
1983
1984 static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
1985                               struct snd_ctl_elem_value *ucontrol)
1986 {
1987         struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1988         struct hda_codec *codec = info->private_data;
1989         struct hdmi_spec *spec = codec->spec;
1990         int pin_idx = kcontrol->private_value;
1991         struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1992         int i;
1993
1994         for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
1995                 ucontrol->value.integer.value[i] = per_pin->chmap[i];
1996         return 0;
1997 }
1998
1999 static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
2000                               struct snd_ctl_elem_value *ucontrol)
2001 {
2002         struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2003         struct hda_codec *codec = info->private_data;
2004         struct hdmi_spec *spec = codec->spec;
2005         int pin_idx = kcontrol->private_value;
2006         struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2007         unsigned int ctl_idx;
2008         struct snd_pcm_substream *substream;
2009         unsigned char chmap[8];
2010         int i, err, ca, prepared = 0;
2011
2012         ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2013         substream = snd_pcm_chmap_substream(info, ctl_idx);
2014         if (!substream || !substream->runtime)
2015                 return 0; /* just for avoiding error from alsactl restore */
2016         switch (substream->runtime->status->state) {
2017         case SNDRV_PCM_STATE_OPEN:
2018         case SNDRV_PCM_STATE_SETUP:
2019                 break;
2020         case SNDRV_PCM_STATE_PREPARED:
2021                 prepared = 1;
2022                 break;
2023         default:
2024                 return -EBUSY;
2025         }
2026         memset(chmap, 0, sizeof(chmap));
2027         for (i = 0; i < ARRAY_SIZE(chmap); i++)
2028                 chmap[i] = ucontrol->value.integer.value[i];
2029         if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
2030                 return 0;
2031         ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
2032         if (ca < 0)
2033                 return -EINVAL;
2034         if (spec->ops.chmap_validate) {
2035                 err = spec->ops.chmap_validate(ca, ARRAY_SIZE(chmap), chmap);
2036                 if (err)
2037                         return err;
2038         }
2039         mutex_lock(&per_pin->lock);
2040         per_pin->chmap_set = true;
2041         memcpy(per_pin->chmap, chmap, sizeof(chmap));
2042         if (prepared)
2043                 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2044         mutex_unlock(&per_pin->lock);
2045
2046         return 0;
2047 }
2048
2049 static int generic_hdmi_build_pcms(struct hda_codec *codec)
2050 {
2051         struct hdmi_spec *spec = codec->spec;
2052         int pin_idx;
2053
2054         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2055                 struct hda_pcm *info;
2056                 struct hda_pcm_stream *pstr;
2057
2058                 info = snd_hda_codec_pcm_new(codec, "HDMI %d", pin_idx);
2059                 if (!info)
2060                         return -ENOMEM;
2061                 spec->pcm_rec[pin_idx] = info;
2062                 info->pcm_type = HDA_PCM_TYPE_HDMI;
2063                 info->own_chmap = true;
2064
2065                 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2066                 pstr->substreams = 1;
2067                 pstr->ops = generic_ops;
2068                 /* other pstr fields are set in open */
2069         }
2070
2071         return 0;
2072 }
2073
2074 static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
2075 {
2076         char hdmi_str[32] = "HDMI/DP";
2077         struct hdmi_spec *spec = codec->spec;
2078         struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2079         int pcmdev = get_pcm_rec(spec, pin_idx)->device;
2080
2081         if (pcmdev > 0)
2082                 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2083         if (!is_jack_detectable(codec, per_pin->pin_nid))
2084                 strncat(hdmi_str, " Phantom",
2085                         sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2086
2087         return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str);
2088 }
2089
2090 static int generic_hdmi_build_controls(struct hda_codec *codec)
2091 {
2092         struct hdmi_spec *spec = codec->spec;
2093         int err;
2094         int pin_idx;
2095
2096         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2097                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2098
2099                 err = generic_hdmi_build_jack(codec, pin_idx);
2100                 if (err < 0)
2101                         return err;
2102
2103                 err = snd_hda_create_dig_out_ctls(codec,
2104                                                   per_pin->pin_nid,
2105                                                   per_pin->mux_nids[0],
2106                                                   HDA_PCM_TYPE_HDMI);
2107                 if (err < 0)
2108                         return err;
2109                 snd_hda_spdif_ctls_unassign(codec, pin_idx);
2110
2111                 /* add control for ELD Bytes */
2112                 err = hdmi_create_eld_ctl(codec, pin_idx,
2113                                           get_pcm_rec(spec, pin_idx)->device);
2114
2115                 if (err < 0)
2116                         return err;
2117
2118                 hdmi_present_sense(per_pin, 0);
2119         }
2120
2121         /* add channel maps */
2122         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2123                 struct hda_pcm *pcm;
2124                 struct snd_pcm_chmap *chmap;
2125                 struct snd_kcontrol *kctl;
2126                 int i;
2127
2128                 pcm = spec->pcm_rec[pin_idx];
2129                 if (!pcm || !pcm->pcm)
2130                         break;
2131                 err = snd_pcm_add_chmap_ctls(pcm->pcm,
2132                                              SNDRV_PCM_STREAM_PLAYBACK,
2133                                              NULL, 0, pin_idx, &chmap);
2134                 if (err < 0)
2135                         return err;
2136                 /* override handlers */
2137                 chmap->private_data = codec;
2138                 kctl = chmap->kctl;
2139                 for (i = 0; i < kctl->count; i++)
2140                         kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
2141                 kctl->info = hdmi_chmap_ctl_info;
2142                 kctl->get = hdmi_chmap_ctl_get;
2143                 kctl->put = hdmi_chmap_ctl_put;
2144                 kctl->tlv.c = hdmi_chmap_ctl_tlv;
2145         }
2146
2147         return 0;
2148 }
2149
2150 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2151 {
2152         struct hdmi_spec *spec = codec->spec;
2153         int pin_idx;
2154
2155         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2156                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2157
2158                 per_pin->codec = codec;
2159                 mutex_init(&per_pin->lock);
2160                 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2161                 eld_proc_new(per_pin, pin_idx);
2162         }
2163         return 0;
2164 }
2165
2166 static int generic_hdmi_init(struct hda_codec *codec)
2167 {
2168         struct hdmi_spec *spec = codec->spec;
2169         int pin_idx;
2170
2171         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2172                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2173                 hda_nid_t pin_nid = per_pin->pin_nid;
2174
2175                 hdmi_init_pin(codec, pin_nid);
2176                 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2177                         codec->jackpoll_interval > 0 ? jack_callback : NULL);
2178         }
2179         return 0;
2180 }
2181
2182 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2183 {
2184         snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2185         snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2186 }
2187
2188 static void hdmi_array_free(struct hdmi_spec *spec)
2189 {
2190         snd_array_free(&spec->pins);
2191         snd_array_free(&spec->cvts);
2192 }
2193
2194 static void generic_hdmi_free(struct hda_codec *codec)
2195 {
2196         struct hdmi_spec *spec = codec->spec;
2197         int pin_idx;
2198
2199         if (is_haswell_plus(codec) || is_valleyview_plus(codec))
2200                 snd_hdac_i915_register_notifier(NULL);
2201
2202         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2203                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2204
2205                 cancel_delayed_work_sync(&per_pin->work);
2206                 eld_proc_free(per_pin);
2207         }
2208
2209         hdmi_array_free(spec);
2210         kfree(spec);
2211 }
2212
2213 #ifdef CONFIG_PM
2214 static int generic_hdmi_resume(struct hda_codec *codec)
2215 {
2216         struct hdmi_spec *spec = codec->spec;
2217         int pin_idx;
2218
2219         codec->patch_ops.init(codec);
2220         regcache_sync(codec->core.regmap);
2221
2222         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2223                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2224                 hdmi_present_sense(per_pin, 1);
2225         }
2226         return 0;
2227 }
2228 #endif
2229
2230 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2231         .init                   = generic_hdmi_init,
2232         .free                   = generic_hdmi_free,
2233         .build_pcms             = generic_hdmi_build_pcms,
2234         .build_controls         = generic_hdmi_build_controls,
2235         .unsol_event            = hdmi_unsol_event,
2236 #ifdef CONFIG_PM
2237         .resume                 = generic_hdmi_resume,
2238 #endif
2239 };
2240
2241 static const struct hdmi_ops generic_standard_hdmi_ops = {
2242         .pin_get_eld                            = snd_hdmi_get_eld,
2243         .pin_get_slot_channel                   = hdmi_pin_get_slot_channel,
2244         .pin_set_slot_channel                   = hdmi_pin_set_slot_channel,
2245         .pin_setup_infoframe                    = hdmi_pin_setup_infoframe,
2246         .pin_hbr_setup                          = hdmi_pin_hbr_setup,
2247         .setup_stream                           = hdmi_setup_stream,
2248         .chmap_cea_alloc_validate_get_type      = hdmi_chmap_cea_alloc_validate_get_type,
2249         .cea_alloc_to_tlv_chmap                 = hdmi_cea_alloc_to_tlv_chmap,
2250 };
2251
2252
2253 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2254                                              hda_nid_t nid)
2255 {
2256         struct hdmi_spec *spec = codec->spec;
2257         hda_nid_t conns[4];
2258         int nconns;
2259
2260         nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2261         if (nconns == spec->num_cvts &&
2262             !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2263                 return;
2264
2265         /* override pins connection list */
2266         codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2267         snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2268 }
2269
2270 #define INTEL_VENDOR_NID 0x08
2271 #define INTEL_GET_VENDOR_VERB 0xf81
2272 #define INTEL_SET_VENDOR_VERB 0x781
2273 #define INTEL_EN_DP12                   0x02 /* enable DP 1.2 features */
2274 #define INTEL_EN_ALL_PIN_CVTS   0x01 /* enable 2nd & 3rd pins and convertors */
2275
2276 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2277                                           bool update_tree)
2278 {
2279         unsigned int vendor_param;
2280
2281         vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2282                                 INTEL_GET_VENDOR_VERB, 0);
2283         if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2284                 return;
2285
2286         vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2287         vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2288                                 INTEL_SET_VENDOR_VERB, vendor_param);
2289         if (vendor_param == -1)
2290                 return;
2291
2292         if (update_tree)
2293                 snd_hda_codec_update_widgets(codec);
2294 }
2295
2296 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2297 {
2298         unsigned int vendor_param;
2299
2300         vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2301                                 INTEL_GET_VENDOR_VERB, 0);
2302         if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2303                 return;
2304
2305         /* enable DP1.2 mode */
2306         vendor_param |= INTEL_EN_DP12;
2307         snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2308         snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2309                                 INTEL_SET_VENDOR_VERB, vendor_param);
2310 }
2311
2312 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2313  * Otherwise you may get severe h/w communication errors.
2314  */
2315 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2316                                 unsigned int power_state)
2317 {
2318         if (power_state == AC_PWRST_D0) {
2319                 intel_haswell_enable_all_pins(codec, false);
2320                 intel_haswell_fixup_enable_dp12(codec);
2321         }
2322
2323         snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2324         snd_hda_codec_set_power_to_all(codec, fg, power_state);
2325 }
2326
2327 static void intel_pin_eld_notify(void *audio_ptr, int port)
2328 {
2329         struct hda_codec *codec = audio_ptr;
2330         int pin_nid = port + 0x04;
2331
2332         check_presence_and_report(codec, pin_nid);
2333 }
2334
2335 static int patch_generic_hdmi(struct hda_codec *codec)
2336 {
2337         struct hdmi_spec *spec;
2338
2339         spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2340         if (spec == NULL)
2341                 return -ENOMEM;
2342
2343         spec->ops = generic_standard_hdmi_ops;
2344         codec->spec = spec;
2345         hdmi_array_init(spec, 4);
2346
2347         if (is_haswell_plus(codec)) {
2348                 intel_haswell_enable_all_pins(codec, true);
2349                 intel_haswell_fixup_enable_dp12(codec);
2350         }
2351
2352         /* For Valleyview/Cherryview, only the display codec is in the display
2353          * power well and can use link_power ops to request/release the power.
2354          * For Haswell/Broadwell, the controller is also in the power well and
2355          * can cover the codec power request, and so need not set this flag.
2356          * For previous platforms, there is no such power well feature.
2357          */
2358         if (is_valleyview_plus(codec) || is_skylake(codec))
2359                 codec->core.link_power_control = 1;
2360
2361         if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
2362                 codec->depop_delay = 0;
2363                 spec->i915_audio_ops.audio_ptr = codec;
2364                 spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify;
2365                 snd_hdac_i915_register_notifier(&spec->i915_audio_ops);
2366         }
2367
2368         if (hdmi_parse_codec(codec) < 0) {
2369                 codec->spec = NULL;
2370                 kfree(spec);
2371                 return -EINVAL;
2372         }
2373         codec->patch_ops = generic_hdmi_patch_ops;
2374         if (is_haswell_plus(codec)) {
2375                 codec->patch_ops.set_power_state = haswell_set_power_state;
2376                 codec->dp_mst = true;
2377         }
2378
2379         /* Enable runtime pm for HDMI audio codec of HSW/BDW/SKL/BYT/BSW */
2380         if (is_haswell_plus(codec) || is_valleyview_plus(codec))
2381                 codec->auto_runtime_pm = 1;
2382
2383         generic_hdmi_init_per_pins(codec);
2384
2385         init_channel_allocations();
2386
2387         return 0;
2388 }
2389
2390 /*
2391  * Shared non-generic implementations
2392  */
2393
2394 static int simple_playback_build_pcms(struct hda_codec *codec)
2395 {
2396         struct hdmi_spec *spec = codec->spec;
2397         struct hda_pcm *info;
2398         unsigned int chans;
2399         struct hda_pcm_stream *pstr;
2400         struct hdmi_spec_per_cvt *per_cvt;
2401
2402         per_cvt = get_cvt(spec, 0);
2403         chans = get_wcaps(codec, per_cvt->cvt_nid);
2404         chans = get_wcaps_channels(chans);
2405
2406         info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2407         if (!info)
2408                 return -ENOMEM;
2409         spec->pcm_rec[0] = info;
2410         info->pcm_type = HDA_PCM_TYPE_HDMI;
2411         pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2412         *pstr = spec->pcm_playback;
2413         pstr->nid = per_cvt->cvt_nid;
2414         if (pstr->channels_max <= 2 && chans && chans <= 16)
2415                 pstr->channels_max = chans;
2416
2417         return 0;
2418 }
2419
2420 /* unsolicited event for jack sensing */
2421 static void simple_hdmi_unsol_event(struct hda_codec *codec,
2422                                     unsigned int res)
2423 {
2424         snd_hda_jack_set_dirty_all(codec);
2425         snd_hda_jack_report_sync(codec);
2426 }
2427
2428 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
2429  * as long as spec->pins[] is set correctly
2430  */
2431 #define simple_hdmi_build_jack  generic_hdmi_build_jack
2432
2433 static int simple_playback_build_controls(struct hda_codec *codec)
2434 {
2435         struct hdmi_spec *spec = codec->spec;
2436         struct hdmi_spec_per_cvt *per_cvt;
2437         int err;
2438
2439         per_cvt = get_cvt(spec, 0);
2440         err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2441                                           per_cvt->cvt_nid,
2442                                           HDA_PCM_TYPE_HDMI);
2443         if (err < 0)
2444                 return err;
2445         return simple_hdmi_build_jack(codec, 0);
2446 }
2447
2448 static int simple_playback_init(struct hda_codec *codec)
2449 {
2450         struct hdmi_spec *spec = codec->spec;
2451         struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2452         hda_nid_t pin = per_pin->pin_nid;
2453
2454         snd_hda_codec_write(codec, pin, 0,
2455                             AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2456         /* some codecs require to unmute the pin */
2457         if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2458                 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2459                                     AMP_OUT_UNMUTE);
2460         snd_hda_jack_detect_enable(codec, pin);
2461         return 0;
2462 }
2463
2464 static void simple_playback_free(struct hda_codec *codec)
2465 {
2466         struct hdmi_spec *spec = codec->spec;
2467
2468         hdmi_array_free(spec);
2469         kfree(spec);
2470 }
2471
2472 /*
2473  * Nvidia specific implementations
2474  */
2475
2476 #define Nv_VERB_SET_Channel_Allocation          0xF79
2477 #define Nv_VERB_SET_Info_Frame_Checksum         0xF7A
2478 #define Nv_VERB_SET_Audio_Protection_On         0xF98
2479 #define Nv_VERB_SET_Audio_Protection_Off        0xF99
2480
2481 #define nvhdmi_master_con_nid_7x        0x04
2482 #define nvhdmi_master_pin_nid_7x        0x05
2483
2484 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2485         /*front, rear, clfe, rear_surr */
2486         0x6, 0x8, 0xa, 0xc,
2487 };
2488
2489 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2490         /* set audio protect on */
2491         { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2492         /* enable digital output on pin widget */
2493         { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2494         {} /* terminator */
2495 };
2496
2497 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
2498         /* set audio protect on */
2499         { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2500         /* enable digital output on pin widget */
2501         { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2502         { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2503         { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2504         { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2505         { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2506         {} /* terminator */
2507 };
2508
2509 #ifdef LIMITED_RATE_FMT_SUPPORT
2510 /* support only the safe format and rate */
2511 #define SUPPORTED_RATES         SNDRV_PCM_RATE_48000
2512 #define SUPPORTED_MAXBPS        16
2513 #define SUPPORTED_FORMATS       SNDRV_PCM_FMTBIT_S16_LE
2514 #else
2515 /* support all rates and formats */
2516 #define SUPPORTED_RATES \
2517         (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2518         SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2519          SNDRV_PCM_RATE_192000)
2520 #define SUPPORTED_MAXBPS        24
2521 #define SUPPORTED_FORMATS \
2522         (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2523 #endif
2524
2525 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2526 {
2527         snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2528         return 0;
2529 }
2530
2531 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
2532 {
2533         snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
2534         return 0;
2535 }
2536
2537 static unsigned int channels_2_6_8[] = {
2538         2, 6, 8
2539 };
2540
2541 static unsigned int channels_2_8[] = {
2542         2, 8
2543 };
2544
2545 static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2546         .count = ARRAY_SIZE(channels_2_6_8),
2547         .list = channels_2_6_8,
2548         .mask = 0,
2549 };
2550
2551 static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2552         .count = ARRAY_SIZE(channels_2_8),
2553         .list = channels_2_8,
2554         .mask = 0,
2555 };
2556
2557 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2558                                     struct hda_codec *codec,
2559                                     struct snd_pcm_substream *substream)
2560 {
2561         struct hdmi_spec *spec = codec->spec;
2562         struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2563
2564         switch (codec->preset->id) {
2565         case 0x10de0002:
2566         case 0x10de0003:
2567         case 0x10de0005:
2568         case 0x10de0006:
2569                 hw_constraints_channels = &hw_constraints_2_8_channels;
2570                 break;
2571         case 0x10de0007:
2572                 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2573                 break;
2574         default:
2575                 break;
2576         }
2577
2578         if (hw_constraints_channels != NULL) {
2579                 snd_pcm_hw_constraint_list(substream->runtime, 0,
2580                                 SNDRV_PCM_HW_PARAM_CHANNELS,
2581                                 hw_constraints_channels);
2582         } else {
2583                 snd_pcm_hw_constraint_step(substream->runtime, 0,
2584                                            SNDRV_PCM_HW_PARAM_CHANNELS, 2);
2585         }
2586
2587         return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2588 }
2589
2590 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2591                                      struct hda_codec *codec,
2592                                      struct snd_pcm_substream *substream)
2593 {
2594         struct hdmi_spec *spec = codec->spec;
2595         return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2596 }
2597
2598 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2599                                        struct hda_codec *codec,
2600                                        unsigned int stream_tag,
2601                                        unsigned int format,
2602                                        struct snd_pcm_substream *substream)
2603 {
2604         struct hdmi_spec *spec = codec->spec;
2605         return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2606                                              stream_tag, format, substream);
2607 }
2608
2609 static const struct hda_pcm_stream simple_pcm_playback = {
2610         .substreams = 1,
2611         .channels_min = 2,
2612         .channels_max = 2,
2613         .ops = {
2614                 .open = simple_playback_pcm_open,
2615                 .close = simple_playback_pcm_close,
2616                 .prepare = simple_playback_pcm_prepare
2617         },
2618 };
2619
2620 static const struct hda_codec_ops simple_hdmi_patch_ops = {
2621         .build_controls = simple_playback_build_controls,
2622         .build_pcms = simple_playback_build_pcms,
2623         .init = simple_playback_init,
2624         .free = simple_playback_free,
2625         .unsol_event = simple_hdmi_unsol_event,
2626 };
2627
2628 static int patch_simple_hdmi(struct hda_codec *codec,
2629                              hda_nid_t cvt_nid, hda_nid_t pin_nid)
2630 {
2631         struct hdmi_spec *spec;
2632         struct hdmi_spec_per_cvt *per_cvt;
2633         struct hdmi_spec_per_pin *per_pin;
2634
2635         spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2636         if (!spec)
2637                 return -ENOMEM;
2638
2639         codec->spec = spec;
2640         hdmi_array_init(spec, 1);
2641
2642         spec->multiout.num_dacs = 0;  /* no analog */
2643         spec->multiout.max_channels = 2;
2644         spec->multiout.dig_out_nid = cvt_nid;
2645         spec->num_cvts = 1;
2646         spec->num_pins = 1;
2647         per_pin = snd_array_new(&spec->pins);
2648         per_cvt = snd_array_new(&spec->cvts);
2649         if (!per_pin || !per_cvt) {
2650                 simple_playback_free(codec);
2651                 return -ENOMEM;
2652         }
2653         per_cvt->cvt_nid = cvt_nid;
2654         per_pin->pin_nid = pin_nid;
2655         spec->pcm_playback = simple_pcm_playback;
2656
2657         codec->patch_ops = simple_hdmi_patch_ops;
2658
2659         return 0;
2660 }
2661
2662 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2663                                                     int channels)
2664 {
2665         unsigned int chanmask;
2666         int chan = channels ? (channels - 1) : 1;
2667
2668         switch (channels) {
2669         default:
2670         case 0:
2671         case 2:
2672                 chanmask = 0x00;
2673                 break;
2674         case 4:
2675                 chanmask = 0x08;
2676                 break;
2677         case 6:
2678                 chanmask = 0x0b;
2679                 break;
2680         case 8:
2681                 chanmask = 0x13;
2682                 break;
2683         }
2684
2685         /* Set the audio infoframe channel allocation and checksum fields.  The
2686          * channel count is computed implicitly by the hardware. */
2687         snd_hda_codec_write(codec, 0x1, 0,
2688                         Nv_VERB_SET_Channel_Allocation, chanmask);
2689
2690         snd_hda_codec_write(codec, 0x1, 0,
2691                         Nv_VERB_SET_Info_Frame_Checksum,
2692                         (0x71 - chan - chanmask));
2693 }
2694
2695 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2696                                    struct hda_codec *codec,
2697                                    struct snd_pcm_substream *substream)
2698 {
2699         struct hdmi_spec *spec = codec->spec;
2700         int i;
2701
2702         snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2703                         0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2704         for (i = 0; i < 4; i++) {
2705                 /* set the stream id */
2706                 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2707                                 AC_VERB_SET_CHANNEL_STREAMID, 0);
2708                 /* set the stream format */
2709                 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2710                                 AC_VERB_SET_STREAM_FORMAT, 0);
2711         }
2712
2713         /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2714          * streams are disabled. */
2715         nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2716
2717         return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2718 }
2719
2720 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2721                                      struct hda_codec *codec,
2722                                      unsigned int stream_tag,
2723                                      unsigned int format,
2724                                      struct snd_pcm_substream *substream)
2725 {
2726         int chs;
2727         unsigned int dataDCC2, channel_id;
2728         int i;
2729         struct hdmi_spec *spec = codec->spec;
2730         struct hda_spdif_out *spdif;
2731         struct hdmi_spec_per_cvt *per_cvt;
2732
2733         mutex_lock(&codec->spdif_mutex);
2734         per_cvt = get_cvt(spec, 0);
2735         spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
2736
2737         chs = substream->runtime->channels;
2738
2739         dataDCC2 = 0x2;
2740
2741         /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
2742         if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
2743                 snd_hda_codec_write(codec,
2744                                 nvhdmi_master_con_nid_7x,
2745                                 0,
2746                                 AC_VERB_SET_DIGI_CONVERT_1,
2747                                 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2748
2749         /* set the stream id */
2750         snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2751                         AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2752
2753         /* set the stream format */
2754         snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2755                         AC_VERB_SET_STREAM_FORMAT, format);
2756
2757         /* turn on again (if needed) */
2758         /* enable and set the channel status audio/data flag */
2759         if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
2760                 snd_hda_codec_write(codec,
2761                                 nvhdmi_master_con_nid_7x,
2762                                 0,
2763                                 AC_VERB_SET_DIGI_CONVERT_1,
2764                                 spdif->ctls & 0xff);
2765                 snd_hda_codec_write(codec,
2766                                 nvhdmi_master_con_nid_7x,
2767                                 0,
2768                                 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2769         }
2770
2771         for (i = 0; i < 4; i++) {
2772                 if (chs == 2)
2773                         channel_id = 0;
2774                 else
2775                         channel_id = i * 2;
2776
2777                 /* turn off SPDIF once;
2778                  *otherwise the IEC958 bits won't be updated
2779                  */
2780                 if (codec->spdif_status_reset &&
2781                 (spdif->ctls & AC_DIG1_ENABLE))
2782                         snd_hda_codec_write(codec,
2783                                 nvhdmi_con_nids_7x[i],
2784                                 0,
2785                                 AC_VERB_SET_DIGI_CONVERT_1,
2786                                 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2787                 /* set the stream id */
2788                 snd_hda_codec_write(codec,
2789                                 nvhdmi_con_nids_7x[i],
2790                                 0,
2791                                 AC_VERB_SET_CHANNEL_STREAMID,
2792                                 (stream_tag << 4) | channel_id);
2793                 /* set the stream format */
2794                 snd_hda_codec_write(codec,
2795                                 nvhdmi_con_nids_7x[i],
2796                                 0,
2797                                 AC_VERB_SET_STREAM_FORMAT,
2798                                 format);
2799                 /* turn on again (if needed) */
2800                 /* enable and set the channel status audio/data flag */
2801                 if (codec->spdif_status_reset &&
2802                 (spdif->ctls & AC_DIG1_ENABLE)) {
2803                         snd_hda_codec_write(codec,
2804                                         nvhdmi_con_nids_7x[i],
2805                                         0,
2806                                         AC_VERB_SET_DIGI_CONVERT_1,
2807                                         spdif->ctls & 0xff);
2808                         snd_hda_codec_write(codec,
2809                                         nvhdmi_con_nids_7x[i],
2810                                         0,
2811                                         AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2812                 }
2813         }
2814
2815         nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
2816
2817         mutex_unlock(&codec->spdif_mutex);
2818         return 0;
2819 }
2820
2821 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
2822         .substreams = 1,
2823         .channels_min = 2,
2824         .channels_max = 8,
2825         .nid = nvhdmi_master_con_nid_7x,
2826         .rates = SUPPORTED_RATES,
2827         .maxbps = SUPPORTED_MAXBPS,
2828         .formats = SUPPORTED_FORMATS,
2829         .ops = {
2830                 .open = simple_playback_pcm_open,
2831                 .close = nvhdmi_8ch_7x_pcm_close,
2832                 .prepare = nvhdmi_8ch_7x_pcm_prepare
2833         },
2834 };
2835
2836 static int patch_nvhdmi_2ch(struct hda_codec *codec)
2837 {
2838         struct hdmi_spec *spec;
2839         int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2840                                     nvhdmi_master_pin_nid_7x);
2841         if (err < 0)
2842                 return err;
2843
2844         codec->patch_ops.init = nvhdmi_7x_init_2ch;
2845         /* override the PCM rates, etc, as the codec doesn't give full list */
2846         spec = codec->spec;
2847         spec->pcm_playback.rates = SUPPORTED_RATES;
2848         spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2849         spec->pcm_playback.formats = SUPPORTED_FORMATS;
2850         return 0;
2851 }
2852
2853 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2854 {
2855         struct hdmi_spec *spec = codec->spec;
2856         int err = simple_playback_build_pcms(codec);
2857         if (!err) {
2858                 struct hda_pcm *info = get_pcm_rec(spec, 0);
2859                 info->own_chmap = true;
2860         }
2861         return err;
2862 }
2863
2864 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2865 {
2866         struct hdmi_spec *spec = codec->spec;
2867         struct hda_pcm *info;
2868         struct snd_pcm_chmap *chmap;
2869         int err;
2870
2871         err = simple_playback_build_controls(codec);
2872         if (err < 0)
2873                 return err;
2874
2875         /* add channel maps */
2876         info = get_pcm_rec(spec, 0);
2877         err = snd_pcm_add_chmap_ctls(info->pcm,
2878                                      SNDRV_PCM_STREAM_PLAYBACK,
2879                                      snd_pcm_alt_chmaps, 8, 0, &chmap);
2880         if (err < 0)
2881                 return err;
2882         switch (codec->preset->id) {
2883         case 0x10de0002:
2884         case 0x10de0003:
2885         case 0x10de0005:
2886         case 0x10de0006:
2887                 chmap->channel_mask = (1U << 2) | (1U << 8);
2888                 break;
2889         case 0x10de0007:
2890                 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2891         }
2892         return 0;
2893 }
2894
2895 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2896 {
2897         struct hdmi_spec *spec;
2898         int err = patch_nvhdmi_2ch(codec);
2899         if (err < 0)
2900                 return err;
2901         spec = codec->spec;
2902         spec->multiout.max_channels = 8;
2903         spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
2904         codec->patch_ops.init = nvhdmi_7x_init_8ch;
2905         codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2906         codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
2907
2908         /* Initialize the audio infoframe channel mask and checksum to something
2909          * valid */
2910         nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2911
2912         return 0;
2913 }
2914
2915 /*
2916  * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
2917  * - 0x10de0015
2918  * - 0x10de0040
2919  */
2920 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
2921                                                     int channels)
2922 {
2923         if (cap->ca_index == 0x00 && channels == 2)
2924                 return SNDRV_CTL_TLVT_CHMAP_FIXED;
2925
2926         return hdmi_chmap_cea_alloc_validate_get_type(cap, channels);
2927 }
2928
2929 static int nvhdmi_chmap_validate(int ca, int chs, unsigned char *map)
2930 {
2931         if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
2932                 return -EINVAL;
2933
2934         return 0;
2935 }
2936
2937 static int patch_nvhdmi(struct hda_codec *codec)
2938 {
2939         struct hdmi_spec *spec;
2940         int err;
2941
2942         err = patch_generic_hdmi(codec);
2943         if (err)
2944                 return err;
2945
2946         spec = codec->spec;
2947         spec->dyn_pin_out = true;
2948
2949         spec->ops.chmap_cea_alloc_validate_get_type =
2950                 nvhdmi_chmap_cea_alloc_validate_get_type;
2951         spec->ops.chmap_validate = nvhdmi_chmap_validate;
2952
2953         return 0;
2954 }
2955
2956 /*
2957  * The HDA codec on NVIDIA Tegra contains two scratch registers that are
2958  * accessed using vendor-defined verbs. These registers can be used for
2959  * interoperability between the HDA and HDMI drivers.
2960  */
2961
2962 /* Audio Function Group node */
2963 #define NVIDIA_AFG_NID 0x01
2964
2965 /*
2966  * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
2967  * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
2968  * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
2969  * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
2970  * additional bit (at position 30) to signal the validity of the format.
2971  *
2972  * | 31      | 30    | 29  16 | 15   0 |
2973  * +---------+-------+--------+--------+
2974  * | TRIGGER | VALID | UNUSED | FORMAT |
2975  * +-----------------------------------|
2976  *
2977  * Note that for the trigger bit to take effect it needs to change value
2978  * (i.e. it needs to be toggled).
2979  */
2980 #define NVIDIA_GET_SCRATCH0             0xfa6
2981 #define NVIDIA_SET_SCRATCH0_BYTE0       0xfa7
2982 #define NVIDIA_SET_SCRATCH0_BYTE1       0xfa8
2983 #define NVIDIA_SET_SCRATCH0_BYTE2       0xfa9
2984 #define NVIDIA_SET_SCRATCH0_BYTE3       0xfaa
2985 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
2986 #define NVIDIA_SCRATCH_VALID   (1 << 6)
2987
2988 #define NVIDIA_GET_SCRATCH1             0xfab
2989 #define NVIDIA_SET_SCRATCH1_BYTE0       0xfac
2990 #define NVIDIA_SET_SCRATCH1_BYTE1       0xfad
2991 #define NVIDIA_SET_SCRATCH1_BYTE2       0xfae
2992 #define NVIDIA_SET_SCRATCH1_BYTE3       0xfaf
2993
2994 /*
2995  * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
2996  * the format is invalidated so that the HDMI codec can be disabled.
2997  */
2998 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
2999 {
3000         unsigned int value;
3001
3002         /* bits [31:30] contain the trigger and valid bits */
3003         value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3004                                    NVIDIA_GET_SCRATCH0, 0);
3005         value = (value >> 24) & 0xff;
3006
3007         /* bits [15:0] are used to store the HDA format */
3008         snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3009                             NVIDIA_SET_SCRATCH0_BYTE0,
3010                             (format >> 0) & 0xff);
3011         snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3012                             NVIDIA_SET_SCRATCH0_BYTE1,
3013                             (format >> 8) & 0xff);
3014
3015         /* bits [16:24] are unused */
3016         snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3017                             NVIDIA_SET_SCRATCH0_BYTE2, 0);
3018
3019         /*
3020          * Bit 30 signals that the data is valid and hence that HDMI audio can
3021          * be enabled.
3022          */
3023         if (format == 0)
3024                 value &= ~NVIDIA_SCRATCH_VALID;
3025         else
3026                 value |= NVIDIA_SCRATCH_VALID;
3027
3028         /*
3029          * Whenever the trigger bit is toggled, an interrupt is raised in the
3030          * HDMI codec. The HDMI driver will use that as trigger to update its
3031          * configuration.
3032          */
3033         value ^= NVIDIA_SCRATCH_TRIGGER;
3034
3035         snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3036                             NVIDIA_SET_SCRATCH0_BYTE3, value);
3037 }
3038
3039 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3040                                   struct hda_codec *codec,
3041                                   unsigned int stream_tag,
3042                                   unsigned int format,
3043                                   struct snd_pcm_substream *substream)
3044 {
3045         int err;
3046
3047         err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3048                                                 format, substream);
3049         if (err < 0)
3050                 return err;
3051
3052         /* notify the HDMI codec of the format change */
3053         tegra_hdmi_set_format(codec, format);
3054
3055         return 0;
3056 }
3057
3058 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3059                                   struct hda_codec *codec,
3060                                   struct snd_pcm_substream *substream)
3061 {
3062         /* invalidate the format in the HDMI codec */
3063         tegra_hdmi_set_format(codec, 0);
3064
3065         return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3066 }
3067
3068 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3069 {
3070         struct hdmi_spec *spec = codec->spec;
3071         unsigned int i;
3072
3073         for (i = 0; i < spec->num_pins; i++) {
3074                 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3075
3076                 if (pcm->pcm_type == type)
3077                         return pcm;
3078         }
3079
3080         return NULL;
3081 }
3082
3083 static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3084 {
3085         struct hda_pcm_stream *stream;
3086         struct hda_pcm *pcm;
3087         int err;
3088
3089         err = generic_hdmi_build_pcms(codec);
3090         if (err < 0)
3091                 return err;
3092
3093         pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3094         if (!pcm)
3095                 return -ENODEV;
3096
3097         /*
3098          * Override ->prepare() and ->cleanup() operations to notify the HDMI
3099          * codec about format changes.
3100          */
3101         stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3102         stream->ops.prepare = tegra_hdmi_pcm_prepare;
3103         stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3104
3105         return 0;
3106 }
3107
3108 static int patch_tegra_hdmi(struct hda_codec *codec)
3109 {
3110         int err;
3111
3112         err = patch_generic_hdmi(codec);
3113         if (err)
3114                 return err;
3115
3116         codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3117
3118         return 0;
3119 }
3120
3121 /*
3122  * ATI/AMD-specific implementations
3123  */
3124
3125 #define is_amdhdmi_rev3_or_later(codec) \
3126         ((codec)->core.vendor_id == 0x1002aa01 && \
3127          ((codec)->core.revision_id & 0xff00) >= 0x0300)
3128 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3129
3130 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3131 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3132 #define ATI_VERB_SET_DOWNMIX_INFO       0x772
3133 #define ATI_VERB_SET_MULTICHANNEL_01    0x777
3134 #define ATI_VERB_SET_MULTICHANNEL_23    0x778
3135 #define ATI_VERB_SET_MULTICHANNEL_45    0x779
3136 #define ATI_VERB_SET_MULTICHANNEL_67    0x77a
3137 #define ATI_VERB_SET_HBR_CONTROL        0x77c
3138 #define ATI_VERB_SET_MULTICHANNEL_1     0x785
3139 #define ATI_VERB_SET_MULTICHANNEL_3     0x786
3140 #define ATI_VERB_SET_MULTICHANNEL_5     0x787
3141 #define ATI_VERB_SET_MULTICHANNEL_7     0x788
3142 #define ATI_VERB_SET_MULTICHANNEL_MODE  0x789
3143 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3144 #define ATI_VERB_GET_DOWNMIX_INFO       0xf72
3145 #define ATI_VERB_GET_MULTICHANNEL_01    0xf77
3146 #define ATI_VERB_GET_MULTICHANNEL_23    0xf78
3147 #define ATI_VERB_GET_MULTICHANNEL_45    0xf79
3148 #define ATI_VERB_GET_MULTICHANNEL_67    0xf7a
3149 #define ATI_VERB_GET_HBR_CONTROL        0xf7c
3150 #define ATI_VERB_GET_MULTICHANNEL_1     0xf85
3151 #define ATI_VERB_GET_MULTICHANNEL_3     0xf86
3152 #define ATI_VERB_GET_MULTICHANNEL_5     0xf87
3153 #define ATI_VERB_GET_MULTICHANNEL_7     0xf88
3154 #define ATI_VERB_GET_MULTICHANNEL_MODE  0xf89
3155
3156 /* AMD specific HDA cvt verbs */
3157 #define ATI_VERB_SET_RAMP_RATE          0x770
3158 #define ATI_VERB_GET_RAMP_RATE          0xf70
3159
3160 #define ATI_OUT_ENABLE 0x1
3161
3162 #define ATI_MULTICHANNEL_MODE_PAIRED    0
3163 #define ATI_MULTICHANNEL_MODE_SINGLE    1
3164
3165 #define ATI_HBR_CAPABLE 0x01
3166 #define ATI_HBR_ENABLE 0x10
3167
3168 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3169                            unsigned char *buf, int *eld_size)
3170 {
3171         /* call hda_eld.c ATI/AMD-specific function */
3172         return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3173                                     is_amdhdmi_rev3_or_later(codec));
3174 }
3175
3176 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3177                                         int active_channels, int conn_type)
3178 {
3179         snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3180 }
3181
3182 static int atihdmi_paired_swap_fc_lfe(int pos)
3183 {
3184         /*
3185          * ATI/AMD have automatic FC/LFE swap built-in
3186          * when in pairwise mapping mode.
3187          */
3188
3189         switch (pos) {
3190                 /* see channel_allocations[].speakers[] */
3191                 case 2: return 3;
3192                 case 3: return 2;
3193                 default: break;
3194         }
3195
3196         return pos;
3197 }
3198
3199 static int atihdmi_paired_chmap_validate(int ca, int chs, unsigned char *map)
3200 {
3201         struct cea_channel_speaker_allocation *cap;
3202         int i, j;
3203
3204         /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3205
3206         cap = &channel_allocations[get_channel_allocation_order(ca)];
3207         for (i = 0; i < chs; ++i) {
3208                 int mask = to_spk_mask(map[i]);
3209                 bool ok = false;
3210                 bool companion_ok = false;
3211
3212                 if (!mask)
3213                         continue;
3214
3215                 for (j = 0 + i % 2; j < 8; j += 2) {
3216                         int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3217                         if (cap->speakers[chan_idx] == mask) {
3218                                 /* channel is in a supported position */
3219                                 ok = true;
3220
3221                                 if (i % 2 == 0 && i + 1 < chs) {
3222                                         /* even channel, check the odd companion */
3223                                         int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3224                                         int comp_mask_req = to_spk_mask(map[i+1]);
3225                                         int comp_mask_act = cap->speakers[comp_chan_idx];
3226
3227                                         if (comp_mask_req == comp_mask_act)
3228                                                 companion_ok = true;
3229                                         else
3230                                                 return -EINVAL;
3231                                 }
3232                                 break;
3233                         }
3234                 }
3235
3236                 if (!ok)
3237                         return -EINVAL;
3238
3239                 if (companion_ok)
3240                         i++; /* companion channel already checked */
3241         }
3242
3243         return 0;
3244 }
3245
3246 static int atihdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3247                                         int hdmi_slot, int stream_channel)
3248 {
3249         int verb;
3250         int ati_channel_setup = 0;
3251
3252         if (hdmi_slot > 7)
3253                 return -EINVAL;
3254
3255         if (!has_amd_full_remap_support(codec)) {
3256                 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3257
3258                 /* In case this is an odd slot but without stream channel, do not
3259                  * disable the slot since the corresponding even slot could have a
3260                  * channel. In case neither have a channel, the slot pair will be
3261                  * disabled when this function is called for the even slot. */
3262                 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3263                         return 0;
3264
3265                 hdmi_slot -= hdmi_slot % 2;
3266
3267                 if (stream_channel != 0xf)
3268                         stream_channel -= stream_channel % 2;
3269         }
3270
3271         verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3272
3273         /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3274
3275         if (stream_channel != 0xf)
3276                 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3277
3278         return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3279 }
3280
3281 static int atihdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3282                                         int asp_slot)
3283 {
3284         bool was_odd = false;
3285         int ati_asp_slot = asp_slot;
3286         int verb;
3287         int ati_channel_setup;
3288
3289         if (asp_slot > 7)
3290                 return -EINVAL;
3291
3292         if (!has_amd_full_remap_support(codec)) {
3293                 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3294                 if (ati_asp_slot % 2 != 0) {
3295                         ati_asp_slot -= 1;
3296                         was_odd = true;
3297                 }
3298         }
3299
3300         verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3301
3302         ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3303
3304         if (!(ati_channel_setup & ATI_OUT_ENABLE))
3305                 return 0xf;
3306
3307         return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3308 }
3309
3310 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
3311                                                             int channels)
3312 {
3313         int c;
3314
3315         /*
3316          * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3317          * we need to take that into account (a single channel may take 2
3318          * channel slots if we need to carry a silent channel next to it).
3319          * On Rev3+ AMD codecs this function is not used.
3320          */
3321         int chanpairs = 0;
3322
3323         /* We only produce even-numbered channel count TLVs */
3324         if ((channels % 2) != 0)
3325                 return -1;
3326
3327         for (c = 0; c < 7; c += 2) {
3328                 if (cap->speakers[c] || cap->speakers[c+1])
3329                         chanpairs++;
3330         }
3331
3332         if (chanpairs * 2 != channels)
3333                 return -1;
3334
3335         return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3336 }
3337
3338 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
3339                                                   unsigned int *chmap, int channels)
3340 {
3341         /* produce paired maps for pre-rev3 ATI/AMD codecs */
3342         int count = 0;
3343         int c;
3344
3345         for (c = 7; c >= 0; c--) {
3346                 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3347                 int spk = cap->speakers[chan];
3348                 if (!spk) {
3349                         /* add N/A channel if the companion channel is occupied */
3350                         if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3351                                 chmap[count++] = SNDRV_CHMAP_NA;
3352
3353                         continue;
3354                 }
3355
3356                 chmap[count++] = spk_to_chmap(spk);
3357         }
3358
3359         WARN_ON(count != channels);
3360 }
3361
3362 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3363                                  bool hbr)
3364 {
3365         int hbr_ctl, hbr_ctl_new;
3366
3367         hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3368         if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3369                 if (hbr)
3370                         hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3371                 else
3372                         hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3373
3374                 codec_dbg(codec,
3375                           "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3376                                 pin_nid,
3377                                 hbr_ctl == hbr_ctl_new ? "" : "new-",
3378                                 hbr_ctl_new);
3379
3380                 if (hbr_ctl != hbr_ctl_new)
3381                         snd_hda_codec_write(codec, pin_nid, 0,
3382                                                 ATI_VERB_SET_HBR_CONTROL,
3383                                                 hbr_ctl_new);
3384
3385         } else if (hbr)
3386                 return -EINVAL;
3387
3388         return 0;
3389 }
3390
3391 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3392                                 hda_nid_t pin_nid, u32 stream_tag, int format)
3393 {
3394
3395         if (is_amdhdmi_rev3_or_later(codec)) {
3396                 int ramp_rate = 180; /* default as per AMD spec */
3397                 /* disable ramp-up/down for non-pcm as per AMD spec */
3398                 if (format & AC_FMT_TYPE_NON_PCM)
3399                         ramp_rate = 0;
3400
3401                 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3402         }
3403
3404         return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3405 }
3406
3407
3408 static int atihdmi_init(struct hda_codec *codec)
3409 {
3410         struct hdmi_spec *spec = codec->spec;
3411         int pin_idx, err;
3412
3413         err = generic_hdmi_init(codec);
3414
3415         if (err)
3416                 return err;
3417
3418         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3419                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3420
3421                 /* make sure downmix information in infoframe is zero */
3422                 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3423
3424                 /* enable channel-wise remap mode if supported */
3425                 if (has_amd_full_remap_support(codec))
3426                         snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3427                                             ATI_VERB_SET_MULTICHANNEL_MODE,
3428                                             ATI_MULTICHANNEL_MODE_SINGLE);
3429         }
3430
3431         return 0;
3432 }
3433
3434 static int patch_atihdmi(struct hda_codec *codec)
3435 {
3436         struct hdmi_spec *spec;
3437         struct hdmi_spec_per_cvt *per_cvt;
3438         int err, cvt_idx;
3439
3440         err = patch_generic_hdmi(codec);
3441
3442         if (err)
3443                 return err;
3444
3445         codec->patch_ops.init = atihdmi_init;
3446
3447         spec = codec->spec;
3448
3449         spec->ops.pin_get_eld = atihdmi_pin_get_eld;
3450         spec->ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3451         spec->ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3452         spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
3453         spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
3454         spec->ops.setup_stream = atihdmi_setup_stream;
3455
3456         if (!has_amd_full_remap_support(codec)) {
3457                 /* override to ATI/AMD-specific versions with pairwise mapping */
3458                 spec->ops.chmap_cea_alloc_validate_get_type =
3459                         atihdmi_paired_chmap_cea_alloc_validate_get_type;
3460                 spec->ops.cea_alloc_to_tlv_chmap = atihdmi_paired_cea_alloc_to_tlv_chmap;
3461                 spec->ops.chmap_validate = atihdmi_paired_chmap_validate;
3462         }
3463
3464         /* ATI/AMD converters do not advertise all of their capabilities */
3465         for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3466                 per_cvt = get_cvt(spec, cvt_idx);
3467                 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3468                 per_cvt->rates |= SUPPORTED_RATES;
3469                 per_cvt->formats |= SUPPORTED_FORMATS;
3470                 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3471         }
3472
3473         spec->channels_max = max(spec->channels_max, 8u);
3474
3475         return 0;
3476 }
3477
3478 /* VIA HDMI Implementation */
3479 #define VIAHDMI_CVT_NID 0x02    /* audio converter1 */
3480 #define VIAHDMI_PIN_NID 0x03    /* HDMI output pin1 */
3481
3482 static int patch_via_hdmi(struct hda_codec *codec)
3483 {
3484         return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3485 }
3486
3487 /*
3488  * patch entries
3489  */
3490 static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
3491 { .id = 0x1002793c, .name = "RS600 HDMI",       .patch = patch_atihdmi },
3492 { .id = 0x10027919, .name = "RS600 HDMI",       .patch = patch_atihdmi },
3493 { .id = 0x1002791a, .name = "RS690/780 HDMI",   .patch = patch_atihdmi },
3494 { .id = 0x1002aa01, .name = "R6xx HDMI",        .patch = patch_atihdmi },
3495 { .id = 0x10951390, .name = "SiI1390 HDMI",     .patch = patch_generic_hdmi },
3496 { .id = 0x10951392, .name = "SiI1392 HDMI",     .patch = patch_generic_hdmi },
3497 { .id = 0x17e80047, .name = "Chrontel HDMI",    .patch = patch_generic_hdmi },
3498 { .id = 0x10de0002, .name = "MCP77/78 HDMI",    .patch = patch_nvhdmi_8ch_7x },
3499 { .id = 0x10de0003, .name = "MCP77/78 HDMI",    .patch = patch_nvhdmi_8ch_7x },
3500 { .id = 0x10de0005, .name = "MCP77/78 HDMI",    .patch = patch_nvhdmi_8ch_7x },
3501 { .id = 0x10de0006, .name = "MCP77/78 HDMI",    .patch = patch_nvhdmi_8ch_7x },
3502 { .id = 0x10de0007, .name = "MCP79/7A HDMI",    .patch = patch_nvhdmi_8ch_7x },
3503 { .id = 0x10de000a, .name = "GPU 0a HDMI/DP",   .patch = patch_nvhdmi },
3504 { .id = 0x10de000b, .name = "GPU 0b HDMI/DP",   .patch = patch_nvhdmi },
3505 { .id = 0x10de000c, .name = "MCP89 HDMI",       .patch = patch_nvhdmi },
3506 { .id = 0x10de000d, .name = "GPU 0d HDMI/DP",   .patch = patch_nvhdmi },
3507 { .id = 0x10de0010, .name = "GPU 10 HDMI/DP",   .patch = patch_nvhdmi },
3508 { .id = 0x10de0011, .name = "GPU 11 HDMI/DP",   .patch = patch_nvhdmi },
3509 { .id = 0x10de0012, .name = "GPU 12 HDMI/DP",   .patch = patch_nvhdmi },
3510 { .id = 0x10de0013, .name = "GPU 13 HDMI/DP",   .patch = patch_nvhdmi },
3511 { .id = 0x10de0014, .name = "GPU 14 HDMI/DP",   .patch = patch_nvhdmi },
3512 { .id = 0x10de0015, .name = "GPU 15 HDMI/DP",   .patch = patch_nvhdmi },
3513 { .id = 0x10de0016, .name = "GPU 16 HDMI/DP",   .patch = patch_nvhdmi },
3514 /* 17 is known to be absent */
3515 { .id = 0x10de0018, .name = "GPU 18 HDMI/DP",   .patch = patch_nvhdmi },
3516 { .id = 0x10de0019, .name = "GPU 19 HDMI/DP",   .patch = patch_nvhdmi },
3517 { .id = 0x10de001a, .name = "GPU 1a HDMI/DP",   .patch = patch_nvhdmi },
3518 { .id = 0x10de001b, .name = "GPU 1b HDMI/DP",   .patch = patch_nvhdmi },
3519 { .id = 0x10de001c, .name = "GPU 1c HDMI/DP",   .patch = patch_nvhdmi },
3520 { .id = 0x10de0020, .name = "Tegra30 HDMI",     .patch = patch_tegra_hdmi },
3521 { .id = 0x10de0022, .name = "Tegra114 HDMI",    .patch = patch_tegra_hdmi },
3522 { .id = 0x10de0028, .name = "Tegra124 HDMI",    .patch = patch_tegra_hdmi },
3523 { .id = 0x10de0029, .name = "Tegra210 HDMI/DP", .patch = patch_tegra_hdmi },
3524 { .id = 0x10de0040, .name = "GPU 40 HDMI/DP",   .patch = patch_nvhdmi },
3525 { .id = 0x10de0041, .name = "GPU 41 HDMI/DP",   .patch = patch_nvhdmi },
3526 { .id = 0x10de0042, .name = "GPU 42 HDMI/DP",   .patch = patch_nvhdmi },
3527 { .id = 0x10de0043, .name = "GPU 43 HDMI/DP",   .patch = patch_nvhdmi },
3528 { .id = 0x10de0044, .name = "GPU 44 HDMI/DP",   .patch = patch_nvhdmi },
3529 { .id = 0x10de0051, .name = "GPU 51 HDMI/DP",   .patch = patch_nvhdmi },
3530 { .id = 0x10de0060, .name = "GPU 60 HDMI/DP",   .patch = patch_nvhdmi },
3531 { .id = 0x10de0067, .name = "MCP67 HDMI",       .patch = patch_nvhdmi_2ch },
3532 { .id = 0x10de0070, .name = "GPU 70 HDMI/DP",   .patch = patch_nvhdmi },
3533 { .id = 0x10de0071, .name = "GPU 71 HDMI/DP",   .patch = patch_nvhdmi },
3534 { .id = 0x10de0072, .name = "GPU 72 HDMI/DP",   .patch = patch_nvhdmi },
3535 { .id = 0x10de007d, .name = "GPU 7d HDMI/DP",   .patch = patch_nvhdmi },
3536 { .id = 0x10de8001, .name = "MCP73 HDMI",       .patch = patch_nvhdmi_2ch },
3537 { .id = 0x11069f80, .name = "VX900 HDMI/DP",    .patch = patch_via_hdmi },
3538 { .id = 0x11069f81, .name = "VX900 HDMI/DP",    .patch = patch_via_hdmi },
3539 { .id = 0x11069f84, .name = "VX11 HDMI/DP",     .patch = patch_generic_hdmi },
3540 { .id = 0x11069f85, .name = "VX11 HDMI/DP",     .patch = patch_generic_hdmi },
3541 { .id = 0x80860054, .name = "IbexPeak HDMI",    .patch = patch_generic_hdmi },
3542 { .id = 0x80862801, .name = "Bearlake HDMI",    .patch = patch_generic_hdmi },
3543 { .id = 0x80862802, .name = "Cantiga HDMI",     .patch = patch_generic_hdmi },
3544 { .id = 0x80862803, .name = "Eaglelake HDMI",   .patch = patch_generic_hdmi },
3545 { .id = 0x80862804, .name = "IbexPeak HDMI",    .patch = patch_generic_hdmi },
3546 { .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
3547 { .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
3548 { .id = 0x80862807, .name = "Haswell HDMI",     .patch = patch_generic_hdmi },
3549 { .id = 0x80862808, .name = "Broadwell HDMI",   .patch = patch_generic_hdmi },
3550 { .id = 0x80862809, .name = "Skylake HDMI",     .patch = patch_generic_hdmi },
3551 { .id = 0x8086280a, .name = "Broxton HDMI",     .patch = patch_generic_hdmi },
3552 { .id = 0x80862880, .name = "CedarTrail HDMI",  .patch = patch_generic_hdmi },
3553 { .id = 0x80862882, .name = "Valleyview2 HDMI", .patch = patch_generic_hdmi },
3554 { .id = 0x80862883, .name = "Braswell HDMI",    .patch = patch_generic_hdmi },
3555 { .id = 0x808629fb, .name = "Crestline HDMI",   .patch = patch_generic_hdmi },
3556 /* special ID for generic HDMI */
3557 { .id = HDA_CODEC_ID_GENERIC_HDMI, .patch = patch_generic_hdmi },
3558 {} /* terminator */
3559 };
3560
3561 MODULE_ALIAS("snd-hda-codec-id:1002793c");
3562 MODULE_ALIAS("snd-hda-codec-id:10027919");
3563 MODULE_ALIAS("snd-hda-codec-id:1002791a");
3564 MODULE_ALIAS("snd-hda-codec-id:1002aa01");
3565 MODULE_ALIAS("snd-hda-codec-id:10951390");
3566 MODULE_ALIAS("snd-hda-codec-id:10951392");
3567 MODULE_ALIAS("snd-hda-codec-id:10de0002");
3568 MODULE_ALIAS("snd-hda-codec-id:10de0003");
3569 MODULE_ALIAS("snd-hda-codec-id:10de0005");
3570 MODULE_ALIAS("snd-hda-codec-id:10de0006");
3571 MODULE_ALIAS("snd-hda-codec-id:10de0007");
3572 MODULE_ALIAS("snd-hda-codec-id:10de000a");
3573 MODULE_ALIAS("snd-hda-codec-id:10de000b");
3574 MODULE_ALIAS("snd-hda-codec-id:10de000c");
3575 MODULE_ALIAS("snd-hda-codec-id:10de000d");
3576 MODULE_ALIAS("snd-hda-codec-id:10de0010");
3577 MODULE_ALIAS("snd-hda-codec-id:10de0011");
3578 MODULE_ALIAS("snd-hda-codec-id:10de0012");
3579 MODULE_ALIAS("snd-hda-codec-id:10de0013");
3580 MODULE_ALIAS("snd-hda-codec-id:10de0014");
3581 MODULE_ALIAS("snd-hda-codec-id:10de0015");
3582 MODULE_ALIAS("snd-hda-codec-id:10de0016");
3583 MODULE_ALIAS("snd-hda-codec-id:10de0018");
3584 MODULE_ALIAS("snd-hda-codec-id:10de0019");
3585 MODULE_ALIAS("snd-hda-codec-id:10de001a");
3586 MODULE_ALIAS("snd-hda-codec-id:10de001b");
3587 MODULE_ALIAS("snd-hda-codec-id:10de001c");
3588 MODULE_ALIAS("snd-hda-codec-id:10de0028");
3589 MODULE_ALIAS("snd-hda-codec-id:10de0040");
3590 MODULE_ALIAS("snd-hda-codec-id:10de0041");
3591 MODULE_ALIAS("snd-hda-codec-id:10de0042");
3592 MODULE_ALIAS("snd-hda-codec-id:10de0043");
3593 MODULE_ALIAS("snd-hda-codec-id:10de0044");
3594 MODULE_ALIAS("snd-hda-codec-id:10de0051");
3595 MODULE_ALIAS("snd-hda-codec-id:10de0060");
3596 MODULE_ALIAS("snd-hda-codec-id:10de0067");
3597 MODULE_ALIAS("snd-hda-codec-id:10de0070");
3598 MODULE_ALIAS("snd-hda-codec-id:10de0071");
3599 MODULE_ALIAS("snd-hda-codec-id:10de0072");
3600 MODULE_ALIAS("snd-hda-codec-id:10de007d");
3601 MODULE_ALIAS("snd-hda-codec-id:10de8001");
3602 MODULE_ALIAS("snd-hda-codec-id:11069f80");
3603 MODULE_ALIAS("snd-hda-codec-id:11069f81");
3604 MODULE_ALIAS("snd-hda-codec-id:11069f84");
3605 MODULE_ALIAS("snd-hda-codec-id:11069f85");
3606 MODULE_ALIAS("snd-hda-codec-id:17e80047");
3607 MODULE_ALIAS("snd-hda-codec-id:80860054");
3608 MODULE_ALIAS("snd-hda-codec-id:80862801");
3609 MODULE_ALIAS("snd-hda-codec-id:80862802");
3610 MODULE_ALIAS("snd-hda-codec-id:80862803");
3611 MODULE_ALIAS("snd-hda-codec-id:80862804");
3612 MODULE_ALIAS("snd-hda-codec-id:80862805");
3613 MODULE_ALIAS("snd-hda-codec-id:80862806");
3614 MODULE_ALIAS("snd-hda-codec-id:80862807");
3615 MODULE_ALIAS("snd-hda-codec-id:80862808");
3616 MODULE_ALIAS("snd-hda-codec-id:80862809");
3617 MODULE_ALIAS("snd-hda-codec-id:8086280a");
3618 MODULE_ALIAS("snd-hda-codec-id:80862880");
3619 MODULE_ALIAS("snd-hda-codec-id:80862882");
3620 MODULE_ALIAS("snd-hda-codec-id:80862883");
3621 MODULE_ALIAS("snd-hda-codec-id:808629fb");
3622
3623 MODULE_LICENSE("GPL");
3624 MODULE_DESCRIPTION("HDMI HD-audio codec");
3625 MODULE_ALIAS("snd-hda-codec-intelhdmi");
3626 MODULE_ALIAS("snd-hda-codec-nvhdmi");
3627 MODULE_ALIAS("snd-hda-codec-atihdmi");
3628
3629 static struct hda_codec_driver hdmi_driver = {
3630         .preset = snd_hda_preset_hdmi,
3631 };
3632
3633 module_hda_codec_driver(hdmi_driver);