2 * rt5665.c -- RT5665/RT5658 ALSA SoC audio codec driver
4 * Copyright 2016 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
17 #include <linux/i2c.h>
18 #include <linux/platform_device.h>
19 #include <linux/spi/spi.h>
20 #include <linux/acpi.h>
21 #include <linux/gpio.h>
22 #include <linux/of_gpio.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/mutex.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/jack.h>
29 #include <sound/soc.h>
30 #include <sound/soc-dapm.h>
31 #include <sound/initval.h>
32 #include <sound/tlv.h>
33 #include <sound/rt5665.h>
38 #define RT5665_NUM_SUPPLIES 3
40 static const char *rt5665_supply_names[RT5665_NUM_SUPPLIES] = {
47 struct snd_soc_codec *codec;
48 struct rt5665_platform_data pdata;
49 struct regmap *regmap;
50 struct gpio_desc *gpiod_ldo1_en;
51 struct gpio_desc *gpiod_reset;
52 struct snd_soc_jack *hs_jack;
53 struct regulator_bulk_data supplies[RT5665_NUM_SUPPLIES];
54 struct delayed_work jack_detect_work;
55 struct delayed_work calibrate_work;
56 struct delayed_work jd_check_work;
57 struct mutex calibrate_mutex;
61 int lrck[RT5665_AIFS];
62 int bclk[RT5665_AIFS];
63 int master[RT5665_AIFS];
71 int irq_work_delay_time;
72 unsigned int sar_adc_value;
75 static const struct reg_default rt5665_reg[] = {
466 static bool rt5665_volatile_register(struct device *dev, unsigned int reg)
470 case RT5665_EJD_CTRL_2:
471 case RT5665_GPIO_STA:
472 case RT5665_INT_ST_1:
473 case RT5665_IL_CMD_1:
474 case RT5665_4BTN_IL_CMD_1:
475 case RT5665_PSV_IL_CMD_1:
476 case RT5665_AJD1_CTRL:
477 case RT5665_JD_CTRL_3:
478 case RT5665_STO_NG2_CTRL_1:
479 case RT5665_SAR_IL_CMD_4:
480 case RT5665_DEVICE_ID:
481 case RT5665_STO1_DAC_SIL_DET ... RT5665_STO2_DAC_SIL_DET:
482 case RT5665_MONO_AMP_CALIB_STA1 ... RT5665_MONO_AMP_CALIB_STA6:
483 case RT5665_HP_IMP_SENS_CTRL_12 ... RT5665_HP_IMP_SENS_CTRL_15:
484 case RT5665_HP_CALIB_STA_1 ... RT5665_HP_CALIB_STA_11:
491 static bool rt5665_readable_register(struct device *dev, unsigned int reg)
495 case RT5665_VENDOR_ID:
496 case RT5665_VENDOR_ID_1:
497 case RT5665_DEVICE_ID:
499 case RT5665_HP_CTRL_1:
500 case RT5665_HP_CTRL_2:
501 case RT5665_MONO_OUT:
502 case RT5665_HPL_GAIN:
503 case RT5665_HPR_GAIN:
504 case RT5665_MONO_GAIN:
505 case RT5665_CAL_BST_CTRL:
506 case RT5665_CBJ_BST_CTRL:
509 case RT5665_INL1_INR1_VOL:
510 case RT5665_EJD_CTRL_1:
511 case RT5665_EJD_CTRL_2:
512 case RT5665_EJD_CTRL_3:
513 case RT5665_EJD_CTRL_4:
514 case RT5665_EJD_CTRL_5:
515 case RT5665_EJD_CTRL_6:
516 case RT5665_EJD_CTRL_7:
517 case RT5665_DAC2_CTRL:
518 case RT5665_DAC2_DIG_VOL:
519 case RT5665_DAC1_DIG_VOL:
520 case RT5665_DAC3_DIG_VOL:
521 case RT5665_DAC3_CTRL:
522 case RT5665_STO1_ADC_DIG_VOL:
523 case RT5665_MONO_ADC_DIG_VOL:
524 case RT5665_STO2_ADC_DIG_VOL:
525 case RT5665_STO1_ADC_BOOST:
526 case RT5665_MONO_ADC_BOOST:
527 case RT5665_STO2_ADC_BOOST:
528 case RT5665_HP_IMP_GAIN_1:
529 case RT5665_HP_IMP_GAIN_2:
530 case RT5665_STO1_ADC_MIXER:
531 case RT5665_MONO_ADC_MIXER:
532 case RT5665_STO2_ADC_MIXER:
533 case RT5665_AD_DA_MIXER:
534 case RT5665_STO1_DAC_MIXER:
535 case RT5665_MONO_DAC_MIXER:
536 case RT5665_STO2_DAC_MIXER:
537 case RT5665_A_DAC1_MUX:
538 case RT5665_A_DAC2_MUX:
539 case RT5665_DIG_INF2_DATA:
540 case RT5665_DIG_INF3_DATA:
541 case RT5665_PDM_OUT_CTRL:
542 case RT5665_PDM_DATA_CTRL_1:
543 case RT5665_PDM_DATA_CTRL_2:
544 case RT5665_PDM_DATA_CTRL_3:
545 case RT5665_PDM_DATA_CTRL_4:
546 case RT5665_REC1_GAIN:
547 case RT5665_REC1_L1_MIXER:
548 case RT5665_REC1_L2_MIXER:
549 case RT5665_REC1_R1_MIXER:
550 case RT5665_REC1_R2_MIXER:
551 case RT5665_REC2_GAIN:
552 case RT5665_REC2_L1_MIXER:
553 case RT5665_REC2_L2_MIXER:
554 case RT5665_REC2_R1_MIXER:
555 case RT5665_REC2_R2_MIXER:
557 case RT5665_ALC_BACK_GAIN:
558 case RT5665_MONOMIX_GAIN:
559 case RT5665_MONOMIX_IN_GAIN:
560 case RT5665_OUT_L_GAIN:
561 case RT5665_OUT_L_MIXER:
562 case RT5665_OUT_R_GAIN:
563 case RT5665_OUT_R_MIXER:
564 case RT5665_LOUT_MIXER:
565 case RT5665_PWR_DIG_1:
566 case RT5665_PWR_DIG_2:
567 case RT5665_PWR_ANLG_1:
568 case RT5665_PWR_ANLG_2:
569 case RT5665_PWR_ANLG_3:
570 case RT5665_PWR_MIXER:
573 case RT5665_HPF_CTRL1:
574 case RT5665_DMIC_CTRL_1:
575 case RT5665_DMIC_CTRL_2:
576 case RT5665_I2S1_SDP:
577 case RT5665_I2S2_SDP:
578 case RT5665_I2S3_SDP:
579 case RT5665_ADDA_CLK_1:
580 case RT5665_ADDA_CLK_2:
581 case RT5665_I2S1_F_DIV_CTRL_1:
582 case RT5665_I2S1_F_DIV_CTRL_2:
583 case RT5665_TDM_CTRL_1:
584 case RT5665_TDM_CTRL_2:
585 case RT5665_TDM_CTRL_3:
586 case RT5665_TDM_CTRL_4:
587 case RT5665_TDM_CTRL_5:
588 case RT5665_TDM_CTRL_6:
589 case RT5665_TDM_CTRL_7:
590 case RT5665_TDM_CTRL_8:
592 case RT5665_PLL_CTRL_1:
593 case RT5665_PLL_CTRL_2:
606 case RT5665_HP_CHARGE_PUMP_1:
607 case RT5665_HP_CHARGE_PUMP_2:
608 case RT5665_MICBIAS_1:
609 case RT5665_MICBIAS_2:
613 case RT5665_RC_CLK_CTRL:
614 case RT5665_I2S_M_CLK_CTRL_1:
615 case RT5665_I2S2_F_DIV_CTRL_1:
616 case RT5665_I2S2_F_DIV_CTRL_2:
617 case RT5665_I2S3_F_DIV_CTRL_1:
618 case RT5665_I2S3_F_DIV_CTRL_2:
619 case RT5665_EQ_CTRL_1:
620 case RT5665_EQ_CTRL_2:
621 case RT5665_IRQ_CTRL_1:
622 case RT5665_IRQ_CTRL_2:
623 case RT5665_IRQ_CTRL_3:
624 case RT5665_IRQ_CTRL_4:
625 case RT5665_IRQ_CTRL_5:
626 case RT5665_IRQ_CTRL_6:
627 case RT5665_INT_ST_1:
628 case RT5665_GPIO_CTRL_1:
629 case RT5665_GPIO_CTRL_2:
630 case RT5665_GPIO_CTRL_3:
631 case RT5665_GPIO_CTRL_4:
632 case RT5665_GPIO_STA:
633 case RT5665_HP_AMP_DET_CTRL_1:
634 case RT5665_HP_AMP_DET_CTRL_2:
635 case RT5665_MID_HP_AMP_DET:
636 case RT5665_LOW_HP_AMP_DET:
637 case RT5665_SV_ZCD_1:
638 case RT5665_SV_ZCD_2:
639 case RT5665_IL_CMD_1:
640 case RT5665_IL_CMD_2:
641 case RT5665_IL_CMD_3:
642 case RT5665_IL_CMD_4:
643 case RT5665_4BTN_IL_CMD_1:
644 case RT5665_4BTN_IL_CMD_2:
645 case RT5665_4BTN_IL_CMD_3:
646 case RT5665_PSV_IL_CMD_1:
647 case RT5665_ADC_STO1_HP_CTRL_1:
648 case RT5665_ADC_STO1_HP_CTRL_2:
649 case RT5665_ADC_MONO_HP_CTRL_1:
650 case RT5665_ADC_MONO_HP_CTRL_2:
651 case RT5665_ADC_STO2_HP_CTRL_1:
652 case RT5665_ADC_STO2_HP_CTRL_2:
653 case RT5665_AJD1_CTRL:
656 case RT5665_JD_CTRL_1:
657 case RT5665_JD_CTRL_2:
658 case RT5665_JD_CTRL_3:
659 case RT5665_DIG_MISC:
662 case RT5665_DAC_ADC_DIG_VOL1:
663 case RT5665_DAC_ADC_DIG_VOL2:
664 case RT5665_BIAS_CUR_CTRL_1:
665 case RT5665_BIAS_CUR_CTRL_2:
666 case RT5665_BIAS_CUR_CTRL_3:
667 case RT5665_BIAS_CUR_CTRL_4:
668 case RT5665_BIAS_CUR_CTRL_5:
669 case RT5665_BIAS_CUR_CTRL_6:
670 case RT5665_BIAS_CUR_CTRL_7:
671 case RT5665_BIAS_CUR_CTRL_8:
672 case RT5665_BIAS_CUR_CTRL_9:
673 case RT5665_BIAS_CUR_CTRL_10:
674 case RT5665_VREF_REC_OP_FB_CAP_CTRL:
675 case RT5665_CHARGE_PUMP_1:
676 case RT5665_DIG_IN_CTRL_1:
677 case RT5665_DIG_IN_CTRL_2:
678 case RT5665_PAD_DRIVING_CTRL:
679 case RT5665_SOFT_RAMP_DEPOP:
681 case RT5665_CHOP_DAC:
682 case RT5665_CHOP_ADC:
683 case RT5665_CALIB_ADC_CTRL:
684 case RT5665_VOL_TEST:
685 case RT5665_TEST_MODE_CTRL_1:
686 case RT5665_TEST_MODE_CTRL_2:
687 case RT5665_TEST_MODE_CTRL_3:
688 case RT5665_TEST_MODE_CTRL_4:
689 case RT5665_BASSBACK_CTRL:
690 case RT5665_STO_NG2_CTRL_1:
691 case RT5665_STO_NG2_CTRL_2:
692 case RT5665_STO_NG2_CTRL_3:
693 case RT5665_STO_NG2_CTRL_4:
694 case RT5665_STO_NG2_CTRL_5:
695 case RT5665_STO_NG2_CTRL_6:
696 case RT5665_STO_NG2_CTRL_7:
697 case RT5665_STO_NG2_CTRL_8:
698 case RT5665_MONO_NG2_CTRL_1:
699 case RT5665_MONO_NG2_CTRL_2:
700 case RT5665_MONO_NG2_CTRL_3:
701 case RT5665_MONO_NG2_CTRL_4:
702 case RT5665_MONO_NG2_CTRL_5:
703 case RT5665_MONO_NG2_CTRL_6:
704 case RT5665_STO1_DAC_SIL_DET:
705 case RT5665_MONOL_DAC_SIL_DET:
706 case RT5665_MONOR_DAC_SIL_DET:
707 case RT5665_STO2_DAC_SIL_DET:
708 case RT5665_SIL_PSV_CTRL1:
709 case RT5665_SIL_PSV_CTRL2:
710 case RT5665_SIL_PSV_CTRL3:
711 case RT5665_SIL_PSV_CTRL4:
712 case RT5665_SIL_PSV_CTRL5:
713 case RT5665_SIL_PSV_CTRL6:
714 case RT5665_MONO_AMP_CALIB_CTRL_1:
715 case RT5665_MONO_AMP_CALIB_CTRL_2:
716 case RT5665_MONO_AMP_CALIB_CTRL_3:
717 case RT5665_MONO_AMP_CALIB_CTRL_4:
718 case RT5665_MONO_AMP_CALIB_CTRL_5:
719 case RT5665_MONO_AMP_CALIB_CTRL_6:
720 case RT5665_MONO_AMP_CALIB_CTRL_7:
721 case RT5665_MONO_AMP_CALIB_STA1:
722 case RT5665_MONO_AMP_CALIB_STA2:
723 case RT5665_MONO_AMP_CALIB_STA3:
724 case RT5665_MONO_AMP_CALIB_STA4:
725 case RT5665_MONO_AMP_CALIB_STA6:
726 case RT5665_HP_IMP_SENS_CTRL_01:
727 case RT5665_HP_IMP_SENS_CTRL_02:
728 case RT5665_HP_IMP_SENS_CTRL_03:
729 case RT5665_HP_IMP_SENS_CTRL_04:
730 case RT5665_HP_IMP_SENS_CTRL_05:
731 case RT5665_HP_IMP_SENS_CTRL_06:
732 case RT5665_HP_IMP_SENS_CTRL_07:
733 case RT5665_HP_IMP_SENS_CTRL_08:
734 case RT5665_HP_IMP_SENS_CTRL_09:
735 case RT5665_HP_IMP_SENS_CTRL_10:
736 case RT5665_HP_IMP_SENS_CTRL_11:
737 case RT5665_HP_IMP_SENS_CTRL_12:
738 case RT5665_HP_IMP_SENS_CTRL_13:
739 case RT5665_HP_IMP_SENS_CTRL_14:
740 case RT5665_HP_IMP_SENS_CTRL_15:
741 case RT5665_HP_IMP_SENS_CTRL_16:
742 case RT5665_HP_IMP_SENS_CTRL_17:
743 case RT5665_HP_IMP_SENS_CTRL_18:
744 case RT5665_HP_IMP_SENS_CTRL_19:
745 case RT5665_HP_IMP_SENS_CTRL_20:
746 case RT5665_HP_IMP_SENS_CTRL_21:
747 case RT5665_HP_IMP_SENS_CTRL_22:
748 case RT5665_HP_IMP_SENS_CTRL_23:
749 case RT5665_HP_IMP_SENS_CTRL_24:
750 case RT5665_HP_IMP_SENS_CTRL_25:
751 case RT5665_HP_IMP_SENS_CTRL_26:
752 case RT5665_HP_IMP_SENS_CTRL_27:
753 case RT5665_HP_IMP_SENS_CTRL_28:
754 case RT5665_HP_IMP_SENS_CTRL_29:
755 case RT5665_HP_IMP_SENS_CTRL_30:
756 case RT5665_HP_IMP_SENS_CTRL_31:
757 case RT5665_HP_IMP_SENS_CTRL_32:
758 case RT5665_HP_IMP_SENS_CTRL_33:
759 case RT5665_HP_IMP_SENS_CTRL_34:
760 case RT5665_HP_LOGIC_CTRL_1:
761 case RT5665_HP_LOGIC_CTRL_2:
762 case RT5665_HP_LOGIC_CTRL_3:
763 case RT5665_HP_CALIB_CTRL_1:
764 case RT5665_HP_CALIB_CTRL_2:
765 case RT5665_HP_CALIB_CTRL_3:
766 case RT5665_HP_CALIB_CTRL_4:
767 case RT5665_HP_CALIB_CTRL_5:
768 case RT5665_HP_CALIB_CTRL_6:
769 case RT5665_HP_CALIB_CTRL_7:
770 case RT5665_HP_CALIB_CTRL_9:
771 case RT5665_HP_CALIB_CTRL_10:
772 case RT5665_HP_CALIB_CTRL_11:
773 case RT5665_HP_CALIB_STA_1:
774 case RT5665_HP_CALIB_STA_2:
775 case RT5665_HP_CALIB_STA_3:
776 case RT5665_HP_CALIB_STA_4:
777 case RT5665_HP_CALIB_STA_5:
778 case RT5665_HP_CALIB_STA_6:
779 case RT5665_HP_CALIB_STA_7:
780 case RT5665_HP_CALIB_STA_8:
781 case RT5665_HP_CALIB_STA_9:
782 case RT5665_HP_CALIB_STA_10:
783 case RT5665_HP_CALIB_STA_11:
784 case RT5665_PGM_TAB_CTRL1:
785 case RT5665_PGM_TAB_CTRL2:
786 case RT5665_PGM_TAB_CTRL3:
787 case RT5665_PGM_TAB_CTRL4:
788 case RT5665_PGM_TAB_CTRL5:
789 case RT5665_PGM_TAB_CTRL6:
790 case RT5665_PGM_TAB_CTRL7:
791 case RT5665_PGM_TAB_CTRL8:
792 case RT5665_PGM_TAB_CTRL9:
793 case RT5665_SAR_IL_CMD_1:
794 case RT5665_SAR_IL_CMD_2:
795 case RT5665_SAR_IL_CMD_3:
796 case RT5665_SAR_IL_CMD_4:
797 case RT5665_SAR_IL_CMD_5:
798 case RT5665_SAR_IL_CMD_6:
799 case RT5665_SAR_IL_CMD_7:
800 case RT5665_SAR_IL_CMD_8:
801 case RT5665_SAR_IL_CMD_9:
802 case RT5665_SAR_IL_CMD_10:
803 case RT5665_SAR_IL_CMD_11:
804 case RT5665_SAR_IL_CMD_12:
805 case RT5665_DRC1_CTRL_0:
806 case RT5665_DRC1_CTRL_1:
807 case RT5665_DRC1_CTRL_2:
808 case RT5665_DRC1_CTRL_3:
809 case RT5665_DRC1_CTRL_4:
810 case RT5665_DRC1_CTRL_5:
811 case RT5665_DRC1_CTRL_6:
812 case RT5665_DRC1_HARD_LMT_CTRL_1:
813 case RT5665_DRC1_HARD_LMT_CTRL_2:
814 case RT5665_DRC1_PRIV_1:
815 case RT5665_DRC1_PRIV_2:
816 case RT5665_DRC1_PRIV_3:
817 case RT5665_DRC1_PRIV_4:
818 case RT5665_DRC1_PRIV_5:
819 case RT5665_DRC1_PRIV_6:
820 case RT5665_DRC1_PRIV_7:
821 case RT5665_DRC1_PRIV_8:
822 case RT5665_ALC_PGA_CTRL_1:
823 case RT5665_ALC_PGA_CTRL_2:
824 case RT5665_ALC_PGA_CTRL_3:
825 case RT5665_ALC_PGA_CTRL_4:
826 case RT5665_ALC_PGA_CTRL_5:
827 case RT5665_ALC_PGA_CTRL_6:
828 case RT5665_ALC_PGA_CTRL_7:
829 case RT5665_ALC_PGA_CTRL_8:
830 case RT5665_ALC_PGA_STA_1:
831 case RT5665_ALC_PGA_STA_2:
832 case RT5665_ALC_PGA_STA_3:
833 case RT5665_EQ_AUTO_RCV_CTRL1:
834 case RT5665_EQ_AUTO_RCV_CTRL2:
835 case RT5665_EQ_AUTO_RCV_CTRL3:
836 case RT5665_EQ_AUTO_RCV_CTRL4:
837 case RT5665_EQ_AUTO_RCV_CTRL5:
838 case RT5665_EQ_AUTO_RCV_CTRL6:
839 case RT5665_EQ_AUTO_RCV_CTRL7:
840 case RT5665_EQ_AUTO_RCV_CTRL8:
841 case RT5665_EQ_AUTO_RCV_CTRL9:
842 case RT5665_EQ_AUTO_RCV_CTRL10:
843 case RT5665_EQ_AUTO_RCV_CTRL11:
844 case RT5665_EQ_AUTO_RCV_CTRL12:
845 case RT5665_EQ_AUTO_RCV_CTRL13:
846 case RT5665_ADC_L_EQ_LPF1_A1:
847 case RT5665_R_EQ_LPF1_A1:
848 case RT5665_L_EQ_LPF1_H0:
849 case RT5665_R_EQ_LPF1_H0:
850 case RT5665_L_EQ_BPF1_A1:
851 case RT5665_R_EQ_BPF1_A1:
852 case RT5665_L_EQ_BPF1_A2:
853 case RT5665_R_EQ_BPF1_A2:
854 case RT5665_L_EQ_BPF1_H0:
855 case RT5665_R_EQ_BPF1_H0:
856 case RT5665_L_EQ_BPF2_A1:
857 case RT5665_R_EQ_BPF2_A1:
858 case RT5665_L_EQ_BPF2_A2:
859 case RT5665_R_EQ_BPF2_A2:
860 case RT5665_L_EQ_BPF2_H0:
861 case RT5665_R_EQ_BPF2_H0:
862 case RT5665_L_EQ_BPF3_A1:
863 case RT5665_R_EQ_BPF3_A1:
864 case RT5665_L_EQ_BPF3_A2:
865 case RT5665_R_EQ_BPF3_A2:
866 case RT5665_L_EQ_BPF3_H0:
867 case RT5665_R_EQ_BPF3_H0:
868 case RT5665_L_EQ_BPF4_A1:
869 case RT5665_R_EQ_BPF4_A1:
870 case RT5665_L_EQ_BPF4_A2:
871 case RT5665_R_EQ_BPF4_A2:
872 case RT5665_L_EQ_BPF4_H0:
873 case RT5665_R_EQ_BPF4_H0:
874 case RT5665_L_EQ_HPF1_A1:
875 case RT5665_R_EQ_HPF1_A1:
876 case RT5665_L_EQ_HPF1_H0:
877 case RT5665_R_EQ_HPF1_H0:
878 case RT5665_L_EQ_PRE_VOL:
879 case RT5665_R_EQ_PRE_VOL:
880 case RT5665_L_EQ_POST_VOL:
881 case RT5665_R_EQ_POST_VOL:
882 case RT5665_SCAN_MODE_CTRL:
883 case RT5665_I2C_MODE:
890 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0);
891 static const DECLARE_TLV_DB_SCALE(mono_vol_tlv, -1400, 150, 0);
892 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
893 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
894 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
895 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
896 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
897 static const DECLARE_TLV_DB_SCALE(in_bst_tlv, -1200, 75, 0);
899 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
900 static const DECLARE_TLV_DB_RANGE(bst_tlv,
901 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
902 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
903 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
904 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
905 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
906 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
907 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
910 /* Interface data select */
911 static const char * const rt5665_data_select[] = {
912 "L/R", "R/L", "L/L", "R/R"
915 static const SOC_ENUM_SINGLE_DECL(rt5665_if1_1_01_adc_enum,
916 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT01_SFT, rt5665_data_select);
918 static const SOC_ENUM_SINGLE_DECL(rt5665_if1_1_23_adc_enum,
919 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT23_SFT, rt5665_data_select);
921 static const SOC_ENUM_SINGLE_DECL(rt5665_if1_1_45_adc_enum,
922 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT45_SFT, rt5665_data_select);
924 static const SOC_ENUM_SINGLE_DECL(rt5665_if1_1_67_adc_enum,
925 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT67_SFT, rt5665_data_select);
927 static const SOC_ENUM_SINGLE_DECL(rt5665_if1_2_01_adc_enum,
928 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT01_SFT, rt5665_data_select);
930 static const SOC_ENUM_SINGLE_DECL(rt5665_if1_2_23_adc_enum,
931 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT23_SFT, rt5665_data_select);
933 static const SOC_ENUM_SINGLE_DECL(rt5665_if1_2_45_adc_enum,
934 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT45_SFT, rt5665_data_select);
936 static const SOC_ENUM_SINGLE_DECL(rt5665_if1_2_67_adc_enum,
937 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT67_SFT, rt5665_data_select);
939 static const SOC_ENUM_SINGLE_DECL(rt5665_if2_1_dac_enum,
940 RT5665_DIG_INF2_DATA, RT5665_IF2_1_DAC_SEL_SFT, rt5665_data_select);
942 static const SOC_ENUM_SINGLE_DECL(rt5665_if2_1_adc_enum,
943 RT5665_DIG_INF2_DATA, RT5665_IF2_1_ADC_SEL_SFT, rt5665_data_select);
945 static const SOC_ENUM_SINGLE_DECL(rt5665_if2_2_dac_enum,
946 RT5665_DIG_INF2_DATA, RT5665_IF2_2_DAC_SEL_SFT, rt5665_data_select);
948 static const SOC_ENUM_SINGLE_DECL(rt5665_if2_2_adc_enum,
949 RT5665_DIG_INF2_DATA, RT5665_IF2_2_ADC_SEL_SFT, rt5665_data_select);
951 static const SOC_ENUM_SINGLE_DECL(rt5665_if3_dac_enum,
952 RT5665_DIG_INF3_DATA, RT5665_IF3_DAC_SEL_SFT, rt5665_data_select);
954 static const SOC_ENUM_SINGLE_DECL(rt5665_if3_adc_enum,
955 RT5665_DIG_INF3_DATA, RT5665_IF3_ADC_SEL_SFT, rt5665_data_select);
957 static const struct snd_kcontrol_new rt5665_if1_1_01_adc_swap_mux =
958 SOC_DAPM_ENUM("IF1_1 01 ADC Swap Mux", rt5665_if1_1_01_adc_enum);
960 static const struct snd_kcontrol_new rt5665_if1_1_23_adc_swap_mux =
961 SOC_DAPM_ENUM("IF1_1 23 ADC Swap Mux", rt5665_if1_1_23_adc_enum);
963 static const struct snd_kcontrol_new rt5665_if1_1_45_adc_swap_mux =
964 SOC_DAPM_ENUM("IF1_1 45 ADC Swap Mux", rt5665_if1_1_45_adc_enum);
966 static const struct snd_kcontrol_new rt5665_if1_1_67_adc_swap_mux =
967 SOC_DAPM_ENUM("IF1_1 67 ADC Swap Mux", rt5665_if1_1_67_adc_enum);
969 static const struct snd_kcontrol_new rt5665_if1_2_01_adc_swap_mux =
970 SOC_DAPM_ENUM("IF1_2 01 ADC Swap Mux", rt5665_if1_2_01_adc_enum);
972 static const struct snd_kcontrol_new rt5665_if1_2_23_adc_swap_mux =
973 SOC_DAPM_ENUM("IF1_2 23 ADC1 Swap Mux", rt5665_if1_2_23_adc_enum);
975 static const struct snd_kcontrol_new rt5665_if1_2_45_adc_swap_mux =
976 SOC_DAPM_ENUM("IF1_2 45 ADC1 Swap Mux", rt5665_if1_2_45_adc_enum);
978 static const struct snd_kcontrol_new rt5665_if1_2_67_adc_swap_mux =
979 SOC_DAPM_ENUM("IF1_2 67 ADC1 Swap Mux", rt5665_if1_2_67_adc_enum);
981 static const struct snd_kcontrol_new rt5665_if2_1_dac_swap_mux =
982 SOC_DAPM_ENUM("IF2_1 DAC Swap Source", rt5665_if2_1_dac_enum);
984 static const struct snd_kcontrol_new rt5665_if2_1_adc_swap_mux =
985 SOC_DAPM_ENUM("IF2_1 ADC Swap Source", rt5665_if2_1_adc_enum);
987 static const struct snd_kcontrol_new rt5665_if2_2_dac_swap_mux =
988 SOC_DAPM_ENUM("IF2_2 DAC Swap Source", rt5665_if2_2_dac_enum);
990 static const struct snd_kcontrol_new rt5665_if2_2_adc_swap_mux =
991 SOC_DAPM_ENUM("IF2_2 ADC Swap Source", rt5665_if2_2_adc_enum);
993 static const struct snd_kcontrol_new rt5665_if3_dac_swap_mux =
994 SOC_DAPM_ENUM("IF3 DAC Swap Source", rt5665_if3_dac_enum);
996 static const struct snd_kcontrol_new rt5665_if3_adc_swap_mux =
997 SOC_DAPM_ENUM("IF3 ADC Swap Source", rt5665_if3_adc_enum);
999 static int rt5665_hp_vol_put(struct snd_kcontrol *kcontrol,
1000 struct snd_ctl_elem_value *ucontrol)
1002 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1003 int ret = snd_soc_put_volsw(kcontrol, ucontrol);
1005 if (snd_soc_read(codec, RT5665_STO_NG2_CTRL_1) & RT5665_NG2_EN) {
1006 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
1007 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
1008 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
1009 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
1015 static int rt5665_mono_vol_put(struct snd_kcontrol *kcontrol,
1016 struct snd_ctl_elem_value *ucontrol)
1018 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1019 int ret = snd_soc_put_volsw(kcontrol, ucontrol);
1021 if (snd_soc_read(codec, RT5665_MONO_NG2_CTRL_1) & RT5665_NG2_EN) {
1022 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
1023 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
1024 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
1025 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
1032 * rt5665_sel_asrc_clk_src - select ASRC clock source for a set of filters
1033 * @codec: SoC audio codec device.
1034 * @filter_mask: mask of filters.
1035 * @clk_src: clock source
1037 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5665 can
1038 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1039 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1040 * ASRC function will track i2s clock and generate a corresponding system clock
1041 * for codec. This function provides an API to select the clock source for a
1042 * set of filters specified by the mask. And the codec driver will turn on ASRC
1043 * for these filters if ASRC is selected as their clock source.
1045 int rt5665_sel_asrc_clk_src(struct snd_soc_codec *codec,
1046 unsigned int filter_mask, unsigned int clk_src)
1048 unsigned int asrc2_mask = 0;
1049 unsigned int asrc2_value = 0;
1050 unsigned int asrc3_mask = 0;
1051 unsigned int asrc3_value = 0;
1054 case RT5665_CLK_SEL_SYS:
1055 case RT5665_CLK_SEL_I2S1_ASRC:
1056 case RT5665_CLK_SEL_I2S2_ASRC:
1057 case RT5665_CLK_SEL_I2S3_ASRC:
1058 case RT5665_CLK_SEL_SYS2:
1059 case RT5665_CLK_SEL_SYS3:
1060 case RT5665_CLK_SEL_SYS4:
1067 if (filter_mask & RT5665_DA_STEREO1_FILTER) {
1068 asrc2_mask |= RT5665_DA_STO1_CLK_SEL_MASK;
1069 asrc2_value = (asrc2_value & ~RT5665_DA_STO1_CLK_SEL_MASK)
1070 | (clk_src << RT5665_DA_STO1_CLK_SEL_SFT);
1073 if (filter_mask & RT5665_DA_STEREO2_FILTER) {
1074 asrc2_mask |= RT5665_DA_STO2_CLK_SEL_MASK;
1075 asrc2_value = (asrc2_value & ~RT5665_DA_STO2_CLK_SEL_MASK)
1076 | (clk_src << RT5665_DA_STO2_CLK_SEL_SFT);
1079 if (filter_mask & RT5665_DA_MONO_L_FILTER) {
1080 asrc2_mask |= RT5665_DA_MONOL_CLK_SEL_MASK;
1081 asrc2_value = (asrc2_value & ~RT5665_DA_MONOL_CLK_SEL_MASK)
1082 | (clk_src << RT5665_DA_MONOL_CLK_SEL_SFT);
1085 if (filter_mask & RT5665_DA_MONO_R_FILTER) {
1086 asrc2_mask |= RT5665_DA_MONOR_CLK_SEL_MASK;
1087 asrc2_value = (asrc2_value & ~RT5665_DA_MONOR_CLK_SEL_MASK)
1088 | (clk_src << RT5665_DA_MONOR_CLK_SEL_SFT);
1091 if (filter_mask & RT5665_AD_STEREO1_FILTER) {
1092 asrc3_mask |= RT5665_AD_STO1_CLK_SEL_MASK;
1093 asrc3_value = (asrc2_value & ~RT5665_AD_STO1_CLK_SEL_MASK)
1094 | (clk_src << RT5665_AD_STO1_CLK_SEL_SFT);
1097 if (filter_mask & RT5665_AD_STEREO2_FILTER) {
1098 asrc3_mask |= RT5665_AD_STO2_CLK_SEL_MASK;
1099 asrc3_value = (asrc2_value & ~RT5665_AD_STO2_CLK_SEL_MASK)
1100 | (clk_src << RT5665_AD_STO2_CLK_SEL_SFT);
1103 if (filter_mask & RT5665_AD_MONO_L_FILTER) {
1104 asrc3_mask |= RT5665_AD_MONOL_CLK_SEL_MASK;
1105 asrc3_value = (asrc3_value & ~RT5665_AD_MONOL_CLK_SEL_MASK)
1106 | (clk_src << RT5665_AD_MONOL_CLK_SEL_SFT);
1109 if (filter_mask & RT5665_AD_MONO_R_FILTER) {
1110 asrc3_mask |= RT5665_AD_MONOR_CLK_SEL_MASK;
1111 asrc3_value = (asrc3_value & ~RT5665_AD_MONOR_CLK_SEL_MASK)
1112 | (clk_src << RT5665_AD_MONOR_CLK_SEL_SFT);
1116 snd_soc_update_bits(codec, RT5665_ASRC_2,
1117 asrc2_mask, asrc2_value);
1120 snd_soc_update_bits(codec, RT5665_ASRC_3,
1121 asrc3_mask, asrc3_value);
1125 EXPORT_SYMBOL_GPL(rt5665_sel_asrc_clk_src);
1127 static int rt5665_button_detect(struct snd_soc_codec *codec)
1131 val = snd_soc_read(codec, RT5665_4BTN_IL_CMD_1);
1132 btn_type = val & 0xfff0;
1133 snd_soc_write(codec, RT5665_4BTN_IL_CMD_1, val);
1138 static void rt5665_enable_push_button_irq(struct snd_soc_codec *codec,
1142 snd_soc_write(codec, RT5665_4BTN_IL_CMD_1, 0x0003);
1143 snd_soc_update_bits(codec, RT5665_SAR_IL_CMD_9, 0x1, 0x1);
1144 snd_soc_write(codec, RT5665_IL_CMD_1, 0x0048);
1145 snd_soc_update_bits(codec, RT5665_4BTN_IL_CMD_2,
1146 RT5665_4BTN_IL_MASK | RT5665_4BTN_IL_RST_MASK,
1147 RT5665_4BTN_IL_EN | RT5665_4BTN_IL_NOR);
1148 snd_soc_update_bits(codec, RT5665_IRQ_CTRL_3,
1149 RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_EN);
1151 snd_soc_update_bits(codec, RT5665_IRQ_CTRL_3,
1152 RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_DIS);
1153 snd_soc_update_bits(codec, RT5665_4BTN_IL_CMD_2,
1154 RT5665_4BTN_IL_MASK, RT5665_4BTN_IL_DIS);
1155 snd_soc_update_bits(codec, RT5665_4BTN_IL_CMD_2,
1156 RT5665_4BTN_IL_RST_MASK, RT5665_4BTN_IL_RST);
1161 * rt5665_headset_detect - Detect headset.
1162 * @codec: SoC audio codec device.
1163 * @jack_insert: Jack insert or not.
1165 * Detect whether is headset or not when jack inserted.
1167 * Returns detect status.
1169 static int rt5665_headset_detect(struct snd_soc_codec *codec, int jack_insert)
1171 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
1172 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1173 unsigned int sar_hs_type, val;
1176 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
1177 snd_soc_dapm_sync(dapm);
1179 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100,
1182 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
1184 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
1187 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
1189 usleep_range(10000, 15000);
1190 regmap_read(rt5665->regmap, RT5665_GPIO_STA,
1195 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
1197 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_3, 0x3424);
1198 regmap_write(rt5665->regmap, RT5665_IL_CMD_1, 0x0048);
1199 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0xa291);
1201 usleep_range(10000, 15000);
1203 rt5665->sar_adc_value = snd_soc_read(rt5665->codec,
1204 RT5665_SAR_IL_CMD_4) & 0x7ff;
1206 sar_hs_type = rt5665->pdata.sar_hs_type ?
1207 rt5665->pdata.sar_hs_type : 729;
1209 if (rt5665->sar_adc_value > sar_hs_type) {
1210 rt5665->jack_type = SND_JACK_HEADSET;
1211 rt5665_enable_push_button_irq(codec, true);
1213 rt5665->jack_type = SND_JACK_HEADPHONE;
1214 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1,
1216 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2,
1218 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1219 snd_soc_dapm_sync(dapm);
1222 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0x2291);
1223 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100, 0);
1224 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1225 snd_soc_dapm_sync(dapm);
1226 if (rt5665->jack_type == SND_JACK_HEADSET)
1227 rt5665_enable_push_button_irq(codec, false);
1228 rt5665->jack_type = 0;
1231 dev_dbg(codec->dev, "jack_type = %d\n", rt5665->jack_type);
1232 return rt5665->jack_type;
1235 static irqreturn_t rt5665_irq(int irq, void *data)
1237 struct rt5665_priv *rt5665 = data;
1239 mod_delayed_work(system_power_efficient_wq,
1240 &rt5665->jack_detect_work, msecs_to_jiffies(250));
1245 static void rt5665_jd_check_handler(struct work_struct *work)
1247 struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv,
1248 jd_check_work.work);
1250 if (snd_soc_read(rt5665->codec, RT5665_AJD1_CTRL) & 0x0010) {
1252 rt5665->jack_type = rt5665_headset_detect(rt5665->codec, 0);
1254 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
1256 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1257 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1259 schedule_delayed_work(&rt5665->jd_check_work, 500);
1263 int rt5665_set_jack_detect(struct snd_soc_codec *codec,
1264 struct snd_soc_jack *hs_jack)
1266 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
1268 switch (rt5665->pdata.jd_src) {
1270 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
1271 RT5665_GP1_PIN_MASK, RT5665_GP1_PIN_IRQ);
1272 regmap_update_bits(rt5665->regmap, RT5665_RC_CLK_CTRL,
1274 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_2,
1275 RT5665_PWR_JD1, RT5665_PWR_JD1);
1276 regmap_update_bits(rt5665->regmap, RT5665_IRQ_CTRL_1, 0x8, 0x8);
1279 case RT5665_JD_NULL:
1283 dev_warn(codec->dev, "Wrong JD source\n");
1287 rt5665->hs_jack = hs_jack;
1291 EXPORT_SYMBOL_GPL(rt5665_set_jack_detect);
1293 static void rt5665_jack_detect_handler(struct work_struct *work)
1295 struct rt5665_priv *rt5665 =
1296 container_of(work, struct rt5665_priv, jack_detect_work.work);
1299 while (!rt5665->codec) {
1300 pr_debug("%s codec = null\n", __func__);
1301 usleep_range(10000, 15000);
1304 while (!rt5665->codec->component.card->instantiated) {
1305 pr_debug("%s\n", __func__);
1306 usleep_range(10000, 15000);
1309 mutex_lock(&rt5665->calibrate_mutex);
1311 val = snd_soc_read(rt5665->codec, RT5665_AJD1_CTRL) & 0x0010;
1314 if (rt5665->jack_type == 0) {
1315 /* jack was out, report jack type */
1317 rt5665_headset_detect(rt5665->codec, 1);
1319 /* jack is already in, report button event */
1320 rt5665->jack_type = SND_JACK_HEADSET;
1321 btn_type = rt5665_button_detect(rt5665->codec);
1323 * rt5665 can report three kinds of button behavior,
1324 * one click, double click and hold. However,
1325 * currently we will report button pressed/released
1326 * event. So all the three button behaviors are
1327 * treated as button pressed.
1333 rt5665->jack_type |= SND_JACK_BTN_0;
1338 rt5665->jack_type |= SND_JACK_BTN_1;
1343 rt5665->jack_type |= SND_JACK_BTN_2;
1348 rt5665->jack_type |= SND_JACK_BTN_3;
1350 case 0x0000: /* unpressed */
1354 dev_err(rt5665->codec->dev,
1355 "Unexpected button code 0x%04x\n",
1362 rt5665->jack_type = rt5665_headset_detect(rt5665->codec, 0);
1365 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
1367 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1368 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1370 if (rt5665->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1371 SND_JACK_BTN_2 | SND_JACK_BTN_3))
1372 schedule_delayed_work(&rt5665->jd_check_work, 0);
1374 cancel_delayed_work_sync(&rt5665->jd_check_work);
1376 mutex_unlock(&rt5665->calibrate_mutex);
1379 static const struct snd_kcontrol_new rt5665_snd_controls[] = {
1380 /* Headphone Output Volume */
1381 SOC_DOUBLE_R_EXT_TLV("Headphone Playback Volume", RT5665_HPL_GAIN,
1382 RT5665_HPR_GAIN, RT5665_G_HP_SFT, 15, 1, snd_soc_get_volsw,
1383 rt5665_hp_vol_put, hp_vol_tlv),
1385 /* Mono Output Volume */
1386 SOC_SINGLE_EXT_TLV("Mono Playback Volume", RT5665_MONO_GAIN,
1387 RT5665_L_VOL_SFT, 15, 1, snd_soc_get_volsw,
1388 rt5665_mono_vol_put, mono_vol_tlv),
1391 SOC_DOUBLE_TLV("OUT Playback Volume", RT5665_LOUT, RT5665_L_VOL_SFT,
1392 RT5665_R_VOL_SFT, 39, 1, out_vol_tlv),
1394 /* DAC Digital Volume */
1395 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5665_DAC1_DIG_VOL,
1396 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv),
1397 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5665_DAC2_DIG_VOL,
1398 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv),
1399 SOC_DOUBLE("DAC2 Playback Switch", RT5665_DAC2_CTRL,
1400 RT5665_M_DAC2_L_VOL_SFT, RT5665_M_DAC2_R_VOL_SFT, 1, 1),
1402 /* IN1/IN2/IN3/IN4 Volume */
1403 SOC_SINGLE_TLV("IN1 Boost Volume", RT5665_IN1_IN2,
1404 RT5665_BST1_SFT, 69, 0, in_bst_tlv),
1405 SOC_SINGLE_TLV("IN2 Boost Volume", RT5665_IN1_IN2,
1406 RT5665_BST2_SFT, 69, 0, in_bst_tlv),
1407 SOC_SINGLE_TLV("IN3 Boost Volume", RT5665_IN3_IN4,
1408 RT5665_BST3_SFT, 69, 0, in_bst_tlv),
1409 SOC_SINGLE_TLV("IN4 Boost Volume", RT5665_IN3_IN4,
1410 RT5665_BST4_SFT, 69, 0, in_bst_tlv),
1411 SOC_SINGLE_TLV("CBJ Boost Volume", RT5665_CBJ_BST_CTRL,
1412 RT5665_BST_CBJ_SFT, 8, 0, bst_tlv),
1414 /* INL/INR Volume Control */
1415 SOC_DOUBLE_TLV("IN Capture Volume", RT5665_INL1_INR1_VOL,
1416 RT5665_INL_VOL_SFT, RT5665_INR_VOL_SFT, 31, 1, in_vol_tlv),
1418 /* ADC Digital Volume Control */
1419 SOC_DOUBLE("STO1 ADC Capture Switch", RT5665_STO1_ADC_DIG_VOL,
1420 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1421 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5665_STO1_ADC_DIG_VOL,
1422 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1423 SOC_DOUBLE("Mono ADC Capture Switch", RT5665_MONO_ADC_DIG_VOL,
1424 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1425 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5665_MONO_ADC_DIG_VOL,
1426 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1427 SOC_DOUBLE("STO2 ADC Capture Switch", RT5665_STO2_ADC_DIG_VOL,
1428 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1429 SOC_DOUBLE_TLV("STO2 ADC Capture Volume", RT5665_STO2_ADC_DIG_VOL,
1430 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1432 /* ADC Boost Volume Control */
1433 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5665_STO1_ADC_BOOST,
1434 RT5665_STO1_ADC_L_BST_SFT, RT5665_STO1_ADC_R_BST_SFT,
1437 SOC_DOUBLE_TLV("Mono ADC Boost Gain Volume", RT5665_MONO_ADC_BOOST,
1438 RT5665_MONO_ADC_L_BST_SFT, RT5665_MONO_ADC_R_BST_SFT,
1441 SOC_DOUBLE_TLV("STO2 ADC Boost Gain Volume", RT5665_STO2_ADC_BOOST,
1442 RT5665_STO2_ADC_L_BST_SFT, RT5665_STO2_ADC_R_BST_SFT,
1447 * set_dmic_clk - Set parameter of dmic.
1450 * @kcontrol: The kcontrol of this widget.
1453 * Choose dmic clock between 1MHz and 3MHz.
1454 * It is better for clock to approximate 3MHz.
1456 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1457 struct snd_kcontrol *kcontrol, int event)
1459 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1460 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
1461 int pd, idx = -EINVAL;
1463 pd = rl6231_get_pre_div(rt5665->regmap,
1464 RT5665_ADDA_CLK_1, RT5665_I2S_PD1_SFT);
1465 idx = rl6231_calc_dmic_clk(rt5665->sysclk / pd);
1468 dev_err(codec->dev, "Failed to set DMIC clock\n");
1470 snd_soc_update_bits(codec, RT5665_DMIC_CTRL_1,
1471 RT5665_DMIC_CLK_MASK, idx << RT5665_DMIC_CLK_SFT);
1476 static int rt5665_charge_pump_event(struct snd_soc_dapm_widget *w,
1477 struct snd_kcontrol *kcontrol, int event)
1479 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1482 case SND_SOC_DAPM_PRE_PMU:
1483 snd_soc_update_bits(codec, RT5665_HP_CHARGE_PUMP_1,
1484 RT5665_PM_HP_MASK | RT5665_OSW_L_MASK,
1485 RT5665_PM_HP_HV | RT5665_OSW_L_EN);
1487 case SND_SOC_DAPM_POST_PMD:
1488 snd_soc_update_bits(codec, RT5665_HP_CHARGE_PUMP_1,
1489 RT5665_PM_HP_MASK | RT5665_OSW_L_MASK,
1490 RT5665_PM_HP_LV | RT5665_OSW_L_DIS);
1499 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
1500 struct snd_soc_dapm_widget *sink)
1503 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1505 val = snd_soc_read(codec, RT5665_GLB_CLK);
1506 val &= RT5665_SCLK_SRC_MASK;
1507 if (val == RT5665_SCLK_SRC_PLL1)
1513 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1514 struct snd_soc_dapm_widget *sink)
1516 unsigned int reg, shift, val;
1517 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1520 case RT5665_ADC_MONO_R_ASRC_SFT:
1521 reg = RT5665_ASRC_3;
1522 shift = RT5665_AD_MONOR_CLK_SEL_SFT;
1524 case RT5665_ADC_MONO_L_ASRC_SFT:
1525 reg = RT5665_ASRC_3;
1526 shift = RT5665_AD_MONOL_CLK_SEL_SFT;
1528 case RT5665_ADC_STO1_ASRC_SFT:
1529 reg = RT5665_ASRC_3;
1530 shift = RT5665_AD_STO1_CLK_SEL_SFT;
1532 case RT5665_ADC_STO2_ASRC_SFT:
1533 reg = RT5665_ASRC_3;
1534 shift = RT5665_AD_STO2_CLK_SEL_SFT;
1536 case RT5665_DAC_MONO_R_ASRC_SFT:
1537 reg = RT5665_ASRC_2;
1538 shift = RT5665_DA_MONOR_CLK_SEL_SFT;
1540 case RT5665_DAC_MONO_L_ASRC_SFT:
1541 reg = RT5665_ASRC_2;
1542 shift = RT5665_DA_MONOL_CLK_SEL_SFT;
1544 case RT5665_DAC_STO1_ASRC_SFT:
1545 reg = RT5665_ASRC_2;
1546 shift = RT5665_DA_STO1_CLK_SEL_SFT;
1548 case RT5665_DAC_STO2_ASRC_SFT:
1549 reg = RT5665_ASRC_2;
1550 shift = RT5665_DA_STO2_CLK_SEL_SFT;
1556 val = (snd_soc_read(codec, reg) >> shift) & 0xf;
1558 case RT5665_CLK_SEL_I2S1_ASRC:
1559 case RT5665_CLK_SEL_I2S2_ASRC:
1560 case RT5665_CLK_SEL_I2S3_ASRC:
1561 /* I2S_Pre_Div1 should be 1 in asrc mode */
1562 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
1563 RT5665_I2S_PD1_MASK, RT5665_I2S_PD1_2);
1572 static const struct snd_kcontrol_new rt5665_sto1_adc_l_mix[] = {
1573 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER,
1574 RT5665_M_STO1_ADC_L1_SFT, 1, 1),
1575 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER,
1576 RT5665_M_STO1_ADC_L2_SFT, 1, 1),
1579 static const struct snd_kcontrol_new rt5665_sto1_adc_r_mix[] = {
1580 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER,
1581 RT5665_M_STO1_ADC_R1_SFT, 1, 1),
1582 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER,
1583 RT5665_M_STO1_ADC_R2_SFT, 1, 1),
1586 static const struct snd_kcontrol_new rt5665_sto2_adc_l_mix[] = {
1587 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER,
1588 RT5665_M_STO2_ADC_L1_SFT, 1, 1),
1589 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER,
1590 RT5665_M_STO2_ADC_L2_SFT, 1, 1),
1593 static const struct snd_kcontrol_new rt5665_sto2_adc_r_mix[] = {
1594 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER,
1595 RT5665_M_STO2_ADC_R1_SFT, 1, 1),
1596 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER,
1597 RT5665_M_STO2_ADC_R2_SFT, 1, 1),
1600 static const struct snd_kcontrol_new rt5665_mono_adc_l_mix[] = {
1601 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER,
1602 RT5665_M_MONO_ADC_L1_SFT, 1, 1),
1603 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER,
1604 RT5665_M_MONO_ADC_L2_SFT, 1, 1),
1607 static const struct snd_kcontrol_new rt5665_mono_adc_r_mix[] = {
1608 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER,
1609 RT5665_M_MONO_ADC_R1_SFT, 1, 1),
1610 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER,
1611 RT5665_M_MONO_ADC_R2_SFT, 1, 1),
1614 static const struct snd_kcontrol_new rt5665_dac_l_mix[] = {
1615 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER,
1616 RT5665_M_ADCMIX_L_SFT, 1, 1),
1617 SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER,
1618 RT5665_M_DAC1_L_SFT, 1, 1),
1621 static const struct snd_kcontrol_new rt5665_dac_r_mix[] = {
1622 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER,
1623 RT5665_M_ADCMIX_R_SFT, 1, 1),
1624 SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER,
1625 RT5665_M_DAC1_R_SFT, 1, 1),
1628 static const struct snd_kcontrol_new rt5665_sto1_dac_l_mix[] = {
1629 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER,
1630 RT5665_M_DAC_L1_STO_L_SFT, 1, 1),
1631 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER,
1632 RT5665_M_DAC_R1_STO_L_SFT, 1, 1),
1633 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER,
1634 RT5665_M_DAC_L2_STO_L_SFT, 1, 1),
1635 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER,
1636 RT5665_M_DAC_R2_STO_L_SFT, 1, 1),
1639 static const struct snd_kcontrol_new rt5665_sto1_dac_r_mix[] = {
1640 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER,
1641 RT5665_M_DAC_L1_STO_R_SFT, 1, 1),
1642 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER,
1643 RT5665_M_DAC_R1_STO_R_SFT, 1, 1),
1644 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER,
1645 RT5665_M_DAC_L2_STO_R_SFT, 1, 1),
1646 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER,
1647 RT5665_M_DAC_R2_STO_R_SFT, 1, 1),
1650 static const struct snd_kcontrol_new rt5665_sto2_dac_l_mix[] = {
1651 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO2_DAC_MIXER,
1652 RT5665_M_DAC_L1_STO2_L_SFT, 1, 1),
1653 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO2_DAC_MIXER,
1654 RT5665_M_DAC_L2_STO2_L_SFT, 1, 1),
1655 SOC_DAPM_SINGLE("DAC L3 Switch", RT5665_STO2_DAC_MIXER,
1656 RT5665_M_DAC_L3_STO2_L_SFT, 1, 1),
1659 static const struct snd_kcontrol_new rt5665_sto2_dac_r_mix[] = {
1660 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO2_DAC_MIXER,
1661 RT5665_M_DAC_R1_STO2_R_SFT, 1, 1),
1662 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO2_DAC_MIXER,
1663 RT5665_M_DAC_R2_STO2_R_SFT, 1, 1),
1664 SOC_DAPM_SINGLE("DAC R3 Switch", RT5665_STO2_DAC_MIXER,
1665 RT5665_M_DAC_R3_STO2_R_SFT, 1, 1),
1668 static const struct snd_kcontrol_new rt5665_mono_dac_l_mix[] = {
1669 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER,
1670 RT5665_M_DAC_L1_MONO_L_SFT, 1, 1),
1671 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER,
1672 RT5665_M_DAC_R1_MONO_L_SFT, 1, 1),
1673 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER,
1674 RT5665_M_DAC_L2_MONO_L_SFT, 1, 1),
1675 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER,
1676 RT5665_M_DAC_R2_MONO_L_SFT, 1, 1),
1679 static const struct snd_kcontrol_new rt5665_mono_dac_r_mix[] = {
1680 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER,
1681 RT5665_M_DAC_L1_MONO_R_SFT, 1, 1),
1682 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER,
1683 RT5665_M_DAC_R1_MONO_R_SFT, 1, 1),
1684 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER,
1685 RT5665_M_DAC_L2_MONO_R_SFT, 1, 1),
1686 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER,
1687 RT5665_M_DAC_R2_MONO_R_SFT, 1, 1),
1690 /* Analog Input Mixer */
1691 static const struct snd_kcontrol_new rt5665_rec1_l_mix[] = {
1692 SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC1_L2_MIXER,
1693 RT5665_M_CBJ_RM1_L_SFT, 1, 1),
1694 SOC_DAPM_SINGLE("INL Switch", RT5665_REC1_L2_MIXER,
1695 RT5665_M_INL_RM1_L_SFT, 1, 1),
1696 SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_L2_MIXER,
1697 RT5665_M_INR_RM1_L_SFT, 1, 1),
1698 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_L2_MIXER,
1699 RT5665_M_BST4_RM1_L_SFT, 1, 1),
1700 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_L2_MIXER,
1701 RT5665_M_BST3_RM1_L_SFT, 1, 1),
1702 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_L2_MIXER,
1703 RT5665_M_BST2_RM1_L_SFT, 1, 1),
1704 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_L2_MIXER,
1705 RT5665_M_BST1_RM1_L_SFT, 1, 1),
1708 static const struct snd_kcontrol_new rt5665_rec1_r_mix[] = {
1709 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC1_R2_MIXER,
1710 RT5665_M_AEC_REF_RM1_R_SFT, 1, 1),
1711 SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_R2_MIXER,
1712 RT5665_M_INR_RM1_R_SFT, 1, 1),
1713 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_R2_MIXER,
1714 RT5665_M_BST4_RM1_R_SFT, 1, 1),
1715 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_R2_MIXER,
1716 RT5665_M_BST3_RM1_R_SFT, 1, 1),
1717 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_R2_MIXER,
1718 RT5665_M_BST2_RM1_R_SFT, 1, 1),
1719 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_R2_MIXER,
1720 RT5665_M_BST1_RM1_R_SFT, 1, 1),
1723 static const struct snd_kcontrol_new rt5665_rec2_l_mix[] = {
1724 SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_L2_MIXER,
1725 RT5665_M_INL_RM2_L_SFT, 1, 1),
1726 SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_L2_MIXER,
1727 RT5665_M_INR_RM2_L_SFT, 1, 1),
1728 SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC2_L2_MIXER,
1729 RT5665_M_CBJ_RM2_L_SFT, 1, 1),
1730 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_L2_MIXER,
1731 RT5665_M_BST4_RM2_L_SFT, 1, 1),
1732 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_L2_MIXER,
1733 RT5665_M_BST3_RM2_L_SFT, 1, 1),
1734 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_L2_MIXER,
1735 RT5665_M_BST2_RM2_L_SFT, 1, 1),
1736 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_L2_MIXER,
1737 RT5665_M_BST1_RM2_L_SFT, 1, 1),
1740 static const struct snd_kcontrol_new rt5665_rec2_r_mix[] = {
1741 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC2_R2_MIXER,
1742 RT5665_M_MONOVOL_RM2_R_SFT, 1, 1),
1743 SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_R2_MIXER,
1744 RT5665_M_INL_RM2_R_SFT, 1, 1),
1745 SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_R2_MIXER,
1746 RT5665_M_INR_RM2_R_SFT, 1, 1),
1747 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_R2_MIXER,
1748 RT5665_M_BST4_RM2_R_SFT, 1, 1),
1749 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_R2_MIXER,
1750 RT5665_M_BST3_RM2_R_SFT, 1, 1),
1751 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_R2_MIXER,
1752 RT5665_M_BST2_RM2_R_SFT, 1, 1),
1753 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_R2_MIXER,
1754 RT5665_M_BST1_RM2_R_SFT, 1, 1),
1757 static const struct snd_kcontrol_new rt5665_monovol_mix[] = {
1758 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN,
1759 RT5665_M_DAC_L2_MM_SFT, 1, 1),
1760 SOC_DAPM_SINGLE("RECMIX2L Switch", RT5665_MONOMIX_IN_GAIN,
1761 RT5665_M_RECMIC2L_MM_SFT, 1, 1),
1762 SOC_DAPM_SINGLE("BST1 Switch", RT5665_MONOMIX_IN_GAIN,
1763 RT5665_M_BST1_MM_SFT, 1, 1),
1764 SOC_DAPM_SINGLE("BST2 Switch", RT5665_MONOMIX_IN_GAIN,
1765 RT5665_M_BST2_MM_SFT, 1, 1),
1766 SOC_DAPM_SINGLE("BST3 Switch", RT5665_MONOMIX_IN_GAIN,
1767 RT5665_M_BST3_MM_SFT, 1, 1),
1770 static const struct snd_kcontrol_new rt5665_out_l_mix[] = {
1771 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_OUT_L_MIXER,
1772 RT5665_M_DAC_L2_OM_L_SFT, 1, 1),
1773 SOC_DAPM_SINGLE("INL Switch", RT5665_OUT_L_MIXER,
1774 RT5665_M_IN_L_OM_L_SFT, 1, 1),
1775 SOC_DAPM_SINGLE("BST1 Switch", RT5665_OUT_L_MIXER,
1776 RT5665_M_BST1_OM_L_SFT, 1, 1),
1777 SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_L_MIXER,
1778 RT5665_M_BST2_OM_L_SFT, 1, 1),
1779 SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_L_MIXER,
1780 RT5665_M_BST3_OM_L_SFT, 1, 1),
1783 static const struct snd_kcontrol_new rt5665_out_r_mix[] = {
1784 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_OUT_R_MIXER,
1785 RT5665_M_DAC_R2_OM_R_SFT, 1, 1),
1786 SOC_DAPM_SINGLE("INR Switch", RT5665_OUT_R_MIXER,
1787 RT5665_M_IN_R_OM_R_SFT, 1, 1),
1788 SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_R_MIXER,
1789 RT5665_M_BST2_OM_R_SFT, 1, 1),
1790 SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_R_MIXER,
1791 RT5665_M_BST3_OM_R_SFT, 1, 1),
1792 SOC_DAPM_SINGLE("BST4 Switch", RT5665_OUT_R_MIXER,
1793 RT5665_M_BST4_OM_R_SFT, 1, 1),
1796 static const struct snd_kcontrol_new rt5665_mono_mix[] = {
1797 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN,
1798 RT5665_M_DAC_L2_MA_SFT, 1, 1),
1799 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_MONOMIX_IN_GAIN,
1800 RT5665_M_MONOVOL_MA_SFT, 1, 1),
1803 static const struct snd_kcontrol_new rt5665_lout_l_mix[] = {
1804 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_LOUT_MIXER,
1805 RT5665_M_DAC_L2_LM_SFT, 1, 1),
1806 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5665_LOUT_MIXER,
1807 RT5665_M_OV_L_LM_SFT, 1, 1),
1810 static const struct snd_kcontrol_new rt5665_lout_r_mix[] = {
1811 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_LOUT_MIXER,
1812 RT5665_M_DAC_R2_LM_SFT, 1, 1),
1813 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5665_LOUT_MIXER,
1814 RT5665_M_OV_R_LM_SFT, 1, 1),
1818 /*MX-17 [6:4], MX-17 [2:0]*/
1819 static const char * const rt5665_dac2_src[] = {
1820 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "Mono ADC MIX"
1823 static const SOC_ENUM_SINGLE_DECL(
1824 rt5665_dac_l2_enum, RT5665_DAC2_CTRL,
1825 RT5665_DAC_L2_SEL_SFT, rt5665_dac2_src);
1827 static const struct snd_kcontrol_new rt5665_dac_l2_mux =
1828 SOC_DAPM_ENUM("Digital DAC L2 Source", rt5665_dac_l2_enum);
1830 static const SOC_ENUM_SINGLE_DECL(
1831 rt5665_dac_r2_enum, RT5665_DAC2_CTRL,
1832 RT5665_DAC_R2_SEL_SFT, rt5665_dac2_src);
1834 static const struct snd_kcontrol_new rt5665_dac_r2_mux =
1835 SOC_DAPM_ENUM("Digital DAC R2 Source", rt5665_dac_r2_enum);
1838 /*MX-1B [6:4], MX-1B [2:0]*/
1839 static const char * const rt5665_dac3_src[] = {
1840 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "STO2 ADC MIX"
1843 static const SOC_ENUM_SINGLE_DECL(
1844 rt5665_dac_l3_enum, RT5665_DAC3_CTRL,
1845 RT5665_DAC_L3_SEL_SFT, rt5665_dac3_src);
1847 static const struct snd_kcontrol_new rt5665_dac_l3_mux =
1848 SOC_DAPM_ENUM("Digital DAC L3 Source", rt5665_dac_l3_enum);
1850 static const SOC_ENUM_SINGLE_DECL(
1851 rt5665_dac_r3_enum, RT5665_DAC3_CTRL,
1852 RT5665_DAC_R3_SEL_SFT, rt5665_dac3_src);
1854 static const struct snd_kcontrol_new rt5665_dac_r3_mux =
1855 SOC_DAPM_ENUM("Digital DAC R3 Source", rt5665_dac_r3_enum);
1857 /* STO1 ADC1 Source */
1858 /* MX-26 [13] [5] */
1859 static const char * const rt5665_sto1_adc1_src[] = {
1863 static const SOC_ENUM_SINGLE_DECL(
1864 rt5665_sto1_adc1l_enum, RT5665_STO1_ADC_MIXER,
1865 RT5665_STO1_ADC1L_SRC_SFT, rt5665_sto1_adc1_src);
1867 static const struct snd_kcontrol_new rt5665_sto1_adc1l_mux =
1868 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1l_enum);
1870 static const SOC_ENUM_SINGLE_DECL(
1871 rt5665_sto1_adc1r_enum, RT5665_STO1_ADC_MIXER,
1872 RT5665_STO1_ADC1R_SRC_SFT, rt5665_sto1_adc1_src);
1874 static const struct snd_kcontrol_new rt5665_sto1_adc1r_mux =
1875 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1r_enum);
1877 /* STO1 ADC Source */
1878 /* MX-26 [11:10] [3:2] */
1879 static const char * const rt5665_sto1_adc_src[] = {
1880 "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
1883 static const SOC_ENUM_SINGLE_DECL(
1884 rt5665_sto1_adcl_enum, RT5665_STO1_ADC_MIXER,
1885 RT5665_STO1_ADCL_SRC_SFT, rt5665_sto1_adc_src);
1887 static const struct snd_kcontrol_new rt5665_sto1_adcl_mux =
1888 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5665_sto1_adcl_enum);
1890 static const SOC_ENUM_SINGLE_DECL(
1891 rt5665_sto1_adcr_enum, RT5665_STO1_ADC_MIXER,
1892 RT5665_STO1_ADCR_SRC_SFT, rt5665_sto1_adc_src);
1894 static const struct snd_kcontrol_new rt5665_sto1_adcr_mux =
1895 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5665_sto1_adcr_enum);
1897 /* STO1 ADC2 Source */
1898 /* MX-26 [12] [4] */
1899 static const char * const rt5665_sto1_adc2_src[] = {
1903 static const SOC_ENUM_SINGLE_DECL(
1904 rt5665_sto1_adc2l_enum, RT5665_STO1_ADC_MIXER,
1905 RT5665_STO1_ADC2L_SRC_SFT, rt5665_sto1_adc2_src);
1907 static const struct snd_kcontrol_new rt5665_sto1_adc2l_mux =
1908 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5665_sto1_adc2l_enum);
1910 static const SOC_ENUM_SINGLE_DECL(
1911 rt5665_sto1_adc2r_enum, RT5665_STO1_ADC_MIXER,
1912 RT5665_STO1_ADC2R_SRC_SFT, rt5665_sto1_adc2_src);
1914 static const struct snd_kcontrol_new rt5665_sto1_adc2r_mux =
1915 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5665_sto1_adc2r_enum);
1917 /* STO1 DMIC Source */
1919 static const char * const rt5665_sto1_dmic_src[] = {
1923 static const SOC_ENUM_SINGLE_DECL(
1924 rt5665_sto1_dmic_enum, RT5665_STO1_ADC_MIXER,
1925 RT5665_STO1_DMIC_SRC_SFT, rt5665_sto1_dmic_src);
1927 static const struct snd_kcontrol_new rt5665_sto1_dmic_mux =
1928 SOC_DAPM_ENUM("Stereo1 DMIC Mux", rt5665_sto1_dmic_enum);
1931 static const char * const rt5665_sto1_dd_l_src[] = {
1932 "STO2 DAC", "MONO DAC"
1935 static const SOC_ENUM_SINGLE_DECL(
1936 rt5665_sto1_dd_l_enum, RT5665_STO1_ADC_MIXER,
1937 RT5665_STO1_DD_L_SRC_SFT, rt5665_sto1_dd_l_src);
1939 static const struct snd_kcontrol_new rt5665_sto1_dd_l_mux =
1940 SOC_DAPM_ENUM("Stereo1 DD L Source", rt5665_sto1_dd_l_enum);
1943 static const char * const rt5665_sto1_dd_r_src[] = {
1944 "STO2 DAC", "MONO DAC", "AEC REF"
1947 static const SOC_ENUM_SINGLE_DECL(
1948 rt5665_sto1_dd_r_enum, RT5665_STO1_ADC_MIXER,
1949 RT5665_STO1_DD_R_SRC_SFT, rt5665_sto1_dd_r_src);
1951 static const struct snd_kcontrol_new rt5665_sto1_dd_r_mux =
1952 SOC_DAPM_ENUM("Stereo1 DD R Source", rt5665_sto1_dd_r_enum);
1954 /* MONO ADC L2 Source */
1956 static const char * const rt5665_mono_adc_l2_src[] = {
1960 static const SOC_ENUM_SINGLE_DECL(
1961 rt5665_mono_adc_l2_enum, RT5665_MONO_ADC_MIXER,
1962 RT5665_MONO_ADC_L2_SRC_SFT, rt5665_mono_adc_l2_src);
1964 static const struct snd_kcontrol_new rt5665_mono_adc_l2_mux =
1965 SOC_DAPM_ENUM("Mono ADC L2 Source", rt5665_mono_adc_l2_enum);
1968 /* MONO ADC L1 Source */
1970 static const char * const rt5665_mono_adc_l1_src[] = {
1974 static const SOC_ENUM_SINGLE_DECL(
1975 rt5665_mono_adc_l1_enum, RT5665_MONO_ADC_MIXER,
1976 RT5665_MONO_ADC_L1_SRC_SFT, rt5665_mono_adc_l1_src);
1978 static const struct snd_kcontrol_new rt5665_mono_adc_l1_mux =
1979 SOC_DAPM_ENUM("Mono ADC L1 Source", rt5665_mono_adc_l1_enum);
1982 static const char * const rt5665_mono_dd_src[] = {
1983 "STO2 DAC", "MONO DAC"
1986 static const SOC_ENUM_SINGLE_DECL(
1987 rt5665_mono_dd_l_enum, RT5665_MONO_ADC_MIXER,
1988 RT5665_MONO_DD_L_SRC_SFT, rt5665_mono_dd_src);
1990 static const struct snd_kcontrol_new rt5665_mono_dd_l_mux =
1991 SOC_DAPM_ENUM("Mono DD L Source", rt5665_mono_dd_l_enum);
1993 static const SOC_ENUM_SINGLE_DECL(
1994 rt5665_mono_dd_r_enum, RT5665_MONO_ADC_MIXER,
1995 RT5665_MONO_DD_R_SRC_SFT, rt5665_mono_dd_src);
1997 static const struct snd_kcontrol_new rt5665_mono_dd_r_mux =
1998 SOC_DAPM_ENUM("Mono DD R Source", rt5665_mono_dd_r_enum);
2000 /* MONO ADC L Source, MONO ADC R Source*/
2001 /* MX-27 [11:10], MX-27 [3:2] */
2002 static const char * const rt5665_mono_adc_src[] = {
2003 "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
2006 static const SOC_ENUM_SINGLE_DECL(
2007 rt5665_mono_adc_l_enum, RT5665_MONO_ADC_MIXER,
2008 RT5665_MONO_ADC_L_SRC_SFT, rt5665_mono_adc_src);
2010 static const struct snd_kcontrol_new rt5665_mono_adc_l_mux =
2011 SOC_DAPM_ENUM("Mono ADC L Source", rt5665_mono_adc_l_enum);
2013 static const SOC_ENUM_SINGLE_DECL(
2014 rt5665_mono_adcr_enum, RT5665_MONO_ADC_MIXER,
2015 RT5665_MONO_ADC_R_SRC_SFT, rt5665_mono_adc_src);
2017 static const struct snd_kcontrol_new rt5665_mono_adc_r_mux =
2018 SOC_DAPM_ENUM("Mono ADC R Source", rt5665_mono_adcr_enum);
2020 /* MONO DMIC L Source */
2022 static const char * const rt5665_mono_dmic_l_src[] = {
2023 "DMIC1 L", "DMIC2 L"
2026 static const SOC_ENUM_SINGLE_DECL(
2027 rt5665_mono_dmic_l_enum, RT5665_MONO_ADC_MIXER,
2028 RT5665_MONO_DMIC_L_SRC_SFT, rt5665_mono_dmic_l_src);
2030 static const struct snd_kcontrol_new rt5665_mono_dmic_l_mux =
2031 SOC_DAPM_ENUM("Mono DMIC L Source", rt5665_mono_dmic_l_enum);
2033 /* MONO ADC R2 Source */
2035 static const char * const rt5665_mono_adc_r2_src[] = {
2039 static const SOC_ENUM_SINGLE_DECL(
2040 rt5665_mono_adc_r2_enum, RT5665_MONO_ADC_MIXER,
2041 RT5665_MONO_ADC_R2_SRC_SFT, rt5665_mono_adc_r2_src);
2043 static const struct snd_kcontrol_new rt5665_mono_adc_r2_mux =
2044 SOC_DAPM_ENUM("Mono ADC R2 Source", rt5665_mono_adc_r2_enum);
2046 /* MONO ADC R1 Source */
2048 static const char * const rt5665_mono_adc_r1_src[] = {
2052 static const SOC_ENUM_SINGLE_DECL(
2053 rt5665_mono_adc_r1_enum, RT5665_MONO_ADC_MIXER,
2054 RT5665_MONO_ADC_R1_SRC_SFT, rt5665_mono_adc_r1_src);
2056 static const struct snd_kcontrol_new rt5665_mono_adc_r1_mux =
2057 SOC_DAPM_ENUM("Mono ADC R1 Source", rt5665_mono_adc_r1_enum);
2059 /* MONO DMIC R Source */
2061 static const char * const rt5665_mono_dmic_r_src[] = {
2062 "DMIC1 R", "DMIC2 R"
2065 static const SOC_ENUM_SINGLE_DECL(
2066 rt5665_mono_dmic_r_enum, RT5665_MONO_ADC_MIXER,
2067 RT5665_MONO_DMIC_R_SRC_SFT, rt5665_mono_dmic_r_src);
2069 static const struct snd_kcontrol_new rt5665_mono_dmic_r_mux =
2070 SOC_DAPM_ENUM("Mono DMIC R Source", rt5665_mono_dmic_r_enum);
2073 /* STO2 ADC1 Source */
2074 /* MX-28 [13] [5] */
2075 static const char * const rt5665_sto2_adc1_src[] = {
2079 static const SOC_ENUM_SINGLE_DECL(
2080 rt5665_sto2_adc1l_enum, RT5665_STO2_ADC_MIXER,
2081 RT5665_STO2_ADC1L_SRC_SFT, rt5665_sto2_adc1_src);
2083 static const struct snd_kcontrol_new rt5665_sto2_adc1l_mux =
2084 SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1l_enum);
2086 static const SOC_ENUM_SINGLE_DECL(
2087 rt5665_sto2_adc1r_enum, RT5665_STO2_ADC_MIXER,
2088 RT5665_STO2_ADC1R_SRC_SFT, rt5665_sto2_adc1_src);
2090 static const struct snd_kcontrol_new rt5665_sto2_adc1r_mux =
2091 SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1r_enum);
2093 /* STO2 ADC Source */
2094 /* MX-28 [11:10] [3:2] */
2095 static const char * const rt5665_sto2_adc_src[] = {
2096 "ADC1 L", "ADC1 R", "ADC2 L"
2099 static const SOC_ENUM_SINGLE_DECL(
2100 rt5665_sto2_adcl_enum, RT5665_STO2_ADC_MIXER,
2101 RT5665_STO2_ADCL_SRC_SFT, rt5665_sto2_adc_src);
2103 static const struct snd_kcontrol_new rt5665_sto2_adcl_mux =
2104 SOC_DAPM_ENUM("Stereo2 ADCL Source", rt5665_sto2_adcl_enum);
2106 static const SOC_ENUM_SINGLE_DECL(
2107 rt5665_sto2_adcr_enum, RT5665_STO2_ADC_MIXER,
2108 RT5665_STO2_ADCR_SRC_SFT, rt5665_sto2_adc_src);
2110 static const struct snd_kcontrol_new rt5665_sto2_adcr_mux =
2111 SOC_DAPM_ENUM("Stereo2 ADCR Source", rt5665_sto2_adcr_enum);
2113 /* STO2 ADC2 Source */
2114 /* MX-28 [12] [4] */
2115 static const char * const rt5665_sto2_adc2_src[] = {
2119 static const SOC_ENUM_SINGLE_DECL(
2120 rt5665_sto2_adc2l_enum, RT5665_STO2_ADC_MIXER,
2121 RT5665_STO2_ADC2L_SRC_SFT, rt5665_sto2_adc2_src);
2123 static const struct snd_kcontrol_new rt5665_sto2_adc2l_mux =
2124 SOC_DAPM_ENUM("Stereo2 ADC2L Source", rt5665_sto2_adc2l_enum);
2126 static const SOC_ENUM_SINGLE_DECL(
2127 rt5665_sto2_adc2r_enum, RT5665_STO2_ADC_MIXER,
2128 RT5665_STO2_ADC2R_SRC_SFT, rt5665_sto2_adc2_src);
2130 static const struct snd_kcontrol_new rt5665_sto2_adc2r_mux =
2131 SOC_DAPM_ENUM("Stereo2 ADC2R Source", rt5665_sto2_adc2r_enum);
2133 /* STO2 DMIC Source */
2135 static const char * const rt5665_sto2_dmic_src[] = {
2139 static const SOC_ENUM_SINGLE_DECL(
2140 rt5665_sto2_dmic_enum, RT5665_STO2_ADC_MIXER,
2141 RT5665_STO2_DMIC_SRC_SFT, rt5665_sto2_dmic_src);
2143 static const struct snd_kcontrol_new rt5665_sto2_dmic_mux =
2144 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5665_sto2_dmic_enum);
2147 static const char * const rt5665_sto2_dd_l_src[] = {
2148 "STO2 DAC", "MONO DAC"
2151 static const SOC_ENUM_SINGLE_DECL(
2152 rt5665_sto2_dd_l_enum, RT5665_STO2_ADC_MIXER,
2153 RT5665_STO2_DD_L_SRC_SFT, rt5665_sto2_dd_l_src);
2155 static const struct snd_kcontrol_new rt5665_sto2_dd_l_mux =
2156 SOC_DAPM_ENUM("Stereo2 DD L Source", rt5665_sto2_dd_l_enum);
2159 static const char * const rt5665_sto2_dd_r_src[] = {
2160 "STO2 DAC", "MONO DAC"
2163 static const SOC_ENUM_SINGLE_DECL(
2164 rt5665_sto2_dd_r_enum, RT5665_STO2_ADC_MIXER,
2165 RT5665_STO2_DD_R_SRC_SFT, rt5665_sto2_dd_r_src);
2167 static const struct snd_kcontrol_new rt5665_sto2_dd_r_mux =
2168 SOC_DAPM_ENUM("Stereo2 DD R Source", rt5665_sto2_dd_r_enum);
2170 /* DAC R1 Source, DAC L1 Source*/
2171 /* MX-29 [11:10], MX-29 [9:8]*/
2172 static const char * const rt5665_dac1_src[] = {
2173 "IF1 DAC1", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC"
2176 static const SOC_ENUM_SINGLE_DECL(
2177 rt5665_dac_r1_enum, RT5665_AD_DA_MIXER,
2178 RT5665_DAC1_R_SEL_SFT, rt5665_dac1_src);
2180 static const struct snd_kcontrol_new rt5665_dac_r1_mux =
2181 SOC_DAPM_ENUM("DAC R1 Source", rt5665_dac_r1_enum);
2183 static const SOC_ENUM_SINGLE_DECL(
2184 rt5665_dac_l1_enum, RT5665_AD_DA_MIXER,
2185 RT5665_DAC1_L_SEL_SFT, rt5665_dac1_src);
2187 static const struct snd_kcontrol_new rt5665_dac_l1_mux =
2188 SOC_DAPM_ENUM("DAC L1 Source", rt5665_dac_l1_enum);
2190 /* DAC Digital Mixer L Source, DAC Digital Mixer R Source*/
2191 /* MX-2D [13:12], MX-2D [9:8]*/
2192 static const char * const rt5665_dig_dac_mix_src[] = {
2193 "Stereo1 DAC Mixer", "Stereo2 DAC Mixer", "Mono DAC Mixer"
2196 static const SOC_ENUM_SINGLE_DECL(
2197 rt5665_dig_dac_mixl_enum, RT5665_A_DAC1_MUX,
2198 RT5665_DAC_MIX_L_SFT, rt5665_dig_dac_mix_src);
2200 static const struct snd_kcontrol_new rt5665_dig_dac_mixl_mux =
2201 SOC_DAPM_ENUM("DAC Digital Mixer L Source", rt5665_dig_dac_mixl_enum);
2203 static const SOC_ENUM_SINGLE_DECL(
2204 rt5665_dig_dac_mixr_enum, RT5665_A_DAC1_MUX,
2205 RT5665_DAC_MIX_R_SFT, rt5665_dig_dac_mix_src);
2207 static const struct snd_kcontrol_new rt5665_dig_dac_mixr_mux =
2208 SOC_DAPM_ENUM("DAC Digital Mixer R Source", rt5665_dig_dac_mixr_enum);
2210 /* Analog DAC L1 Source, Analog DAC R1 Source*/
2211 /* MX-2D [5:4], MX-2D [1:0]*/
2212 static const char * const rt5665_alg_dac1_src[] = {
2213 "Stereo1 DAC Mixer", "DAC1", "DMIC1"
2216 static const SOC_ENUM_SINGLE_DECL(
2217 rt5665_alg_dac_l1_enum, RT5665_A_DAC1_MUX,
2218 RT5665_A_DACL1_SFT, rt5665_alg_dac1_src);
2220 static const struct snd_kcontrol_new rt5665_alg_dac_l1_mux =
2221 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5665_alg_dac_l1_enum);
2223 static const SOC_ENUM_SINGLE_DECL(
2224 rt5665_alg_dac_r1_enum, RT5665_A_DAC1_MUX,
2225 RT5665_A_DACR1_SFT, rt5665_alg_dac1_src);
2227 static const struct snd_kcontrol_new rt5665_alg_dac_r1_mux =
2228 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5665_alg_dac_r1_enum);
2230 /* Analog DAC LR Source, Analog DAC R2 Source*/
2231 /* MX-2E [5:4], MX-2E [0]*/
2232 static const char * const rt5665_alg_dac2_src[] = {
2233 "Mono DAC Mixer", "DAC2"
2236 static const SOC_ENUM_SINGLE_DECL(
2237 rt5665_alg_dac_l2_enum, RT5665_A_DAC2_MUX,
2238 RT5665_A_DACL2_SFT, rt5665_alg_dac2_src);
2240 static const struct snd_kcontrol_new rt5665_alg_dac_l2_mux =
2241 SOC_DAPM_ENUM("Analog DAC L2 Source", rt5665_alg_dac_l2_enum);
2243 static const SOC_ENUM_SINGLE_DECL(
2244 rt5665_alg_dac_r2_enum, RT5665_A_DAC2_MUX,
2245 RT5665_A_DACR2_SFT, rt5665_alg_dac2_src);
2247 static const struct snd_kcontrol_new rt5665_alg_dac_r2_mux =
2248 SOC_DAPM_ENUM("Analog DAC R2 Source", rt5665_alg_dac_r2_enum);
2250 /* Interface2 ADC Data Input*/
2252 static const char * const rt5665_if2_1_adc_in_src[] = {
2253 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2254 "IF1 DAC2", "IF2_2 DAC", "IF3 DAC", "DAC1 MIX"
2257 static const SOC_ENUM_SINGLE_DECL(
2258 rt5665_if2_1_adc_in_enum, RT5665_DIG_INF2_DATA,
2259 RT5665_IF3_ADC_IN_SFT, rt5665_if2_1_adc_in_src);
2261 static const struct snd_kcontrol_new rt5665_if2_1_adc_in_mux =
2262 SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_1_adc_in_enum);
2265 static const char * const rt5665_if2_2_adc_in_src[] = {
2266 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2267 "IF1 DAC2", "IF2_1 DAC", "IF3 DAC", "DAC1 MIX"
2270 static const SOC_ENUM_SINGLE_DECL(
2271 rt5665_if2_2_adc_in_enum, RT5665_DIG_INF2_DATA,
2272 RT5665_IF2_2_ADC_IN_SFT, rt5665_if2_2_adc_in_src);
2274 static const struct snd_kcontrol_new rt5665_if2_2_adc_in_mux =
2275 SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_2_adc_in_enum);
2277 /* Interface3 ADC Data Input*/
2279 static const char * const rt5665_if3_adc_in_src[] = {
2280 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2281 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "DAC1 MIX"
2284 static const SOC_ENUM_SINGLE_DECL(
2285 rt5665_if3_adc_in_enum, RT5665_DIG_INF3_DATA,
2286 RT5665_IF3_ADC_IN_SFT, rt5665_if3_adc_in_src);
2288 static const struct snd_kcontrol_new rt5665_if3_adc_in_mux =
2289 SOC_DAPM_ENUM("IF3 ADC IN Source", rt5665_if3_adc_in_enum);
2292 /* MX-31 [11:10] [9:8] */
2293 static const char * const rt5665_pdm_src[] = {
2294 "Stereo1 DAC", "Stereo2 DAC", "Mono DAC"
2297 static const SOC_ENUM_SINGLE_DECL(
2298 rt5665_pdm_l_enum, RT5665_PDM_OUT_CTRL,
2299 RT5665_PDM1_L_SFT, rt5665_pdm_src);
2301 static const struct snd_kcontrol_new rt5665_pdm_l_mux =
2302 SOC_DAPM_ENUM("PDM L Source", rt5665_pdm_l_enum);
2304 static const SOC_ENUM_SINGLE_DECL(
2305 rt5665_pdm_r_enum, RT5665_PDM_OUT_CTRL,
2306 RT5665_PDM1_R_SFT, rt5665_pdm_src);
2308 static const struct snd_kcontrol_new rt5665_pdm_r_mux =
2309 SOC_DAPM_ENUM("PDM R Source", rt5665_pdm_r_enum);
2312 /* I2S1 TDM ADCDAT Source */
2314 static const char * const rt5665_if1_1_adc1_data_src[] = {
2315 "STO1 ADC", "IF2_1 DAC",
2318 static const SOC_ENUM_SINGLE_DECL(
2319 rt5665_if1_1_adc1_data_enum, RT5665_TDM_CTRL_3,
2320 RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_1_adc1_data_src);
2322 static const struct snd_kcontrol_new rt5665_if1_1_adc1_mux =
2323 SOC_DAPM_ENUM("IF1_1 ADC1 Source", rt5665_if1_1_adc1_data_enum);
2326 static const char * const rt5665_if1_1_adc2_data_src[] = {
2327 "STO2 ADC", "IF2_2 DAC",
2330 static const SOC_ENUM_SINGLE_DECL(
2331 rt5665_if1_1_adc2_data_enum, RT5665_TDM_CTRL_3,
2332 RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_1_adc2_data_src);
2334 static const struct snd_kcontrol_new rt5665_if1_1_adc2_mux =
2335 SOC_DAPM_ENUM("IF1_1 ADC2 Source", rt5665_if1_1_adc2_data_enum);
2338 static const char * const rt5665_if1_1_adc3_data_src[] = {
2339 "MONO ADC", "IF3 DAC",
2342 static const SOC_ENUM_SINGLE_DECL(
2343 rt5665_if1_1_adc3_data_enum, RT5665_TDM_CTRL_3,
2344 RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_1_adc3_data_src);
2346 static const struct snd_kcontrol_new rt5665_if1_1_adc3_mux =
2347 SOC_DAPM_ENUM("IF1_1 ADC3 Source", rt5665_if1_1_adc3_data_enum);
2350 static const char * const rt5665_if1_2_adc1_data_src[] = {
2351 "STO1 ADC", "IF1 DAC",
2354 static const SOC_ENUM_SINGLE_DECL(
2355 rt5665_if1_2_adc1_data_enum, RT5665_TDM_CTRL_4,
2356 RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_2_adc1_data_src);
2358 static const struct snd_kcontrol_new rt5665_if1_2_adc1_mux =
2359 SOC_DAPM_ENUM("IF1_2 ADC1 Source", rt5665_if1_2_adc1_data_enum);
2362 static const char * const rt5665_if1_2_adc2_data_src[] = {
2363 "STO2 ADC", "IF2_1 DAC",
2366 static const SOC_ENUM_SINGLE_DECL(
2367 rt5665_if1_2_adc2_data_enum, RT5665_TDM_CTRL_4,
2368 RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_2_adc2_data_src);
2370 static const struct snd_kcontrol_new rt5665_if1_2_adc2_mux =
2371 SOC_DAPM_ENUM("IF1_2 ADC2 Source", rt5665_if1_2_adc2_data_enum);
2374 static const char * const rt5665_if1_2_adc3_data_src[] = {
2375 "MONO ADC", "IF2_2 DAC",
2378 static const SOC_ENUM_SINGLE_DECL(
2379 rt5665_if1_2_adc3_data_enum, RT5665_TDM_CTRL_4,
2380 RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_2_adc3_data_src);
2382 static const struct snd_kcontrol_new rt5665_if1_2_adc3_mux =
2383 SOC_DAPM_ENUM("IF1_2 ADC3 Source", rt5665_if1_2_adc3_data_enum);
2386 static const char * const rt5665_if1_2_adc4_data_src[] = {
2390 static const SOC_ENUM_SINGLE_DECL(
2391 rt5665_if1_2_adc4_data_enum, RT5665_TDM_CTRL_4,
2392 RT5665_IF1_ADC4_SEL_SFT, rt5665_if1_2_adc4_data_src);
2394 static const struct snd_kcontrol_new rt5665_if1_2_adc4_mux =
2395 SOC_DAPM_ENUM("IF1_2 ADC4 Source", rt5665_if1_2_adc4_data_enum);
2397 /* MX-7a[4:0] MX-7b[4:0] */
2398 static const char * const rt5665_tdm_adc_data_src[] = {
2399 "1234", "1243", "1324", "1342", "1432", "1423",
2400 "2134", "2143", "2314", "2341", "2431", "2413",
2401 "3124", "3142", "3214", "3241", "3412", "3421",
2402 "4123", "4132", "4213", "4231", "4312", "4321"
2405 static const SOC_ENUM_SINGLE_DECL(
2406 rt5665_tdm1_adc_data_enum, RT5665_TDM_CTRL_3,
2407 RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src);
2409 static const struct snd_kcontrol_new rt5665_tdm1_adc_mux =
2410 SOC_DAPM_ENUM("TDM1 ADC Mux", rt5665_tdm1_adc_data_enum);
2412 static const SOC_ENUM_SINGLE_DECL(
2413 rt5665_tdm2_adc_data_enum, RT5665_TDM_CTRL_4,
2414 RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src);
2416 static const struct snd_kcontrol_new rt5665_tdm2_adc_mux =
2417 SOC_DAPM_ENUM("TDM2 ADCDAT Source", rt5665_tdm2_adc_data_enum);
2419 /* Out Volume Switch */
2420 static const struct snd_kcontrol_new monovol_switch =
2421 SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_VOL_L_SFT, 1, 1);
2423 static const struct snd_kcontrol_new outvol_l_switch =
2424 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_L_SFT, 1, 1);
2426 static const struct snd_kcontrol_new outvol_r_switch =
2427 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_R_SFT, 1, 1);
2430 static const struct snd_kcontrol_new mono_switch =
2431 SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_L_MUTE_SFT, 1, 1);
2433 static const struct snd_kcontrol_new hpo_switch =
2434 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5665_HP_CTRL_2,
2435 RT5665_VOL_L_SFT, 1, 0);
2437 static const struct snd_kcontrol_new lout_l_switch =
2438 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_L_MUTE_SFT, 1, 1);
2440 static const struct snd_kcontrol_new lout_r_switch =
2441 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_R_MUTE_SFT, 1, 1);
2443 static const struct snd_kcontrol_new pdm_l_switch =
2444 SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL,
2445 RT5665_M_PDM1_L_SFT, 1, 1);
2447 static const struct snd_kcontrol_new pdm_r_switch =
2448 SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL,
2449 RT5665_M_PDM1_R_SFT, 1, 1);
2451 static int rt5665_mono_event(struct snd_soc_dapm_widget *w,
2452 struct snd_kcontrol *kcontrol, int event)
2454 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2457 case SND_SOC_DAPM_PRE_PMU:
2458 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
2459 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
2460 snd_soc_update_bits(codec, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40,
2462 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x10, 0x10);
2463 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x20, 0x20);
2466 case SND_SOC_DAPM_POST_PMD:
2467 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x20, 0);
2468 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x10, 0);
2469 snd_soc_update_bits(codec, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40,
2471 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
2472 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
2483 static int rt5665_hp_event(struct snd_soc_dapm_widget *w,
2484 struct snd_kcontrol *kcontrol, int event)
2486 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2489 case SND_SOC_DAPM_PRE_PMU:
2490 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
2491 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
2492 snd_soc_write(codec, RT5665_HP_LOGIC_CTRL_2, 0x0003);
2495 case SND_SOC_DAPM_POST_PMD:
2496 snd_soc_write(codec, RT5665_HP_LOGIC_CTRL_2, 0x0002);
2497 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
2498 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
2509 static int rt5665_lout_event(struct snd_soc_dapm_widget *w,
2510 struct snd_kcontrol *kcontrol, int event)
2512 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2515 case SND_SOC_DAPM_POST_PMU:
2516 snd_soc_update_bits(codec, RT5665_DEPOP_1,
2517 RT5665_PUMP_EN, RT5665_PUMP_EN);
2520 case SND_SOC_DAPM_PRE_PMD:
2521 snd_soc_update_bits(codec, RT5665_DEPOP_1,
2533 static int set_dmic_power(struct snd_soc_dapm_widget *w,
2534 struct snd_kcontrol *kcontrol, int event)
2537 case SND_SOC_DAPM_POST_PMU:
2538 /*Add delay to avoid pop noise*/
2549 static int rt5655_set_verf(struct snd_soc_dapm_widget *w,
2550 struct snd_kcontrol *kcontrol, int event)
2552 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2555 case SND_SOC_DAPM_PRE_PMU:
2557 case RT5665_PWR_VREF1_BIT:
2558 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2562 case RT5665_PWR_VREF2_BIT:
2563 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2567 case RT5665_PWR_VREF3_BIT:
2568 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2577 case SND_SOC_DAPM_POST_PMU:
2578 usleep_range(15000, 20000);
2580 case RT5665_PWR_VREF1_BIT:
2581 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2582 RT5665_PWR_FV1, RT5665_PWR_FV1);
2585 case RT5665_PWR_VREF2_BIT:
2586 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2587 RT5665_PWR_FV2, RT5665_PWR_FV2);
2590 case RT5665_PWR_VREF3_BIT:
2591 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2592 RT5665_PWR_FV3, RT5665_PWR_FV3);
2608 static const struct snd_soc_dapm_widget rt5665_dapm_widgets[] = {
2609 SND_SOC_DAPM_SUPPLY("LDO2", RT5665_PWR_ANLG_3, RT5665_PWR_LDO2_BIT, 0,
2611 SND_SOC_DAPM_SUPPLY("PLL", RT5665_PWR_ANLG_3, RT5665_PWR_PLL_BIT, 0,
2613 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5665_PWR_VOL,
2614 RT5665_PWR_MIC_DET_BIT, 0, NULL, 0),
2615 SND_SOC_DAPM_SUPPLY("Vref1", RT5665_PWR_ANLG_1, RT5665_PWR_VREF1_BIT, 0,
2616 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2617 SND_SOC_DAPM_SUPPLY("Vref2", RT5665_PWR_ANLG_1, RT5665_PWR_VREF2_BIT, 0,
2618 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2619 SND_SOC_DAPM_SUPPLY("Vref3", RT5665_PWR_ANLG_1, RT5665_PWR_VREF3_BIT, 0,
2620 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2623 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5665_ASRC_1,
2624 RT5665_I2S1_ASRC_SFT, 0, NULL, 0),
2625 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5665_ASRC_1,
2626 RT5665_I2S2_ASRC_SFT, 0, NULL, 0),
2627 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5665_ASRC_1,
2628 RT5665_I2S3_ASRC_SFT, 0, NULL, 0),
2629 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5665_ASRC_1,
2630 RT5665_DAC_STO1_ASRC_SFT, 0, NULL, 0),
2631 SND_SOC_DAPM_SUPPLY_S("DAC STO2 ASRC", 1, RT5665_ASRC_1,
2632 RT5665_DAC_STO2_ASRC_SFT, 0, NULL, 0),
2633 SND_SOC_DAPM_SUPPLY_S("DAC Mono L ASRC", 1, RT5665_ASRC_1,
2634 RT5665_DAC_MONO_L_ASRC_SFT, 0, NULL, 0),
2635 SND_SOC_DAPM_SUPPLY_S("DAC Mono R ASRC", 1, RT5665_ASRC_1,
2636 RT5665_DAC_MONO_R_ASRC_SFT, 0, NULL, 0),
2637 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5665_ASRC_1,
2638 RT5665_ADC_STO1_ASRC_SFT, 0, NULL, 0),
2639 SND_SOC_DAPM_SUPPLY_S("ADC Mono L ASRC", 1, RT5665_ASRC_1,
2640 RT5665_ADC_MONO_L_ASRC_SFT, 0, NULL, 0),
2641 SND_SOC_DAPM_SUPPLY_S("ADC Mono R ASRC", 1, RT5665_ASRC_1,
2642 RT5665_ADC_MONO_R_ASRC_SFT, 0, NULL, 0),
2643 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5665_ASRC_1,
2644 RT5665_DMIC_STO1_ASRC_SFT, 0, NULL, 0),
2645 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5665_ASRC_1,
2646 RT5665_DMIC_STO2_ASRC_SFT, 0, NULL, 0),
2647 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5665_ASRC_1,
2648 RT5665_DMIC_MONO_L_ASRC_SFT, 0, NULL, 0),
2649 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5665_ASRC_1,
2650 RT5665_DMIC_MONO_R_ASRC_SFT, 0, NULL, 0),
2653 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5665_PWR_ANLG_2, RT5665_PWR_MB1_BIT,
2655 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5665_PWR_ANLG_2, RT5665_PWR_MB2_BIT,
2657 SND_SOC_DAPM_SUPPLY("MICBIAS3", RT5665_PWR_ANLG_2, RT5665_PWR_MB3_BIT,
2661 SND_SOC_DAPM_INPUT("DMIC L1"),
2662 SND_SOC_DAPM_INPUT("DMIC R1"),
2663 SND_SOC_DAPM_INPUT("DMIC L2"),
2664 SND_SOC_DAPM_INPUT("DMIC R2"),
2666 SND_SOC_DAPM_INPUT("IN1P"),
2667 SND_SOC_DAPM_INPUT("IN1N"),
2668 SND_SOC_DAPM_INPUT("IN2P"),
2669 SND_SOC_DAPM_INPUT("IN2N"),
2670 SND_SOC_DAPM_INPUT("IN3P"),
2671 SND_SOC_DAPM_INPUT("IN3N"),
2672 SND_SOC_DAPM_INPUT("IN4P"),
2673 SND_SOC_DAPM_INPUT("IN4N"),
2675 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2676 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2678 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2679 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2680 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5665_DMIC_CTRL_1,
2681 RT5665_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2682 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5665_DMIC_CTRL_1,
2683 RT5665_DMIC_2_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2686 SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM,
2688 SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM,
2690 SND_SOC_DAPM_PGA("BST3", SND_SOC_NOPM,
2692 SND_SOC_DAPM_PGA("BST4", SND_SOC_NOPM,
2694 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
2696 SND_SOC_DAPM_SUPPLY("BST1 Power", RT5665_PWR_ANLG_2,
2697 RT5665_PWR_BST1_BIT, 0, NULL, 0),
2698 SND_SOC_DAPM_SUPPLY("BST2 Power", RT5665_PWR_ANLG_2,
2699 RT5665_PWR_BST2_BIT, 0, NULL, 0),
2700 SND_SOC_DAPM_SUPPLY("BST3 Power", RT5665_PWR_ANLG_2,
2701 RT5665_PWR_BST3_BIT, 0, NULL, 0),
2702 SND_SOC_DAPM_SUPPLY("BST4 Power", RT5665_PWR_ANLG_2,
2703 RT5665_PWR_BST4_BIT, 0, NULL, 0),
2704 SND_SOC_DAPM_SUPPLY("BST1P Power", RT5665_PWR_ANLG_2,
2705 RT5665_PWR_BST1_P_BIT, 0, NULL, 0),
2706 SND_SOC_DAPM_SUPPLY("BST2P Power", RT5665_PWR_ANLG_2,
2707 RT5665_PWR_BST2_P_BIT, 0, NULL, 0),
2708 SND_SOC_DAPM_SUPPLY("BST3P Power", RT5665_PWR_ANLG_2,
2709 RT5665_PWR_BST3_P_BIT, 0, NULL, 0),
2710 SND_SOC_DAPM_SUPPLY("BST4P Power", RT5665_PWR_ANLG_2,
2711 RT5665_PWR_BST4_P_BIT, 0, NULL, 0),
2712 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5665_PWR_ANLG_3,
2713 RT5665_PWR_CBJ_BIT, 0, NULL, 0),
2717 SND_SOC_DAPM_PGA("INL VOL", RT5665_PWR_VOL, RT5665_PWR_IN_L_BIT,
2719 SND_SOC_DAPM_PGA("INR VOL", RT5665_PWR_VOL, RT5665_PWR_IN_R_BIT,
2723 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5665_rec1_l_mix,
2724 ARRAY_SIZE(rt5665_rec1_l_mix)),
2725 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5665_rec1_r_mix,
2726 ARRAY_SIZE(rt5665_rec1_r_mix)),
2727 SND_SOC_DAPM_MIXER("RECMIX2L", SND_SOC_NOPM, 0, 0, rt5665_rec2_l_mix,
2728 ARRAY_SIZE(rt5665_rec2_l_mix)),
2729 SND_SOC_DAPM_MIXER("RECMIX2R", SND_SOC_NOPM, 0, 0, rt5665_rec2_r_mix,
2730 ARRAY_SIZE(rt5665_rec2_r_mix)),
2731 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5665_PWR_ANLG_2,
2732 RT5665_PWR_RM1_L_BIT, 0, NULL, 0),
2733 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5665_PWR_ANLG_2,
2734 RT5665_PWR_RM1_R_BIT, 0, NULL, 0),
2735 SND_SOC_DAPM_SUPPLY("RECMIX2L Power", RT5665_PWR_MIXER,
2736 RT5665_PWR_RM2_L_BIT, 0, NULL, 0),
2737 SND_SOC_DAPM_SUPPLY("RECMIX2R Power", RT5665_PWR_MIXER,
2738 RT5665_PWR_RM2_R_BIT, 0, NULL, 0),
2741 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
2742 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
2743 SND_SOC_DAPM_ADC("ADC2 L", NULL, SND_SOC_NOPM, 0, 0),
2744 SND_SOC_DAPM_ADC("ADC2 R", NULL, SND_SOC_NOPM, 0, 0),
2746 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5665_PWR_DIG_1,
2747 RT5665_PWR_ADC_L1_BIT, 0, NULL, 0),
2748 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5665_PWR_DIG_1,
2749 RT5665_PWR_ADC_R1_BIT, 0, NULL, 0),
2750 SND_SOC_DAPM_SUPPLY("ADC2 L Power", RT5665_PWR_DIG_1,
2751 RT5665_PWR_ADC_L2_BIT, 0, NULL, 0),
2752 SND_SOC_DAPM_SUPPLY("ADC2 R Power", RT5665_PWR_DIG_1,
2753 RT5665_PWR_ADC_R2_BIT, 0, NULL, 0),
2754 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5665_CHOP_ADC,
2755 RT5665_CKGEN_ADC1_SFT, 0, NULL, 0),
2756 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5665_CHOP_ADC,
2757 RT5665_CKGEN_ADC2_SFT, 0, NULL, 0),
2760 SND_SOC_DAPM_MUX("Stereo1 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2761 &rt5665_sto1_dmic_mux),
2762 SND_SOC_DAPM_MUX("Stereo1 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2763 &rt5665_sto1_dmic_mux),
2764 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2765 &rt5665_sto1_adc1l_mux),
2766 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2767 &rt5665_sto1_adc1r_mux),
2768 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2769 &rt5665_sto1_adc2l_mux),
2770 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2771 &rt5665_sto1_adc2r_mux),
2772 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
2773 &rt5665_sto1_adcl_mux),
2774 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
2775 &rt5665_sto1_adcr_mux),
2776 SND_SOC_DAPM_MUX("Stereo1 DD L Mux", SND_SOC_NOPM, 0, 0,
2777 &rt5665_sto1_dd_l_mux),
2778 SND_SOC_DAPM_MUX("Stereo1 DD R Mux", SND_SOC_NOPM, 0, 0,
2779 &rt5665_sto1_dd_r_mux),
2780 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2781 &rt5665_mono_adc_l2_mux),
2782 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2783 &rt5665_mono_adc_r2_mux),
2784 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2785 &rt5665_mono_adc_l1_mux),
2786 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2787 &rt5665_mono_adc_r1_mux),
2788 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2789 &rt5665_mono_dmic_l_mux),
2790 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2791 &rt5665_mono_dmic_r_mux),
2792 SND_SOC_DAPM_MUX("Mono ADC L Mux", SND_SOC_NOPM, 0, 0,
2793 &rt5665_mono_adc_l_mux),
2794 SND_SOC_DAPM_MUX("Mono ADC R Mux", SND_SOC_NOPM, 0, 0,
2795 &rt5665_mono_adc_r_mux),
2796 SND_SOC_DAPM_MUX("Mono DD L Mux", SND_SOC_NOPM, 0, 0,
2797 &rt5665_mono_dd_l_mux),
2798 SND_SOC_DAPM_MUX("Mono DD R Mux", SND_SOC_NOPM, 0, 0,
2799 &rt5665_mono_dd_r_mux),
2800 SND_SOC_DAPM_MUX("Stereo2 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2801 &rt5665_sto2_dmic_mux),
2802 SND_SOC_DAPM_MUX("Stereo2 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2803 &rt5665_sto2_dmic_mux),
2804 SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2805 &rt5665_sto2_adc1l_mux),
2806 SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2807 &rt5665_sto2_adc1r_mux),
2808 SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2809 &rt5665_sto2_adc2l_mux),
2810 SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2811 &rt5665_sto2_adc2r_mux),
2812 SND_SOC_DAPM_MUX("Stereo2 ADC L Mux", SND_SOC_NOPM, 0, 0,
2813 &rt5665_sto2_adcl_mux),
2814 SND_SOC_DAPM_MUX("Stereo2 ADC R Mux", SND_SOC_NOPM, 0, 0,
2815 &rt5665_sto2_adcr_mux),
2816 SND_SOC_DAPM_MUX("Stereo2 DD L Mux", SND_SOC_NOPM, 0, 0,
2817 &rt5665_sto2_dd_l_mux),
2818 SND_SOC_DAPM_MUX("Stereo2 DD R Mux", SND_SOC_NOPM, 0, 0,
2819 &rt5665_sto2_dd_r_mux),
2821 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5665_PWR_DIG_2,
2822 RT5665_PWR_ADC_S1F_BIT, 0, NULL, 0),
2823 SND_SOC_DAPM_SUPPLY("ADC Stereo2 Filter", RT5665_PWR_DIG_2,
2824 RT5665_PWR_ADC_S2F_BIT, 0, NULL, 0),
2825 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5665_STO1_ADC_DIG_VOL,
2826 RT5665_L_MUTE_SFT, 1, rt5665_sto1_adc_l_mix,
2827 ARRAY_SIZE(rt5665_sto1_adc_l_mix)),
2828 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5665_STO1_ADC_DIG_VOL,
2829 RT5665_R_MUTE_SFT, 1, rt5665_sto1_adc_r_mix,
2830 ARRAY_SIZE(rt5665_sto1_adc_r_mix)),
2831 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXL", RT5665_STO2_ADC_DIG_VOL,
2832 RT5665_L_MUTE_SFT, 1, rt5665_sto2_adc_l_mix,
2833 ARRAY_SIZE(rt5665_sto2_adc_l_mix)),
2834 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXR", RT5665_STO2_ADC_DIG_VOL,
2835 RT5665_R_MUTE_SFT, 1, rt5665_sto2_adc_r_mix,
2836 ARRAY_SIZE(rt5665_sto2_adc_r_mix)),
2837 SND_SOC_DAPM_SUPPLY("ADC Mono Left Filter", RT5665_PWR_DIG_2,
2838 RT5665_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2839 SND_SOC_DAPM_MIXER("Mono ADC MIXL", RT5665_MONO_ADC_DIG_VOL,
2840 RT5665_L_MUTE_SFT, 1, rt5665_mono_adc_l_mix,
2841 ARRAY_SIZE(rt5665_mono_adc_l_mix)),
2842 SND_SOC_DAPM_SUPPLY("ADC Mono Right Filter", RT5665_PWR_DIG_2,
2843 RT5665_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2844 SND_SOC_DAPM_MIXER("Mono ADC MIXR", RT5665_MONO_ADC_DIG_VOL,
2845 RT5665_R_MUTE_SFT, 1, rt5665_mono_adc_r_mix,
2846 ARRAY_SIZE(rt5665_mono_adc_r_mix)),
2849 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2850 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2851 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2853 /* Digital Interface */
2854 SND_SOC_DAPM_SUPPLY("I2S1_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_1_BIT,
2856 SND_SOC_DAPM_SUPPLY("I2S1_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_2_BIT,
2858 SND_SOC_DAPM_SUPPLY("I2S2_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_1_BIT,
2860 SND_SOC_DAPM_SUPPLY("I2S2_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_2_BIT,
2862 SND_SOC_DAPM_SUPPLY("I2S3", RT5665_PWR_DIG_1, RT5665_PWR_I2S3_BIT,
2864 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2865 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2866 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2867 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2868 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2869 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2870 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2871 SND_SOC_DAPM_PGA("IF1 DAC3 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2872 SND_SOC_DAPM_PGA("IF1 DAC3 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2874 SND_SOC_DAPM_PGA("IF2_1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2875 SND_SOC_DAPM_PGA("IF2_2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2876 SND_SOC_DAPM_PGA("IF2_1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2877 SND_SOC_DAPM_PGA("IF2_1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2878 SND_SOC_DAPM_PGA("IF2_2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2879 SND_SOC_DAPM_PGA("IF2_2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2880 SND_SOC_DAPM_PGA("IF2_1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2881 SND_SOC_DAPM_PGA("IF2_2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2883 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2884 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2885 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2886 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2888 /* Digital Interface Select */
2889 SND_SOC_DAPM_MUX("IF1_1_ADC1 Mux", SND_SOC_NOPM, 0, 0,
2890 &rt5665_if1_1_adc1_mux),
2891 SND_SOC_DAPM_MUX("IF1_1_ADC2 Mux", SND_SOC_NOPM, 0, 0,
2892 &rt5665_if1_1_adc2_mux),
2893 SND_SOC_DAPM_MUX("IF1_1_ADC3 Mux", SND_SOC_NOPM, 0, 0,
2894 &rt5665_if1_1_adc3_mux),
2895 SND_SOC_DAPM_PGA("IF1_1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2896 SND_SOC_DAPM_MUX("IF1_2_ADC1 Mux", SND_SOC_NOPM, 0, 0,
2897 &rt5665_if1_2_adc1_mux),
2898 SND_SOC_DAPM_MUX("IF1_2_ADC2 Mux", SND_SOC_NOPM, 0, 0,
2899 &rt5665_if1_2_adc2_mux),
2900 SND_SOC_DAPM_MUX("IF1_2_ADC3 Mux", SND_SOC_NOPM, 0, 0,
2901 &rt5665_if1_2_adc3_mux),
2902 SND_SOC_DAPM_MUX("IF1_2_ADC4 Mux", SND_SOC_NOPM, 0, 0,
2903 &rt5665_if1_2_adc4_mux),
2904 SND_SOC_DAPM_MUX("TDM1 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
2905 &rt5665_tdm1_adc_mux),
2906 SND_SOC_DAPM_MUX("TDM1 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
2907 &rt5665_tdm1_adc_mux),
2908 SND_SOC_DAPM_MUX("TDM1 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
2909 &rt5665_tdm1_adc_mux),
2910 SND_SOC_DAPM_MUX("TDM1 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
2911 &rt5665_tdm1_adc_mux),
2912 SND_SOC_DAPM_MUX("TDM2 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
2913 &rt5665_tdm2_adc_mux),
2914 SND_SOC_DAPM_MUX("TDM2 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
2915 &rt5665_tdm2_adc_mux),
2916 SND_SOC_DAPM_MUX("TDM2 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
2917 &rt5665_tdm2_adc_mux),
2918 SND_SOC_DAPM_MUX("TDM2 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
2919 &rt5665_tdm2_adc_mux),
2920 SND_SOC_DAPM_MUX("IF2_1 ADC Mux", SND_SOC_NOPM, 0, 0,
2921 &rt5665_if2_1_adc_in_mux),
2922 SND_SOC_DAPM_MUX("IF2_2 ADC Mux", SND_SOC_NOPM, 0, 0,
2923 &rt5665_if2_2_adc_in_mux),
2924 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2925 &rt5665_if3_adc_in_mux),
2926 SND_SOC_DAPM_MUX("IF1_1 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2927 &rt5665_if1_1_01_adc_swap_mux),
2928 SND_SOC_DAPM_MUX("IF1_1 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2929 &rt5665_if1_1_01_adc_swap_mux),
2930 SND_SOC_DAPM_MUX("IF1_1 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2931 &rt5665_if1_1_23_adc_swap_mux),
2932 SND_SOC_DAPM_MUX("IF1_1 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2933 &rt5665_if1_1_23_adc_swap_mux),
2934 SND_SOC_DAPM_MUX("IF1_1 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2935 &rt5665_if1_1_45_adc_swap_mux),
2936 SND_SOC_DAPM_MUX("IF1_1 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2937 &rt5665_if1_1_45_adc_swap_mux),
2938 SND_SOC_DAPM_MUX("IF1_1 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2939 &rt5665_if1_1_67_adc_swap_mux),
2940 SND_SOC_DAPM_MUX("IF1_1 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2941 &rt5665_if1_1_67_adc_swap_mux),
2942 SND_SOC_DAPM_MUX("IF1_2 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2943 &rt5665_if1_2_01_adc_swap_mux),
2944 SND_SOC_DAPM_MUX("IF1_2 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2945 &rt5665_if1_2_01_adc_swap_mux),
2946 SND_SOC_DAPM_MUX("IF1_2 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2947 &rt5665_if1_2_23_adc_swap_mux),
2948 SND_SOC_DAPM_MUX("IF1_2 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2949 &rt5665_if1_2_23_adc_swap_mux),
2950 SND_SOC_DAPM_MUX("IF1_2 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2951 &rt5665_if1_2_45_adc_swap_mux),
2952 SND_SOC_DAPM_MUX("IF1_2 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2953 &rt5665_if1_2_45_adc_swap_mux),
2954 SND_SOC_DAPM_MUX("IF1_2 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2955 &rt5665_if1_2_67_adc_swap_mux),
2956 SND_SOC_DAPM_MUX("IF1_2 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2957 &rt5665_if1_2_67_adc_swap_mux),
2958 SND_SOC_DAPM_MUX("IF2_1 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
2959 &rt5665_if2_1_dac_swap_mux),
2960 SND_SOC_DAPM_MUX("IF2_1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2961 &rt5665_if2_1_adc_swap_mux),
2962 SND_SOC_DAPM_MUX("IF2_2 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
2963 &rt5665_if2_2_dac_swap_mux),
2964 SND_SOC_DAPM_MUX("IF2_2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2965 &rt5665_if2_2_adc_swap_mux),
2966 SND_SOC_DAPM_MUX("IF3 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
2967 &rt5665_if3_dac_swap_mux),
2968 SND_SOC_DAPM_MUX("IF3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2969 &rt5665_if3_adc_swap_mux),
2971 /* Audio Interface */
2972 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 0", "AIF1_1 Capture",
2973 0, SND_SOC_NOPM, 0, 0),
2974 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 1", "AIF1_1 Capture",
2975 1, SND_SOC_NOPM, 0, 0),
2976 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 2", "AIF1_1 Capture",
2977 2, SND_SOC_NOPM, 0, 0),
2978 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 3", "AIF1_1 Capture",
2979 3, SND_SOC_NOPM, 0, 0),
2980 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 4", "AIF1_1 Capture",
2981 4, SND_SOC_NOPM, 0, 0),
2982 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 5", "AIF1_1 Capture",
2983 5, SND_SOC_NOPM, 0, 0),
2984 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 6", "AIF1_1 Capture",
2985 6, SND_SOC_NOPM, 0, 0),
2986 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 7", "AIF1_1 Capture",
2987 7, SND_SOC_NOPM, 0, 0),
2988 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 0", "AIF1_2 Capture",
2989 0, SND_SOC_NOPM, 0, 0),
2990 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 1", "AIF1_2 Capture",
2991 1, SND_SOC_NOPM, 0, 0),
2992 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 2", "AIF1_2 Capture",
2993 2, SND_SOC_NOPM, 0, 0),
2994 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 3", "AIF1_2 Capture",
2995 3, SND_SOC_NOPM, 0, 0),
2996 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 4", "AIF1_2 Capture",
2997 4, SND_SOC_NOPM, 0, 0),
2998 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 5", "AIF1_2 Capture",
2999 5, SND_SOC_NOPM, 0, 0),
3000 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 6", "AIF1_2 Capture",
3001 6, SND_SOC_NOPM, 0, 0),
3002 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 7", "AIF1_2 Capture",
3003 7, SND_SOC_NOPM, 0, 0),
3004 SND_SOC_DAPM_AIF_OUT("AIF2_1TX", "AIF2_1 Capture",
3005 0, SND_SOC_NOPM, 0, 0),
3006 SND_SOC_DAPM_AIF_OUT("AIF2_2TX", "AIF2_2 Capture",
3007 0, SND_SOC_NOPM, 0, 0),
3008 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture",
3009 0, SND_SOC_NOPM, 0, 0),
3010 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback",
3011 0, SND_SOC_NOPM, 0, 0),
3012 SND_SOC_DAPM_AIF_IN("AIF2_1RX", "AIF2_1 Playback",
3013 0, SND_SOC_NOPM, 0, 0),
3014 SND_SOC_DAPM_AIF_IN("AIF2_2RX", "AIF2_2 Playback",
3015 0, SND_SOC_NOPM, 0, 0),
3016 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback",
3017 0, SND_SOC_NOPM, 0, 0),
3020 /* DAC mixer before sound effect */
3021 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
3022 rt5665_dac_l_mix, ARRAY_SIZE(rt5665_dac_l_mix)),
3023 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
3024 rt5665_dac_r_mix, ARRAY_SIZE(rt5665_dac_r_mix)),
3026 /* DAC channel Mux */
3027 SND_SOC_DAPM_MUX("DAC L1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l1_mux),
3028 SND_SOC_DAPM_MUX("DAC R1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r1_mux),
3029 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l2_mux),
3030 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r2_mux),
3031 SND_SOC_DAPM_MUX("DAC L3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l3_mux),
3032 SND_SOC_DAPM_MUX("DAC R3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r3_mux),
3034 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
3035 &rt5665_alg_dac_l1_mux),
3036 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
3037 &rt5665_alg_dac_r1_mux),
3038 SND_SOC_DAPM_MUX("DAC L2 Source", SND_SOC_NOPM, 0, 0,
3039 &rt5665_alg_dac_l2_mux),
3040 SND_SOC_DAPM_MUX("DAC R2 Source", SND_SOC_NOPM, 0, 0,
3041 &rt5665_alg_dac_r2_mux),
3044 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5665_PWR_DIG_2,
3045 RT5665_PWR_DAC_S1F_BIT, 0, NULL, 0),
3046 SND_SOC_DAPM_SUPPLY("DAC Stereo2 Filter", RT5665_PWR_DIG_2,
3047 RT5665_PWR_DAC_S2F_BIT, 0, NULL, 0),
3048 SND_SOC_DAPM_SUPPLY("DAC Mono Left Filter", RT5665_PWR_DIG_2,
3049 RT5665_PWR_DAC_MF_L_BIT, 0, NULL, 0),
3050 SND_SOC_DAPM_SUPPLY("DAC Mono Right Filter", RT5665_PWR_DIG_2,
3051 RT5665_PWR_DAC_MF_R_BIT, 0, NULL, 0),
3052 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
3053 rt5665_sto1_dac_l_mix, ARRAY_SIZE(rt5665_sto1_dac_l_mix)),
3054 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
3055 rt5665_sto1_dac_r_mix, ARRAY_SIZE(rt5665_sto1_dac_r_mix)),
3056 SND_SOC_DAPM_MIXER("Stereo2 DAC MIXL", SND_SOC_NOPM, 0, 0,
3057 rt5665_sto2_dac_l_mix, ARRAY_SIZE(rt5665_sto2_dac_l_mix)),
3058 SND_SOC_DAPM_MIXER("Stereo2 DAC MIXR", SND_SOC_NOPM, 0, 0,
3059 rt5665_sto2_dac_r_mix, ARRAY_SIZE(rt5665_sto2_dac_r_mix)),
3060 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
3061 rt5665_mono_dac_l_mix, ARRAY_SIZE(rt5665_mono_dac_l_mix)),
3062 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
3063 rt5665_mono_dac_r_mix, ARRAY_SIZE(rt5665_mono_dac_r_mix)),
3064 SND_SOC_DAPM_MUX("DAC MIXL", SND_SOC_NOPM, 0, 0,
3065 &rt5665_dig_dac_mixl_mux),
3066 SND_SOC_DAPM_MUX("DAC MIXR", SND_SOC_NOPM, 0, 0,
3067 &rt5665_dig_dac_mixr_mux),
3070 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
3071 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
3073 SND_SOC_DAPM_SUPPLY("DAC L2 Power", RT5665_PWR_DIG_1,
3074 RT5665_PWR_DAC_L2_BIT, 0, NULL, 0),
3075 SND_SOC_DAPM_SUPPLY("DAC R2 Power", RT5665_PWR_DIG_1,
3076 RT5665_PWR_DAC_R2_BIT, 0, NULL, 0),
3077 SND_SOC_DAPM_DAC("DAC L2", NULL, SND_SOC_NOPM, 0, 0),
3078 SND_SOC_DAPM_DAC("DAC R2", NULL, SND_SOC_NOPM, 0, 0),
3079 SND_SOC_DAPM_PGA("DAC1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3081 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 1, RT5665_CHOP_DAC,
3082 RT5665_CKGEN_DAC1_SFT, 0, NULL, 0),
3083 SND_SOC_DAPM_SUPPLY_S("DAC 2 Clock", 1, RT5665_CHOP_DAC,
3084 RT5665_CKGEN_DAC2_SFT, 0, NULL, 0),
3087 SND_SOC_DAPM_MIXER("MONOVOL MIX", RT5665_PWR_MIXER, RT5665_PWR_MM_BIT,
3088 0, rt5665_monovol_mix, ARRAY_SIZE(rt5665_monovol_mix)),
3089 SND_SOC_DAPM_MIXER("OUT MIXL", RT5665_PWR_MIXER, RT5665_PWR_OM_L_BIT,
3090 0, rt5665_out_l_mix, ARRAY_SIZE(rt5665_out_l_mix)),
3091 SND_SOC_DAPM_MIXER("OUT MIXR", RT5665_PWR_MIXER, RT5665_PWR_OM_R_BIT,
3092 0, rt5665_out_r_mix, ARRAY_SIZE(rt5665_out_r_mix)),
3095 SND_SOC_DAPM_SWITCH("MONOVOL", RT5665_PWR_VOL, RT5665_PWR_MV_BIT, 0,
3097 SND_SOC_DAPM_SWITCH("OUTVOL L", RT5665_PWR_VOL, RT5665_PWR_OV_L_BIT, 0,
3099 SND_SOC_DAPM_SWITCH("OUTVOL R", RT5665_PWR_VOL, RT5665_PWR_OV_R_BIT, 0,
3103 SND_SOC_DAPM_MIXER("Mono MIX", SND_SOC_NOPM, 0, 0, rt5665_mono_mix,
3104 ARRAY_SIZE(rt5665_mono_mix)),
3105 SND_SOC_DAPM_MIXER("LOUT L MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_l_mix,
3106 ARRAY_SIZE(rt5665_lout_l_mix)),
3107 SND_SOC_DAPM_MIXER("LOUT R MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_r_mix,
3108 ARRAY_SIZE(rt5665_lout_r_mix)),
3109 SND_SOC_DAPM_PGA_S("Mono Amp", 1, RT5665_PWR_ANLG_1, RT5665_PWR_MA_BIT,
3110 0, rt5665_mono_event, SND_SOC_DAPM_POST_PMD |
3111 SND_SOC_DAPM_PRE_PMU),
3112 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5665_hp_event,
3113 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
3114 SND_SOC_DAPM_PGA_S("LOUT Amp", 1, RT5665_PWR_ANLG_1,
3115 RT5665_PWR_LM_BIT, 0, rt5665_lout_event,
3116 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
3117 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
3119 SND_SOC_DAPM_SUPPLY("Charge Pump", SND_SOC_NOPM, 0, 0,
3120 rt5665_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
3121 SND_SOC_DAPM_POST_PMD),
3123 SND_SOC_DAPM_SWITCH("Mono Playback", SND_SOC_NOPM, 0, 0,
3125 SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
3127 SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
3129 SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
3131 SND_SOC_DAPM_SWITCH("PDM L Playback", SND_SOC_NOPM, 0, 0,
3133 SND_SOC_DAPM_SWITCH("PDM R Playback", SND_SOC_NOPM, 0, 0,
3137 SND_SOC_DAPM_SUPPLY("PDM Power", RT5665_PWR_DIG_2,
3138 RT5665_PWR_PDM1_BIT, 0, NULL, 0),
3139 SND_SOC_DAPM_MUX("PDM L Mux", SND_SOC_NOPM,
3140 0, 1, &rt5665_pdm_l_mux),
3141 SND_SOC_DAPM_MUX("PDM R Mux", SND_SOC_NOPM,
3142 0, 1, &rt5665_pdm_r_mux),
3145 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5665_CLK_DET, RT5665_SYS_CLK_DET,
3147 SND_SOC_DAPM_SUPPLY("CLKDET HP", RT5665_CLK_DET, RT5665_HP_CLK_DET,
3149 SND_SOC_DAPM_SUPPLY("CLKDET MONO", RT5665_CLK_DET, RT5665_MONO_CLK_DET,
3151 SND_SOC_DAPM_SUPPLY("CLKDET LOUT", RT5665_CLK_DET, RT5665_LOUT_CLK_DET,
3153 SND_SOC_DAPM_SUPPLY("CLKDET", RT5665_CLK_DET, RT5665_POW_CLK_DET,
3157 SND_SOC_DAPM_OUTPUT("HPOL"),
3158 SND_SOC_DAPM_OUTPUT("HPOR"),
3159 SND_SOC_DAPM_OUTPUT("LOUTL"),
3160 SND_SOC_DAPM_OUTPUT("LOUTR"),
3161 SND_SOC_DAPM_OUTPUT("MONOOUT"),
3162 SND_SOC_DAPM_OUTPUT("PDML"),
3163 SND_SOC_DAPM_OUTPUT("PDMR"),
3166 static const struct snd_soc_dapm_route rt5665_dapm_routes[] = {
3168 {"ADC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll},
3169 {"ADC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll},
3170 {"ADC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll},
3171 {"ADC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll},
3172 {"DAC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll},
3173 {"DAC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll},
3174 {"DAC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll},
3175 {"DAC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll},
3178 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
3179 {"ADC Mono Left Filter", NULL, "ADC Mono L ASRC", is_using_asrc},
3180 {"ADC Mono Right Filter", NULL, "ADC Mono R ASRC", is_using_asrc},
3181 {"DAC Mono Left Filter", NULL, "DAC Mono L ASRC", is_using_asrc},
3182 {"DAC Mono Right Filter", NULL, "DAC Mono R ASRC", is_using_asrc},
3183 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
3184 {"DAC Stereo2 Filter", NULL, "DAC STO2 ASRC", is_using_asrc},
3185 {"I2S1 ASRC", NULL, "CLKDET"},
3186 {"I2S2 ASRC", NULL, "CLKDET"},
3187 {"I2S3 ASRC", NULL, "CLKDET"},
3190 {"Mic Det Power", NULL, "Vref2"},
3191 {"MICBIAS1", NULL, "Vref1"},
3192 {"MICBIAS1", NULL, "Vref2"},
3193 {"MICBIAS2", NULL, "Vref1"},
3194 {"MICBIAS2", NULL, "Vref2"},
3195 {"MICBIAS3", NULL, "Vref1"},
3196 {"MICBIAS3", NULL, "Vref2"},
3198 {"Stereo1 DMIC L Mux", NULL, "DMIC STO1 ASRC"},
3199 {"Stereo1 DMIC R Mux", NULL, "DMIC STO1 ASRC"},
3200 {"Stereo2 DMIC L Mux", NULL, "DMIC STO2 ASRC"},
3201 {"Stereo2 DMIC R Mux", NULL, "DMIC STO2 ASRC"},
3202 {"Mono DMIC L Mux", NULL, "DMIC MONO L ASRC"},
3203 {"Mono DMIC R Mux", NULL, "DMIC MONO R ASRC"},
3205 {"I2S1_1", NULL, "I2S1 ASRC"},
3206 {"I2S1_2", NULL, "I2S1 ASRC"},
3207 {"I2S2_1", NULL, "I2S2 ASRC"},
3208 {"I2S2_2", NULL, "I2S2 ASRC"},
3209 {"I2S3", NULL, "I2S3 ASRC"},
3211 {"CLKDET SYS", NULL, "CLKDET"},
3212 {"CLKDET HP", NULL, "CLKDET"},
3213 {"CLKDET MONO", NULL, "CLKDET"},
3214 {"CLKDET LOUT", NULL, "CLKDET"},
3216 {"IN1P", NULL, "LDO2"},
3217 {"IN2P", NULL, "LDO2"},
3218 {"IN3P", NULL, "LDO2"},
3219 {"IN4P", NULL, "LDO2"},
3221 {"DMIC1", NULL, "DMIC L1"},
3222 {"DMIC1", NULL, "DMIC R1"},
3223 {"DMIC2", NULL, "DMIC L2"},
3224 {"DMIC2", NULL, "DMIC R2"},
3226 {"BST1", NULL, "IN1P"},
3227 {"BST1", NULL, "IN1N"},
3228 {"BST1", NULL, "BST1 Power"},
3229 {"BST1", NULL, "BST1P Power"},
3230 {"BST2", NULL, "IN2P"},
3231 {"BST2", NULL, "IN2N"},
3232 {"BST2", NULL, "BST2 Power"},
3233 {"BST2", NULL, "BST2P Power"},
3234 {"BST3", NULL, "IN3P"},
3235 {"BST3", NULL, "IN3N"},
3236 {"BST3", NULL, "BST3 Power"},
3237 {"BST3", NULL, "BST3P Power"},
3238 {"BST4", NULL, "IN4P"},
3239 {"BST4", NULL, "IN4N"},
3240 {"BST4", NULL, "BST4 Power"},
3241 {"BST4", NULL, "BST4P Power"},
3242 {"BST1 CBJ", NULL, "IN1P"},
3243 {"BST1 CBJ", NULL, "IN1N"},
3244 {"BST1 CBJ", NULL, "CBJ Power"},
3245 {"CBJ Power", NULL, "Vref2"},
3247 {"INL VOL", NULL, "IN3P"},
3248 {"INR VOL", NULL, "IN3N"},
3250 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
3251 {"RECMIX1L", "INL Switch", "INL VOL"},
3252 {"RECMIX1L", "INR Switch", "INR VOL"},
3253 {"RECMIX1L", "BST4 Switch", "BST4"},
3254 {"RECMIX1L", "BST3 Switch", "BST3"},
3255 {"RECMIX1L", "BST2 Switch", "BST2"},
3256 {"RECMIX1L", "BST1 Switch", "BST1"},
3257 {"RECMIX1L", NULL, "RECMIX1L Power"},
3259 {"RECMIX1R", "MONOVOL Switch", "MONOVOL"},
3260 {"RECMIX1R", "INR Switch", "INR VOL"},
3261 {"RECMIX1R", "BST4 Switch", "BST4"},
3262 {"RECMIX1R", "BST3 Switch", "BST3"},
3263 {"RECMIX1R", "BST2 Switch", "BST2"},
3264 {"RECMIX1R", "BST1 Switch", "BST1"},
3265 {"RECMIX1R", NULL, "RECMIX1R Power"},
3267 {"RECMIX2L", "CBJ Switch", "BST1 CBJ"},
3268 {"RECMIX2L", "INL Switch", "INL VOL"},
3269 {"RECMIX2L", "INR Switch", "INR VOL"},
3270 {"RECMIX2L", "BST4 Switch", "BST4"},
3271 {"RECMIX2L", "BST3 Switch", "BST3"},
3272 {"RECMIX2L", "BST2 Switch", "BST2"},
3273 {"RECMIX2L", "BST1 Switch", "BST1"},
3274 {"RECMIX2L", NULL, "RECMIX2L Power"},
3276 {"RECMIX2R", "MONOVOL Switch", "MONOVOL"},
3277 {"RECMIX2R", "INL Switch", "INL VOL"},
3278 {"RECMIX2R", "INR Switch", "INR VOL"},
3279 {"RECMIX2R", "BST4 Switch", "BST4"},
3280 {"RECMIX2R", "BST3 Switch", "BST3"},
3281 {"RECMIX2R", "BST2 Switch", "BST2"},
3282 {"RECMIX2R", "BST1 Switch", "BST1"},
3283 {"RECMIX2R", NULL, "RECMIX2R Power"},
3285 {"ADC1 L", NULL, "RECMIX1L"},
3286 {"ADC1 L", NULL, "ADC1 L Power"},
3287 {"ADC1 L", NULL, "ADC1 clock"},
3288 {"ADC1 R", NULL, "RECMIX1R"},
3289 {"ADC1 R", NULL, "ADC1 R Power"},
3290 {"ADC1 R", NULL, "ADC1 clock"},
3292 {"ADC2 L", NULL, "RECMIX2L"},
3293 {"ADC2 L", NULL, "ADC2 L Power"},
3294 {"ADC2 L", NULL, "ADC2 clock"},
3295 {"ADC2 R", NULL, "RECMIX2R"},
3296 {"ADC2 R", NULL, "ADC2 R Power"},
3297 {"ADC2 R", NULL, "ADC2 clock"},
3299 {"DMIC L1", NULL, "DMIC CLK"},
3300 {"DMIC L1", NULL, "DMIC1 Power"},
3301 {"DMIC R1", NULL, "DMIC CLK"},
3302 {"DMIC R1", NULL, "DMIC1 Power"},
3303 {"DMIC L2", NULL, "DMIC CLK"},
3304 {"DMIC L2", NULL, "DMIC2 Power"},
3305 {"DMIC R2", NULL, "DMIC CLK"},
3306 {"DMIC R2", NULL, "DMIC2 Power"},
3308 {"Stereo1 DMIC L Mux", "DMIC1", "DMIC L1"},
3309 {"Stereo1 DMIC L Mux", "DMIC2", "DMIC L2"},
3311 {"Stereo1 DMIC R Mux", "DMIC1", "DMIC R1"},
3312 {"Stereo1 DMIC R Mux", "DMIC2", "DMIC R2"},
3314 {"Mono DMIC L Mux", "DMIC1 L", "DMIC L1"},
3315 {"Mono DMIC L Mux", "DMIC2 L", "DMIC L2"},
3317 {"Mono DMIC R Mux", "DMIC1 R", "DMIC R1"},
3318 {"Mono DMIC R Mux", "DMIC2 R", "DMIC R2"},
3320 {"Stereo2 DMIC L Mux", "DMIC1", "DMIC L1"},
3321 {"Stereo2 DMIC L Mux", "DMIC2", "DMIC L2"},
3323 {"Stereo2 DMIC R Mux", "DMIC1", "DMIC R1"},
3324 {"Stereo2 DMIC R Mux", "DMIC2", "DMIC R2"},
3326 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
3327 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
3328 {"Stereo1 ADC L Mux", "ADC2 L", "ADC2 L"},
3329 {"Stereo1 ADC L Mux", "ADC2 R", "ADC2 R"},
3330 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
3331 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
3332 {"Stereo1 ADC R Mux", "ADC2 L", "ADC2 L"},
3333 {"Stereo1 ADC R Mux", "ADC2 R", "ADC2 R"},
3335 {"Stereo1 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3336 {"Stereo1 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3338 {"Stereo1 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3339 {"Stereo1 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3341 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
3342 {"Stereo1 ADC L1 Mux", "DD Mux", "Stereo1 DD L Mux"},
3343 {"Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC L Mux"},
3344 {"Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
3346 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
3347 {"Stereo1 ADC R1 Mux", "DD Mux", "Stereo1 DD R Mux"},
3348 {"Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC R Mux"},
3349 {"Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
3351 {"Mono ADC L Mux", "ADC1 L", "ADC1 L"},
3352 {"Mono ADC L Mux", "ADC1 R", "ADC1 R"},
3353 {"Mono ADC L Mux", "ADC2 L", "ADC2 L"},
3354 {"Mono ADC L Mux", "ADC2 R", "ADC2 R"},
3356 {"Mono ADC R Mux", "ADC1 L", "ADC1 L"},
3357 {"Mono ADC R Mux", "ADC1 R", "ADC1 R"},
3358 {"Mono ADC R Mux", "ADC2 L", "ADC2 L"},
3359 {"Mono ADC R Mux", "ADC2 R", "ADC2 R"},
3361 {"Mono DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3362 {"Mono DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3364 {"Mono DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3365 {"Mono DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3367 {"Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux"},
3368 {"Mono ADC L2 Mux", "DAC MIXL", "DAC MIXL"},
3369 {"Mono ADC L1 Mux", "DD Mux", "Mono DD L Mux"},
3370 {"Mono ADC L1 Mux", "ADC", "Mono ADC L Mux"},
3372 {"Mono ADC R1 Mux", "DD Mux", "Mono DD R Mux"},
3373 {"Mono ADC R1 Mux", "ADC", "Mono ADC R Mux"},
3374 {"Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux"},
3375 {"Mono ADC R2 Mux", "DAC MIXR", "DAC MIXR"},
3377 {"Stereo2 ADC L Mux", "ADC1 L", "ADC1 L"},
3378 {"Stereo2 ADC L Mux", "ADC2 L", "ADC2 L"},
3379 {"Stereo2 ADC L Mux", "ADC1 R", "ADC1 R"},
3380 {"Stereo2 ADC R Mux", "ADC1 L", "ADC1 L"},
3381 {"Stereo2 ADC R Mux", "ADC2 L", "ADC2 L"},
3382 {"Stereo2 ADC R Mux", "ADC1 R", "ADC1 R"},
3384 {"Stereo2 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3385 {"Stereo2 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3387 {"Stereo2 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3388 {"Stereo2 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3390 {"Stereo2 ADC L1 Mux", "ADC", "Stereo2 ADC L Mux"},
3391 {"Stereo2 ADC L1 Mux", "DD Mux", "Stereo2 DD L Mux"},
3392 {"Stereo2 ADC L2 Mux", "DMIC", "Stereo2 DMIC L Mux"},
3393 {"Stereo2 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
3395 {"Stereo2 ADC R1 Mux", "ADC", "Stereo2 ADC R Mux"},
3396 {"Stereo2 ADC R1 Mux", "DD Mux", "Stereo2 DD R Mux"},
3397 {"Stereo2 ADC R2 Mux", "DMIC", "Stereo2 DMIC R Mux"},
3398 {"Stereo2 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
3400 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
3401 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
3402 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
3404 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
3405 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
3406 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
3408 {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
3409 {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
3410 {"Mono ADC MIXL", NULL, "ADC Mono Left Filter"},
3412 {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
3413 {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
3414 {"Mono ADC MIXR", NULL, "ADC Mono Right Filter"},
3416 {"Stereo2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux"},
3417 {"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"},
3418 {"Stereo2 ADC MIXL", NULL, "ADC Stereo2 Filter"},
3420 {"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"},
3421 {"Stereo2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux"},
3422 {"Stereo2 ADC MIXR", NULL, "ADC Stereo2 Filter"},
3424 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
3425 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
3426 {"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL"},
3427 {"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR"},
3428 {"Mono ADC MIX", NULL, "Mono ADC MIXL"},
3429 {"Mono ADC MIX", NULL, "Mono ADC MIXR"},
3431 {"IF1_1_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3432 {"IF1_1_ADC1 Mux", "IF2_1 DAC", "IF2_1 DAC"},
3433 {"IF1_1_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3434 {"IF1_1_ADC2 Mux", "IF2_2 DAC", "IF2_2 DAC"},
3435 {"IF1_1_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
3436 {"IF1_1_ADC3 Mux", "IF3 DAC", "IF3 DAC"},
3437 {"IF1_1_ADC4", NULL, "DAC1 MIX"},
3439 {"IF1_2_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3440 {"IF1_2_ADC1 Mux", "IF1 DAC", "IF1 DAC1"},
3441 {"IF1_2_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3442 {"IF1_2_ADC2 Mux", "IF2_1 DAC", "IF2_1 DAC"},
3443 {"IF1_2_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
3444 {"IF1_2_ADC3 Mux", "IF2_2 DAC", "IF2_2 DAC"},
3445 {"IF1_2_ADC4 Mux", "DAC1", "DAC1 MIX"},
3446 {"IF1_2_ADC4 Mux", "IF3 DAC", "IF3 DAC"},
3448 {"TDM1 slot 01 Data Mux", "1234", "IF1_1_ADC1 Mux"},
3449 {"TDM1 slot 01 Data Mux", "1243", "IF1_1_ADC1 Mux"},
3450 {"TDM1 slot 01 Data Mux", "1324", "IF1_1_ADC1 Mux"},
3451 {"TDM1 slot 01 Data Mux", "1342", "IF1_1_ADC1 Mux"},
3452 {"TDM1 slot 01 Data Mux", "1432", "IF1_1_ADC1 Mux"},
3453 {"TDM1 slot 01 Data Mux", "1423", "IF1_1_ADC1 Mux"},
3454 {"TDM1 slot 01 Data Mux", "2134", "IF1_1_ADC2 Mux"},
3455 {"TDM1 slot 01 Data Mux", "2143", "IF1_1_ADC2 Mux"},
3456 {"TDM1 slot 01 Data Mux", "2314", "IF1_1_ADC2 Mux"},
3457 {"TDM1 slot 01 Data Mux", "2341", "IF1_1_ADC2 Mux"},
3458 {"TDM1 slot 01 Data Mux", "2431", "IF1_1_ADC2 Mux"},
3459 {"TDM1 slot 01 Data Mux", "2413", "IF1_1_ADC2 Mux"},
3460 {"TDM1 slot 01 Data Mux", "3124", "IF1_1_ADC3 Mux"},
3461 {"TDM1 slot 01 Data Mux", "3142", "IF1_1_ADC3 Mux"},
3462 {"TDM1 slot 01 Data Mux", "3214", "IF1_1_ADC3 Mux"},
3463 {"TDM1 slot 01 Data Mux", "3241", "IF1_1_ADC3 Mux"},
3464 {"TDM1 slot 01 Data Mux", "3412", "IF1_1_ADC3 Mux"},
3465 {"TDM1 slot 01 Data Mux", "3421", "IF1_1_ADC3 Mux"},
3466 {"TDM1 slot 01 Data Mux", "4123", "IF1_1_ADC4"},
3467 {"TDM1 slot 01 Data Mux", "4132", "IF1_1_ADC4"},
3468 {"TDM1 slot 01 Data Mux", "4213", "IF1_1_ADC4"},
3469 {"TDM1 slot 01 Data Mux", "4231", "IF1_1_ADC4"},
3470 {"TDM1 slot 01 Data Mux", "4312", "IF1_1_ADC4"},
3471 {"TDM1 slot 01 Data Mux", "4321", "IF1_1_ADC4"},
3472 {"TDM1 slot 01 Data Mux", NULL, "I2S1_1"},
3474 {"TDM1 slot 23 Data Mux", "1234", "IF1_1_ADC2 Mux"},
3475 {"TDM1 slot 23 Data Mux", "1243", "IF1_1_ADC2 Mux"},
3476 {"TDM1 slot 23 Data Mux", "1324", "IF1_1_ADC3 Mux"},
3477 {"TDM1 slot 23 Data Mux", "1342", "IF1_1_ADC3 Mux"},
3478 {"TDM1 slot 23 Data Mux", "1432", "IF1_1_ADC4"},
3479 {"TDM1 slot 23 Data Mux", "1423", "IF1_1_ADC4"},
3480 {"TDM1 slot 23 Data Mux", "2134", "IF1_1_ADC1 Mux"},
3481 {"TDM1 slot 23 Data Mux", "2143", "IF1_1_ADC1 Mux"},
3482 {"TDM1 slot 23 Data Mux", "2314", "IF1_1_ADC3 Mux"},
3483 {"TDM1 slot 23 Data Mux", "2341", "IF1_1_ADC3 Mux"},
3484 {"TDM1 slot 23 Data Mux", "2431", "IF1_1_ADC4"},
3485 {"TDM1 slot 23 Data Mux", "2413", "IF1_1_ADC4"},
3486 {"TDM1 slot 23 Data Mux", "3124", "IF1_1_ADC1 Mux"},
3487 {"TDM1 slot 23 Data Mux", "3142", "IF1_1_ADC1 Mux"},
3488 {"TDM1 slot 23 Data Mux", "3214", "IF1_1_ADC2 Mux"},
3489 {"TDM1 slot 23 Data Mux", "3241", "IF1_1_ADC2 Mux"},
3490 {"TDM1 slot 23 Data Mux", "3412", "IF1_1_ADC4"},
3491 {"TDM1 slot 23 Data Mux", "3421", "IF1_1_ADC4"},
3492 {"TDM1 slot 23 Data Mux", "4123", "IF1_1_ADC1 Mux"},
3493 {"TDM1 slot 23 Data Mux", "4132", "IF1_1_ADC1 Mux"},
3494 {"TDM1 slot 23 Data Mux", "4213", "IF1_1_ADC2 Mux"},
3495 {"TDM1 slot 23 Data Mux", "4231", "IF1_1_ADC2 Mux"},
3496 {"TDM1 slot 23 Data Mux", "4312", "IF1_1_ADC3 Mux"},
3497 {"TDM1 slot 23 Data Mux", "4321", "IF1_1_ADC3 Mux"},
3498 {"TDM1 slot 23 Data Mux", NULL, "I2S1_1"},
3500 {"TDM1 slot 45 Data Mux", "1234", "IF1_1_ADC3 Mux"},
3501 {"TDM1 slot 45 Data Mux", "1243", "IF1_1_ADC4"},
3502 {"TDM1 slot 45 Data Mux", "1324", "IF1_1_ADC2 Mux"},
3503 {"TDM1 slot 45 Data Mux", "1342", "IF1_1_ADC4"},
3504 {"TDM1 slot 45 Data Mux", "1432", "IF1_1_ADC3 Mux"},
3505 {"TDM1 slot 45 Data Mux", "1423", "IF1_1_ADC2 Mux"},
3506 {"TDM1 slot 45 Data Mux", "2134", "IF1_1_ADC3 Mux"},
3507 {"TDM1 slot 45 Data Mux", "2143", "IF1_1_ADC4"},
3508 {"TDM1 slot 45 Data Mux", "2314", "IF1_1_ADC1 Mux"},
3509 {"TDM1 slot 45 Data Mux", "2341", "IF1_1_ADC4"},
3510 {"TDM1 slot 45 Data Mux", "2431", "IF1_1_ADC3 Mux"},
3511 {"TDM1 slot 45 Data Mux", "2413", "IF1_1_ADC1 Mux"},
3512 {"TDM1 slot 45 Data Mux", "3124", "IF1_1_ADC2 Mux"},
3513 {"TDM1 slot 45 Data Mux", "3142", "IF1_1_ADC4"},
3514 {"TDM1 slot 45 Data Mux", "3214", "IF1_1_ADC1 Mux"},
3515 {"TDM1 slot 45 Data Mux", "3241", "IF1_1_ADC4"},
3516 {"TDM1 slot 45 Data Mux", "3412", "IF1_1_ADC1 Mux"},
3517 {"TDM1 slot 45 Data Mux", "3421", "IF1_1_ADC2 Mux"},
3518 {"TDM1 slot 45 Data Mux", "4123", "IF1_1_ADC2 Mux"},
3519 {"TDM1 slot 45 Data Mux", "4132", "IF1_1_ADC3 Mux"},
3520 {"TDM1 slot 45 Data Mux", "4213", "IF1_1_ADC1 Mux"},
3521 {"TDM1 slot 45 Data Mux", "4231", "IF1_1_ADC3 Mux"},
3522 {"TDM1 slot 45 Data Mux", "4312", "IF1_1_ADC1 Mux"},
3523 {"TDM1 slot 45 Data Mux", "4321", "IF1_1_ADC2 Mux"},
3524 {"TDM1 slot 45 Data Mux", NULL, "I2S1_1"},
3526 {"TDM1 slot 67 Data Mux", "1234", "IF1_1_ADC4"},
3527 {"TDM1 slot 67 Data Mux", "1243", "IF1_1_ADC3 Mux"},
3528 {"TDM1 slot 67 Data Mux", "1324", "IF1_1_ADC4"},
3529 {"TDM1 slot 67 Data Mux", "1342", "IF1_1_ADC2 Mux"},
3530 {"TDM1 slot 67 Data Mux", "1432", "IF1_1_ADC2 Mux"},
3531 {"TDM1 slot 67 Data Mux", "1423", "IF1_1_ADC3 Mux"},
3532 {"TDM1 slot 67 Data Mux", "2134", "IF1_1_ADC4"},
3533 {"TDM1 slot 67 Data Mux", "2143", "IF1_1_ADC3 Mux"},
3534 {"TDM1 slot 67 Data Mux", "2314", "IF1_1_ADC4"},
3535 {"TDM1 slot 67 Data Mux", "2341", "IF1_1_ADC1 Mux"},
3536 {"TDM1 slot 67 Data Mux", "2431", "IF1_1_ADC1 Mux"},
3537 {"TDM1 slot 67 Data Mux", "2413", "IF1_1_ADC3 Mux"},
3538 {"TDM1 slot 67 Data Mux", "3124", "IF1_1_ADC4"},
3539 {"TDM1 slot 67 Data Mux", "3142", "IF1_1_ADC2 Mux"},
3540 {"TDM1 slot 67 Data Mux", "3214", "IF1_1_ADC4"},
3541 {"TDM1 slot 67 Data Mux", "3241", "IF1_1_ADC1 Mux"},
3542 {"TDM1 slot 67 Data Mux", "3412", "IF1_1_ADC2 Mux"},
3543 {"TDM1 slot 67 Data Mux", "3421", "IF1_1_ADC1 Mux"},
3544 {"TDM1 slot 67 Data Mux", "4123", "IF1_1_ADC3 Mux"},
3545 {"TDM1 slot 67 Data Mux", "4132", "IF1_1_ADC2 Mux"},
3546 {"TDM1 slot 67 Data Mux", "4213", "IF1_1_ADC3 Mux"},
3547 {"TDM1 slot 67 Data Mux", "4231", "IF1_1_ADC1 Mux"},
3548 {"TDM1 slot 67 Data Mux", "4312", "IF1_1_ADC2 Mux"},
3549 {"TDM1 slot 67 Data Mux", "4321", "IF1_1_ADC1 Mux"},
3550 {"TDM1 slot 67 Data Mux", NULL, "I2S1_1"},
3553 {"TDM2 slot 01 Data Mux", "1234", "IF1_2_ADC1 Mux"},
3554 {"TDM2 slot 01 Data Mux", "1243", "IF1_2_ADC1 Mux"},
3555 {"TDM2 slot 01 Data Mux", "1324", "IF1_2_ADC1 Mux"},
3556 {"TDM2 slot 01 Data Mux", "1342", "IF1_2_ADC1 Mux"},
3557 {"TDM2 slot 01 Data Mux", "1432", "IF1_2_ADC1 Mux"},
3558 {"TDM2 slot 01 Data Mux", "1423", "IF1_2_ADC1 Mux"},
3559 {"TDM2 slot 01 Data Mux", "2134", "IF1_2_ADC2 Mux"},
3560 {"TDM2 slot 01 Data Mux", "2143", "IF1_2_ADC2 Mux"},
3561 {"TDM2 slot 01 Data Mux", "2314", "IF1_2_ADC2 Mux"},
3562 {"TDM2 slot 01 Data Mux", "2341", "IF1_2_ADC2 Mux"},
3563 {"TDM2 slot 01 Data Mux", "2431", "IF1_2_ADC2 Mux"},
3564 {"TDM2 slot 01 Data Mux", "2413", "IF1_2_ADC2 Mux"},
3565 {"TDM2 slot 01 Data Mux", "3124", "IF1_2_ADC3 Mux"},
3566 {"TDM2 slot 01 Data Mux", "3142", "IF1_2_ADC3 Mux"},
3567 {"TDM2 slot 01 Data Mux", "3214", "IF1_2_ADC3 Mux"},
3568 {"TDM2 slot 01 Data Mux", "3241", "IF1_2_ADC3 Mux"},
3569 {"TDM2 slot 01 Data Mux", "3412", "IF1_2_ADC3 Mux"},
3570 {"TDM2 slot 01 Data Mux", "3421", "IF1_2_ADC3 Mux"},
3571 {"TDM2 slot 01 Data Mux", "4123", "IF1_2_ADC4 Mux"},
3572 {"TDM2 slot 01 Data Mux", "4132", "IF1_2_ADC4 Mux"},
3573 {"TDM2 slot 01 Data Mux", "4213", "IF1_2_ADC4 Mux"},
3574 {"TDM2 slot 01 Data Mux", "4231", "IF1_2_ADC4 Mux"},
3575 {"TDM2 slot 01 Data Mux", "4312", "IF1_2_ADC4 Mux"},
3576 {"TDM2 slot 01 Data Mux", "4321", "IF1_2_ADC4 Mux"},
3577 {"TDM2 slot 01 Data Mux", NULL, "I2S1_2"},
3579 {"TDM2 slot 23 Data Mux", "1234", "IF1_2_ADC2 Mux"},
3580 {"TDM2 slot 23 Data Mux", "1243", "IF1_2_ADC2 Mux"},
3581 {"TDM2 slot 23 Data Mux", "1324", "IF1_2_ADC3 Mux"},
3582 {"TDM2 slot 23 Data Mux", "1342", "IF1_2_ADC3 Mux"},
3583 {"TDM2 slot 23 Data Mux", "1432", "IF1_2_ADC4 Mux"},
3584 {"TDM2 slot 23 Data Mux", "1423", "IF1_2_ADC4 Mux"},
3585 {"TDM2 slot 23 Data Mux", "2134", "IF1_2_ADC1 Mux"},
3586 {"TDM2 slot 23 Data Mux", "2143", "IF1_2_ADC1 Mux"},
3587 {"TDM2 slot 23 Data Mux", "2314", "IF1_2_ADC3 Mux"},
3588 {"TDM2 slot 23 Data Mux", "2341", "IF1_2_ADC3 Mux"},
3589 {"TDM2 slot 23 Data Mux", "2431", "IF1_2_ADC4 Mux"},
3590 {"TDM2 slot 23 Data Mux", "2413", "IF1_2_ADC4 Mux"},
3591 {"TDM2 slot 23 Data Mux", "3124", "IF1_2_ADC1 Mux"},
3592 {"TDM2 slot 23 Data Mux", "3142", "IF1_2_ADC1 Mux"},
3593 {"TDM2 slot 23 Data Mux", "3214", "IF1_2_ADC2 Mux"},
3594 {"TDM2 slot 23 Data Mux", "3241", "IF1_2_ADC2 Mux"},
3595 {"TDM2 slot 23 Data Mux", "3412", "IF1_2_ADC4 Mux"},
3596 {"TDM2 slot 23 Data Mux", "3421", "IF1_2_ADC4 Mux"},
3597 {"TDM2 slot 23 Data Mux", "4123", "IF1_2_ADC1 Mux"},
3598 {"TDM2 slot 23 Data Mux", "4132", "IF1_2_ADC1 Mux"},
3599 {"TDM2 slot 23 Data Mux", "4213", "IF1_2_ADC2 Mux"},
3600 {"TDM2 slot 23 Data Mux", "4231", "IF1_2_ADC2 Mux"},
3601 {"TDM2 slot 23 Data Mux", "4312", "IF1_2_ADC3 Mux"},
3602 {"TDM2 slot 23 Data Mux", "4321", "IF1_2_ADC3 Mux"},
3603 {"TDM2 slot 23 Data Mux", NULL, "I2S1_2"},
3605 {"TDM2 slot 45 Data Mux", "1234", "IF1_2_ADC3 Mux"},
3606 {"TDM2 slot 45 Data Mux", "1243", "IF1_2_ADC4 Mux"},
3607 {"TDM2 slot 45 Data Mux", "1324", "IF1_2_ADC2 Mux"},
3608 {"TDM2 slot 45 Data Mux", "1342", "IF1_2_ADC4 Mux"},
3609 {"TDM2 slot 45 Data Mux", "1432", "IF1_2_ADC3 Mux"},
3610 {"TDM2 slot 45 Data Mux", "1423", "IF1_2_ADC2 Mux"},
3611 {"TDM2 slot 45 Data Mux", "2134", "IF1_2_ADC3 Mux"},
3612 {"TDM2 slot 45 Data Mux", "2143", "IF1_2_ADC4 Mux"},
3613 {"TDM2 slot 45 Data Mux", "2314", "IF1_2_ADC1 Mux"},
3614 {"TDM2 slot 45 Data Mux", "2341", "IF1_2_ADC4 Mux"},
3615 {"TDM2 slot 45 Data Mux", "2431", "IF1_2_ADC3 Mux"},
3616 {"TDM2 slot 45 Data Mux", "2413", "IF1_2_ADC1 Mux"},
3617 {"TDM2 slot 45 Data Mux", "3124", "IF1_2_ADC2 Mux"},
3618 {"TDM2 slot 45 Data Mux", "3142", "IF1_2_ADC4 Mux"},
3619 {"TDM2 slot 45 Data Mux", "3214", "IF1_2_ADC1 Mux"},
3620 {"TDM2 slot 45 Data Mux", "3241", "IF1_2_ADC4 Mux"},
3621 {"TDM2 slot 45 Data Mux", "3412", "IF1_2_ADC1 Mux"},
3622 {"TDM2 slot 45 Data Mux", "3421", "IF1_2_ADC2 Mux"},
3623 {"TDM2 slot 45 Data Mux", "4123", "IF1_2_ADC2 Mux"},
3624 {"TDM2 slot 45 Data Mux", "4132", "IF1_2_ADC3 Mux"},
3625 {"TDM2 slot 45 Data Mux", "4213", "IF1_2_ADC1 Mux"},
3626 {"TDM2 slot 45 Data Mux", "4231", "IF1_2_ADC3 Mux"},
3627 {"TDM2 slot 45 Data Mux", "4312", "IF1_2_ADC1 Mux"},
3628 {"TDM2 slot 45 Data Mux", "4321", "IF1_2_ADC2 Mux"},
3629 {"TDM2 slot 45 Data Mux", NULL, "I2S1_2"},
3631 {"TDM2 slot 67 Data Mux", "1234", "IF1_2_ADC4 Mux"},
3632 {"TDM2 slot 67 Data Mux", "1243", "IF1_2_ADC3 Mux"},
3633 {"TDM2 slot 67 Data Mux", "1324", "IF1_2_ADC4 Mux"},
3634 {"TDM2 slot 67 Data Mux", "1342", "IF1_2_ADC2 Mux"},
3635 {"TDM2 slot 67 Data Mux", "1432", "IF1_2_ADC2 Mux"},
3636 {"TDM2 slot 67 Data Mux", "1423", "IF1_2_ADC3 Mux"},
3637 {"TDM2 slot 67 Data Mux", "2134", "IF1_2_ADC4 Mux"},
3638 {"TDM2 slot 67 Data Mux", "2143", "IF1_2_ADC3 Mux"},
3639 {"TDM2 slot 67 Data Mux", "2314", "IF1_2_ADC4 Mux"},
3640 {"TDM2 slot 67 Data Mux", "2341", "IF1_2_ADC1 Mux"},
3641 {"TDM2 slot 67 Data Mux", "2431", "IF1_2_ADC1 Mux"},
3642 {"TDM2 slot 67 Data Mux", "2413", "IF1_2_ADC3 Mux"},
3643 {"TDM2 slot 67 Data Mux", "3124", "IF1_2_ADC4 Mux"},
3644 {"TDM2 slot 67 Data Mux", "3142", "IF1_2_ADC2 Mux"},
3645 {"TDM2 slot 67 Data Mux", "3214", "IF1_2_ADC4 Mux"},
3646 {"TDM2 slot 67 Data Mux", "3241", "IF1_2_ADC1 Mux"},
3647 {"TDM2 slot 67 Data Mux", "3412", "IF1_2_ADC2 Mux"},
3648 {"TDM2 slot 67 Data Mux", "3421", "IF1_2_ADC1 Mux"},
3649 {"TDM2 slot 67 Data Mux", "4123", "IF1_2_ADC3 Mux"},
3650 {"TDM2 slot 67 Data Mux", "4132", "IF1_2_ADC2 Mux"},
3651 {"TDM2 slot 67 Data Mux", "4213", "IF1_2_ADC3 Mux"},
3652 {"TDM2 slot 67 Data Mux", "4231", "IF1_2_ADC1 Mux"},
3653 {"TDM2 slot 67 Data Mux", "4312", "IF1_2_ADC2 Mux"},
3654 {"TDM2 slot 67 Data Mux", "4321", "IF1_2_ADC1 Mux"},
3655 {"TDM2 slot 67 Data Mux", NULL, "I2S1_2"},
3657 {"IF1_1 0 ADC Swap Mux", "L/R", "TDM1 slot 01 Data Mux"},
3658 {"IF1_1 0 ADC Swap Mux", "L/L", "TDM1 slot 01 Data Mux"},
3659 {"IF1_1 1 ADC Swap Mux", "R/L", "TDM1 slot 01 Data Mux"},
3660 {"IF1_1 1 ADC Swap Mux", "R/R", "TDM1 slot 01 Data Mux"},
3661 {"IF1_1 2 ADC Swap Mux", "L/R", "TDM1 slot 23 Data Mux"},
3662 {"IF1_1 2 ADC Swap Mux", "R/L", "TDM1 slot 23 Data Mux"},
3663 {"IF1_1 3 ADC Swap Mux", "L/L", "TDM1 slot 23 Data Mux"},
3664 {"IF1_1 3 ADC Swap Mux", "R/R", "TDM1 slot 23 Data Mux"},
3665 {"IF1_1 4 ADC Swap Mux", "L/R", "TDM1 slot 45 Data Mux"},
3666 {"IF1_1 4 ADC Swap Mux", "R/L", "TDM1 slot 45 Data Mux"},
3667 {"IF1_1 5 ADC Swap Mux", "L/L", "TDM1 slot 45 Data Mux"},
3668 {"IF1_1 5 ADC Swap Mux", "R/R", "TDM1 slot 45 Data Mux"},
3669 {"IF1_1 6 ADC Swap Mux", "L/R", "TDM1 slot 67 Data Mux"},
3670 {"IF1_1 6 ADC Swap Mux", "R/L", "TDM1 slot 67 Data Mux"},
3671 {"IF1_1 7 ADC Swap Mux", "L/L", "TDM1 slot 67 Data Mux"},
3672 {"IF1_1 7 ADC Swap Mux", "R/R", "TDM1 slot 67 Data Mux"},
3673 {"IF1_2 0 ADC Swap Mux", "L/R", "TDM2 slot 01 Data Mux"},
3674 {"IF1_2 0 ADC Swap Mux", "R/L", "TDM2 slot 01 Data Mux"},
3675 {"IF1_2 1 ADC Swap Mux", "L/L", "TDM2 slot 01 Data Mux"},
3676 {"IF1_2 1 ADC Swap Mux", "R/R", "TDM2 slot 01 Data Mux"},
3677 {"IF1_2 2 ADC Swap Mux", "L/R", "TDM2 slot 23 Data Mux"},
3678 {"IF1_2 2 ADC Swap Mux", "R/L", "TDM2 slot 23 Data Mux"},
3679 {"IF1_2 3 ADC Swap Mux", "L/L", "TDM2 slot 23 Data Mux"},
3680 {"IF1_2 3 ADC Swap Mux", "R/R", "TDM2 slot 23 Data Mux"},
3681 {"IF1_2 4 ADC Swap Mux", "L/R", "TDM2 slot 45 Data Mux"},
3682 {"IF1_2 4 ADC Swap Mux", "R/L", "TDM2 slot 45 Data Mux"},
3683 {"IF1_2 5 ADC Swap Mux", "L/L", "TDM2 slot 45 Data Mux"},
3684 {"IF1_2 5 ADC Swap Mux", "R/R", "TDM2 slot 45 Data Mux"},
3685 {"IF1_2 6 ADC Swap Mux", "L/R", "TDM2 slot 67 Data Mux"},
3686 {"IF1_2 6 ADC Swap Mux", "R/L", "TDM2 slot 67 Data Mux"},
3687 {"IF1_2 7 ADC Swap Mux", "L/L", "TDM2 slot 67 Data Mux"},
3688 {"IF1_2 7 ADC Swap Mux", "R/R", "TDM2 slot 67 Data Mux"},
3690 {"IF2_1 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3691 {"IF2_1 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3692 {"IF2_1 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3693 {"IF2_1 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3694 {"IF2_1 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3695 {"IF2_1 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
3696 {"IF2_1 ADC Mux", "IF3 DAC", "IF3 DAC"},
3697 {"IF2_1 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3698 {"IF2_1 ADC", NULL, "IF2_1 ADC Mux"},
3699 {"IF2_1 ADC", NULL, "I2S2_1"},
3701 {"IF2_2 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3702 {"IF2_2 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3703 {"IF2_2 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3704 {"IF2_2 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3705 {"IF2_2 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3706 {"IF2_2 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
3707 {"IF2_2 ADC Mux", "IF3 DAC", "IF3 DAC"},
3708 {"IF2_2 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3709 {"IF2_2 ADC", NULL, "IF2_2 ADC Mux"},
3710 {"IF2_2 ADC", NULL, "I2S2_2"},
3712 {"IF3 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3713 {"IF3 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3714 {"IF3 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3715 {"IF3 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3716 {"IF3 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3717 {"IF3 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
3718 {"IF3 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
3719 {"IF3 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3720 {"IF3 ADC", NULL, "IF3 ADC Mux"},
3721 {"IF3 ADC", NULL, "I2S3"},
3723 {"AIF1_1TX slot 0", NULL, "IF1_1 0 ADC Swap Mux"},
3724 {"AIF1_1TX slot 1", NULL, "IF1_1 1 ADC Swap Mux"},
3725 {"AIF1_1TX slot 2", NULL, "IF1_1 2 ADC Swap Mux"},
3726 {"AIF1_1TX slot 3", NULL, "IF1_1 3 ADC Swap Mux"},
3727 {"AIF1_1TX slot 4", NULL, "IF1_1 4 ADC Swap Mux"},
3728 {"AIF1_1TX slot 5", NULL, "IF1_1 5 ADC Swap Mux"},
3729 {"AIF1_1TX slot 6", NULL, "IF1_1 6 ADC Swap Mux"},
3730 {"AIF1_1TX slot 7", NULL, "IF1_1 7 ADC Swap Mux"},
3731 {"AIF1_2TX slot 0", NULL, "IF1_2 0 ADC Swap Mux"},
3732 {"AIF1_2TX slot 1", NULL, "IF1_2 1 ADC Swap Mux"},
3733 {"AIF1_2TX slot 2", NULL, "IF1_2 2 ADC Swap Mux"},
3734 {"AIF1_2TX slot 3", NULL, "IF1_2 3 ADC Swap Mux"},
3735 {"AIF1_2TX slot 4", NULL, "IF1_2 4 ADC Swap Mux"},
3736 {"AIF1_2TX slot 5", NULL, "IF1_2 5 ADC Swap Mux"},
3737 {"AIF1_2TX slot 6", NULL, "IF1_2 6 ADC Swap Mux"},
3738 {"AIF1_2TX slot 7", NULL, "IF1_2 7 ADC Swap Mux"},
3739 {"IF2_1 ADC Swap Mux", "L/R", "IF2_1 ADC"},
3740 {"IF2_1 ADC Swap Mux", "R/L", "IF2_1 ADC"},
3741 {"IF2_1 ADC Swap Mux", "L/L", "IF2_1 ADC"},
3742 {"IF2_1 ADC Swap Mux", "R/R", "IF2_1 ADC"},
3743 {"AIF2_1TX", NULL, "IF2_1 ADC Swap Mux"},
3744 {"IF2_2 ADC Swap Mux", "L/R", "IF2_2 ADC"},
3745 {"IF2_2 ADC Swap Mux", "R/L", "IF2_2 ADC"},
3746 {"IF2_2 ADC Swap Mux", "L/L", "IF2_2 ADC"},
3747 {"IF2_2 ADC Swap Mux", "R/R", "IF2_2 ADC"},
3748 {"AIF2_2TX", NULL, "IF2_2 ADC Swap Mux"},
3749 {"IF3 ADC Swap Mux", "L/R", "IF3 ADC"},
3750 {"IF3 ADC Swap Mux", "R/L", "IF3 ADC"},
3751 {"IF3 ADC Swap Mux", "L/L", "IF3 ADC"},
3752 {"IF3 ADC Swap Mux", "R/R", "IF3 ADC"},
3753 {"AIF3TX", NULL, "IF3 ADC Swap Mux"},
3755 {"IF1 DAC1", NULL, "AIF1RX"},
3756 {"IF1 DAC2", NULL, "AIF1RX"},
3757 {"IF1 DAC3", NULL, "AIF1RX"},
3758 {"IF2_1 DAC Swap Mux", "L/R", "AIF2_1RX"},
3759 {"IF2_1 DAC Swap Mux", "R/L", "AIF2_1RX"},
3760 {"IF2_1 DAC Swap Mux", "L/L", "AIF2_1RX"},
3761 {"IF2_1 DAC Swap Mux", "R/R", "AIF2_1RX"},
3762 {"IF2_2 DAC Swap Mux", "L/R", "AIF2_2RX"},
3763 {"IF2_2 DAC Swap Mux", "R/L", "AIF2_2RX"},
3764 {"IF2_2 DAC Swap Mux", "L/L", "AIF2_2RX"},
3765 {"IF2_2 DAC Swap Mux", "R/R", "AIF2_2RX"},
3766 {"IF2_1 DAC", NULL, "IF2_1 DAC Swap Mux"},
3767 {"IF2_2 DAC", NULL, "IF2_2 DAC Swap Mux"},
3768 {"IF3 DAC Swap Mux", "L/R", "AIF3RX"},
3769 {"IF3 DAC Swap Mux", "R/L", "AIF3RX"},
3770 {"IF3 DAC Swap Mux", "L/L", "AIF3RX"},
3771 {"IF3 DAC Swap Mux", "R/R", "AIF3RX"},
3772 {"IF3 DAC", NULL, "IF3 DAC Swap Mux"},
3774 {"IF1 DAC1", NULL, "I2S1_1"},
3775 {"IF1 DAC2", NULL, "I2S1_1"},
3776 {"IF1 DAC3", NULL, "I2S1_1"},
3777 {"IF2_1 DAC", NULL, "I2S2_1"},
3778 {"IF2_2 DAC", NULL, "I2S2_2"},
3779 {"IF3 DAC", NULL, "I2S3"},
3781 {"IF1 DAC1 L", NULL, "IF1 DAC1"},
3782 {"IF1 DAC1 R", NULL, "IF1 DAC1"},
3783 {"IF1 DAC2 L", NULL, "IF1 DAC2"},
3784 {"IF1 DAC2 R", NULL, "IF1 DAC2"},
3785 {"IF1 DAC3 L", NULL, "IF1 DAC3"},
3786 {"IF1 DAC3 R", NULL, "IF1 DAC3"},
3787 {"IF2_1 DAC L", NULL, "IF2_1 DAC"},
3788 {"IF2_1 DAC R", NULL, "IF2_1 DAC"},
3789 {"IF2_2 DAC L", NULL, "IF2_2 DAC"},
3790 {"IF2_2 DAC R", NULL, "IF2_2 DAC"},
3791 {"IF3 DAC L", NULL, "IF3 DAC"},
3792 {"IF3 DAC R", NULL, "IF3 DAC"},
3794 {"DAC L1 Mux", "IF1 DAC1", "IF1 DAC1 L"},
3795 {"DAC L1 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3796 {"DAC L1 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3797 {"DAC L1 Mux", "IF3 DAC", "IF3 DAC L"},
3798 {"DAC L1 Mux", NULL, "DAC Stereo1 Filter"},
3800 {"DAC R1 Mux", "IF1 DAC1", "IF1 DAC1 R"},
3801 {"DAC R1 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3802 {"DAC R1 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3803 {"DAC R1 Mux", "IF3 DAC", "IF3 DAC R"},
3804 {"DAC R1 Mux", NULL, "DAC Stereo1 Filter"},
3806 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
3807 {"DAC1 MIXL", "DAC1 Switch", "DAC L1 Mux"},
3808 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
3809 {"DAC1 MIXR", "DAC1 Switch", "DAC R1 Mux"},
3811 {"DAC1 MIX", NULL, "DAC1 MIXL"},
3812 {"DAC1 MIX", NULL, "DAC1 MIXR"},
3814 {"DAC L2 Mux", "IF1 DAC2", "IF1 DAC2 L"},
3815 {"DAC L2 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3816 {"DAC L2 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3817 {"DAC L2 Mux", "IF3 DAC", "IF3 DAC L"},
3818 {"DAC L2 Mux", "Mono ADC MIX", "Mono ADC MIXL"},
3819 {"DAC L2 Mux", NULL, "DAC Mono Left Filter"},
3821 {"DAC R2 Mux", "IF1 DAC2", "IF1 DAC2 R"},
3822 {"DAC R2 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3823 {"DAC R2 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3824 {"DAC R2 Mux", "IF3 DAC", "IF3 DAC R"},
3825 {"DAC R2 Mux", "Mono ADC MIX", "Mono ADC MIXR"},
3826 {"DAC R2 Mux", NULL, "DAC Mono Right Filter"},
3828 {"DAC L3 Mux", "IF1 DAC2", "IF1 DAC2 L"},
3829 {"DAC L3 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3830 {"DAC L3 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3831 {"DAC L3 Mux", "IF3 DAC", "IF3 DAC L"},
3832 {"DAC L3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXL"},
3833 {"DAC L3 Mux", NULL, "DAC Stereo2 Filter"},
3835 {"DAC R3 Mux", "IF1 DAC2", "IF1 DAC2 R"},
3836 {"DAC R3 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3837 {"DAC R3 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3838 {"DAC R3 Mux", "IF3 DAC", "IF3 DAC R"},
3839 {"DAC R3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXR"},
3840 {"DAC R3 Mux", NULL, "DAC Stereo2 Filter"},
3842 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3843 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
3844 {"Stereo1 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3845 {"Stereo1 DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
3847 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3848 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
3849 {"Stereo1 DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
3850 {"Stereo1 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3852 {"Stereo2 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3853 {"Stereo2 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3854 {"Stereo2 DAC MIXL", "DAC L3 Switch", "DAC L3 Mux"},
3856 {"Stereo2 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3857 {"Stereo2 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3858 {"Stereo2 DAC MIXR", "DAC R3 Switch", "DAC R3 Mux"},
3860 {"Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3861 {"Mono DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
3862 {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3863 {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
3864 {"Mono DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
3865 {"Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3866 {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
3867 {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3869 {"DAC MIXL", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
3870 {"DAC MIXL", "Stereo2 DAC Mixer", "Stereo2 DAC MIXL"},
3871 {"DAC MIXL", "Mono DAC Mixer", "Mono DAC MIXL"},
3872 {"DAC MIXR", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
3873 {"DAC MIXR", "Stereo2 DAC Mixer", "Stereo2 DAC MIXR"},
3874 {"DAC MIXR", "Mono DAC Mixer", "Mono DAC MIXR"},
3876 {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
3877 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
3878 {"DAC L1 Source", "DMIC1", "DMIC L1"},
3879 {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
3880 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
3881 {"DAC R1 Source", "DMIC1", "DMIC R1"},
3883 {"DAC L2 Source", "DAC2", "DAC L2 Mux"},
3884 {"DAC L2 Source", "Mono DAC Mixer", "Mono DAC MIXL"},
3885 {"DAC L2 Source", NULL, "DAC L2 Power"},
3886 {"DAC R2 Source", "DAC2", "DAC R2 Mux"},
3887 {"DAC R2 Source", "Mono DAC Mixer", "Mono DAC MIXR"},
3888 {"DAC R2 Source", NULL, "DAC R2 Power"},
3890 {"DAC L1", NULL, "DAC L1 Source"},
3891 {"DAC R1", NULL, "DAC R1 Source"},
3892 {"DAC L2", NULL, "DAC L2 Source"},
3893 {"DAC R2", NULL, "DAC R2 Source"},
3895 {"DAC L1", NULL, "DAC 1 Clock"},
3896 {"DAC R1", NULL, "DAC 1 Clock"},
3897 {"DAC L2", NULL, "DAC 2 Clock"},
3898 {"DAC R2", NULL, "DAC 2 Clock"},
3900 {"MONOVOL MIX", "DAC L2 Switch", "DAC L2"},
3901 {"MONOVOL MIX", "RECMIX2L Switch", "RECMIX2L"},
3902 {"MONOVOL MIX", "BST1 Switch", "BST1"},
3903 {"MONOVOL MIX", "BST2 Switch", "BST2"},
3904 {"MONOVOL MIX", "BST3 Switch", "BST3"},
3906 {"OUT MIXL", "DAC L2 Switch", "DAC L2"},
3907 {"OUT MIXL", "INL Switch", "INL VOL"},
3908 {"OUT MIXL", "BST1 Switch", "BST1"},
3909 {"OUT MIXL", "BST2 Switch", "BST2"},
3910 {"OUT MIXL", "BST3 Switch", "BST3"},
3911 {"OUT MIXR", "DAC R2 Switch", "DAC R2"},
3912 {"OUT MIXR", "INR Switch", "INR VOL"},
3913 {"OUT MIXR", "BST2 Switch", "BST2"},
3914 {"OUT MIXR", "BST3 Switch", "BST3"},
3915 {"OUT MIXR", "BST4 Switch", "BST4"},
3917 {"MONOVOL", "Switch", "MONOVOL MIX"},
3918 {"Mono MIX", "DAC L2 Switch", "DAC L2"},
3919 {"Mono MIX", "MONOVOL Switch", "MONOVOL"},
3920 {"Mono Amp", NULL, "Mono MIX"},
3921 {"Mono Amp", NULL, "Vref2"},
3922 {"Mono Amp", NULL, "Vref3"},
3923 {"Mono Amp", NULL, "CLKDET SYS"},
3924 {"Mono Amp", NULL, "CLKDET MONO"},
3925 {"Mono Playback", "Switch", "Mono Amp"},
3926 {"MONOOUT", NULL, "Mono Playback"},
3928 {"HP Amp", NULL, "DAC L1"},
3929 {"HP Amp", NULL, "DAC R1"},
3930 {"HP Amp", NULL, "Charge Pump"},
3931 {"HP Amp", NULL, "CLKDET SYS"},
3932 {"HP Amp", NULL, "CLKDET HP"},
3933 {"HP Amp", NULL, "CBJ Power"},
3934 {"HP Amp", NULL, "Vref2"},
3935 {"HPO Playback", "Switch", "HP Amp"},
3936 {"HPOL", NULL, "HPO Playback"},
3937 {"HPOR", NULL, "HPO Playback"},
3939 {"OUTVOL L", "Switch", "OUT MIXL"},
3940 {"OUTVOL R", "Switch", "OUT MIXR"},
3941 {"LOUT L MIX", "DAC L2 Switch", "DAC L2"},
3942 {"LOUT L MIX", "OUTVOL L Switch", "OUTVOL L"},
3943 {"LOUT R MIX", "DAC R2 Switch", "DAC R2"},
3944 {"LOUT R MIX", "OUTVOL R Switch", "OUTVOL R"},
3945 {"LOUT Amp", NULL, "LOUT L MIX"},
3946 {"LOUT Amp", NULL, "LOUT R MIX"},
3947 {"LOUT Amp", NULL, "Vref1"},
3948 {"LOUT Amp", NULL, "Vref2"},
3949 {"LOUT Amp", NULL, "CLKDET SYS"},
3950 {"LOUT Amp", NULL, "CLKDET LOUT"},
3951 {"LOUT L Playback", "Switch", "LOUT Amp"},
3952 {"LOUT R Playback", "Switch", "LOUT Amp"},
3953 {"LOUTL", NULL, "LOUT L Playback"},
3954 {"LOUTR", NULL, "LOUT R Playback"},
3956 {"PDM L Mux", "Mono DAC", "Mono DAC MIXL"},
3957 {"PDM L Mux", "Stereo1 DAC", "Stereo1 DAC MIXL"},
3958 {"PDM L Mux", "Stereo2 DAC", "Stereo2 DAC MIXL"},
3959 {"PDM L Mux", NULL, "PDM Power"},
3960 {"PDM R Mux", "Mono DAC", "Mono DAC MIXR"},
3961 {"PDM R Mux", "Stereo1 DAC", "Stereo1 DAC MIXR"},
3962 {"PDM R Mux", "Stereo2 DAC", "Stereo2 DAC MIXR"},
3963 {"PDM R Mux", NULL, "PDM Power"},
3964 {"PDM L Playback", "Switch", "PDM L Mux"},
3965 {"PDM R Playback", "Switch", "PDM R Mux"},
3966 {"PDML", NULL, "PDM L Playback"},
3967 {"PDMR", NULL, "PDM R Playback"},
3970 static int rt5665_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
3971 unsigned int rx_mask, int slots, int slot_width)
3973 struct snd_soc_codec *codec = dai->codec;
3974 unsigned int val = 0;
3976 if (rx_mask || tx_mask)
3977 val |= RT5665_I2S1_MODE_TDM;
3981 val |= RT5665_TDM_IN_CH_4;
3982 val |= RT5665_TDM_OUT_CH_4;
3985 val |= RT5665_TDM_IN_CH_6;
3986 val |= RT5665_TDM_OUT_CH_6;
3989 val |= RT5665_TDM_IN_CH_8;
3990 val |= RT5665_TDM_OUT_CH_8;
3998 switch (slot_width) {
4000 val |= RT5665_TDM_IN_LEN_20;
4001 val |= RT5665_TDM_OUT_LEN_20;
4004 val |= RT5665_TDM_IN_LEN_24;
4005 val |= RT5665_TDM_OUT_LEN_24;
4008 val |= RT5665_TDM_IN_LEN_32;
4009 val |= RT5665_TDM_OUT_LEN_32;
4017 snd_soc_update_bits(codec, RT5665_TDM_CTRL_1,
4018 RT5665_I2S1_MODE_MASK | RT5665_TDM_IN_CH_MASK |
4019 RT5665_TDM_OUT_CH_MASK | RT5665_TDM_IN_LEN_MASK |
4020 RT5665_TDM_OUT_LEN_MASK, val);
4026 static int rt5665_hw_params(struct snd_pcm_substream *substream,
4027 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
4029 struct snd_soc_codec *codec = dai->codec;
4030 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4031 unsigned int val_len = 0, val_clk, mask_clk, val_bits = 0x0100;
4032 int pre_div, frame_size;
4034 rt5665->lrck[dai->id] = params_rate(params);
4035 pre_div = rl6231_get_clk_info(rt5665->sysclk, rt5665->lrck[dai->id]);
4037 dev_err(codec->dev, "Unsupported clock setting %d for DAI %d\n",
4038 rt5665->lrck[dai->id], dai->id);
4041 frame_size = snd_soc_params_to_frame_size(params);
4042 if (frame_size < 0) {
4043 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
4047 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
4048 rt5665->lrck[dai->id], pre_div, dai->id);
4050 switch (params_width(params)) {
4055 val_len |= RT5665_I2S_DL_20;
4059 val_len |= RT5665_I2S_DL_24;
4063 val_len |= RT5665_I2S_DL_8;
4072 if (params_channels(params) > 2)
4073 rt5665_set_tdm_slot(dai, 0xf, 0xf,
4074 params_channels(params), params_width(params));
4075 mask_clk = RT5665_I2S_PD1_MASK;
4076 val_clk = pre_div << RT5665_I2S_PD1_SFT;
4077 snd_soc_update_bits(codec, RT5665_I2S1_SDP,
4078 RT5665_I2S_DL_MASK, val_len);
4082 mask_clk = RT5665_I2S_PD2_MASK;
4083 val_clk = pre_div << RT5665_I2S_PD2_SFT;
4084 snd_soc_update_bits(codec, RT5665_I2S2_SDP,
4085 RT5665_I2S_DL_MASK, val_len);
4088 mask_clk = RT5665_I2S_PD3_MASK;
4089 val_clk = pre_div << RT5665_I2S_PD3_SFT;
4090 snd_soc_update_bits(codec, RT5665_I2S3_SDP,
4091 RT5665_I2S_DL_MASK, val_len);
4094 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
4098 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1, mask_clk, val_clk);
4099 snd_soc_update_bits(codec, RT5665_STO1_DAC_SIL_DET, 0x3700, val_bits);
4101 switch (rt5665->lrck[dai->id]) {
4103 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4104 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4105 RT5665_DAC_OSR_32 | RT5665_ADC_OSR_32);
4108 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4109 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4110 RT5665_DAC_OSR_64 | RT5665_ADC_OSR_64);
4113 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4114 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4115 RT5665_DAC_OSR_128 | RT5665_ADC_OSR_128);
4122 static int rt5665_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
4124 struct snd_soc_codec *codec = dai->codec;
4125 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4126 unsigned int reg_val = 0;
4128 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4129 case SND_SOC_DAIFMT_CBM_CFM:
4130 rt5665->master[dai->id] = 1;
4132 case SND_SOC_DAIFMT_CBS_CFS:
4133 reg_val |= RT5665_I2S_MS_S;
4134 rt5665->master[dai->id] = 0;
4140 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
4141 case SND_SOC_DAIFMT_NB_NF:
4143 case SND_SOC_DAIFMT_IB_NF:
4144 reg_val |= RT5665_I2S_BP_INV;
4150 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
4151 case SND_SOC_DAIFMT_I2S:
4153 case SND_SOC_DAIFMT_LEFT_J:
4154 reg_val |= RT5665_I2S_DF_LEFT;
4156 case SND_SOC_DAIFMT_DSP_A:
4157 reg_val |= RT5665_I2S_DF_PCM_A;
4159 case SND_SOC_DAIFMT_DSP_B:
4160 reg_val |= RT5665_I2S_DF_PCM_B;
4169 snd_soc_update_bits(codec, RT5665_I2S1_SDP,
4170 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4171 RT5665_I2S_DF_MASK, reg_val);
4175 snd_soc_update_bits(codec, RT5665_I2S2_SDP,
4176 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4177 RT5665_I2S_DF_MASK, reg_val);
4180 snd_soc_update_bits(codec, RT5665_I2S3_SDP,
4181 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4182 RT5665_I2S_DF_MASK, reg_val);
4185 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
4191 static int rt5665_set_dai_sysclk(struct snd_soc_dai *dai,
4192 int clk_id, unsigned int freq, int dir)
4194 struct snd_soc_codec *codec = dai->codec;
4195 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4196 unsigned int reg_val = 0;
4198 if (freq == rt5665->sysclk && clk_id == rt5665->sysclk_src)
4202 case RT5665_SCLK_S_MCLK:
4203 reg_val |= RT5665_SCLK_SRC_MCLK;
4205 case RT5665_SCLK_S_PLL1:
4206 reg_val |= RT5665_SCLK_SRC_PLL1;
4208 case RT5665_SCLK_S_RCCLK:
4209 reg_val |= RT5665_SCLK_SRC_RCCLK;
4212 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
4215 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4216 RT5665_SCLK_SRC_MASK, reg_val);
4217 rt5665->sysclk = freq;
4218 rt5665->sysclk_src = clk_id;
4220 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
4225 static int rt5665_set_codec_pll(struct snd_soc_codec *codec, int pll_id,
4226 int source, unsigned int freq_in,
4227 unsigned int freq_out)
4229 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4230 struct rl6231_pll_code pll_code;
4233 if (source == rt5665->pll_src && freq_in == rt5665->pll_in &&
4234 freq_out == rt5665->pll_out)
4237 if (!freq_in || !freq_out) {
4238 dev_dbg(codec->dev, "PLL disabled\n");
4241 rt5665->pll_out = 0;
4242 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4243 RT5665_SCLK_SRC_MASK, RT5665_SCLK_SRC_MCLK);
4248 case RT5665_PLL1_S_MCLK:
4249 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4250 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_MCLK);
4252 case RT5665_PLL1_S_BCLK1:
4253 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4254 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK1);
4256 case RT5665_PLL1_S_BCLK2:
4257 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4258 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK2);
4260 case RT5665_PLL1_S_BCLK3:
4261 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4262 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK3);
4265 dev_err(codec->dev, "Unknown PLL Source %d\n", source);
4269 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
4271 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
4275 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
4276 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4277 pll_code.n_code, pll_code.k_code);
4279 snd_soc_write(codec, RT5665_PLL_CTRL_1,
4280 pll_code.n_code << RT5665_PLL_N_SFT | pll_code.k_code);
4281 snd_soc_write(codec, RT5665_PLL_CTRL_2,
4282 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5665_PLL_M_SFT |
4283 pll_code.m_bp << RT5665_PLL_M_BP_SFT);
4285 rt5665->pll_in = freq_in;
4286 rt5665->pll_out = freq_out;
4287 rt5665->pll_src = source;
4292 static int rt5665_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
4294 struct snd_soc_codec *codec = dai->codec;
4295 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4297 dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio);
4299 rt5665->bclk[dai->id] = ratio;
4305 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4306 RT5665_I2S_BCLK_MS2_MASK,
4307 RT5665_I2S_BCLK_MS2_64);
4310 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4311 RT5665_I2S_BCLK_MS3_MASK,
4312 RT5665_I2S_BCLK_MS3_64);
4320 static int rt5665_set_bias_level(struct snd_soc_codec *codec,
4321 enum snd_soc_bias_level level)
4323 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4326 case SND_SOC_BIAS_PREPARE:
4327 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
4328 RT5665_DIG_GATE_CTRL, RT5665_DIG_GATE_CTRL);
4331 case SND_SOC_BIAS_STANDBY:
4332 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
4333 RT5665_PWR_LDO, RT5665_PWR_LDO);
4334 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4335 RT5665_PWR_MB, RT5665_PWR_MB);
4336 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
4337 RT5665_DIG_GATE_CTRL, 0);
4339 case SND_SOC_BIAS_OFF:
4340 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
4342 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4353 static int rt5665_probe(struct snd_soc_codec *codec)
4355 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4357 rt5665->codec = codec;
4359 schedule_delayed_work(&rt5665->calibrate_work, msecs_to_jiffies(100));
4364 static int rt5665_remove(struct snd_soc_codec *codec)
4366 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4368 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4374 static int rt5665_suspend(struct snd_soc_codec *codec)
4376 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4378 regcache_cache_only(rt5665->regmap, true);
4379 regcache_mark_dirty(rt5665->regmap);
4383 static int rt5665_resume(struct snd_soc_codec *codec)
4385 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4387 regcache_cache_only(rt5665->regmap, false);
4388 regcache_sync(rt5665->regmap);
4393 #define rt5665_suspend NULL
4394 #define rt5665_resume NULL
4397 #define RT5665_STEREO_RATES SNDRV_PCM_RATE_8000_192000
4398 #define RT5665_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4399 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4401 static const struct snd_soc_dai_ops rt5665_aif_dai_ops = {
4402 .hw_params = rt5665_hw_params,
4403 .set_fmt = rt5665_set_dai_fmt,
4404 .set_sysclk = rt5665_set_dai_sysclk,
4405 .set_tdm_slot = rt5665_set_tdm_slot,
4406 .set_bclk_ratio = rt5665_set_bclk_ratio,
4409 static struct snd_soc_dai_driver rt5665_dai[] = {
4411 .name = "rt5665-aif1_1",
4412 .id = RT5665_AIF1_1,
4414 .stream_name = "AIF1 Playback",
4417 .rates = RT5665_STEREO_RATES,
4418 .formats = RT5665_FORMATS,
4421 .stream_name = "AIF1_1 Capture",
4424 .rates = RT5665_STEREO_RATES,
4425 .formats = RT5665_FORMATS,
4427 .ops = &rt5665_aif_dai_ops,
4430 .name = "rt5665-aif1_2",
4431 .id = RT5665_AIF1_2,
4433 .stream_name = "AIF1_2 Capture",
4436 .rates = RT5665_STEREO_RATES,
4437 .formats = RT5665_FORMATS,
4439 .ops = &rt5665_aif_dai_ops,
4442 .name = "rt5665-aif2_1",
4443 .id = RT5665_AIF2_1,
4445 .stream_name = "AIF2_1 Playback",
4448 .rates = RT5665_STEREO_RATES,
4449 .formats = RT5665_FORMATS,
4452 .stream_name = "AIF2_1 Capture",
4455 .rates = RT5665_STEREO_RATES,
4456 .formats = RT5665_FORMATS,
4458 .ops = &rt5665_aif_dai_ops,
4461 .name = "rt5665-aif2_2",
4462 .id = RT5665_AIF2_2,
4464 .stream_name = "AIF2_2 Playback",
4467 .rates = RT5665_STEREO_RATES,
4468 .formats = RT5665_FORMATS,
4471 .stream_name = "AIF2_2 Capture",
4474 .rates = RT5665_STEREO_RATES,
4475 .formats = RT5665_FORMATS,
4477 .ops = &rt5665_aif_dai_ops,
4480 .name = "rt5665-aif3",
4483 .stream_name = "AIF3 Playback",
4486 .rates = RT5665_STEREO_RATES,
4487 .formats = RT5665_FORMATS,
4490 .stream_name = "AIF3 Capture",
4493 .rates = RT5665_STEREO_RATES,
4494 .formats = RT5665_FORMATS,
4496 .ops = &rt5665_aif_dai_ops,
4500 static struct snd_soc_codec_driver soc_codec_dev_rt5665 = {
4501 .probe = rt5665_probe,
4502 .remove = rt5665_remove,
4503 .suspend = rt5665_suspend,
4504 .resume = rt5665_resume,
4505 .set_bias_level = rt5665_set_bias_level,
4506 .idle_bias_off = true,
4507 .component_driver = {
4508 .controls = rt5665_snd_controls,
4509 .num_controls = ARRAY_SIZE(rt5665_snd_controls),
4510 .dapm_widgets = rt5665_dapm_widgets,
4511 .num_dapm_widgets = ARRAY_SIZE(rt5665_dapm_widgets),
4512 .dapm_routes = rt5665_dapm_routes,
4513 .num_dapm_routes = ARRAY_SIZE(rt5665_dapm_routes),
4515 .set_pll = rt5665_set_codec_pll,
4519 static const struct regmap_config rt5665_regmap = {
4522 .max_register = 0x0400,
4523 .volatile_reg = rt5665_volatile_register,
4524 .readable_reg = rt5665_readable_register,
4525 .cache_type = REGCACHE_RBTREE,
4526 .reg_defaults = rt5665_reg,
4527 .num_reg_defaults = ARRAY_SIZE(rt5665_reg),
4528 .use_single_rw = true,
4531 static const struct i2c_device_id rt5665_i2c_id[] = {
4535 MODULE_DEVICE_TABLE(i2c, rt5665_i2c_id);
4537 static int rt5665_parse_dt(struct rt5665_priv *rt5665, struct device *dev)
4539 rt5665->pdata.in1_diff = of_property_read_bool(dev->of_node,
4540 "realtek,in1-differential");
4541 rt5665->pdata.in2_diff = of_property_read_bool(dev->of_node,
4542 "realtek,in2-differential");
4543 rt5665->pdata.in3_diff = of_property_read_bool(dev->of_node,
4544 "realtek,in3-differential");
4545 rt5665->pdata.in4_diff = of_property_read_bool(dev->of_node,
4546 "realtek,in4-differential");
4548 of_property_read_u32(dev->of_node, "realtek,dmic1-data-pin",
4549 &rt5665->pdata.dmic1_data_pin);
4550 of_property_read_u32(dev->of_node, "realtek,dmic2-data-pin",
4551 &rt5665->pdata.dmic2_data_pin);
4552 of_property_read_u32(dev->of_node, "realtek,jd-src",
4553 &rt5665->pdata.jd_src);
4555 rt5665->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
4556 "realtek,ldo1-en-gpios", 0);
4561 static void rt5665_calibrate(struct rt5665_priv *rt5665)
4565 mutex_lock(&rt5665->calibrate_mutex);
4567 regcache_cache_bypass(rt5665->regmap, true);
4569 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4570 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
4571 regmap_write(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1, 0x0c26);
4572 regmap_write(rt5665->regmap, RT5665_MONOMIX_IN_GAIN, 0x021f);
4573 regmap_write(rt5665->regmap, RT5665_MONO_OUT, 0x480a);
4574 regmap_write(rt5665->regmap, RT5665_PWR_MIXER, 0x083f);
4575 regmap_write(rt5665->regmap, RT5665_PWR_DIG_1, 0x0180);
4576 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_1, 0x4040);
4577 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0000);
4578 regmap_write(rt5665->regmap, RT5665_DIG_MISC, 0x0001);
4579 regmap_write(rt5665->regmap, RT5665_MICBIAS_2, 0x0380);
4580 regmap_write(rt5665->regmap, RT5665_GLB_CLK, 0x8000);
4581 regmap_write(rt5665->regmap, RT5665_ADDA_CLK_1, 0x1000);
4582 regmap_write(rt5665->regmap, RT5665_CHOP_DAC, 0x3030);
4583 regmap_write(rt5665->regmap, RT5665_CALIB_ADC_CTRL, 0x3c05);
4584 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xaa3e);
4585 usleep_range(15000, 20000);
4586 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xfe7e);
4587 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_2, 0x0321);
4589 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_1, 0xfc00);
4592 regmap_read(rt5665->regmap, RT5665_HP_CALIB_STA_1, &value);
4594 usleep_range(10000, 10005);
4599 pr_err("HP Calibration Failure\n");
4600 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4601 regcache_cache_bypass(rt5665->regmap, false);
4608 regmap_write(rt5665->regmap, RT5665_MONO_AMP_CALIB_CTRL_1, 0x9e24);
4611 regmap_read(rt5665->regmap, RT5665_MONO_AMP_CALIB_STA1, &value);
4613 usleep_range(10000, 10005);
4618 pr_err("MONO Calibration Failure\n");
4619 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4620 regcache_cache_bypass(rt5665->regmap, false);
4627 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4628 regcache_cache_bypass(rt5665->regmap, false);
4630 regcache_mark_dirty(rt5665->regmap);
4631 regcache_sync(rt5665->regmap);
4633 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
4634 regmap_write(rt5665->regmap, RT5665_ASRC_8, 0x0120);
4637 mutex_unlock(&rt5665->calibrate_mutex);
4640 static void rt5665_calibrate_handler(struct work_struct *work)
4642 struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv,
4643 calibrate_work.work);
4645 while (!rt5665->codec->component.card->instantiated) {
4646 pr_debug("%s\n", __func__);
4647 usleep_range(10000, 15000);
4650 rt5665_calibrate(rt5665);
4653 static int rt5665_i2c_probe(struct i2c_client *i2c,
4654 const struct i2c_device_id *id)
4656 struct rt5665_platform_data *pdata = dev_get_platdata(&i2c->dev);
4657 struct rt5665_priv *rt5665;
4661 rt5665 = devm_kzalloc(&i2c->dev, sizeof(struct rt5665_priv),
4667 i2c_set_clientdata(i2c, rt5665);
4670 rt5665->pdata = *pdata;
4672 rt5665_parse_dt(rt5665, &i2c->dev);
4674 for (i = 0; i < ARRAY_SIZE(rt5665->supplies); i++)
4675 rt5665->supplies[i].supply = rt5665_supply_names[i];
4677 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5665->supplies),
4680 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
4684 ret = regulator_bulk_enable(ARRAY_SIZE(rt5665->supplies),
4687 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
4691 if (gpio_is_valid(rt5665->pdata.ldo1_en)) {
4692 if (devm_gpio_request_one(&i2c->dev, rt5665->pdata.ldo1_en,
4693 GPIOF_OUT_INIT_HIGH, "rt5665"))
4694 dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n");
4697 /* Sleep for 300 ms miniumum */
4698 usleep_range(300000, 350000);
4700 rt5665->regmap = devm_regmap_init_i2c(i2c, &rt5665_regmap);
4701 if (IS_ERR(rt5665->regmap)) {
4702 ret = PTR_ERR(rt5665->regmap);
4703 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4708 regmap_read(rt5665->regmap, RT5665_DEVICE_ID, &val);
4709 if (val != DEVICE_ID) {
4711 "Device with ID register %x is not rt5665\n", val);
4715 regmap_read(rt5665->regmap, RT5665_RESET, &val);
4718 rt5665->id = CODEC_5666;
4721 rt5665->id = CODEC_5668;
4725 rt5665->id = CODEC_5665;
4729 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4731 /* line in diff mode*/
4732 if (rt5665->pdata.in1_diff)
4733 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
4734 RT5665_IN1_DF_MASK, RT5665_IN1_DF_MASK);
4735 if (rt5665->pdata.in2_diff)
4736 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
4737 RT5665_IN2_DF_MASK, RT5665_IN2_DF_MASK);
4738 if (rt5665->pdata.in3_diff)
4739 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
4740 RT5665_IN3_DF_MASK, RT5665_IN3_DF_MASK);
4741 if (rt5665->pdata.in4_diff)
4742 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
4743 RT5665_IN4_DF_MASK, RT5665_IN4_DF_MASK);
4746 if (rt5665->pdata.dmic1_data_pin != RT5665_DMIC1_NULL ||
4747 rt5665->pdata.dmic2_data_pin != RT5665_DMIC2_NULL) {
4748 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
4749 RT5665_GP9_PIN_MASK, RT5665_GP9_PIN_DMIC1_SCL);
4750 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4751 RT5665_GP8_PIN_MASK, RT5665_GP8_PIN_DMIC2_SCL);
4752 switch (rt5665->pdata.dmic1_data_pin) {
4753 case RT5665_DMIC1_DATA_IN2N:
4754 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4755 RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_IN2N);
4758 case RT5665_DMIC1_DATA_GPIO4:
4759 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4760 RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_GPIO4);
4761 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4762 RT5665_GP4_PIN_MASK, RT5665_GP4_PIN_DMIC1_SDA);
4766 dev_dbg(&i2c->dev, "no DMIC1\n");
4770 switch (rt5665->pdata.dmic2_data_pin) {
4771 case RT5665_DMIC2_DATA_IN2P:
4772 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4773 RT5665_DMIC_2_DP_MASK, RT5665_DMIC_2_DP_IN2P);
4776 case RT5665_DMIC2_DATA_GPIO5:
4777 regmap_update_bits(rt5665->regmap,
4779 RT5665_DMIC_2_DP_MASK,
4780 RT5665_DMIC_2_DP_GPIO5);
4781 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4782 RT5665_GP5_PIN_MASK, RT5665_GP5_PIN_DMIC2_SDA);
4786 dev_dbg(&i2c->dev, "no DMIC2\n");
4792 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0002);
4793 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
4794 0xf000 | RT5665_VREF_POW_MASK, 0xe000 | RT5665_VREF_POW_REG);
4795 /* Work around for pow_pump */
4796 regmap_update_bits(rt5665->regmap, RT5665_STO1_DAC_SIL_DET,
4797 RT5665_DEB_STO_DAC_MASK, RT5665_DEB_80_MS);
4799 regmap_update_bits(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1,
4800 RT5665_PM_HP_MASK, RT5665_PM_HP_HV);
4802 /* Set GPIO4,8 as input for combo jack */
4803 if (rt5665->id == CODEC_5666) {
4804 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
4805 RT5665_GP4_PF_MASK, RT5665_GP4_PF_IN);
4806 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_3,
4807 RT5665_GP8_PF_MASK, RT5665_GP8_PF_IN);
4810 /* Enhance performance*/
4811 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4812 RT5665_HP_DRIVER_MASK | RT5665_LDO1_DVO_MASK,
4813 RT5665_HP_DRIVER_5X | RT5665_LDO1_DVO_12);
4815 INIT_DELAYED_WORK(&rt5665->jack_detect_work,
4816 rt5665_jack_detect_handler);
4817 INIT_DELAYED_WORK(&rt5665->calibrate_work,
4818 rt5665_calibrate_handler);
4819 INIT_DELAYED_WORK(&rt5665->jd_check_work,
4820 rt5665_jd_check_handler);
4822 mutex_init(&rt5665->calibrate_mutex);
4825 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
4826 rt5665_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
4827 | IRQF_ONESHOT, "rt5665", rt5665);
4829 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
4833 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5665,
4834 rt5665_dai, ARRAY_SIZE(rt5665_dai));
4837 static int rt5665_i2c_remove(struct i2c_client *i2c)
4839 snd_soc_unregister_codec(&i2c->dev);
4844 static void rt5665_i2c_shutdown(struct i2c_client *client)
4846 struct rt5665_priv *rt5665 = i2c_get_clientdata(client);
4848 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4852 static const struct of_device_id rt5665_of_match[] = {
4853 {.compatible = "realtek,rt5665"},
4854 {.compatible = "realtek,rt5666"},
4855 {.compatible = "realtek,rt5668"},
4858 MODULE_DEVICE_TABLE(of, rt5665_of_match);
4862 static struct acpi_device_id rt5665_acpi_match[] = {
4868 MODULE_DEVICE_TABLE(acpi, rt5665_acpi_match);
4871 struct i2c_driver rt5665_i2c_driver = {
4874 .of_match_table = of_match_ptr(rt5665_of_match),
4875 .acpi_match_table = ACPI_PTR(rt5665_acpi_match),
4877 .probe = rt5665_i2c_probe,
4878 .remove = rt5665_i2c_remove,
4879 .shutdown = rt5665_i2c_shutdown,
4880 .id_table = rt5665_i2c_id,
4882 module_i2c_driver(rt5665_i2c_driver);
4884 MODULE_DESCRIPTION("ASoC RT5665 driver");
4885 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
4886 MODULE_LICENSE("GPL v2");