2 * wm8993.c -- WM8993 ALSA SoC audio driver
4 * Copyright 2009-12 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
18 #include <linux/i2c.h>
19 #include <linux/regmap.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/spi/spi.h>
22 #include <linux/slab.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/tlv.h>
27 #include <sound/soc.h>
28 #include <sound/initval.h>
29 #include <sound/wm8993.h>
34 #define WM8993_NUM_SUPPLIES 6
35 static const char *wm8993_supply_names[WM8993_NUM_SUPPLIES] = {
44 static const struct reg_default wm8993_reg_defaults[] = {
45 { 1, 0x0000 }, /* R1 - Power Management (1) */
46 { 2, 0x6000 }, /* R2 - Power Management (2) */
47 { 3, 0x0000 }, /* R3 - Power Management (3) */
48 { 4, 0x4050 }, /* R4 - Audio Interface (1) */
49 { 5, 0x4000 }, /* R5 - Audio Interface (2) */
50 { 6, 0x01C8 }, /* R6 - Clocking 1 */
51 { 7, 0x0000 }, /* R7 - Clocking 2 */
52 { 8, 0x0000 }, /* R8 - Audio Interface (3) */
53 { 9, 0x0040 }, /* R9 - Audio Interface (4) */
54 { 10, 0x0004 }, /* R10 - DAC CTRL */
55 { 11, 0x00C0 }, /* R11 - Left DAC Digital Volume */
56 { 12, 0x00C0 }, /* R12 - Right DAC Digital Volume */
57 { 13, 0x0000 }, /* R13 - Digital Side Tone */
58 { 14, 0x0300 }, /* R14 - ADC CTRL */
59 { 15, 0x00C0 }, /* R15 - Left ADC Digital Volume */
60 { 16, 0x00C0 }, /* R16 - Right ADC Digital Volume */
61 { 18, 0x0000 }, /* R18 - GPIO CTRL 1 */
62 { 19, 0x0010 }, /* R19 - GPIO1 */
63 { 20, 0x0000 }, /* R20 - IRQ_DEBOUNCE */
64 { 21, 0x0000 }, /* R21 - Inputs Clamp */
65 { 22, 0x8000 }, /* R22 - GPIOCTRL 2 */
66 { 23, 0x0800 }, /* R23 - GPIO_POL */
67 { 24, 0x008B }, /* R24 - Left Line Input 1&2 Volume */
68 { 25, 0x008B }, /* R25 - Left Line Input 3&4 Volume */
69 { 26, 0x008B }, /* R26 - Right Line Input 1&2 Volume */
70 { 27, 0x008B }, /* R27 - Right Line Input 3&4 Volume */
71 { 28, 0x006D }, /* R28 - Left Output Volume */
72 { 29, 0x006D }, /* R29 - Right Output Volume */
73 { 30, 0x0066 }, /* R30 - Line Outputs Volume */
74 { 31, 0x0020 }, /* R31 - HPOUT2 Volume */
75 { 32, 0x0079 }, /* R32 - Left OPGA Volume */
76 { 33, 0x0079 }, /* R33 - Right OPGA Volume */
77 { 34, 0x0003 }, /* R34 - SPKMIXL Attenuation */
78 { 35, 0x0003 }, /* R35 - SPKMIXR Attenuation */
79 { 36, 0x0011 }, /* R36 - SPKOUT Mixers */
80 { 37, 0x0100 }, /* R37 - SPKOUT Boost */
81 { 38, 0x0079 }, /* R38 - Speaker Volume Left */
82 { 39, 0x0079 }, /* R39 - Speaker Volume Right */
83 { 40, 0x0000 }, /* R40 - Input Mixer2 */
84 { 41, 0x0000 }, /* R41 - Input Mixer3 */
85 { 42, 0x0000 }, /* R42 - Input Mixer4 */
86 { 43, 0x0000 }, /* R43 - Input Mixer5 */
87 { 44, 0x0000 }, /* R44 - Input Mixer6 */
88 { 45, 0x0000 }, /* R45 - Output Mixer1 */
89 { 46, 0x0000 }, /* R46 - Output Mixer2 */
90 { 47, 0x0000 }, /* R47 - Output Mixer3 */
91 { 48, 0x0000 }, /* R48 - Output Mixer4 */
92 { 49, 0x0000 }, /* R49 - Output Mixer5 */
93 { 50, 0x0000 }, /* R50 - Output Mixer6 */
94 { 51, 0x0000 }, /* R51 - HPOUT2 Mixer */
95 { 52, 0x0000 }, /* R52 - Line Mixer1 */
96 { 53, 0x0000 }, /* R53 - Line Mixer2 */
97 { 54, 0x0000 }, /* R54 - Speaker Mixer */
98 { 55, 0x0000 }, /* R55 - Additional Control */
99 { 56, 0x0000 }, /* R56 - AntiPOP1 */
100 { 57, 0x0000 }, /* R57 - AntiPOP2 */
101 { 58, 0x0000 }, /* R58 - MICBIAS */
102 { 60, 0x0000 }, /* R60 - FLL Control 1 */
103 { 61, 0x0000 }, /* R61 - FLL Control 2 */
104 { 62, 0x0000 }, /* R62 - FLL Control 3 */
105 { 63, 0x2EE0 }, /* R63 - FLL Control 4 */
106 { 64, 0x0002 }, /* R64 - FLL Control 5 */
107 { 65, 0x2287 }, /* R65 - Clocking 3 */
108 { 66, 0x025F }, /* R66 - Clocking 4 */
109 { 67, 0x0000 }, /* R67 - MW Slave Control */
110 { 69, 0x0002 }, /* R69 - Bus Control 1 */
111 { 70, 0x0000 }, /* R70 - Write Sequencer 0 */
112 { 71, 0x0000 }, /* R71 - Write Sequencer 1 */
113 { 72, 0x0000 }, /* R72 - Write Sequencer 2 */
114 { 73, 0x0000 }, /* R73 - Write Sequencer 3 */
115 { 74, 0x0000 }, /* R74 - Write Sequencer 4 */
116 { 75, 0x0000 }, /* R75 - Write Sequencer 5 */
117 { 76, 0x1F25 }, /* R76 - Charge Pump 1 */
118 { 81, 0x0000 }, /* R81 - Class W 0 */
119 { 85, 0x054A }, /* R85 - DC Servo 1 */
120 { 87, 0x0000 }, /* R87 - DC Servo 3 */
121 { 96, 0x0100 }, /* R96 - Analogue HP 0 */
122 { 98, 0x0000 }, /* R98 - EQ1 */
123 { 99, 0x000C }, /* R99 - EQ2 */
124 { 100, 0x000C }, /* R100 - EQ3 */
125 { 101, 0x000C }, /* R101 - EQ4 */
126 { 102, 0x000C }, /* R102 - EQ5 */
127 { 103, 0x000C }, /* R103 - EQ6 */
128 { 104, 0x0FCA }, /* R104 - EQ7 */
129 { 105, 0x0400 }, /* R105 - EQ8 */
130 { 106, 0x00D8 }, /* R106 - EQ9 */
131 { 107, 0x1EB5 }, /* R107 - EQ10 */
132 { 108, 0xF145 }, /* R108 - EQ11 */
133 { 109, 0x0B75 }, /* R109 - EQ12 */
134 { 110, 0x01C5 }, /* R110 - EQ13 */
135 { 111, 0x1C58 }, /* R111 - EQ14 */
136 { 112, 0xF373 }, /* R112 - EQ15 */
137 { 113, 0x0A54 }, /* R113 - EQ16 */
138 { 114, 0x0558 }, /* R114 - EQ17 */
139 { 115, 0x168E }, /* R115 - EQ18 */
140 { 116, 0xF829 }, /* R116 - EQ19 */
141 { 117, 0x07AD }, /* R117 - EQ20 */
142 { 118, 0x1103 }, /* R118 - EQ21 */
143 { 119, 0x0564 }, /* R119 - EQ22 */
144 { 120, 0x0559 }, /* R120 - EQ23 */
145 { 121, 0x4000 }, /* R121 - EQ24 */
146 { 122, 0x0000 }, /* R122 - Digital Pulls */
147 { 123, 0x0F08 }, /* R123 - DRC Control 1 */
148 { 124, 0x0000 }, /* R124 - DRC Control 2 */
149 { 125, 0x0080 }, /* R125 - DRC Control 3 */
150 { 126, 0x0000 }, /* R126 - DRC Control 4 */
156 } clk_sys_rates[] = {
185 int div; /* *10 due to .5s */
207 struct wm_hubs_data hubs_data;
209 struct regmap *regmap;
210 struct regulator_bulk_data supplies[WM8993_NUM_SUPPLIES];
211 struct wm8993_platform_data pdata;
212 struct completion fll_lock;
217 unsigned int mclk_rate;
218 unsigned int sysclk_rate;
221 unsigned int fll_fref;
222 unsigned int fll_fout;
226 static bool wm8993_volatile(struct device *dev, unsigned int reg)
229 case WM8993_SOFTWARE_RESET:
230 case WM8993_GPIO_CTRL_1:
231 case WM8993_DC_SERVO_0:
232 case WM8993_DC_SERVO_READBACK_0:
233 case WM8993_DC_SERVO_READBACK_1:
234 case WM8993_DC_SERVO_READBACK_2:
241 static bool wm8993_readable(struct device *dev, unsigned int reg)
244 case WM8993_SOFTWARE_RESET:
245 case WM8993_POWER_MANAGEMENT_1:
246 case WM8993_POWER_MANAGEMENT_2:
247 case WM8993_POWER_MANAGEMENT_3:
248 case WM8993_AUDIO_INTERFACE_1:
249 case WM8993_AUDIO_INTERFACE_2:
250 case WM8993_CLOCKING_1:
251 case WM8993_CLOCKING_2:
252 case WM8993_AUDIO_INTERFACE_3:
253 case WM8993_AUDIO_INTERFACE_4:
254 case WM8993_DAC_CTRL:
255 case WM8993_LEFT_DAC_DIGITAL_VOLUME:
256 case WM8993_RIGHT_DAC_DIGITAL_VOLUME:
257 case WM8993_DIGITAL_SIDE_TONE:
258 case WM8993_ADC_CTRL:
259 case WM8993_LEFT_ADC_DIGITAL_VOLUME:
260 case WM8993_RIGHT_ADC_DIGITAL_VOLUME:
261 case WM8993_GPIO_CTRL_1:
263 case WM8993_IRQ_DEBOUNCE:
264 case WM8993_GPIOCTRL_2:
265 case WM8993_GPIO_POL:
266 case WM8993_LEFT_LINE_INPUT_1_2_VOLUME:
267 case WM8993_LEFT_LINE_INPUT_3_4_VOLUME:
268 case WM8993_RIGHT_LINE_INPUT_1_2_VOLUME:
269 case WM8993_RIGHT_LINE_INPUT_3_4_VOLUME:
270 case WM8993_LEFT_OUTPUT_VOLUME:
271 case WM8993_RIGHT_OUTPUT_VOLUME:
272 case WM8993_LINE_OUTPUTS_VOLUME:
273 case WM8993_HPOUT2_VOLUME:
274 case WM8993_LEFT_OPGA_VOLUME:
275 case WM8993_RIGHT_OPGA_VOLUME:
276 case WM8993_SPKMIXL_ATTENUATION:
277 case WM8993_SPKMIXR_ATTENUATION:
278 case WM8993_SPKOUT_MIXERS:
279 case WM8993_SPKOUT_BOOST:
280 case WM8993_SPEAKER_VOLUME_LEFT:
281 case WM8993_SPEAKER_VOLUME_RIGHT:
282 case WM8993_INPUT_MIXER2:
283 case WM8993_INPUT_MIXER3:
284 case WM8993_INPUT_MIXER4:
285 case WM8993_INPUT_MIXER5:
286 case WM8993_INPUT_MIXER6:
287 case WM8993_OUTPUT_MIXER1:
288 case WM8993_OUTPUT_MIXER2:
289 case WM8993_OUTPUT_MIXER3:
290 case WM8993_OUTPUT_MIXER4:
291 case WM8993_OUTPUT_MIXER5:
292 case WM8993_OUTPUT_MIXER6:
293 case WM8993_HPOUT2_MIXER:
294 case WM8993_LINE_MIXER1:
295 case WM8993_LINE_MIXER2:
296 case WM8993_SPEAKER_MIXER:
297 case WM8993_ADDITIONAL_CONTROL:
298 case WM8993_ANTIPOP1:
299 case WM8993_ANTIPOP2:
301 case WM8993_FLL_CONTROL_1:
302 case WM8993_FLL_CONTROL_2:
303 case WM8993_FLL_CONTROL_3:
304 case WM8993_FLL_CONTROL_4:
305 case WM8993_FLL_CONTROL_5:
306 case WM8993_CLOCKING_3:
307 case WM8993_CLOCKING_4:
308 case WM8993_MW_SLAVE_CONTROL:
309 case WM8993_BUS_CONTROL_1:
310 case WM8993_WRITE_SEQUENCER_0:
311 case WM8993_WRITE_SEQUENCER_1:
312 case WM8993_WRITE_SEQUENCER_2:
313 case WM8993_WRITE_SEQUENCER_3:
314 case WM8993_WRITE_SEQUENCER_4:
315 case WM8993_WRITE_SEQUENCER_5:
316 case WM8993_CHARGE_PUMP_1:
317 case WM8993_CLASS_W_0:
318 case WM8993_DC_SERVO_0:
319 case WM8993_DC_SERVO_1:
320 case WM8993_DC_SERVO_3:
321 case WM8993_DC_SERVO_READBACK_0:
322 case WM8993_DC_SERVO_READBACK_1:
323 case WM8993_DC_SERVO_READBACK_2:
324 case WM8993_ANALOGUE_HP_0:
349 case WM8993_DIGITAL_PULLS:
350 case WM8993_DRC_CONTROL_1:
351 case WM8993_DRC_CONTROL_2:
352 case WM8993_DRC_CONTROL_3:
353 case WM8993_DRC_CONTROL_4:
368 /* The size in bits of the FLL divide multiplied by 10
369 * to allow rounding later */
370 #define FIXED_FLL_SIZE ((1 << 16) * 10)
379 { 64000, 128000, 3, 8 },
380 { 128000, 256000, 2, 4 },
381 { 256000, 1000000, 1, 2 },
382 { 1000000, 13500000, 0, 1 },
385 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
389 unsigned int K, Ndiv, Nmod, target;
393 /* Fref must be <=13.5MHz */
395 fll_div->fll_clk_ref_div = 0;
396 while ((Fref / div) > 13500000) {
398 fll_div->fll_clk_ref_div++;
401 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
407 pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
409 /* Apply the division for our remaining calculations */
412 /* Fvco should be 90-100MHz; don't check the upper bound */
415 while (target < 90000000) {
419 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
424 fll_div->fll_outdiv = div;
426 pr_debug("Fvco=%dHz\n", target);
428 /* Find an appropriate FLL_FRATIO and factor it out of the target */
429 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
430 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
431 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
432 target /= fll_fratios[i].ratio;
436 if (i == ARRAY_SIZE(fll_fratios)) {
437 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
441 /* Now, calculate N.K */
442 Ndiv = target / Fref;
445 Nmod = target % Fref;
446 pr_debug("Nmod=%d\n", Nmod);
448 /* Calculate fractional part - scale up so we can round. */
449 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
453 K = Kpart & 0xFFFFFFFF;
458 /* Move down to proper range now rounding is done */
461 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
462 fll_div->n, fll_div->k,
463 fll_div->fll_fratio, fll_div->fll_outdiv,
464 fll_div->fll_clk_ref_div);
469 static int _wm8993_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
470 unsigned int Fref, unsigned int Fout)
472 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
473 struct i2c_client *i2c = to_i2c_client(codec->dev);
474 u16 reg1, reg4, reg5;
475 struct _fll_div fll_div;
476 unsigned int timeout;
480 if (Fref == wm8993->fll_fref && Fout == wm8993->fll_fout)
483 /* Disable the FLL */
485 dev_dbg(codec->dev, "FLL disabled\n");
486 wm8993->fll_fref = 0;
487 wm8993->fll_fout = 0;
489 reg1 = snd_soc_read(codec, WM8993_FLL_CONTROL_1);
490 reg1 &= ~WM8993_FLL_ENA;
491 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1);
496 ret = fll_factors(&fll_div, Fref, Fout);
500 reg5 = snd_soc_read(codec, WM8993_FLL_CONTROL_5);
501 reg5 &= ~WM8993_FLL_CLK_SRC_MASK;
504 case WM8993_FLL_MCLK:
507 case WM8993_FLL_LRCLK:
511 case WM8993_FLL_BCLK:
516 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
520 /* Any FLL configuration change requires that the FLL be
522 reg1 = snd_soc_read(codec, WM8993_FLL_CONTROL_1);
523 reg1 &= ~WM8993_FLL_ENA;
524 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1);
526 /* Apply the configuration */
528 reg1 |= WM8993_FLL_FRAC_MASK;
530 reg1 &= ~WM8993_FLL_FRAC_MASK;
531 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1);
533 snd_soc_write(codec, WM8993_FLL_CONTROL_2,
534 (fll_div.fll_outdiv << WM8993_FLL_OUTDIV_SHIFT) |
535 (fll_div.fll_fratio << WM8993_FLL_FRATIO_SHIFT));
536 snd_soc_write(codec, WM8993_FLL_CONTROL_3, fll_div.k);
538 reg4 = snd_soc_read(codec, WM8993_FLL_CONTROL_4);
539 reg4 &= ~WM8993_FLL_N_MASK;
540 reg4 |= fll_div.n << WM8993_FLL_N_SHIFT;
541 snd_soc_write(codec, WM8993_FLL_CONTROL_4, reg4);
543 reg5 &= ~WM8993_FLL_CLK_REF_DIV_MASK;
544 reg5 |= fll_div.fll_clk_ref_div << WM8993_FLL_CLK_REF_DIV_SHIFT;
545 snd_soc_write(codec, WM8993_FLL_CONTROL_5, reg5);
547 /* If we've got an interrupt wired up make sure we get it */
549 timeout = msecs_to_jiffies(20);
550 else if (Fref < 1000000)
551 timeout = msecs_to_jiffies(3);
553 timeout = msecs_to_jiffies(1);
555 try_wait_for_completion(&wm8993->fll_lock);
558 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1 | WM8993_FLL_ENA);
560 timeout = wait_for_completion_timeout(&wm8993->fll_lock, timeout);
561 if (i2c->irq && !timeout)
562 dev_warn(codec->dev, "Timed out waiting for FLL\n");
564 dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
566 wm8993->fll_fref = Fref;
567 wm8993->fll_fout = Fout;
568 wm8993->fll_src = source;
573 static int wm8993_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
574 unsigned int Fref, unsigned int Fout)
576 return _wm8993_set_fll(dai->codec, fll_id, source, Fref, Fout);
579 static int configure_clock(struct snd_soc_codec *codec)
581 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
584 /* This should be done on init() for bypass paths */
585 switch (wm8993->sysclk_source) {
586 case WM8993_SYSCLK_MCLK:
587 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8993->mclk_rate);
589 reg = snd_soc_read(codec, WM8993_CLOCKING_2);
590 reg &= ~(WM8993_MCLK_DIV | WM8993_SYSCLK_SRC);
591 if (wm8993->mclk_rate > 13500000) {
592 reg |= WM8993_MCLK_DIV;
593 wm8993->sysclk_rate = wm8993->mclk_rate / 2;
595 reg &= ~WM8993_MCLK_DIV;
596 wm8993->sysclk_rate = wm8993->mclk_rate;
598 snd_soc_write(codec, WM8993_CLOCKING_2, reg);
601 case WM8993_SYSCLK_FLL:
602 dev_dbg(codec->dev, "Using %dHz FLL clock\n",
605 reg = snd_soc_read(codec, WM8993_CLOCKING_2);
606 reg |= WM8993_SYSCLK_SRC;
607 if (wm8993->fll_fout > 13500000) {
608 reg |= WM8993_MCLK_DIV;
609 wm8993->sysclk_rate = wm8993->fll_fout / 2;
611 reg &= ~WM8993_MCLK_DIV;
612 wm8993->sysclk_rate = wm8993->fll_fout;
614 snd_soc_write(codec, WM8993_CLOCKING_2, reg);
618 dev_err(codec->dev, "System clock not configured\n");
622 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8993->sysclk_rate);
627 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
628 static const DECLARE_TLV_DB_SCALE(drc_comp_threash, -4500, 75, 0);
629 static const DECLARE_TLV_DB_SCALE(drc_comp_amp, -2250, 75, 0);
630 static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
631 static const unsigned int drc_max_tlv[] = {
632 TLV_DB_RANGE_HEAD(2),
633 0, 2, TLV_DB_SCALE_ITEM(1200, 600, 0),
634 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
636 static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
637 static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -1800, 300, 0);
638 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
639 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
640 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
642 static const char *dac_deemph_text[] = {
649 static SOC_ENUM_SINGLE_DECL(dac_deemph,
650 WM8993_DAC_CTRL, 4, dac_deemph_text);
652 static const char *adc_hpf_text[] = {
659 static SOC_ENUM_SINGLE_DECL(adc_hpf,
660 WM8993_ADC_CTRL, 5, adc_hpf_text);
662 static const char *drc_path_text[] = {
667 static SOC_ENUM_SINGLE_DECL(drc_path,
668 WM8993_DRC_CONTROL_1, 14, drc_path_text);
670 static const char *drc_r0_text[] = {
679 static SOC_ENUM_SINGLE_DECL(drc_r0,
680 WM8993_DRC_CONTROL_3, 8, drc_r0_text);
682 static const char *drc_r1_text[] = {
690 static SOC_ENUM_SINGLE_DECL(drc_r1,
691 WM8993_DRC_CONTROL_4, 13, drc_r1_text);
693 static const char *drc_attack_text[] = {
708 static SOC_ENUM_SINGLE_DECL(drc_attack,
709 WM8993_DRC_CONTROL_2, 12, drc_attack_text);
711 static const char *drc_decay_text[] = {
723 static SOC_ENUM_SINGLE_DECL(drc_decay,
724 WM8993_DRC_CONTROL_2, 8, drc_decay_text);
726 static const char *drc_ff_text[] = {
731 static SOC_ENUM_SINGLE_DECL(drc_ff,
732 WM8993_DRC_CONTROL_3, 7, drc_ff_text);
734 static const char *drc_qr_rate_text[] = {
740 static SOC_ENUM_SINGLE_DECL(drc_qr_rate,
741 WM8993_DRC_CONTROL_3, 0, drc_qr_rate_text);
743 static const char *drc_smooth_text[] = {
749 static SOC_ENUM_SINGLE_DECL(drc_smooth,
750 WM8993_DRC_CONTROL_1, 4, drc_smooth_text);
752 static const struct snd_kcontrol_new wm8993_snd_controls[] = {
753 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8993_DIGITAL_SIDE_TONE,
754 5, 9, 12, 0, sidetone_tlv),
756 SOC_SINGLE("DRC Switch", WM8993_DRC_CONTROL_1, 15, 1, 0),
757 SOC_ENUM("DRC Path", drc_path),
758 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8993_DRC_CONTROL_2,
759 2, 60, 1, drc_comp_threash),
760 SOC_SINGLE_TLV("DRC Compressor Amplitude Volume", WM8993_DRC_CONTROL_3,
761 11, 30, 1, drc_comp_amp),
762 SOC_ENUM("DRC R0", drc_r0),
763 SOC_ENUM("DRC R1", drc_r1),
764 SOC_SINGLE_TLV("DRC Minimum Volume", WM8993_DRC_CONTROL_1, 2, 3, 1,
766 SOC_SINGLE_TLV("DRC Maximum Volume", WM8993_DRC_CONTROL_1, 0, 3, 0,
768 SOC_ENUM("DRC Attack Rate", drc_attack),
769 SOC_ENUM("DRC Decay Rate", drc_decay),
770 SOC_ENUM("DRC FF Delay", drc_ff),
771 SOC_SINGLE("DRC Anti-clip Switch", WM8993_DRC_CONTROL_1, 9, 1, 0),
772 SOC_SINGLE("DRC Quick Release Switch", WM8993_DRC_CONTROL_1, 10, 1, 0),
773 SOC_SINGLE_TLV("DRC Quick Release Volume", WM8993_DRC_CONTROL_3, 2, 3, 0,
775 SOC_ENUM("DRC Quick Release Rate", drc_qr_rate),
776 SOC_SINGLE("DRC Smoothing Switch", WM8993_DRC_CONTROL_1, 11, 1, 0),
777 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8993_DRC_CONTROL_1, 8, 1, 0),
778 SOC_ENUM("DRC Smoothing Hysteresis Threshold", drc_smooth),
779 SOC_SINGLE_TLV("DRC Startup Volume", WM8993_DRC_CONTROL_4, 8, 18, 0,
782 SOC_SINGLE("EQ Switch", WM8993_EQ1, 0, 1, 0),
784 SOC_DOUBLE_R_TLV("Capture Volume", WM8993_LEFT_ADC_DIGITAL_VOLUME,
785 WM8993_RIGHT_ADC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
786 SOC_SINGLE("ADC High Pass Filter Switch", WM8993_ADC_CTRL, 8, 1, 0),
787 SOC_ENUM("ADC High Pass Filter Mode", adc_hpf),
789 SOC_DOUBLE_R_TLV("Playback Volume", WM8993_LEFT_DAC_DIGITAL_VOLUME,
790 WM8993_RIGHT_DAC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
791 SOC_SINGLE_TLV("Playback Boost Volume", WM8993_AUDIO_INTERFACE_2, 10, 3, 0,
793 SOC_ENUM("DAC Deemphasis", dac_deemph),
795 SOC_SINGLE_TLV("SPKL DAC Volume", WM8993_SPKMIXL_ATTENUATION,
796 2, 1, 1, wm_hubs_spkmix_tlv),
798 SOC_SINGLE_TLV("SPKR DAC Volume", WM8993_SPKMIXR_ATTENUATION,
799 2, 1, 1, wm_hubs_spkmix_tlv),
802 static const struct snd_kcontrol_new wm8993_eq_controls[] = {
803 SOC_SINGLE_TLV("EQ1 Volume", WM8993_EQ2, 0, 24, 0, eq_tlv),
804 SOC_SINGLE_TLV("EQ2 Volume", WM8993_EQ3, 0, 24, 0, eq_tlv),
805 SOC_SINGLE_TLV("EQ3 Volume", WM8993_EQ4, 0, 24, 0, eq_tlv),
806 SOC_SINGLE_TLV("EQ4 Volume", WM8993_EQ5, 0, 24, 0, eq_tlv),
807 SOC_SINGLE_TLV("EQ5 Volume", WM8993_EQ6, 0, 24, 0, eq_tlv),
810 static int clk_sys_event(struct snd_soc_dapm_widget *w,
811 struct snd_kcontrol *kcontrol, int event)
813 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
816 case SND_SOC_DAPM_PRE_PMU:
817 return configure_clock(codec);
819 case SND_SOC_DAPM_POST_PMD:
826 static const struct snd_kcontrol_new left_speaker_mixer[] = {
827 SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 7, 1, 0),
828 SOC_DAPM_SINGLE("IN1LP Switch", WM8993_SPEAKER_MIXER, 5, 1, 0),
829 SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 3, 1, 0),
830 SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
833 static const struct snd_kcontrol_new right_speaker_mixer[] = {
834 SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
835 SOC_DAPM_SINGLE("IN1RP Switch", WM8993_SPEAKER_MIXER, 4, 1, 0),
836 SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 2, 1, 0),
837 SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 0, 1, 0),
840 static const char *aif_text[] = {
844 static SOC_ENUM_SINGLE_DECL(aifoutl_enum,
845 WM8993_AUDIO_INTERFACE_1, 15, aif_text);
847 static const struct snd_kcontrol_new aifoutl_mux =
848 SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum);
850 static SOC_ENUM_SINGLE_DECL(aifoutr_enum,
851 WM8993_AUDIO_INTERFACE_1, 14, aif_text);
853 static const struct snd_kcontrol_new aifoutr_mux =
854 SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum);
856 static SOC_ENUM_SINGLE_DECL(aifinl_enum,
857 WM8993_AUDIO_INTERFACE_2, 15, aif_text);
859 static const struct snd_kcontrol_new aifinl_mux =
860 SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum);
862 static SOC_ENUM_SINGLE_DECL(aifinr_enum,
863 WM8993_AUDIO_INTERFACE_2, 14, aif_text);
865 static const struct snd_kcontrol_new aifinr_mux =
866 SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum);
868 static const char *sidetone_text[] = {
869 "None", "Left", "Right"
872 static SOC_ENUM_SINGLE_DECL(sidetonel_enum,
873 WM8993_DIGITAL_SIDE_TONE, 2, sidetone_text);
875 static const struct snd_kcontrol_new sidetonel_mux =
876 SOC_DAPM_ENUM("Left Sidetone", sidetonel_enum);
878 static SOC_ENUM_SINGLE_DECL(sidetoner_enum,
879 WM8993_DIGITAL_SIDE_TONE, 0, sidetone_text);
881 static const struct snd_kcontrol_new sidetoner_mux =
882 SOC_DAPM_ENUM("Right Sidetone", sidetoner_enum);
884 static const struct snd_soc_dapm_widget wm8993_dapm_widgets[] = {
885 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8993_BUS_CONTROL_1, 1, 0, clk_sys_event,
886 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
887 SND_SOC_DAPM_SUPPLY("TOCLK", WM8993_CLOCKING_1, 14, 0, NULL, 0),
888 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8993_CLOCKING_3, 0, 0, NULL, 0),
889 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, NULL, 0),
891 SND_SOC_DAPM_ADC("ADCL", NULL, WM8993_POWER_MANAGEMENT_2, 1, 0),
892 SND_SOC_DAPM_ADC("ADCR", NULL, WM8993_POWER_MANAGEMENT_2, 0, 0),
894 SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux),
895 SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux),
897 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
898 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
900 SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
901 SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
903 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux),
904 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux),
906 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &sidetonel_mux),
907 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &sidetoner_mux),
909 SND_SOC_DAPM_DAC("DACL", NULL, WM8993_POWER_MANAGEMENT_3, 1, 0),
910 SND_SOC_DAPM_DAC("DACR", NULL, WM8993_POWER_MANAGEMENT_3, 0, 0),
912 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
913 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
915 SND_SOC_DAPM_MIXER("SPKL", WM8993_POWER_MANAGEMENT_3, 8, 0,
916 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
917 SND_SOC_DAPM_MIXER("SPKR", WM8993_POWER_MANAGEMENT_3, 9, 0,
918 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
919 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
922 static const struct snd_soc_dapm_route routes[] = {
923 { "MICBIAS1", NULL, "VMID" },
924 { "MICBIAS2", NULL, "VMID" },
926 { "ADCL", NULL, "CLK_SYS" },
927 { "ADCL", NULL, "CLK_DSP" },
928 { "ADCR", NULL, "CLK_SYS" },
929 { "ADCR", NULL, "CLK_DSP" },
931 { "AIFOUTL Mux", "Left", "ADCL" },
932 { "AIFOUTL Mux", "Right", "ADCR" },
933 { "AIFOUTR Mux", "Left", "ADCL" },
934 { "AIFOUTR Mux", "Right", "ADCR" },
936 { "AIFOUTL", NULL, "AIFOUTL Mux" },
937 { "AIFOUTR", NULL, "AIFOUTR Mux" },
939 { "DACL Mux", "Left", "AIFINL" },
940 { "DACL Mux", "Right", "AIFINR" },
941 { "DACR Mux", "Left", "AIFINL" },
942 { "DACR Mux", "Right", "AIFINR" },
944 { "DACL Sidetone", "Left", "ADCL" },
945 { "DACL Sidetone", "Right", "ADCR" },
946 { "DACR Sidetone", "Left", "ADCL" },
947 { "DACR Sidetone", "Right", "ADCR" },
949 { "DACL", NULL, "CLK_SYS" },
950 { "DACL", NULL, "CLK_DSP" },
951 { "DACL", NULL, "DACL Mux" },
952 { "DACL", NULL, "DACL Sidetone" },
953 { "DACR", NULL, "CLK_SYS" },
954 { "DACR", NULL, "CLK_DSP" },
955 { "DACR", NULL, "DACR Mux" },
956 { "DACR", NULL, "DACR Sidetone" },
958 { "Left Output Mixer", "DAC Switch", "DACL" },
960 { "Right Output Mixer", "DAC Switch", "DACR" },
962 { "Left Output PGA", NULL, "CLK_SYS" },
964 { "Right Output PGA", NULL, "CLK_SYS" },
966 { "SPKL", "DAC Switch", "DACL" },
967 { "SPKL", NULL, "CLK_SYS" },
969 { "SPKR", "DAC Switch", "DACR" },
970 { "SPKR", NULL, "CLK_SYS" },
972 { "Left Headphone Mux", "DAC", "DACL" },
973 { "Right Headphone Mux", "DAC", "DACR" },
976 static int wm8993_set_bias_level(struct snd_soc_codec *codec,
977 enum snd_soc_bias_level level)
979 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
982 wm_hubs_set_bias_level(codec, level);
985 case SND_SOC_BIAS_ON:
986 case SND_SOC_BIAS_PREPARE:
988 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
989 WM8993_VMID_SEL_MASK, 0x2);
990 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2,
991 WM8993_TSHUT_ENA, WM8993_TSHUT_ENA);
994 case SND_SOC_BIAS_STANDBY:
995 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
996 ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies),
1001 regcache_cache_only(wm8993->regmap, false);
1002 regcache_sync(wm8993->regmap);
1004 wm_hubs_vmid_ena(codec);
1006 /* Bring up VMID with fast soft start */
1007 snd_soc_update_bits(codec, WM8993_ANTIPOP2,
1008 WM8993_STARTUP_BIAS_ENA |
1009 WM8993_VMID_BUF_ENA |
1010 WM8993_VMID_RAMP_MASK |
1012 WM8993_STARTUP_BIAS_ENA |
1013 WM8993_VMID_BUF_ENA |
1014 WM8993_VMID_RAMP_MASK |
1017 /* If either line output is single ended we
1018 * need the VMID buffer */
1019 if (!wm8993->pdata.lineout1_diff ||
1020 !wm8993->pdata.lineout2_diff)
1021 snd_soc_update_bits(codec, WM8993_ANTIPOP1,
1022 WM8993_LINEOUT_VMID_BUF_ENA,
1023 WM8993_LINEOUT_VMID_BUF_ENA);
1026 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1027 WM8993_VMID_SEL_MASK |
1029 WM8993_BIAS_ENA | 0x2);
1032 /* Switch to normal bias */
1033 snd_soc_update_bits(codec, WM8993_ANTIPOP2,
1035 WM8993_STARTUP_BIAS_ENA, 0);
1039 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1040 WM8993_VMID_SEL_MASK, 0x4);
1042 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2,
1043 WM8993_TSHUT_ENA, 0);
1046 case SND_SOC_BIAS_OFF:
1047 snd_soc_update_bits(codec, WM8993_ANTIPOP1,
1048 WM8993_LINEOUT_VMID_BUF_ENA, 0);
1050 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1051 WM8993_VMID_SEL_MASK | WM8993_BIAS_ENA,
1054 snd_soc_update_bits(codec, WM8993_ANTIPOP2,
1055 WM8993_STARTUP_BIAS_ENA |
1056 WM8993_VMID_BUF_ENA |
1057 WM8993_VMID_RAMP_MASK |
1058 WM8993_BIAS_SRC, 0);
1060 regcache_cache_only(wm8993->regmap, true);
1061 regcache_mark_dirty(wm8993->regmap);
1063 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies),
1071 static int wm8993_set_sysclk(struct snd_soc_dai *codec_dai,
1072 int clk_id, unsigned int freq, int dir)
1074 struct snd_soc_codec *codec = codec_dai->codec;
1075 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1078 case WM8993_SYSCLK_MCLK:
1079 wm8993->mclk_rate = freq;
1080 case WM8993_SYSCLK_FLL:
1081 wm8993->sysclk_source = clk_id;
1091 static int wm8993_set_dai_fmt(struct snd_soc_dai *dai,
1094 struct snd_soc_codec *codec = dai->codec;
1095 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1096 unsigned int aif1 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_1);
1097 unsigned int aif4 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_4);
1099 aif1 &= ~(WM8993_BCLK_DIR | WM8993_AIF_BCLK_INV |
1100 WM8993_AIF_LRCLK_INV | WM8993_AIF_FMT_MASK);
1101 aif4 &= ~WM8993_LRCLK_DIR;
1103 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1104 case SND_SOC_DAIFMT_CBS_CFS:
1107 case SND_SOC_DAIFMT_CBS_CFM:
1108 aif4 |= WM8993_LRCLK_DIR;
1111 case SND_SOC_DAIFMT_CBM_CFS:
1112 aif1 |= WM8993_BCLK_DIR;
1115 case SND_SOC_DAIFMT_CBM_CFM:
1116 aif1 |= WM8993_BCLK_DIR;
1117 aif4 |= WM8993_LRCLK_DIR;
1124 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1125 case SND_SOC_DAIFMT_DSP_B:
1126 aif1 |= WM8993_AIF_LRCLK_INV;
1127 case SND_SOC_DAIFMT_DSP_A:
1130 case SND_SOC_DAIFMT_I2S:
1133 case SND_SOC_DAIFMT_RIGHT_J:
1135 case SND_SOC_DAIFMT_LEFT_J:
1142 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1143 case SND_SOC_DAIFMT_DSP_A:
1144 case SND_SOC_DAIFMT_DSP_B:
1145 /* frame inversion not valid for DSP modes */
1146 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1147 case SND_SOC_DAIFMT_NB_NF:
1149 case SND_SOC_DAIFMT_IB_NF:
1150 aif1 |= WM8993_AIF_BCLK_INV;
1157 case SND_SOC_DAIFMT_I2S:
1158 case SND_SOC_DAIFMT_RIGHT_J:
1159 case SND_SOC_DAIFMT_LEFT_J:
1160 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1161 case SND_SOC_DAIFMT_NB_NF:
1163 case SND_SOC_DAIFMT_IB_IF:
1164 aif1 |= WM8993_AIF_BCLK_INV | WM8993_AIF_LRCLK_INV;
1166 case SND_SOC_DAIFMT_IB_NF:
1167 aif1 |= WM8993_AIF_BCLK_INV;
1169 case SND_SOC_DAIFMT_NB_IF:
1170 aif1 |= WM8993_AIF_LRCLK_INV;
1180 snd_soc_write(codec, WM8993_AUDIO_INTERFACE_1, aif1);
1181 snd_soc_write(codec, WM8993_AUDIO_INTERFACE_4, aif4);
1186 static int wm8993_hw_params(struct snd_pcm_substream *substream,
1187 struct snd_pcm_hw_params *params,
1188 struct snd_soc_dai *dai)
1190 struct snd_soc_codec *codec = dai->codec;
1191 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1192 int ret, i, best, best_val, cur_val;
1193 unsigned int clocking1, clocking3, aif1, aif4;
1195 clocking1 = snd_soc_read(codec, WM8993_CLOCKING_1);
1196 clocking1 &= ~WM8993_BCLK_DIV_MASK;
1198 clocking3 = snd_soc_read(codec, WM8993_CLOCKING_3);
1199 clocking3 &= ~(WM8993_CLK_SYS_RATE_MASK | WM8993_SAMPLE_RATE_MASK);
1201 aif1 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_1);
1202 aif1 &= ~WM8993_AIF_WL_MASK;
1204 aif4 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_4);
1205 aif4 &= ~WM8993_LRCLK_RATE_MASK;
1207 /* What BCLK do we need? */
1208 wm8993->fs = params_rate(params);
1209 wm8993->bclk = 2 * wm8993->fs;
1210 if (wm8993->tdm_slots) {
1211 dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n",
1212 wm8993->tdm_slots, wm8993->tdm_width);
1213 wm8993->bclk *= wm8993->tdm_width * wm8993->tdm_slots;
1215 switch (params_width(params)) {
1236 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8993->bclk);
1238 ret = configure_clock(codec);
1242 /* Select nearest CLK_SYS_RATE */
1244 best_val = abs((wm8993->sysclk_rate / clk_sys_rates[0].ratio)
1246 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1247 cur_val = abs((wm8993->sysclk_rate /
1248 clk_sys_rates[i].ratio) - wm8993->fs);
1249 if (cur_val < best_val) {
1254 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1255 clk_sys_rates[best].ratio);
1256 clocking3 |= (clk_sys_rates[best].clk_sys_rate
1257 << WM8993_CLK_SYS_RATE_SHIFT);
1261 best_val = abs(wm8993->fs - sample_rates[0].rate);
1262 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1264 cur_val = abs(wm8993->fs - sample_rates[i].rate);
1265 if (cur_val < best_val) {
1270 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1271 sample_rates[best].rate);
1272 clocking3 |= (sample_rates[best].sample_rate
1273 << WM8993_SAMPLE_RATE_SHIFT);
1278 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1279 cur_val = ((wm8993->sysclk_rate * 10) / bclk_divs[i].div)
1281 if (cur_val < 0) /* Table is sorted */
1283 if (cur_val < best_val) {
1288 wm8993->bclk = (wm8993->sysclk_rate * 10) / bclk_divs[best].div;
1289 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1290 bclk_divs[best].div, wm8993->bclk);
1291 clocking1 |= bclk_divs[best].bclk_div << WM8993_BCLK_DIV_SHIFT;
1293 /* LRCLK is a simple fraction of BCLK */
1294 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8993->bclk / wm8993->fs);
1295 aif4 |= wm8993->bclk / wm8993->fs;
1297 snd_soc_write(codec, WM8993_CLOCKING_1, clocking1);
1298 snd_soc_write(codec, WM8993_CLOCKING_3, clocking3);
1299 snd_soc_write(codec, WM8993_AUDIO_INTERFACE_1, aif1);
1300 snd_soc_write(codec, WM8993_AUDIO_INTERFACE_4, aif4);
1302 /* ReTune Mobile? */
1303 if (wm8993->pdata.num_retune_configs) {
1304 u16 eq1 = snd_soc_read(codec, WM8993_EQ1);
1305 struct wm8993_retune_mobile_setting *s;
1308 best_val = abs(wm8993->pdata.retune_configs[0].rate
1310 for (i = 0; i < wm8993->pdata.num_retune_configs; i++) {
1311 cur_val = abs(wm8993->pdata.retune_configs[i].rate
1313 if (cur_val < best_val) {
1318 s = &wm8993->pdata.retune_configs[best];
1320 dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n",
1323 /* Disable EQ while we reconfigure */
1324 snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, 0);
1326 for (i = 1; i < ARRAY_SIZE(s->config); i++)
1327 snd_soc_write(codec, WM8993_EQ1 + i, s->config[i]);
1329 snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, eq1);
1335 static int wm8993_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1337 struct snd_soc_codec *codec = codec_dai->codec;
1340 reg = snd_soc_read(codec, WM8993_DAC_CTRL);
1343 reg |= WM8993_DAC_MUTE;
1345 reg &= ~WM8993_DAC_MUTE;
1347 snd_soc_write(codec, WM8993_DAC_CTRL, reg);
1352 static int wm8993_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1353 unsigned int rx_mask, int slots, int slot_width)
1355 struct snd_soc_codec *codec = dai->codec;
1356 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1360 /* Don't need to validate anything if we're turning off TDM */
1362 wm8993->tdm_slots = 0;
1366 /* Note that we allow configurations we can't handle ourselves -
1367 * for example, we can generate clocks for slots 2 and up even if
1368 * we can't use those slots ourselves.
1370 aif1 |= WM8993_AIFADC_TDM;
1371 aif2 |= WM8993_AIFDAC_TDM;
1377 aif1 |= WM8993_AIFADC_TDM_CHAN;
1388 aif2 |= WM8993_AIFDAC_TDM_CHAN;
1395 wm8993->tdm_width = slot_width;
1396 wm8993->tdm_slots = slots / 2;
1398 snd_soc_update_bits(codec, WM8993_AUDIO_INTERFACE_1,
1399 WM8993_AIFADC_TDM | WM8993_AIFADC_TDM_CHAN, aif1);
1400 snd_soc_update_bits(codec, WM8993_AUDIO_INTERFACE_2,
1401 WM8993_AIFDAC_TDM | WM8993_AIFDAC_TDM_CHAN, aif2);
1406 static irqreturn_t wm8993_irq(int irq, void *data)
1408 struct wm8993_priv *wm8993 = data;
1411 ret = regmap_read(wm8993->regmap, WM8993_GPIO_CTRL_1, &val);
1413 dev_err(wm8993->dev, "Failed to read interrupt status: %d\n",
1418 ret = regmap_read(wm8993->regmap, WM8993_GPIOCTRL_2, &mask);
1420 dev_err(wm8993->dev, "Failed to read interrupt mask: %d\n",
1425 /* The IRQ pin status is visible in the register too */
1426 val &= ~(mask | WM8993_IRQ);
1430 if (val & WM8993_TEMPOK_EINT)
1431 dev_crit(wm8993->dev, "Thermal warning\n");
1433 if (val & WM8993_FLL_LOCK_EINT) {
1434 dev_dbg(wm8993->dev, "FLL locked\n");
1435 complete(&wm8993->fll_lock);
1438 ret = regmap_write(wm8993->regmap, WM8993_GPIO_CTRL_1, val);
1440 dev_err(wm8993->dev, "Failed to ack interrupt: %d\n", ret);
1445 static const struct snd_soc_dai_ops wm8993_ops = {
1446 .set_sysclk = wm8993_set_sysclk,
1447 .set_fmt = wm8993_set_dai_fmt,
1448 .hw_params = wm8993_hw_params,
1449 .digital_mute = wm8993_digital_mute,
1450 .set_pll = wm8993_set_fll,
1451 .set_tdm_slot = wm8993_set_tdm_slot,
1454 #define WM8993_RATES SNDRV_PCM_RATE_8000_48000
1456 #define WM8993_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1457 SNDRV_PCM_FMTBIT_S20_3LE |\
1458 SNDRV_PCM_FMTBIT_S24_LE |\
1459 SNDRV_PCM_FMTBIT_S32_LE)
1461 static struct snd_soc_dai_driver wm8993_dai = {
1462 .name = "wm8993-hifi",
1464 .stream_name = "Playback",
1467 .rates = WM8993_RATES,
1468 .formats = WM8993_FORMATS,
1472 .stream_name = "Capture",
1475 .rates = WM8993_RATES,
1476 .formats = WM8993_FORMATS,
1480 .symmetric_rates = 1,
1483 static int wm8993_probe(struct snd_soc_codec *codec)
1485 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1486 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1488 wm8993->hubs_data.hp_startup_mode = 1;
1489 wm8993->hubs_data.dcs_codes_l = -2;
1490 wm8993->hubs_data.dcs_codes_r = -2;
1491 wm8993->hubs_data.series_startup = 1;
1493 /* Latch volume update bits and default ZC on */
1494 snd_soc_update_bits(codec, WM8993_RIGHT_DAC_DIGITAL_VOLUME,
1495 WM8993_DAC_VU, WM8993_DAC_VU);
1496 snd_soc_update_bits(codec, WM8993_RIGHT_ADC_DIGITAL_VOLUME,
1497 WM8993_ADC_VU, WM8993_ADC_VU);
1499 /* Manualy manage the HPOUT sequencing for independent stereo
1501 snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0,
1502 WM8993_HPOUT1_AUTO_PU, 0);
1504 /* Use automatic clock configuration */
1505 snd_soc_update_bits(codec, WM8993_CLOCKING_4, WM8993_SR_MODE, 0);
1507 wm_hubs_handle_analogue_pdata(codec, wm8993->pdata.lineout1_diff,
1508 wm8993->pdata.lineout2_diff,
1509 wm8993->pdata.lineout1fb,
1510 wm8993->pdata.lineout2fb,
1511 wm8993->pdata.jd_scthr,
1512 wm8993->pdata.jd_thr,
1513 wm8993->pdata.micbias1_delay,
1514 wm8993->pdata.micbias2_delay,
1515 wm8993->pdata.micbias1_lvl,
1516 wm8993->pdata.micbias2_lvl);
1518 snd_soc_add_codec_controls(codec, wm8993_snd_controls,
1519 ARRAY_SIZE(wm8993_snd_controls));
1520 if (wm8993->pdata.num_retune_configs != 0) {
1521 dev_dbg(codec->dev, "Using ReTune Mobile\n");
1523 dev_dbg(codec->dev, "No ReTune Mobile, using normal EQ\n");
1524 snd_soc_add_codec_controls(codec, wm8993_eq_controls,
1525 ARRAY_SIZE(wm8993_eq_controls));
1528 snd_soc_dapm_new_controls(dapm, wm8993_dapm_widgets,
1529 ARRAY_SIZE(wm8993_dapm_widgets));
1530 wm_hubs_add_analogue_controls(codec);
1532 snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes));
1533 wm_hubs_add_analogue_routes(codec, wm8993->pdata.lineout1_diff,
1534 wm8993->pdata.lineout2_diff);
1536 /* If the line outputs are differential then we aren't presenting
1537 * VMID as an output and can disable it.
1539 if (wm8993->pdata.lineout1_diff && wm8993->pdata.lineout2_diff)
1540 dapm->idle_bias_off = 1;
1547 static int wm8993_suspend(struct snd_soc_codec *codec)
1549 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1550 int fll_fout = wm8993->fll_fout;
1551 int fll_fref = wm8993->fll_fref;
1554 /* Stop the FLL in an orderly fashion */
1555 ret = _wm8993_set_fll(codec, 0, 0, 0, 0);
1557 dev_err(codec->dev, "Failed to stop FLL\n");
1561 wm8993->fll_fout = fll_fout;
1562 wm8993->fll_fref = fll_fref;
1564 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
1569 static int wm8993_resume(struct snd_soc_codec *codec)
1571 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1574 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_STANDBY);
1576 /* Restart the FLL? */
1577 if (wm8993->fll_fout) {
1578 int fll_fout = wm8993->fll_fout;
1579 int fll_fref = wm8993->fll_fref;
1581 wm8993->fll_fref = 0;
1582 wm8993->fll_fout = 0;
1584 ret = _wm8993_set_fll(codec, 0, wm8993->fll_src,
1585 fll_fref, fll_fout);
1587 dev_err(codec->dev, "Failed to restart FLL\n");
1593 #define wm8993_suspend NULL
1594 #define wm8993_resume NULL
1597 /* Tune DC servo configuration */
1598 static const struct reg_sequence wm8993_regmap_patch[] = {
1604 static const struct regmap_config wm8993_regmap = {
1608 .max_register = WM8993_MAX_REGISTER,
1609 .volatile_reg = wm8993_volatile,
1610 .readable_reg = wm8993_readable,
1612 .cache_type = REGCACHE_RBTREE,
1613 .reg_defaults = wm8993_reg_defaults,
1614 .num_reg_defaults = ARRAY_SIZE(wm8993_reg_defaults),
1617 static struct snd_soc_codec_driver soc_codec_dev_wm8993 = {
1618 .probe = wm8993_probe,
1619 .suspend = wm8993_suspend,
1620 .resume = wm8993_resume,
1621 .set_bias_level = wm8993_set_bias_level,
1624 static int wm8993_i2c_probe(struct i2c_client *i2c,
1625 const struct i2c_device_id *id)
1627 struct wm8993_priv *wm8993;
1631 wm8993 = devm_kzalloc(&i2c->dev, sizeof(struct wm8993_priv),
1636 wm8993->dev = &i2c->dev;
1637 init_completion(&wm8993->fll_lock);
1639 wm8993->regmap = devm_regmap_init_i2c(i2c, &wm8993_regmap);
1640 if (IS_ERR(wm8993->regmap)) {
1641 ret = PTR_ERR(wm8993->regmap);
1642 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
1646 i2c_set_clientdata(i2c, wm8993);
1648 for (i = 0; i < ARRAY_SIZE(wm8993->supplies); i++)
1649 wm8993->supplies[i].supply = wm8993_supply_names[i];
1651 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8993->supplies),
1654 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
1658 ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies),
1661 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
1665 ret = regmap_read(wm8993->regmap, WM8993_SOFTWARE_RESET, ®);
1667 dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);
1671 if (reg != 0x8993) {
1672 dev_err(&i2c->dev, "Invalid ID register value %x\n", reg);
1677 ret = regmap_write(wm8993->regmap, WM8993_SOFTWARE_RESET, 0xffff);
1681 ret = regmap_register_patch(wm8993->regmap, wm8993_regmap_patch,
1682 ARRAY_SIZE(wm8993_regmap_patch));
1684 dev_warn(wm8993->dev, "Failed to apply regmap patch: %d\n",
1688 /* Put GPIO1 into interrupt mode (only GPIO1 can output IRQ) */
1689 ret = regmap_update_bits(wm8993->regmap, WM8993_GPIO1,
1691 WM8993_GPIO1_SEL_MASK, 7);
1695 ret = request_threaded_irq(i2c->irq, NULL, wm8993_irq,
1696 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1703 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1705 regcache_cache_only(wm8993->regmap, true);
1707 ret = snd_soc_register_codec(&i2c->dev,
1708 &soc_codec_dev_wm8993, &wm8993_dai, 1);
1710 dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
1718 free_irq(i2c->irq, wm8993);
1720 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1724 static int wm8993_i2c_remove(struct i2c_client *i2c)
1726 struct wm8993_priv *wm8993 = i2c_get_clientdata(i2c);
1728 snd_soc_unregister_codec(&i2c->dev);
1730 free_irq(i2c->irq, wm8993);
1731 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1736 static const struct i2c_device_id wm8993_i2c_id[] = {
1740 MODULE_DEVICE_TABLE(i2c, wm8993_i2c_id);
1742 static struct i2c_driver wm8993_i2c_driver = {
1746 .probe = wm8993_i2c_probe,
1747 .remove = wm8993_i2c_remove,
1748 .id_table = wm8993_i2c_id,
1751 module_i2c_driver(wm8993_i2c_driver);
1753 MODULE_DESCRIPTION("ASoC WM8993 driver");
1754 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1755 MODULE_LICENSE("GPL");