sound/soc/codecs/wm8994.c

   1 /*
   2  * wm8994.c  --  WM8994 ALSA SoC Audio driver
   3  *
   4  * Copyright 2009 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/slab.h>
  24 #include <sound/core.h>
  25 #include <sound/jack.h>
  26 #include <sound/pcm.h>
  27 #include <sound/pcm_params.h>
  28 #include <sound/soc.h>
  29 #include <sound/initval.h>
  30 #include <sound/tlv.h>
  31 #include <trace/events/asoc.h>
  32
  33 #include <linux/mfd/wm8994/core.h>
  34 #include <linux/mfd/wm8994/registers.h>
  35 #include <linux/mfd/wm8994/pdata.h>
  36 #include <linux/mfd/wm8994/gpio.h>
  37
  38 #include "wm8994.h"
  39 #include "wm_hubs.h"
  40
  41 #define WM8994_NUM_DRC 3
  42 #define WM8994_NUM_EQ  3
  43
  44 static int wm8994_drc_base[] = {
  45         WM8994_AIF1_DRC1_1,
  46         WM8994_AIF1_DRC2_1,
  47         WM8994_AIF2_DRC_1,
  48 };
  49
  50 static int wm8994_retune_mobile_base[] = {
  51         WM8994_AIF1_DAC1_EQ_GAINS_1,
  52         WM8994_AIF1_DAC2_EQ_GAINS_1,
  53         WM8994_AIF2_EQ_GAINS_1,
  54 };
  55
  56 static int wm8994_readable(struct snd_soc_codec *codec, unsigned int reg)
  57 {
  58         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  59         struct wm8994 *control = codec->control_data;
  60
  61         switch (reg) {
  62         case WM8994_GPIO_1:
  63         case WM8994_GPIO_2:
  64         case WM8994_GPIO_3:
  65         case WM8994_GPIO_4:
  66         case WM8994_GPIO_5:
  67         case WM8994_GPIO_6:
  68         case WM8994_GPIO_7:
  69         case WM8994_GPIO_8:
  70         case WM8994_GPIO_9:
  71         case WM8994_GPIO_10:
  72         case WM8994_GPIO_11:
  73         case WM8994_INTERRUPT_STATUS_1:
  74         case WM8994_INTERRUPT_STATUS_2:
  75         case WM8994_INTERRUPT_RAW_STATUS_2:
  76                 return 1;
  77
  78         case WM8958_DSP2_PROGRAM:
  79         case WM8958_DSP2_CONFIG:
  80         case WM8958_DSP2_EXECCONTROL:
  81                 if (control->type == WM8958)
  82                         return 1;
  83                 else
  84                         return 0;
  85
  86         default:
  87                 break;
  88         }
  89
  90         if (reg >= WM8994_CACHE_SIZE)
  91                 return 0;
  92         return wm8994_access_masks[reg].readable != 0;
  93 }
  94
  95 static int wm8994_volatile(struct snd_soc_codec *codec, unsigned int reg)
  96 {
  97         if (reg >= WM8994_CACHE_SIZE)
  98                 return 1;
  99
 100         switch (reg) {
 101         case WM8994_SOFTWARE_RESET:
 102         case WM8994_CHIP_REVISION:
 103         case WM8994_DC_SERVO_1:
 104         case WM8994_DC_SERVO_READBACK:
 105         case WM8994_RATE_STATUS:
 106         case WM8994_LDO_1:
 107         case WM8994_LDO_2:
 108         case WM8958_DSP2_EXECCONTROL:
 109         case WM8958_MIC_DETECT_3:
 110         case WM8994_DC_SERVO_4E:
 111                 return 1;
 112         default:
 113                 return 0;
 114         }
 115 }
 116
 117 static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
 118         unsigned int value)
 119 {
 120         int ret;
 121
 122         BUG_ON(reg > WM8994_MAX_REGISTER);
 123
 124         if (!wm8994_volatile(codec, reg)) {
 125                 ret = snd_soc_cache_write(codec, reg, value);
 126                 if (ret != 0)
 127                         dev_err(codec->dev, "Cache write to %x failed: %d\n",
 128                                 reg, ret);
 129         }
 130
 131         return wm8994_reg_write(codec->control_data, reg, value);
 132 }
 133
 134 static unsigned int wm8994_read(struct snd_soc_codec *codec,
 135                                 unsigned int reg)
 136 {
 137         unsigned int val;
 138         int ret;
 139
 140         BUG_ON(reg > WM8994_MAX_REGISTER);
 141
 142         if (!wm8994_volatile(codec, reg) && wm8994_readable(codec, reg) &&
 143             reg < codec->driver->reg_cache_size) {
 144                 ret = snd_soc_cache_read(codec, reg, &val);
 145                 if (ret >= 0)
 146                         return val;
 147                 else
 148                         dev_err(codec->dev, "Cache read from %x failed: %d\n",
 149                                 reg, ret);
 150         }
 151
 152         return wm8994_reg_read(codec->control_data, reg);
 153 }
 154
 155 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
 156 {
 157         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 158         int rate;
 159         int reg1 = 0;
 160         int offset;
 161
 162         if (aif)
 163                 offset = 4;
 164         else
 165                 offset = 0;
 166
 167         switch (wm8994->sysclk[aif]) {
 168         case WM8994_SYSCLK_MCLK1:
 169                 rate = wm8994->mclk[0];
 170                 break;
 171
 172         case WM8994_SYSCLK_MCLK2:
 173                 reg1 |= 0x8;
 174                 rate = wm8994->mclk[1];
 175                 break;
 176
 177         case WM8994_SYSCLK_FLL1:
 178                 reg1 |= 0x10;
 179                 rate = wm8994->fll[0].out;
 180                 break;
 181
 182         case WM8994_SYSCLK_FLL2:
 183                 reg1 |= 0x18;
 184                 rate = wm8994->fll[1].out;
 185                 break;
 186
 187         default:
 188                 return -EINVAL;
 189         }
 190
 191         if (rate >= 13500000) {
 192                 rate /= 2;
 193                 reg1 |= WM8994_AIF1CLK_DIV;
 194
 195                 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
 196                         aif + 1, rate);
 197         }
 198
 199         wm8994->aifclk[aif] = rate;
 200
 201         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
 202                             WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
 203                             reg1);
 204
 205         return 0;
 206 }
 207
 208 static int configure_clock(struct snd_soc_codec *codec)
 209 {
 210         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 211         int change, new;
 212
 213         /* Bring up the AIF clocks first */
 214         configure_aif_clock(codec, 0);
 215         configure_aif_clock(codec, 1);
 216
 217         /* Then switch CLK_SYS over to the higher of them; a change
 218          * can only happen as a result of a clocking change which can
 219          * only be made outside of DAPM so we can safely redo the
 220          * clocking.
 221          */
 222
 223         /* If they're equal it doesn't matter which is used */
 224         if (wm8994->aifclk[0] == wm8994->aifclk[1])
 225                 return 0;
 226
 227         if (wm8994->aifclk[0] < wm8994->aifclk[1])
 228                 new = WM8994_SYSCLK_SRC;
 229         else
 230                 new = 0;
 231
 232         change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
 233                                      WM8994_SYSCLK_SRC, new);
 234         if (!change)
 235                 return 0;
 236
 237         snd_soc_dapm_sync(&codec->dapm);
 238
 239         return 0;
 240 }
 241
 242 static int check_clk_sys(struct snd_soc_dapm_widget *source,
 243                          struct snd_soc_dapm_widget *sink)
 244 {
 245         int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
 246         const char *clk;
 247
 248         /* Check what we're currently using for CLK_SYS */
 249         if (reg & WM8994_SYSCLK_SRC)
 250                 clk = "AIF2CLK";
 251         else
 252                 clk = "AIF1CLK";
 253
 254         return strcmp(source->name, clk) == 0;
 255 }
 256
 257 static const char *sidetone_hpf_text[] = {
 258         "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
 259 };
 260
 261 static const struct soc_enum sidetone_hpf =
 262         SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
 263
 264 static const char *adc_hpf_text[] = {
 265         "HiFi", "Voice 1", "Voice 2", "Voice 3"
 266 };
 267
 268 static const struct soc_enum aif1adc1_hpf =
 269         SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
 270
 271 static const struct soc_enum aif1adc2_hpf =
 272         SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
 273
 274 static const struct soc_enum aif2adc_hpf =
 275         SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
 276
 277 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
 278 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 279 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
 280 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
 281 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 282 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
 283 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
 284
 285 #define WM8994_DRC_SWITCH(xname, reg, shift) \
 286 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 287         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
 288         .put = wm8994_put_drc_sw, \
 289         .private_value =  SOC_SINGLE_VALUE(reg, shift, 1, 0) }
 290
 291 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
 292                              struct snd_ctl_elem_value *ucontrol)
 293 {
 294         struct soc_mixer_control *mc =
 295                 (struct soc_mixer_control *)kcontrol->private_value;
 296         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 297         int mask, ret;
 298
 299         /* Can't enable both ADC and DAC paths simultaneously */
 300         if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
 301                 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
 302                         WM8994_AIF1ADC1R_DRC_ENA_MASK;
 303         else
 304                 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
 305
 306         ret = snd_soc_read(codec, mc->reg);
 307         if (ret < 0)
 308                 return ret;
 309         if (ret & mask)
 310                 return -EINVAL;
 311
 312         return snd_soc_put_volsw(kcontrol, ucontrol);
 313 }
 314
 315 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
 316 {
 317         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 318         struct wm8994_pdata *pdata = wm8994->pdata;
 319         int base = wm8994_drc_base[drc];
 320         int cfg = wm8994->drc_cfg[drc];
 321         int save, i;
 322
 323         /* Save any enables; the configuration should clear them. */
 324         save = snd_soc_read(codec, base);
 325         save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
 326                 WM8994_AIF1ADC1R_DRC_ENA;
 327
 328         for (i = 0; i < WM8994_DRC_REGS; i++)
 329                 snd_soc_update_bits(codec, base + i, 0xffff,
 330                                     pdata->drc_cfgs[cfg].regs[i]);
 331
 332         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
 333                              WM8994_AIF1ADC1L_DRC_ENA |
 334                              WM8994_AIF1ADC1R_DRC_ENA, save);
 335 }
 336
 337 /* Icky as hell but saves code duplication */
 338 static int wm8994_get_drc(const char *name)
 339 {
 340         if (strcmp(name, "AIF1DRC1 Mode") == 0)
 341                 return 0;
 342         if (strcmp(name, "AIF1DRC2 Mode") == 0)
 343                 return 1;
 344         if (strcmp(name, "AIF2DRC Mode") == 0)
 345                 return 2;
 346         return -EINVAL;
 347 }
 348
 349 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
 350                                struct snd_ctl_elem_value *ucontrol)
 351 {
 352         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 353         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 354         struct wm8994_pdata *pdata = wm8994->pdata;
 355         int drc = wm8994_get_drc(kcontrol->id.name);
 356         int value = ucontrol->value.integer.value[0];
 357
 358         if (drc < 0)
 359                 return drc;
 360
 361         if (value >= pdata->num_drc_cfgs)
 362                 return -EINVAL;
 363
 364         wm8994->drc_cfg[drc] = value;
 365
 366         wm8994_set_drc(codec, drc);
 367
 368         return 0;
 369 }
 370
 371 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
 372                                struct snd_ctl_elem_value *ucontrol)
 373 {
 374         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 375         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 376         int drc = wm8994_get_drc(kcontrol->id.name);
 377
 378         ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
 379
 380         return 0;
 381 }
 382
 383 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
 384 {
 385         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 386         struct wm8994_pdata *pdata = wm8994->pdata;
 387         int base = wm8994_retune_mobile_base[block];
 388         int iface, best, best_val, save, i, cfg;
 389
 390         if (!pdata || !wm8994->num_retune_mobile_texts)
 391                 return;
 392
 393         switch (block) {
 394         case 0:
 395         case 1:
 396                 iface = 0;
 397                 break;
 398         case 2:
 399                 iface = 1;
 400                 break;
 401         default:
 402                 return;
 403         }
 404
 405         /* Find the version of the currently selected configuration
 406          * with the nearest sample rate. */
 407         cfg = wm8994->retune_mobile_cfg[block];
 408         best = 0;
 409         best_val = INT_MAX;
 410         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
 411                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
 412                            wm8994->retune_mobile_texts[cfg]) == 0 &&
 413                     abs(pdata->retune_mobile_cfgs[i].rate
 414                         - wm8994->dac_rates[iface]) < best_val) {
 415                         best = i;
 416                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
 417                                        - wm8994->dac_rates[iface]);
 418                 }
 419         }
 420
 421         dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
 422                 block,
 423                 pdata->retune_mobile_cfgs[best].name,
 424                 pdata->retune_mobile_cfgs[best].rate,
 425                 wm8994->dac_rates[iface]);
 426
 427         /* The EQ will be disabled while reconfiguring it, remember the
 428          * current configuration.
 429          */
 430         save = snd_soc_read(codec, base);
 431         save &= WM8994_AIF1DAC1_EQ_ENA;
 432
 433         for (i = 0; i < WM8994_EQ_REGS; i++)
 434                 snd_soc_update_bits(codec, base + i, 0xffff,
 435                                 pdata->retune_mobile_cfgs[best].regs[i]);
 436
 437         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
 438 }
 439
 440 /* Icky as hell but saves code duplication */
 441 static int wm8994_get_retune_mobile_block(const char *name)
 442 {
 443         if (strcmp(name, "AIF1.1 EQ Mode") == 0)
 444                 return 0;
 445         if (strcmp(name, "AIF1.2 EQ Mode") == 0)
 446                 return 1;
 447         if (strcmp(name, "AIF2 EQ Mode") == 0)
 448                 return 2;
 449         return -EINVAL;
 450 }
 451
 452 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 453                                          struct snd_ctl_elem_value *ucontrol)
 454 {
 455         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 456         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 457         struct wm8994_pdata *pdata = wm8994->pdata;
 458         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 459         int value = ucontrol->value.integer.value[0];
 460
 461         if (block < 0)
 462                 return block;
 463
 464         if (value >= pdata->num_retune_mobile_cfgs)
 465                 return -EINVAL;
 466
 467         wm8994->retune_mobile_cfg[block] = value;
 468
 469         wm8994_set_retune_mobile(codec, block);
 470
 471         return 0;
 472 }
 473
 474 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 475                                          struct snd_ctl_elem_value *ucontrol)
 476 {
 477         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 478         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 479         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 480
 481         ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
 482
 483         return 0;
 484 }
 485
 486 static const char *aif_chan_src_text[] = {
 487         "Left", "Right"
 488 };
 489
 490 static const struct soc_enum aif1adcl_src =
 491         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
 492
 493 static const struct soc_enum aif1adcr_src =
 494         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
 495
 496 static const struct soc_enum aif2adcl_src =
 497         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
 498
 499 static const struct soc_enum aif2adcr_src =
 500         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
 501
 502 static const struct soc_enum aif1dacl_src =
 503         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
 504
 505 static const struct soc_enum aif1dacr_src =
 506         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
 507
 508 static const struct soc_enum aif2dacl_src =
 509         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
 510
 511 static const struct soc_enum aif2dacr_src =
 512         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
 513
 514 static const char *osr_text[] = {
 515         "Low Power", "High Performance",
 516 };
 517
 518 static const struct soc_enum dac_osr =
 519         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
 520
 521 static const struct soc_enum adc_osr =
 522         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
 523
 524 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
 525 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
 526                  WM8994_AIF1_ADC1_RIGHT_VOLUME,
 527                  1, 119, 0, digital_tlv),
 528 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
 529                  WM8994_AIF1_ADC2_RIGHT_VOLUME,
 530                  1, 119, 0, digital_tlv),
 531 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
 532                  WM8994_AIF2_ADC_RIGHT_VOLUME,
 533                  1, 119, 0, digital_tlv),
 534
 535 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
 536 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
 537 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
 538 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
 539
 540 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
 541 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
 542 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
 543 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
 544
 545 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
 546                  WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 547 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
 548                  WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 549 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
 550                  WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 551
 552 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
 553 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
 554
 555 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
 556 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
 557 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
 558
 559 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
 560 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
 561 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
 562
 563 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
 564 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
 565 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
 566
 567 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
 568 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
 569 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
 570
 571 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 572                5, 12, 0, st_tlv),
 573 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 574                0, 12, 0, st_tlv),
 575 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 576                5, 12, 0, st_tlv),
 577 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 578                0, 12, 0, st_tlv),
 579 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
 580 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
 581
 582 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
 583 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
 584
 585 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
 586 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
 587
 588 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
 589 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
 590
 591 SOC_ENUM("ADC OSR", adc_osr),
 592 SOC_ENUM("DAC OSR", dac_osr),
 593
 594 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
 595                  WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 596 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
 597              WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
 598
 599 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
 600                  WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 601 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
 602              WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
 603
 604 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
 605                6, 1, 1, wm_hubs_spkmix_tlv),
 606 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
 607                2, 1, 1, wm_hubs_spkmix_tlv),
 608
 609 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
 610                6, 1, 1, wm_hubs_spkmix_tlv),
 611 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
 612                2, 1, 1, wm_hubs_spkmix_tlv),
 613
 614 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
 615                10, 15, 0, wm8994_3d_tlv),
 616 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
 617            8, 1, 0),
 618 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
 619                10, 15, 0, wm8994_3d_tlv),
 620 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
 621            8, 1, 0),
 622 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
 623                10, 15, 0, wm8994_3d_tlv),
 624 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
 625            8, 1, 0),
 626 };
 627
 628 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
 629 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
 630                eq_tlv),
 631 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
 632                eq_tlv),
 633 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
 634                eq_tlv),
 635 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
 636                eq_tlv),
 637 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
 638                eq_tlv),
 639
 640 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
 641                eq_tlv),
 642 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
 643                eq_tlv),
 644 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
 645                eq_tlv),
 646 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
 647                eq_tlv),
 648 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
 649                eq_tlv),
 650
 651 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
 652                eq_tlv),
 653 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
 654                eq_tlv),
 655 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
 656                eq_tlv),
 657 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
 658                eq_tlv),
 659 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
 660                eq_tlv),
 661 };
 662
 663 static const char *wm8958_ng_text[] = {
 664         "30ms", "125ms", "250ms", "500ms",
 665 };
 666
 667 static const struct soc_enum wm8958_aif1dac1_ng_hold =
 668         SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
 669                         WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
 670
 671 static const struct soc_enum wm8958_aif1dac2_ng_hold =
 672         SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
 673                         WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
 674
 675 static const struct soc_enum wm8958_aif2dac_ng_hold =
 676         SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
 677                         WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
 678
 679 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
 680 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
 681
 682 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
 683            WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
 684 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
 685 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
 686                WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
 687                7, 1, ng_tlv),
 688
 689 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
 690            WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
 691 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
 692 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
 693                WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
 694                7, 1, ng_tlv),
 695
 696 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
 697            WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
 698 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
 699 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
 700                WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
 701                7, 1, ng_tlv),
 702 };
 703
 704 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
 705 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
 706                mixin_boost_tlv),
 707 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
 708                mixin_boost_tlv),
 709 };
 710
 711 static int clk_sys_event(struct snd_soc_dapm_widget *w,
 712                          struct snd_kcontrol *kcontrol, int event)
 713 {
 714         struct snd_soc_codec *codec = w->codec;
 715
 716         switch (event) {
 717         case SND_SOC_DAPM_PRE_PMU:
 718                 return configure_clock(codec);
 719
 720         case SND_SOC_DAPM_POST_PMD:
 721                 configure_clock(codec);
 722                 break;
 723         }
 724
 725         return 0;
 726 }
 727
 728 static void vmid_reference(struct snd_soc_codec *codec)
 729 {
 730         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 731
 732         pm_runtime_get_sync(codec->dev);
 733
 734         wm8994->vmid_refcount++;
 735
 736         dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
 737                 wm8994->vmid_refcount);
 738
 739         if (wm8994->vmid_refcount == 1) {
 740                 /* Startup bias, VMID ramp & buffer */
 741                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 742                                     WM8994_STARTUP_BIAS_ENA |
 743                                     WM8994_VMID_BUF_ENA |
 744                                     WM8994_VMID_RAMP_MASK,
 745                                     WM8994_STARTUP_BIAS_ENA |
 746                                     WM8994_VMID_BUF_ENA |
 747                                     (0x3 << WM8994_VMID_RAMP_SHIFT));
 748
 749                 /* Main bias enable, VMID=2x40k */
 750                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 751                                     WM8994_BIAS_ENA |
 752                                     WM8994_VMID_SEL_MASK,
 753                                     WM8994_BIAS_ENA | 0x2);
 754
 755                 msleep(20);
 756         }
 757 }
 758
 759 static void vmid_dereference(struct snd_soc_codec *codec)
 760 {
 761         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 762
 763         wm8994->vmid_refcount--;
 764
 765         dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
 766                 wm8994->vmid_refcount);
 767
 768         if (wm8994->vmid_refcount == 0) {
 769                 /* Switch over to startup biases */
 770                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 771                                     WM8994_BIAS_SRC |
 772                                     WM8994_STARTUP_BIAS_ENA |
 773                                     WM8994_VMID_BUF_ENA |
 774                                     WM8994_VMID_RAMP_MASK,
 775                                     WM8994_BIAS_SRC |
 776                                     WM8994_STARTUP_BIAS_ENA |
 777                                     WM8994_VMID_BUF_ENA |
 778                                     (1 << WM8994_VMID_RAMP_SHIFT));
 779
 780                 /* Disable main biases */
 781                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 782                                     WM8994_BIAS_ENA |
 783                                     WM8994_VMID_SEL_MASK, 0);
 784
 785                 /* Discharge line */
 786                 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
 787                                     WM8994_LINEOUT1_DISCH |
 788                                     WM8994_LINEOUT2_DISCH,
 789                                     WM8994_LINEOUT1_DISCH |
 790                                     WM8994_LINEOUT2_DISCH);
 791
 792                 msleep(5);
 793
 794                 /* Switch off startup biases */
 795                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 796                                     WM8994_BIAS_SRC |
 797                                     WM8994_STARTUP_BIAS_ENA |
 798                                     WM8994_VMID_BUF_ENA |
 799                                     WM8994_VMID_RAMP_MASK, 0);
 800         }
 801
 802         pm_runtime_put(codec->dev);
 803 }
 804
 805 static int vmid_event(struct snd_soc_dapm_widget *w,
 806                       struct snd_kcontrol *kcontrol, int event)
 807 {
 808         struct snd_soc_codec *codec = w->codec;
 809
 810         switch (event) {
 811         case SND_SOC_DAPM_PRE_PMU:
 812                 vmid_reference(codec);
 813                 break;
 814
 815         case SND_SOC_DAPM_POST_PMD:
 816                 vmid_dereference(codec);
 817                 break;
 818         }
 819
 820         return 0;
 821 }
 822
 823 static void wm8994_update_class_w(struct snd_soc_codec *codec)
 824 {
 825         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 826         int enable = 1;
 827         int source = 0;  /* GCC flow analysis can't track enable */
 828         int reg, reg_r;
 829
 830         /* Only support direct DAC->headphone paths */
 831         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
 832         if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
 833                 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
 834                 enable = 0;
 835         }
 836
 837         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
 838         if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
 839                 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
 840                 enable = 0;
 841         }
 842
 843         /* We also need the same setting for L/R and only one path */
 844         reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
 845         switch (reg) {
 846         case WM8994_AIF2DACL_TO_DAC1L:
 847                 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
 848                 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 849                 break;
 850         case WM8994_AIF1DAC2L_TO_DAC1L:
 851                 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
 852                 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 853                 break;
 854         case WM8994_AIF1DAC1L_TO_DAC1L:
 855                 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
 856                 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 857                 break;
 858         default:
 859                 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
 860                 enable = 0;
 861                 break;
 862         }
 863
 864         reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
 865         if (reg_r != reg) {
 866                 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
 867                 enable = 0;
 868         }
 869
 870         if (enable) {
 871                 dev_dbg(codec->dev, "Class W enabled\n");
 872                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 873                                     WM8994_CP_DYN_PWR |
 874                                     WM8994_CP_DYN_SRC_SEL_MASK,
 875                                     source | WM8994_CP_DYN_PWR);
 876                 wm8994->hubs.class_w = true;
 877
 878         } else {
 879                 dev_dbg(codec->dev, "Class W disabled\n");
 880                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 881                                     WM8994_CP_DYN_PWR, 0);
 882                 wm8994->hubs.class_w = false;
 883         }
 884 }
 885
 886 static int late_enable_ev(struct snd_soc_dapm_widget *w,
 887                           struct snd_kcontrol *kcontrol, int event)
 888 {
 889         struct snd_soc_codec *codec = w->codec;
 890         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 891
 892         switch (event) {
 893         case SND_SOC_DAPM_PRE_PMU:
 894                 if (wm8994->aif1clk_enable) {
 895                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
 896                                             WM8994_AIF1CLK_ENA_MASK,
 897                                             WM8994_AIF1CLK_ENA);
 898                         wm8994->aif1clk_enable = 0;
 899                 }
 900                 if (wm8994->aif2clk_enable) {
 901                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
 902                                             WM8994_AIF2CLK_ENA_MASK,
 903                                             WM8994_AIF2CLK_ENA);
 904                         wm8994->aif2clk_enable = 0;
 905                 }
 906                 break;
 907         }
 908
 909         /* We may also have postponed startup of DSP, handle that. */
 910         wm8958_aif_ev(w, kcontrol, event);
 911
 912         return 0;
 913 }
 914
 915 static int late_disable_ev(struct snd_soc_dapm_widget *w,
 916                            struct snd_kcontrol *kcontrol, int event)
 917 {
 918         struct snd_soc_codec *codec = w->codec;
 919         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 920
 921         switch (event) {
 922         case SND_SOC_DAPM_POST_PMD:
 923                 if (wm8994->aif1clk_disable) {
 924                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
 925                                             WM8994_AIF1CLK_ENA_MASK, 0);
 926                         wm8994->aif1clk_disable = 0;
 927                 }
 928                 if (wm8994->aif2clk_disable) {
 929                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
 930                                             WM8994_AIF2CLK_ENA_MASK, 0);
 931                         wm8994->aif2clk_disable = 0;
 932                 }
 933                 break;
 934         }
 935
 936         return 0;
 937 }
 938
 939 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
 940                       struct snd_kcontrol *kcontrol, int event)
 941 {
 942         struct snd_soc_codec *codec = w->codec;
 943         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 944
 945         switch (event) {
 946         case SND_SOC_DAPM_PRE_PMU:
 947                 wm8994->aif1clk_enable = 1;
 948                 break;
 949         case SND_SOC_DAPM_POST_PMD:
 950                 wm8994->aif1clk_disable = 1;
 951                 break;
 952         }
 953
 954         return 0;
 955 }
 956
 957 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
 958                       struct snd_kcontrol *kcontrol, int event)
 959 {
 960         struct snd_soc_codec *codec = w->codec;
 961         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 962
 963         switch (event) {
 964         case SND_SOC_DAPM_PRE_PMU:
 965                 wm8994->aif2clk_enable = 1;
 966                 break;
 967         case SND_SOC_DAPM_POST_PMD:
 968                 wm8994->aif2clk_disable = 1;
 969                 break;
 970         }
 971
 972         return 0;
 973 }
 974
 975 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
 976                       struct snd_kcontrol *kcontrol, int event)
 977 {
 978         late_enable_ev(w, kcontrol, event);
 979         return 0;
 980 }
 981
 982 static int micbias_ev(struct snd_soc_dapm_widget *w,
 983                       struct snd_kcontrol *kcontrol, int event)
 984 {
 985         late_enable_ev(w, kcontrol, event);
 986         return 0;
 987 }
 988
 989 static int dac_ev(struct snd_soc_dapm_widget *w,
 990                   struct snd_kcontrol *kcontrol, int event)
 991 {
 992         struct snd_soc_codec *codec = w->codec;
 993         unsigned int mask = 1 << w->shift;
 994
 995         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
 996                             mask, mask);
 997         return 0;
 998 }
 999
1000 static const char *hp_mux_text[] = {
1001         "Mixer",
1002         "DAC",
1003 };
1004
1005 #define WM8994_HP_ENUM(xname, xenum) \
1006 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1007         .info = snd_soc_info_enum_double, \
1008         .get = snd_soc_dapm_get_enum_double, \
1009         .put = wm8994_put_hp_enum, \
1010         .private_value = (unsigned long)&xenum }
1011
1012 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1013                               struct snd_ctl_elem_value *ucontrol)
1014 {
1015         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1016         struct snd_soc_dapm_widget *w = wlist->widgets[0];
1017         struct snd_soc_codec *codec = w->codec;
1018         int ret;
1019
1020         ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1021
1022         wm8994_update_class_w(codec);
1023
1024         return ret;
1025 }
1026
1027 static const struct soc_enum hpl_enum =
1028         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1029
1030 static const struct snd_kcontrol_new hpl_mux =
1031         WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1032
1033 static const struct soc_enum hpr_enum =
1034         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1035
1036 static const struct snd_kcontrol_new hpr_mux =
1037         WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1038
1039 static const char *adc_mux_text[] = {
1040         "ADC",
1041         "DMIC",
1042 };
1043
1044 static const struct soc_enum adc_enum =
1045         SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1046
1047 static const struct snd_kcontrol_new adcl_mux =
1048         SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1049
1050 static const struct snd_kcontrol_new adcr_mux =
1051         SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1052
1053 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1054 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1055 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1056 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1057 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1058 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1059 };
1060
1061 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1062 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1063 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1064 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1065 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1066 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1067 };
1068
1069 /* Debugging; dump chip status after DAPM transitions */
1070 static int post_ev(struct snd_soc_dapm_widget *w,
1071             struct snd_kcontrol *kcontrol, int event)
1072 {
1073         struct snd_soc_codec *codec = w->codec;
1074         dev_dbg(codec->dev, "SRC status: %x\n",
1075                 snd_soc_read(codec,
1076                              WM8994_RATE_STATUS));
1077         return 0;
1078 }
1079
1080 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1081 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1082                 1, 1, 0),
1083 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1084                 0, 1, 0),
1085 };
1086
1087 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1088 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1089                 1, 1, 0),
1090 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1091                 0, 1, 0),
1092 };
1093
1094 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1095 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1096                 1, 1, 0),
1097 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1098                 0, 1, 0),
1099 };
1100
1101 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1102 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1103                 1, 1, 0),
1104 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1105                 0, 1, 0),
1106 };
1107
1108 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1109 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1110                 5, 1, 0),
1111 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1112                 4, 1, 0),
1113 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1114                 2, 1, 0),
1115 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1116                 1, 1, 0),
1117 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1118                 0, 1, 0),
1119 };
1120
1121 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1122 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1123                 5, 1, 0),
1124 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1125                 4, 1, 0),
1126 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1127                 2, 1, 0),
1128 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1129                 1, 1, 0),
1130 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1131                 0, 1, 0),
1132 };
1133
1134 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1135 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1136         .info = snd_soc_info_volsw, \
1137         .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1138         .private_value =  SOC_SINGLE_VALUE(reg, shift, max, invert) }
1139
1140 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1141                               struct snd_ctl_elem_value *ucontrol)
1142 {
1143         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1144         struct snd_soc_dapm_widget *w = wlist->widgets[0];
1145         struct snd_soc_codec *codec = w->codec;
1146         int ret;
1147
1148         ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1149
1150         wm8994_update_class_w(codec);
1151
1152         return ret;
1153 }
1154
1155 static const struct snd_kcontrol_new dac1l_mix[] = {
1156 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1157                       5, 1, 0),
1158 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1159                       4, 1, 0),
1160 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1161                       2, 1, 0),
1162 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1163                       1, 1, 0),
1164 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1165                       0, 1, 0),
1166 };
1167
1168 static const struct snd_kcontrol_new dac1r_mix[] = {
1169 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1170                       5, 1, 0),
1171 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1172                       4, 1, 0),
1173 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1174                       2, 1, 0),
1175 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1176                       1, 1, 0),
1177 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1178                       0, 1, 0),
1179 };
1180
1181 static const char *sidetone_text[] = {
1182         "ADC/DMIC1", "DMIC2",
1183 };
1184
1185 static const struct soc_enum sidetone1_enum =
1186         SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1187
1188 static const struct snd_kcontrol_new sidetone1_mux =
1189         SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1190
1191 static const struct soc_enum sidetone2_enum =
1192         SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1193
1194 static const struct snd_kcontrol_new sidetone2_mux =
1195         SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1196
1197 static const char *aif1dac_text[] = {
1198         "AIF1DACDAT", "AIF3DACDAT",
1199 };
1200
1201 static const struct soc_enum aif1dac_enum =
1202         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1203
1204 static const struct snd_kcontrol_new aif1dac_mux =
1205         SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1206
1207 static const char *aif2dac_text[] = {
1208         "AIF2DACDAT", "AIF3DACDAT",
1209 };
1210
1211 static const struct soc_enum aif2dac_enum =
1212         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1213
1214 static const struct snd_kcontrol_new aif2dac_mux =
1215         SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1216
1217 static const char *aif2adc_text[] = {
1218         "AIF2ADCDAT", "AIF3DACDAT",
1219 };
1220
1221 static const struct soc_enum aif2adc_enum =
1222         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1223
1224 static const struct snd_kcontrol_new aif2adc_mux =
1225         SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1226
1227 static const char *aif3adc_text[] = {
1228         "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1229 };
1230
1231 static const struct soc_enum wm8994_aif3adc_enum =
1232         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1233
1234 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1235         SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1236
1237 static const struct soc_enum wm8958_aif3adc_enum =
1238         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1239
1240 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1241         SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1242
1243 static const char *mono_pcm_out_text[] = {
1244         "None", "AIF2ADCL", "AIF2ADCR",
1245 };
1246
1247 static const struct soc_enum mono_pcm_out_enum =
1248         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1249
1250 static const struct snd_kcontrol_new mono_pcm_out_mux =
1251         SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1252
1253 static const char *aif2dac_src_text[] = {
1254         "AIF2", "AIF3",
1255 };
1256
1257 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1258 static const struct soc_enum aif2dacl_src_enum =
1259         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1260
1261 static const struct snd_kcontrol_new aif2dacl_src_mux =
1262         SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1263
1264 static const struct soc_enum aif2dacr_src_enum =
1265         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1266
1267 static const struct snd_kcontrol_new aif2dacr_src_mux =
1268         SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1269
1270 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1271 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1272         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1273 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1274         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1275
1276 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1277         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1278 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1279         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1280 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1281         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1282 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1283         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1284 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1285         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1286
1287 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1288                      left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1289                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1290 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1291                      right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1292                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1293 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1294                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1295 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1296                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1297
1298 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1299 };
1300
1301 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1302 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1303 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1304 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1305 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1306                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1307 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1308                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1309 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1310 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1311 };
1312
1313 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1314 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1315         dac_ev, SND_SOC_DAPM_PRE_PMU),
1316 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1317         dac_ev, SND_SOC_DAPM_PRE_PMU),
1318 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1319         dac_ev, SND_SOC_DAPM_PRE_PMU),
1320 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1321         dac_ev, SND_SOC_DAPM_PRE_PMU),
1322 };
1323
1324 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1325 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1326 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1327 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1328 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1329 };
1330
1331 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1332 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1333                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1334 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1335                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1336 };
1337
1338 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1339 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1340 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1341 };
1342
1343 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1344 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1345 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1346 SND_SOC_DAPM_INPUT("Clock"),
1347
1348 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1349                       SND_SOC_DAPM_PRE_PMU),
1350 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1351                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1352
1353 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1354                     SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1355
1356 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1357 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1358 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1359
1360 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1361                      0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1362 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1363                      0, WM8994_POWER_MANAGEMENT_4, 8, 0),
1364 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1365                       WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
1366                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1367 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1368                       WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1369                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1370
1371 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1372                      0, WM8994_POWER_MANAGEMENT_4, 11, 0),
1373 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1374                      0, WM8994_POWER_MANAGEMENT_4, 10, 0),
1375 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1376                       WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
1377                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1378 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1379                       WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1380                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1381
1382 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1383                    aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1384 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1385                    aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1386
1387 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1388                    aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1389 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1390                    aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1391
1392 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1393                    aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1394 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1395                    aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1396
1397 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1398 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1399
1400 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1401                    dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1402 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1403                    dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1404
1405 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1406                      WM8994_POWER_MANAGEMENT_4, 13, 0),
1407 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1408                      WM8994_POWER_MANAGEMENT_4, 12, 0),
1409 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1410                       WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1411                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1412 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1413                       WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1414                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1415
1416 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1417 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1418 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1419 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1420
1421 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1422 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1423 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1424
1425 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1426 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1427
1428 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1429
1430 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1431 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1432 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1433 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1434
1435 /* Power is done with the muxes since the ADC power also controls the
1436  * downsampling chain, the chip will automatically manage the analogue
1437  * specific portions.
1438  */
1439 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1440 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1441
1442 SND_SOC_DAPM_POST("Debug log", post_ev),
1443 };
1444
1445 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1446 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1447 };
1448
1449 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1450 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1451 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1452 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1453 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1454 };
1455
1456 static const struct snd_soc_dapm_route intercon[] = {
1457         { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1458         { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1459
1460         { "DSP1CLK", NULL, "CLK_SYS" },
1461         { "DSP2CLK", NULL, "CLK_SYS" },
1462         { "DSPINTCLK", NULL, "CLK_SYS" },
1463
1464         { "AIF1ADC1L", NULL, "AIF1CLK" },
1465         { "AIF1ADC1L", NULL, "DSP1CLK" },
1466         { "AIF1ADC1R", NULL, "AIF1CLK" },
1467         { "AIF1ADC1R", NULL, "DSP1CLK" },
1468         { "AIF1ADC1R", NULL, "DSPINTCLK" },
1469
1470         { "AIF1DAC1L", NULL, "AIF1CLK" },
1471         { "AIF1DAC1L", NULL, "DSP1CLK" },
1472         { "AIF1DAC1R", NULL, "AIF1CLK" },
1473         { "AIF1DAC1R", NULL, "DSP1CLK" },
1474         { "AIF1DAC1R", NULL, "DSPINTCLK" },
1475
1476         { "AIF1ADC2L", NULL, "AIF1CLK" },
1477         { "AIF1ADC2L", NULL, "DSP1CLK" },
1478         { "AIF1ADC2R", NULL, "AIF1CLK" },
1479         { "AIF1ADC2R", NULL, "DSP1CLK" },
1480         { "AIF1ADC2R", NULL, "DSPINTCLK" },
1481
1482         { "AIF1DAC2L", NULL, "AIF1CLK" },
1483         { "AIF1DAC2L", NULL, "DSP1CLK" },
1484         { "AIF1DAC2R", NULL, "AIF1CLK" },
1485         { "AIF1DAC2R", NULL, "DSP1CLK" },
1486         { "AIF1DAC2R", NULL, "DSPINTCLK" },
1487
1488         { "AIF2ADCL", NULL, "AIF2CLK" },
1489         { "AIF2ADCL", NULL, "DSP2CLK" },
1490         { "AIF2ADCR", NULL, "AIF2CLK" },
1491         { "AIF2ADCR", NULL, "DSP2CLK" },
1492         { "AIF2ADCR", NULL, "DSPINTCLK" },
1493
1494         { "AIF2DACL", NULL, "AIF2CLK" },
1495         { "AIF2DACL", NULL, "DSP2CLK" },
1496         { "AIF2DACR", NULL, "AIF2CLK" },
1497         { "AIF2DACR", NULL, "DSP2CLK" },
1498         { "AIF2DACR", NULL, "DSPINTCLK" },
1499
1500         { "DMIC1L", NULL, "DMIC1DAT" },
1501         { "DMIC1L", NULL, "CLK_SYS" },
1502         { "DMIC1R", NULL, "DMIC1DAT" },
1503         { "DMIC1R", NULL, "CLK_SYS" },
1504         { "DMIC2L", NULL, "DMIC2DAT" },
1505         { "DMIC2L", NULL, "CLK_SYS" },
1506         { "DMIC2R", NULL, "DMIC2DAT" },
1507         { "DMIC2R", NULL, "CLK_SYS" },
1508
1509         { "ADCL", NULL, "AIF1CLK" },
1510         { "ADCL", NULL, "DSP1CLK" },
1511         { "ADCL", NULL, "DSPINTCLK" },
1512
1513         { "ADCR", NULL, "AIF1CLK" },
1514         { "ADCR", NULL, "DSP1CLK" },
1515         { "ADCR", NULL, "DSPINTCLK" },
1516
1517         { "ADCL Mux", "ADC", "ADCL" },
1518         { "ADCL Mux", "DMIC", "DMIC1L" },
1519         { "ADCR Mux", "ADC", "ADCR" },
1520         { "ADCR Mux", "DMIC", "DMIC1R" },
1521
1522         { "DAC1L", NULL, "AIF1CLK" },
1523         { "DAC1L", NULL, "DSP1CLK" },
1524         { "DAC1L", NULL, "DSPINTCLK" },
1525
1526         { "DAC1R", NULL, "AIF1CLK" },
1527         { "DAC1R", NULL, "DSP1CLK" },
1528         { "DAC1R", NULL, "DSPINTCLK" },
1529
1530         { "DAC2L", NULL, "AIF2CLK" },
1531         { "DAC2L", NULL, "DSP2CLK" },
1532         { "DAC2L", NULL, "DSPINTCLK" },
1533
1534         { "DAC2R", NULL, "AIF2DACR" },
1535         { "DAC2R", NULL, "AIF2CLK" },
1536         { "DAC2R", NULL, "DSP2CLK" },
1537         { "DAC2R", NULL, "DSPINTCLK" },
1538
1539         { "TOCLK", NULL, "CLK_SYS" },
1540
1541         /* AIF1 outputs */
1542         { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1543         { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1544         { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1545
1546         { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1547         { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1548         { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1549
1550         { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1551         { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1552         { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1553
1554         { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1555         { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1556         { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1557
1558         /* Pin level routing for AIF3 */
1559         { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1560         { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1561         { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1562         { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1563
1564         { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1565         { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1566         { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1567         { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1568         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1569         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1570         { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1571
1572         /* DAC1 inputs */
1573         { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1574         { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1575         { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1576         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1577         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1578
1579         { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1580         { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1581         { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1582         { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1583         { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1584
1585         /* DAC2/AIF2 outputs  */
1586         { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1587         { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1588         { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1589         { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1590         { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1591         { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1592
1593         { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1594         { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1595         { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1596         { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1597         { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1598         { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1599
1600         { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1601         { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1602         { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1603         { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1604
1605         { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1606
1607         /* AIF3 output */
1608         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1609         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1610         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1611         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1612         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1613         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1614         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1615         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1616
1617         /* Sidetone */
1618         { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1619         { "Left Sidetone", "DMIC2", "DMIC2L" },
1620         { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1621         { "Right Sidetone", "DMIC2", "DMIC2R" },
1622
1623         /* Output stages */
1624         { "Left Output Mixer", "DAC Switch", "DAC1L" },
1625         { "Right Output Mixer", "DAC Switch", "DAC1R" },
1626
1627         { "SPKL", "DAC1 Switch", "DAC1L" },
1628         { "SPKL", "DAC2 Switch", "DAC2L" },
1629
1630         { "SPKR", "DAC1 Switch", "DAC1R" },
1631         { "SPKR", "DAC2 Switch", "DAC2R" },
1632
1633         { "Left Headphone Mux", "DAC", "DAC1L" },
1634         { "Right Headphone Mux", "DAC", "DAC1R" },
1635 };
1636
1637 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1638         { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1639         { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1640         { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1641         { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1642         { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1643         { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1644         { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1645         { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1646 };
1647
1648 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1649         { "DAC1L", NULL, "DAC1L Mixer" },
1650         { "DAC1R", NULL, "DAC1R Mixer" },
1651         { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1652         { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1653 };
1654
1655 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1656         { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1657         { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1658         { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1659         { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1660         { "MICBIAS1", NULL, "CLK_SYS" },
1661         { "MICBIAS1", NULL, "MICBIAS Supply" },
1662         { "MICBIAS2", NULL, "CLK_SYS" },
1663         { "MICBIAS2", NULL, "MICBIAS Supply" },
1664 };
1665
1666 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1667         { "AIF2DACL", NULL, "AIF2DAC Mux" },
1668         { "AIF2DACR", NULL, "AIF2DAC Mux" },
1669         { "MICBIAS1", NULL, "VMID" },
1670         { "MICBIAS2", NULL, "VMID" },
1671 };
1672
1673 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1674         { "AIF2DACL", NULL, "AIF2DACL Mux" },
1675         { "AIF2DACR", NULL, "AIF2DACR Mux" },
1676
1677         { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1678         { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1679         { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1680         { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1681
1682         { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1683         { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1684
1685         { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1686 };
1687
1688 /* The size in bits of the FLL divide multiplied by 10
1689  * to allow rounding later */
1690 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1691
1692 struct fll_div {
1693         u16 outdiv;
1694         u16 n;
1695         u16 k;
1696         u16 clk_ref_div;
1697         u16 fll_fratio;
1698 };
1699
1700 static int wm8994_get_fll_config(struct fll_div *fll,
1701                                  int freq_in, int freq_out)
1702 {
1703         u64 Kpart;
1704         unsigned int K, Ndiv, Nmod;
1705
1706         pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1707
1708         /* Scale the input frequency down to <= 13.5MHz */
1709         fll->clk_ref_div = 0;
1710         while (freq_in > 13500000) {
1711                 fll->clk_ref_div++;
1712                 freq_in /= 2;
1713
1714                 if (fll->clk_ref_div > 3)
1715                         return -EINVAL;
1716         }
1717         pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1718
1719         /* Scale the output to give 90MHz<=Fvco<=100MHz */
1720         fll->outdiv = 3;
1721         while (freq_out * (fll->outdiv + 1) < 90000000) {
1722                 fll->outdiv++;
1723                 if (fll->outdiv > 63)
1724                         return -EINVAL;
1725         }
1726         freq_out *= fll->outdiv + 1;
1727         pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1728
1729         if (freq_in > 1000000) {
1730                 fll->fll_fratio = 0;
1731         } else if (freq_in > 256000) {
1732                 fll->fll_fratio = 1;
1733                 freq_in *= 2;
1734         } else if (freq_in > 128000) {
1735                 fll->fll_fratio = 2;
1736                 freq_in *= 4;
1737         } else if (freq_in > 64000) {
1738                 fll->fll_fratio = 3;
1739                 freq_in *= 8;
1740         } else {
1741                 fll->fll_fratio = 4;
1742                 freq_in *= 16;
1743         }
1744         pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1745
1746         /* Now, calculate N.K */
1747         Ndiv = freq_out / freq_in;
1748
1749         fll->n = Ndiv;
1750         Nmod = freq_out % freq_in;
1751         pr_debug("Nmod=%d\n", Nmod);
1752
1753         /* Calculate fractional part - scale up so we can round. */
1754         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1755
1756         do_div(Kpart, freq_in);
1757
1758         K = Kpart & 0xFFFFFFFF;
1759
1760         if ((K % 10) >= 5)
1761                 K += 5;
1762
1763         /* Move down to proper range now rounding is done */
1764         fll->k = K / 10;
1765
1766         pr_debug("N=%x K=%x\n", fll->n, fll->k);
1767
1768         return 0;
1769 }
1770
1771 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1772                           unsigned int freq_in, unsigned int freq_out)
1773 {
1774         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1775         struct wm8994 *control = codec->control_data;
1776         int reg_offset, ret;
1777         struct fll_div fll;
1778         u16 reg, aif1, aif2;
1779         unsigned long timeout;
1780         bool was_enabled;
1781
1782         aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1783                 & WM8994_AIF1CLK_ENA;
1784
1785         aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1786                 & WM8994_AIF2CLK_ENA;
1787
1788         switch (id) {
1789         case WM8994_FLL1:
1790                 reg_offset = 0;
1791                 id = 0;
1792                 break;
1793         case WM8994_FLL2:
1794                 reg_offset = 0x20;
1795                 id = 1;
1796                 break;
1797         default:
1798                 return -EINVAL;
1799         }
1800
1801         reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
1802         was_enabled = reg & WM8994_FLL1_ENA;
1803
1804         switch (src) {
1805         case 0:
1806                 /* Allow no source specification when stopping */
1807                 if (freq_out)
1808                         return -EINVAL;
1809                 src = wm8994->fll[id].src;
1810                 break;
1811         case WM8994_FLL_SRC_MCLK1:
1812         case WM8994_FLL_SRC_MCLK2:
1813         case WM8994_FLL_SRC_LRCLK:
1814         case WM8994_FLL_SRC_BCLK:
1815                 break;
1816         default:
1817                 return -EINVAL;
1818         }
1819
1820         /* Are we changing anything? */
1821         if (wm8994->fll[id].src == src &&
1822             wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1823                 return 0;
1824
1825         /* If we're stopping the FLL redo the old config - no
1826          * registers will actually be written but we avoid GCC flow
1827          * analysis bugs spewing warnings.
1828          */
1829         if (freq_out)
1830                 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1831         else
1832                 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1833                                             wm8994->fll[id].out);
1834         if (ret < 0)
1835                 return ret;
1836
1837         /* Gate the AIF clocks while we reclock */
1838         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1839                             WM8994_AIF1CLK_ENA, 0);
1840         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1841                             WM8994_AIF2CLK_ENA, 0);
1842
1843         /* We always need to disable the FLL while reconfiguring */
1844         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1845                             WM8994_FLL1_ENA, 0);
1846
1847         reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1848                 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1849         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1850                             WM8994_FLL1_OUTDIV_MASK |
1851                             WM8994_FLL1_FRATIO_MASK, reg);
1852
1853         snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1854
1855         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1856                             WM8994_FLL1_N_MASK,
1857                                     fll.n << WM8994_FLL1_N_SHIFT);
1858
1859         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
1860                             WM8994_FLL1_REFCLK_DIV_MASK |
1861                             WM8994_FLL1_REFCLK_SRC_MASK,
1862                             (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1863                             (src - 1));
1864
1865         /* Clear any pending completion from a previous failure */
1866         try_wait_for_completion(&wm8994->fll_locked[id]);
1867
1868         /* Enable (with fractional mode if required) */
1869         if (freq_out) {
1870                 /* Enable VMID if we need it */
1871                 if (!was_enabled) {
1872                         switch (control->type) {
1873                         case WM8994:
1874                                 vmid_reference(codec);
1875                                 break;
1876                         case WM8958:
1877                                 if (wm8994->revision < 1)
1878                                         vmid_reference(codec);
1879                                 break;
1880                         default:
1881                                 break;
1882                         }
1883                 }
1884
1885                 if (fll.k)
1886                         reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1887                 else
1888                         reg = WM8994_FLL1_ENA;
1889                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1890                                     WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1891                                     reg);
1892
1893                 if (wm8994->fll_locked_irq) {
1894                         timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
1895                                                               msecs_to_jiffies(10));
1896                         if (timeout == 0)
1897                                 dev_warn(codec->dev,
1898                                          "Timed out waiting for FLL lock\n");
1899                 } else {
1900                         msleep(5);
1901                 }
1902         } else {
1903                 if (was_enabled) {
1904                         switch (control->type) {
1905                         case WM8994:
1906                                 vmid_dereference(codec);
1907                                 break;
1908                         case WM8958:
1909                                 if (wm8994->revision < 1)
1910                                         vmid_dereference(codec);
1911                                 break;
1912                         default:
1913                                 break;
1914                         }
1915                 }
1916         }
1917
1918         wm8994->fll[id].in = freq_in;
1919         wm8994->fll[id].out = freq_out;
1920         wm8994->fll[id].src = src;
1921
1922         /* Enable any gated AIF clocks */
1923         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1924                             WM8994_AIF1CLK_ENA, aif1);
1925         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1926                             WM8994_AIF2CLK_ENA, aif2);
1927
1928         configure_clock(codec);
1929
1930         return 0;
1931 }
1932
1933 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
1934 {
1935         struct completion *completion = data;
1936
1937         complete(completion);
1938
1939         return IRQ_HANDLED;
1940 }
1941
1942 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1943
1944 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1945                           unsigned int freq_in, unsigned int freq_out)
1946 {
1947         return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1948 }
1949
1950 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
1951                 int clk_id, unsigned int freq, int dir)
1952 {
1953         struct snd_soc_codec *codec = dai->codec;
1954         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1955         int i;
1956
1957         switch (dai->id) {
1958         case 1:
1959         case 2:
1960                 break;
1961
1962         default:
1963                 /* AIF3 shares clocking with AIF1/2 */
1964                 return -EINVAL;
1965         }
1966
1967         switch (clk_id) {
1968         case WM8994_SYSCLK_MCLK1:
1969                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
1970                 wm8994->mclk[0] = freq;
1971                 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1972                         dai->id, freq);
1973                 break;
1974
1975         case WM8994_SYSCLK_MCLK2:
1976                 /* TODO: Set GPIO AF */
1977                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
1978                 wm8994->mclk[1] = freq;
1979                 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1980                         dai->id, freq);
1981                 break;
1982
1983         case WM8994_SYSCLK_FLL1:
1984                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
1985                 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
1986                 break;
1987
1988         case WM8994_SYSCLK_FLL2:
1989                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
1990                 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
1991                 break;
1992
1993         case WM8994_SYSCLK_OPCLK:
1994                 /* Special case - a division (times 10) is given and
1995                  * no effect on main clocking.
1996                  */
1997                 if (freq) {
1998                         for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
1999                                 if (opclk_divs[i] == freq)
2000                                         break;
2001                         if (i == ARRAY_SIZE(opclk_divs))
2002                                 return -EINVAL;
2003                         snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2004                                             WM8994_OPCLK_DIV_MASK, i);
2005                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2006                                             WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2007                 } else {
2008                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2009                                             WM8994_OPCLK_ENA, 0);
2010                 }
2011
2012         default:
2013                 return -EINVAL;
2014         }
2015
2016         configure_clock(codec);
2017
2018         return 0;
2019 }
2020
2021 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2022                                  enum snd_soc_bias_level level)
2023 {
2024         struct wm8994 *control = codec->control_data;
2025         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2026
2027         switch (level) {
2028         case SND_SOC_BIAS_ON:
2029                 break;
2030
2031         case SND_SOC_BIAS_PREPARE:
2032                 break;
2033
2034         case SND_SOC_BIAS_STANDBY:
2035                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2036                         pm_runtime_get_sync(codec->dev);
2037
2038                         switch (control->type) {
2039                         case WM8994:
2040                                 if (wm8994->revision < 4) {
2041                                         /* Tweak DC servo and DSP
2042                                          * configuration for improved
2043                                          * performance. */
2044                                         snd_soc_write(codec, 0x102, 0x3);
2045                                         snd_soc_write(codec, 0x56, 0x3);
2046                                         snd_soc_write(codec, 0x817, 0);
2047                                         snd_soc_write(codec, 0x102, 0);
2048                                 }
2049                                 break;
2050
2051                         case WM8958:
2052                                 if (wm8994->revision == 0) {
2053                                         /* Optimise performance for rev A */
2054                                         snd_soc_write(codec, 0x102, 0x3);
2055                                         snd_soc_write(codec, 0xcb, 0x81);
2056                                         snd_soc_write(codec, 0x817, 0);
2057                                         snd_soc_write(codec, 0x102, 0);
2058
2059                                         snd_soc_update_bits(codec,
2060                                                             WM8958_CHARGE_PUMP_2,
2061                                                             WM8958_CP_DISCH,
2062                                                             WM8958_CP_DISCH);
2063                                 }
2064                                 break;
2065
2066                         case WM1811:
2067                                 if (wm8994->revision < 2) {
2068                                         snd_soc_write(codec, 0x102, 0x3);
2069                                         snd_soc_write(codec, 0x5d, 0x7e);
2070                                         snd_soc_write(codec, 0x5e, 0x0);
2071                                         snd_soc_write(codec, 0x102, 0x0);
2072                                 }
2073                                 break;
2074                         }
2075
2076                         /* Discharge LINEOUT1 & 2 */
2077                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2078                                             WM8994_LINEOUT1_DISCH |
2079                                             WM8994_LINEOUT2_DISCH,
2080                                             WM8994_LINEOUT1_DISCH |
2081                                             WM8994_LINEOUT2_DISCH);
2082                 }
2083
2084
2085                 break;
2086
2087         case SND_SOC_BIAS_OFF:
2088                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
2089                         wm8994->cur_fw = NULL;
2090
2091                         pm_runtime_put(codec->dev);
2092                 }
2093                 break;
2094         }
2095         codec->dapm.bias_level = level;
2096         return 0;
2097 }
2098
2099 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2100 {
2101         struct snd_soc_codec *codec = dai->codec;
2102         struct wm8994 *control = codec->control_data;
2103         int ms_reg;
2104         int aif1_reg;
2105         int ms = 0;
2106         int aif1 = 0;
2107
2108         switch (dai->id) {
2109         case 1:
2110                 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2111                 aif1_reg = WM8994_AIF1_CONTROL_1;
2112                 break;
2113         case 2:
2114                 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2115                 aif1_reg = WM8994_AIF2_CONTROL_1;
2116                 break;
2117         default:
2118                 return -EINVAL;
2119         }
2120
2121         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2122         case SND_SOC_DAIFMT_CBS_CFS:
2123                 break;
2124         case SND_SOC_DAIFMT_CBM_CFM:
2125                 ms = WM8994_AIF1_MSTR;
2126                 break;
2127         default:
2128                 return -EINVAL;
2129         }
2130
2131         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2132         case SND_SOC_DAIFMT_DSP_B:
2133                 aif1 |= WM8994_AIF1_LRCLK_INV;
2134         case SND_SOC_DAIFMT_DSP_A:
2135                 aif1 |= 0x18;
2136                 break;
2137         case SND_SOC_DAIFMT_I2S:
2138                 aif1 |= 0x10;
2139                 break;
2140         case SND_SOC_DAIFMT_RIGHT_J:
2141                 break;
2142         case SND_SOC_DAIFMT_LEFT_J:
2143                 aif1 |= 0x8;
2144                 break;
2145         default:
2146                 return -EINVAL;
2147         }
2148
2149         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2150         case SND_SOC_DAIFMT_DSP_A:
2151         case SND_SOC_DAIFMT_DSP_B:
2152                 /* frame inversion not valid for DSP modes */
2153                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2154                 case SND_SOC_DAIFMT_NB_NF:
2155                         break;
2156                 case SND_SOC_DAIFMT_IB_NF:
2157                         aif1 |= WM8994_AIF1_BCLK_INV;
2158                         break;
2159                 default:
2160                         return -EINVAL;
2161                 }
2162                 break;
2163
2164         case SND_SOC_DAIFMT_I2S:
2165         case SND_SOC_DAIFMT_RIGHT_J:
2166         case SND_SOC_DAIFMT_LEFT_J:
2167                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2168                 case SND_SOC_DAIFMT_NB_NF:
2169                         break;
2170                 case SND_SOC_DAIFMT_IB_IF:
2171                         aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2172                         break;
2173                 case SND_SOC_DAIFMT_IB_NF:
2174                         aif1 |= WM8994_AIF1_BCLK_INV;
2175                         break;
2176                 case SND_SOC_DAIFMT_NB_IF:
2177                         aif1 |= WM8994_AIF1_LRCLK_INV;
2178                         break;
2179                 default:
2180                         return -EINVAL;
2181                 }
2182                 break;
2183         default:
2184                 return -EINVAL;
2185         }
2186
2187         /* The AIF2 format configuration needs to be mirrored to AIF3
2188          * on WM8958 if it's in use so just do it all the time. */
2189         switch (control->type) {
2190         case WM1811:
2191         case WM8958:
2192                 if (dai->id == 2)
2193                         snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2194                                             WM8994_AIF1_LRCLK_INV |
2195                                             WM8958_AIF3_FMT_MASK, aif1);
2196                 break;
2197
2198         default:
2199                 break;
2200         }
2201
2202         snd_soc_update_bits(codec, aif1_reg,
2203                             WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2204                             WM8994_AIF1_FMT_MASK,
2205                             aif1);
2206         snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2207                             ms);
2208
2209         return 0;
2210 }
2211
2212 static struct {
2213         int val, rate;
2214 } srs[] = {
2215         { 0,   8000 },
2216         { 1,  11025 },
2217         { 2,  12000 },
2218         { 3,  16000 },
2219         { 4,  22050 },
2220         { 5,  24000 },
2221         { 6,  32000 },
2222         { 7,  44100 },
2223         { 8,  48000 },
2224         { 9,  88200 },
2225         { 10, 96000 },
2226 };
2227
2228 static int fs_ratios[] = {
2229         64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2230 };
2231
2232 static int bclk_divs[] = {
2233         10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2234         640, 880, 960, 1280, 1760, 1920
2235 };
2236
2237 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2238                             struct snd_pcm_hw_params *params,
2239                             struct snd_soc_dai *dai)
2240 {
2241         struct snd_soc_codec *codec = dai->codec;
2242         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2243         int aif1_reg;
2244         int aif2_reg;
2245         int bclk_reg;
2246         int lrclk_reg;
2247         int rate_reg;
2248         int aif1 = 0;
2249         int aif2 = 0;
2250         int bclk = 0;
2251         int lrclk = 0;
2252         int rate_val = 0;
2253         int id = dai->id - 1;
2254
2255         int i, cur_val, best_val, bclk_rate, best;
2256
2257         switch (dai->id) {
2258         case 1:
2259                 aif1_reg = WM8994_AIF1_CONTROL_1;
2260                 aif2_reg = WM8994_AIF1_CONTROL_2;
2261                 bclk_reg = WM8994_AIF1_BCLK;
2262                 rate_reg = WM8994_AIF1_RATE;
2263                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2264                     wm8994->lrclk_shared[0]) {
2265                         lrclk_reg = WM8994_AIF1DAC_LRCLK;
2266                 } else {
2267                         lrclk_reg = WM8994_AIF1ADC_LRCLK;
2268                         dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2269                 }
2270                 break;
2271         case 2:
2272                 aif1_reg = WM8994_AIF2_CONTROL_1;
2273                 aif2_reg = WM8994_AIF2_CONTROL_2;
2274                 bclk_reg = WM8994_AIF2_BCLK;
2275                 rate_reg = WM8994_AIF2_RATE;
2276                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2277                     wm8994->lrclk_shared[1]) {
2278                         lrclk_reg = WM8994_AIF2DAC_LRCLK;
2279                 } else {
2280                         lrclk_reg = WM8994_AIF2ADC_LRCLK;
2281                         dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2282                 }
2283                 break;
2284         default:
2285                 return -EINVAL;
2286         }
2287
2288         bclk_rate = params_rate(params) * 2;
2289         switch (params_format(params)) {
2290         case SNDRV_PCM_FORMAT_S16_LE:
2291                 bclk_rate *= 16;
2292                 break;
2293         case SNDRV_PCM_FORMAT_S20_3LE:
2294                 bclk_rate *= 20;
2295                 aif1 |= 0x20;
2296                 break;
2297         case SNDRV_PCM_FORMAT_S24_LE:
2298                 bclk_rate *= 24;
2299                 aif1 |= 0x40;
2300                 break;
2301         case SNDRV_PCM_FORMAT_S32_LE:
2302                 bclk_rate *= 32;
2303                 aif1 |= 0x60;
2304                 break;
2305         default:
2306                 return -EINVAL;
2307         }
2308
2309         /* Try to find an appropriate sample rate; look for an exact match. */
2310         for (i = 0; i < ARRAY_SIZE(srs); i++)
2311                 if (srs[i].rate == params_rate(params))
2312                         break;
2313         if (i == ARRAY_SIZE(srs))
2314                 return -EINVAL;
2315         rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2316
2317         dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2318         dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2319                 dai->id, wm8994->aifclk[id], bclk_rate);
2320
2321         if (params_channels(params) == 1 &&
2322             (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2323                 aif2 |= WM8994_AIF1_MONO;
2324
2325         if (wm8994->aifclk[id] == 0) {
2326                 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2327                 return -EINVAL;
2328         }
2329
2330         /* AIFCLK/fs ratio; look for a close match in either direction */
2331         best = 0;
2332         best_val = abs((fs_ratios[0] * params_rate(params))
2333                        - wm8994->aifclk[id]);
2334         for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2335                 cur_val = abs((fs_ratios[i] * params_rate(params))
2336                               - wm8994->aifclk[id]);
2337                 if (cur_val >= best_val)
2338                         continue;
2339                 best = i;
2340                 best_val = cur_val;
2341         }
2342         dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2343                 dai->id, fs_ratios[best]);
2344         rate_val |= best;
2345
2346         /* We may not get quite the right frequency if using
2347          * approximate clocks so look for the closest match that is
2348          * higher than the target (we need to ensure that there enough
2349          * BCLKs to clock out the samples).
2350          */
2351         best = 0;
2352         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2353                 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2354                 if (cur_val < 0) /* BCLK table is sorted */
2355                         break;
2356                 best = i;
2357         }
2358         bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2359         dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2360                 bclk_divs[best], bclk_rate);
2361         bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2362
2363         lrclk = bclk_rate / params_rate(params);
2364         if (!lrclk) {
2365                 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2366                         bclk_rate);
2367                 return -EINVAL;
2368         }
2369         dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2370                 lrclk, bclk_rate / lrclk);
2371
2372         snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2373         snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2374         snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2375         snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2376                             lrclk);
2377         snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2378                             WM8994_AIF1CLK_RATE_MASK, rate_val);
2379
2380         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2381                 switch (dai->id) {
2382                 case 1:
2383                         wm8994->dac_rates[0] = params_rate(params);
2384                         wm8994_set_retune_mobile(codec, 0);
2385                         wm8994_set_retune_mobile(codec, 1);
2386                         break;
2387                 case 2:
2388                         wm8994->dac_rates[1] = params_rate(params);
2389                         wm8994_set_retune_mobile(codec, 2);
2390                         break;
2391                 }
2392         }
2393
2394         return 0;
2395 }
2396
2397 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2398                                  struct snd_pcm_hw_params *params,
2399                                  struct snd_soc_dai *dai)
2400 {
2401         struct snd_soc_codec *codec = dai->codec;
2402         struct wm8994 *control = codec->control_data;
2403         int aif1_reg;
2404         int aif1 = 0;
2405
2406         switch (dai->id) {
2407         case 3:
2408                 switch (control->type) {
2409                 case WM1811:
2410                 case WM8958:
2411                         aif1_reg = WM8958_AIF3_CONTROL_1;
2412                         break;
2413                 default:
2414                         return 0;
2415                 }
2416         default:
2417                 return 0;
2418         }
2419
2420         switch (params_format(params)) {
2421         case SNDRV_PCM_FORMAT_S16_LE:
2422                 break;
2423         case SNDRV_PCM_FORMAT_S20_3LE:
2424                 aif1 |= 0x20;
2425                 break;
2426         case SNDRV_PCM_FORMAT_S24_LE:
2427                 aif1 |= 0x40;
2428                 break;
2429         case SNDRV_PCM_FORMAT_S32_LE:
2430                 aif1 |= 0x60;
2431                 break;
2432         default:
2433                 return -EINVAL;
2434         }
2435
2436         return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2437 }
2438
2439 static void wm8994_aif_shutdown(struct snd_pcm_substream *substream,
2440                                 struct snd_soc_dai *dai)
2441 {
2442         struct snd_soc_codec *codec = dai->codec;
2443         int rate_reg = 0;
2444
2445         switch (dai->id) {
2446         case 1:
2447                 rate_reg = WM8994_AIF1_RATE;
2448                 break;
2449         case 2:
2450                 rate_reg = WM8994_AIF2_RATE;
2451                 break;
2452         default:
2453                 break;
2454         }
2455
2456         /* If the DAI is idle then configure the divider tree for the
2457          * lowest output rate to save a little power if the clock is
2458          * still active (eg, because it is system clock).
2459          */
2460         if (rate_reg && !dai->playback_active && !dai->capture_active)
2461                 snd_soc_update_bits(codec, rate_reg,
2462                                     WM8994_AIF1_SR_MASK |
2463                                     WM8994_AIF1CLK_RATE_MASK, 0x9);
2464 }
2465
2466 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2467 {
2468         struct snd_soc_codec *codec = codec_dai->codec;
2469         int mute_reg;
2470         int reg;
2471
2472         switch (codec_dai->id) {
2473         case 1:
2474                 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2475                 break;
2476         case 2:
2477                 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2478                 break;
2479         default:
2480                 return -EINVAL;
2481         }
2482
2483         if (mute)
2484                 reg = WM8994_AIF1DAC1_MUTE;
2485         else
2486                 reg = 0;
2487
2488         snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2489
2490         return 0;
2491 }
2492
2493 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2494 {
2495         struct snd_soc_codec *codec = codec_dai->codec;
2496         int reg, val, mask;
2497
2498         switch (codec_dai->id) {
2499         case 1:
2500                 reg = WM8994_AIF1_MASTER_SLAVE;
2501                 mask = WM8994_AIF1_TRI;
2502                 break;
2503         case 2:
2504                 reg = WM8994_AIF2_MASTER_SLAVE;
2505                 mask = WM8994_AIF2_TRI;
2506                 break;
2507         case 3:
2508                 reg = WM8994_POWER_MANAGEMENT_6;
2509                 mask = WM8994_AIF3_TRI;
2510                 break;
2511         default:
2512                 return -EINVAL;
2513         }
2514
2515         if (tristate)
2516                 val = mask;
2517         else
2518                 val = 0;
2519
2520         return snd_soc_update_bits(codec, reg, mask, val);
2521 }
2522
2523 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2524 {
2525         struct snd_soc_codec *codec = dai->codec;
2526
2527         /* Disable the pulls on the AIF if we're using it to save power. */
2528         snd_soc_update_bits(codec, WM8994_GPIO_3,
2529                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2530         snd_soc_update_bits(codec, WM8994_GPIO_4,
2531                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2532         snd_soc_update_bits(codec, WM8994_GPIO_5,
2533                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2534
2535         return 0;
2536 }
2537
2538 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2539
2540 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2541                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2542
2543 static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2544         .set_sysclk     = wm8994_set_dai_sysclk,
2545         .set_fmt        = wm8994_set_dai_fmt,
2546         .hw_params      = wm8994_hw_params,
2547         .shutdown       = wm8994_aif_shutdown,
2548         .digital_mute   = wm8994_aif_mute,
2549         .set_pll        = wm8994_set_fll,
2550         .set_tristate   = wm8994_set_tristate,
2551 };
2552
2553 static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2554         .set_sysclk     = wm8994_set_dai_sysclk,
2555         .set_fmt        = wm8994_set_dai_fmt,
2556         .hw_params      = wm8994_hw_params,
2557         .shutdown       = wm8994_aif_shutdown,
2558         .digital_mute   = wm8994_aif_mute,
2559         .set_pll        = wm8994_set_fll,
2560         .set_tristate   = wm8994_set_tristate,
2561 };
2562
2563 static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2564         .hw_params      = wm8994_aif3_hw_params,
2565         .set_tristate   = wm8994_set_tristate,
2566 };
2567
2568 static struct snd_soc_dai_driver wm8994_dai[] = {
2569         {
2570                 .name = "wm8994-aif1",
2571                 .id = 1,
2572                 .playback = {
2573                         .stream_name = "AIF1 Playback",
2574                         .channels_min = 1,
2575                         .channels_max = 2,
2576                         .rates = WM8994_RATES,
2577                         .formats = WM8994_FORMATS,
2578                 },
2579                 .capture = {
2580                         .stream_name = "AIF1 Capture",
2581                         .channels_min = 1,
2582                         .channels_max = 2,
2583                         .rates = WM8994_RATES,
2584                         .formats = WM8994_FORMATS,
2585                  },
2586                 .ops = &wm8994_aif1_dai_ops,
2587         },
2588         {
2589                 .name = "wm8994-aif2",
2590                 .id = 2,
2591                 .playback = {
2592                         .stream_name = "AIF2 Playback",
2593                         .channels_min = 1,
2594                         .channels_max = 2,
2595                         .rates = WM8994_RATES,
2596                         .formats = WM8994_FORMATS,
2597                 },
2598                 .capture = {
2599                         .stream_name = "AIF2 Capture",
2600                         .channels_min = 1,
2601                         .channels_max = 2,
2602                         .rates = WM8994_RATES,
2603                         .formats = WM8994_FORMATS,
2604                 },
2605                 .probe = wm8994_aif2_probe,
2606                 .ops = &wm8994_aif2_dai_ops,
2607         },
2608         {
2609                 .name = "wm8994-aif3",
2610                 .id = 3,
2611                 .playback = {
2612                         .stream_name = "AIF3 Playback",
2613                         .channels_min = 1,
2614                         .channels_max = 2,
2615                         .rates = WM8994_RATES,
2616                         .formats = WM8994_FORMATS,
2617                 },
2618                 .capture = {
2619                         .stream_name = "AIF3 Capture",
2620                         .channels_min = 1,
2621                         .channels_max = 2,
2622                         .rates = WM8994_RATES,
2623                         .formats = WM8994_FORMATS,
2624                 },
2625                 .ops = &wm8994_aif3_dai_ops,
2626         }
2627 };
2628
2629 #ifdef CONFIG_PM
2630 static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
2631 {
2632         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2633         struct wm8994 *control = codec->control_data;
2634         int i, ret;
2635
2636         switch (control->type) {
2637         case WM8994:
2638                 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2639                 break;
2640         case WM1811:
2641         case WM8958:
2642                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2643                                     WM8958_MICD_ENA, 0);
2644                 break;
2645         }
2646
2647         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2648                 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2649                        sizeof(struct wm8994_fll_config));
2650                 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2651                 if (ret < 0)
2652                         dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2653                                  i + 1, ret);
2654         }
2655
2656         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2657
2658         return 0;
2659 }
2660
2661 static int wm8994_resume(struct snd_soc_codec *codec)
2662 {
2663         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2664         struct wm8994 *control = codec->control_data;
2665         int i, ret;
2666         unsigned int val, mask;
2667
2668         if (wm8994->revision < 4) {
2669                 /* force a HW read */
2670                 val = wm8994_reg_read(codec->control_data,
2671                                       WM8994_POWER_MANAGEMENT_5);
2672
2673                 /* modify the cache only */
2674                 codec->cache_only = 1;
2675                 mask =  WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2676                         WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2677                 val &= mask;
2678                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2679                                     mask, val);
2680                 codec->cache_only = 0;
2681         }
2682
2683         /* Restore the registers */
2684         ret = snd_soc_cache_sync(codec);
2685         if (ret != 0)
2686                 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
2687
2688         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2689
2690         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2691                 if (!wm8994->fll_suspend[i].out)
2692                         continue;
2693
2694                 ret = _wm8994_set_fll(codec, i + 1,
2695                                      wm8994->fll_suspend[i].src,
2696                                      wm8994->fll_suspend[i].in,
2697                                      wm8994->fll_suspend[i].out);
2698                 if (ret < 0)
2699                         dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2700                                  i + 1, ret);
2701         }
2702
2703         switch (control->type) {
2704         case WM8994:
2705                 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2706                         snd_soc_update_bits(codec, WM8994_MICBIAS,
2707                                             WM8994_MICD_ENA, WM8994_MICD_ENA);
2708                 break;
2709         case WM1811:
2710         case WM8958:
2711                 if (wm8994->jack_cb)
2712                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2713                                             WM8958_MICD_ENA, WM8958_MICD_ENA);
2714                 break;
2715         }
2716
2717         return 0;
2718 }
2719 #else
2720 #define wm8994_suspend NULL
2721 #define wm8994_resume NULL
2722 #endif
2723
2724 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2725 {
2726         struct snd_soc_codec *codec = wm8994->codec;
2727         struct wm8994_pdata *pdata = wm8994->pdata;
2728         struct snd_kcontrol_new controls[] = {
2729                 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2730                              wm8994->retune_mobile_enum,
2731                              wm8994_get_retune_mobile_enum,
2732                              wm8994_put_retune_mobile_enum),
2733                 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2734                              wm8994->retune_mobile_enum,
2735                              wm8994_get_retune_mobile_enum,
2736                              wm8994_put_retune_mobile_enum),
2737                 SOC_ENUM_EXT("AIF2 EQ Mode",
2738                              wm8994->retune_mobile_enum,
2739                              wm8994_get_retune_mobile_enum,
2740                              wm8994_put_retune_mobile_enum),
2741         };
2742         int ret, i, j;
2743         const char **t;
2744
2745         /* We need an array of texts for the enum API but the number
2746          * of texts is likely to be less than the number of
2747          * configurations due to the sample rate dependency of the
2748          * configurations. */
2749         wm8994->num_retune_mobile_texts = 0;
2750         wm8994->retune_mobile_texts = NULL;
2751         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2752                 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2753                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
2754                                    wm8994->retune_mobile_texts[j]) == 0)
2755                                 break;
2756                 }
2757
2758                 if (j != wm8994->num_retune_mobile_texts)
2759                         continue;
2760
2761                 /* Expand the array... */
2762                 t = krealloc(wm8994->retune_mobile_texts,
2763                              sizeof(char *) *
2764                              (wm8994->num_retune_mobile_texts + 1),
2765                              GFP_KERNEL);
2766                 if (t == NULL)
2767                         continue;
2768
2769                 /* ...store the new entry... */
2770                 t[wm8994->num_retune_mobile_texts] =
2771                         pdata->retune_mobile_cfgs[i].name;
2772
2773                 /* ...and remember the new version. */
2774                 wm8994->num_retune_mobile_texts++;
2775                 wm8994->retune_mobile_texts = t;
2776         }
2777
2778         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2779                 wm8994->num_retune_mobile_texts);
2780
2781         wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2782         wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2783
2784         ret = snd_soc_add_controls(wm8994->codec, controls,
2785                                    ARRAY_SIZE(controls));
2786         if (ret != 0)
2787                 dev_err(wm8994->codec->dev,
2788                         "Failed to add ReTune Mobile controls: %d\n", ret);
2789 }
2790
2791 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2792 {
2793         struct snd_soc_codec *codec = wm8994->codec;
2794         struct wm8994_pdata *pdata = wm8994->pdata;
2795         int ret, i;
2796
2797         if (!pdata)
2798                 return;
2799
2800         wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2801                                       pdata->lineout2_diff,
2802                                       pdata->lineout1fb,
2803                                       pdata->lineout2fb,
2804                                       pdata->jd_scthr,
2805                                       pdata->jd_thr,
2806                                       pdata->micbias1_lvl,
2807                                       pdata->micbias2_lvl);
2808
2809         dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2810
2811         if (pdata->num_drc_cfgs) {
2812                 struct snd_kcontrol_new controls[] = {
2813                         SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2814                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2815                         SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2816                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2817                         SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2818                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2819                 };
2820
2821                 /* We need an array of texts for the enum API */
2822                 wm8994->drc_texts = kmalloc(sizeof(char *)
2823                                             * pdata->num_drc_cfgs, GFP_KERNEL);
2824                 if (!wm8994->drc_texts) {
2825                         dev_err(wm8994->codec->dev,
2826                                 "Failed to allocate %d DRC config texts\n",
2827                                 pdata->num_drc_cfgs);
2828                         return;
2829                 }
2830
2831                 for (i = 0; i < pdata->num_drc_cfgs; i++)
2832                         wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2833
2834                 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2835                 wm8994->drc_enum.texts = wm8994->drc_texts;
2836
2837                 ret = snd_soc_add_controls(wm8994->codec, controls,
2838                                            ARRAY_SIZE(controls));
2839                 if (ret != 0)
2840                         dev_err(wm8994->codec->dev,
2841                                 "Failed to add DRC mode controls: %d\n", ret);
2842
2843                 for (i = 0; i < WM8994_NUM_DRC; i++)
2844                         wm8994_set_drc(codec, i);
2845         }
2846
2847         dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2848                 pdata->num_retune_mobile_cfgs);
2849
2850         if (pdata->num_retune_mobile_cfgs)
2851                 wm8994_handle_retune_mobile_pdata(wm8994);
2852         else
2853                 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
2854                                      ARRAY_SIZE(wm8994_eq_controls));
2855
2856         for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
2857                 if (pdata->micbias[i]) {
2858                         snd_soc_write(codec, WM8958_MICBIAS1 + i,
2859                                 pdata->micbias[i] & 0xffff);
2860                 }
2861         }
2862 }
2863
2864 /**
2865  * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2866  *
2867  * @codec:   WM8994 codec
2868  * @jack:    jack to report detection events on
2869  * @micbias: microphone bias to detect on
2870  * @det:     value to report for presence detection
2871  * @shrt:    value to report for short detection
2872  *
2873  * Enable microphone detection via IRQ on the WM8994.  If GPIOs are
2874  * being used to bring out signals to the processor then only platform
2875  * data configuration is needed for WM8994 and processor GPIOs should
2876  * be configured using snd_soc_jack_add_gpios() instead.
2877  *
2878  * Configuration of detection levels is available via the micbias1_lvl
2879  * and micbias2_lvl platform data members.
2880  */
2881 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2882                       int micbias, int det, int shrt)
2883 {
2884         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2885         struct wm8994_micdet *micdet;
2886         struct wm8994 *control = codec->control_data;
2887         int reg;
2888
2889         if (control->type != WM8994)
2890                 return -EINVAL;
2891
2892         switch (micbias) {
2893         case 1:
2894                 micdet = &wm8994->micdet[0];
2895                 break;
2896         case 2:
2897                 micdet = &wm8994->micdet[1];
2898                 break;
2899         default:
2900                 return -EINVAL;
2901         }
2902
2903         dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2904                 micbias, det, shrt);
2905
2906         /* Store the configuration */
2907         micdet->jack = jack;
2908         micdet->det = det;
2909         micdet->shrt = shrt;
2910
2911         /* If either of the jacks is set up then enable detection */
2912         if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2913                 reg = WM8994_MICD_ENA;
2914         else
2915                 reg = 0;
2916
2917         snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
2918
2919         return 0;
2920 }
2921 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
2922
2923 static irqreturn_t wm8994_mic_irq(int irq, void *data)
2924 {
2925         struct wm8994_priv *priv = data;
2926         struct snd_soc_codec *codec = priv->codec;
2927         int reg;
2928         int report;
2929
2930 #ifndef CONFIG_SND_SOC_WM8994_MODULE
2931         trace_snd_soc_jack_irq(dev_name(codec->dev));
2932 #endif
2933
2934         reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
2935         if (reg < 0) {
2936                 dev_err(codec->dev, "Failed to read microphone status: %d\n",
2937                         reg);
2938                 return IRQ_HANDLED;
2939         }
2940
2941         dev_dbg(codec->dev, "Microphone status: %x\n", reg);
2942
2943         report = 0;
2944         if (reg & WM8994_MIC1_DET_STS)
2945                 report |= priv->micdet[0].det;
2946         if (reg & WM8994_MIC1_SHRT_STS)
2947                 report |= priv->micdet[0].shrt;
2948         snd_soc_jack_report(priv->micdet[0].jack, report,
2949                             priv->micdet[0].det | priv->micdet[0].shrt);
2950
2951         report = 0;
2952         if (reg & WM8994_MIC2_DET_STS)
2953                 report |= priv->micdet[1].det;
2954         if (reg & WM8994_MIC2_SHRT_STS)
2955                 report |= priv->micdet[1].shrt;
2956         snd_soc_jack_report(priv->micdet[1].jack, report,
2957                             priv->micdet[1].det | priv->micdet[1].shrt);
2958
2959         return IRQ_HANDLED;
2960 }
2961
2962 /* Default microphone detection handler for WM8958 - the user can
2963  * override this if they wish.
2964  */
2965 static void wm8958_default_micdet(u16 status, void *data)
2966 {
2967         struct snd_soc_codec *codec = data;
2968         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2969         int report = 0;
2970
2971         /* If nothing present then clear our statuses */
2972         if (!(status & WM8958_MICD_STS))
2973                 goto done;
2974
2975         report = SND_JACK_MICROPHONE;
2976
2977         /* Everything else is buttons; just assign slots */
2978         if (status & 0x1c)
2979                 report |= SND_JACK_BTN_0;
2980
2981 done:
2982         snd_soc_jack_report(wm8994->micdet[0].jack, report,
2983                             SND_JACK_BTN_0 | SND_JACK_MICROPHONE);
2984 }
2985
2986 /**
2987  * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
2988  *
2989  * @codec:   WM8958 codec
2990  * @jack:    jack to report detection events on
2991  *
2992  * Enable microphone detection functionality for the WM8958.  By
2993  * default simple detection which supports the detection of up to 6
2994  * buttons plus video and microphone functionality is supported.
2995  *
2996  * The WM8958 has an advanced jack detection facility which is able to
2997  * support complex accessory detection, especially when used in
2998  * conjunction with external circuitry.  In order to provide maximum
2999  * flexiblity a callback is provided which allows a completely custom
3000  * detection algorithm.
3001  */
3002 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3003                       wm8958_micdet_cb cb, void *cb_data)
3004 {
3005         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3006         struct wm8994 *control = codec->control_data;
3007
3008         switch (control->type) {
3009         case WM1811:
3010         case WM8958:
3011                 break;
3012         default:
3013                 return -EINVAL;
3014         }
3015
3016         if (jack) {
3017                 if (!cb) {
3018                         dev_dbg(codec->dev, "Using default micdet callback\n");
3019                         cb = wm8958_default_micdet;
3020                         cb_data = codec;
3021                 }
3022
3023                 wm8994->micdet[0].jack = jack;
3024                 wm8994->jack_cb = cb;
3025                 wm8994->jack_cb_data = cb_data;
3026
3027                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3028                                     WM8958_MICD_ENA, WM8958_MICD_ENA);
3029         } else {
3030                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3031                                     WM8958_MICD_ENA, 0);
3032         }
3033
3034         return 0;
3035 }
3036 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3037
3038 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3039 {
3040         struct wm8994_priv *wm8994 = data;
3041         struct snd_soc_codec *codec = wm8994->codec;
3042         int reg, count;
3043
3044         /* We may occasionally read a detection without an impedence
3045          * range being provided - if that happens loop again.
3046          */
3047         count = 10;
3048         do {
3049                 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3050                 if (reg < 0) {
3051                         dev_err(codec->dev,
3052                                 "Failed to read mic detect status: %d\n",
3053                                 reg);
3054                         return IRQ_NONE;
3055                 }
3056
3057                 if (!(reg & WM8958_MICD_VALID)) {
3058                         dev_dbg(codec->dev, "Mic detect data not valid\n");
3059                         goto out;
3060                 }
3061
3062                 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3063                         break;
3064
3065                 msleep(1);
3066         } while (count--);
3067
3068         if (count == 0)
3069                 dev_warn(codec->dev, "No impedence range reported for jack\n");
3070
3071 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3072         trace_snd_soc_jack_irq(dev_name(codec->dev));
3073 #endif
3074
3075         if (wm8994->jack_cb)
3076                 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3077         else
3078                 dev_warn(codec->dev, "Accessory detection with no callback\n");
3079
3080 out:
3081         return IRQ_HANDLED;
3082 }
3083
3084 static irqreturn_t wm8994_fifo_error(int irq, void *data)
3085 {
3086         struct snd_soc_codec *codec = data;
3087
3088         dev_err(codec->dev, "FIFO error\n");
3089
3090         return IRQ_HANDLED;
3091 }
3092
3093 static irqreturn_t wm8994_temp_warn(int irq, void *data)
3094 {
3095         struct snd_soc_codec *codec = data;
3096
3097         dev_err(codec->dev, "Thermal warning\n");
3098
3099         return IRQ_HANDLED;
3100 }
3101
3102 static irqreturn_t wm8994_temp_shut(int irq, void *data)
3103 {
3104         struct snd_soc_codec *codec = data;
3105
3106         dev_crit(codec->dev, "Thermal shutdown\n");
3107
3108         return IRQ_HANDLED;
3109 }
3110
3111 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3112 {
3113         struct wm8994 *control;
3114         struct wm8994_priv *wm8994;
3115         struct snd_soc_dapm_context *dapm = &codec->dapm;
3116         int ret, i;
3117
3118         codec->control_data = dev_get_drvdata(codec->dev->parent);
3119         control = codec->control_data;
3120
3121         wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
3122         if (wm8994 == NULL)
3123                 return -ENOMEM;
3124         snd_soc_codec_set_drvdata(codec, wm8994);
3125
3126         wm8994->pdata = dev_get_platdata(codec->dev->parent);
3127         wm8994->codec = codec;
3128
3129         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3130                 init_completion(&wm8994->fll_locked[i]);
3131
3132         if (wm8994->pdata && wm8994->pdata->micdet_irq)
3133                 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3134         else if (wm8994->pdata && wm8994->pdata->irq_base)
3135                 wm8994->micdet_irq = wm8994->pdata->irq_base +
3136                                      WM8994_IRQ_MIC1_DET;
3137
3138         pm_runtime_enable(codec->dev);
3139         pm_runtime_resume(codec->dev);
3140
3141         /* Read our current status back from the chip - we don't want to
3142          * reset as this may interfere with the GPIO or LDO operation. */
3143         for (i = 0; i < WM8994_CACHE_SIZE; i++) {
3144                 if (!wm8994_readable(codec, i) || wm8994_volatile(codec, i))
3145                         continue;
3146
3147                 ret = wm8994_reg_read(codec->control_data, i);
3148                 if (ret <= 0)
3149                         continue;
3150
3151                 ret = snd_soc_cache_write(codec, i, ret);
3152                 if (ret != 0) {
3153                         dev_err(codec->dev,
3154                                 "Failed to initialise cache for 0x%x: %d\n",
3155                                 i, ret);
3156                         goto err;
3157                 }
3158         }
3159
3160         /* Set revision-specific configuration */
3161         wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3162         switch (control->type) {
3163         case WM8994:
3164                 switch (wm8994->revision) {
3165                 case 2:
3166                 case 3:
3167                         wm8994->hubs.dcs_codes_l = -5;
3168                         wm8994->hubs.dcs_codes_r = -5;
3169                         wm8994->hubs.hp_startup_mode = 1;
3170                         wm8994->hubs.dcs_readback_mode = 1;
3171                         wm8994->hubs.series_startup = 1;
3172                         break;
3173                 default:
3174                         wm8994->hubs.dcs_readback_mode = 2;
3175                         break;
3176                 }
3177                 break;
3178
3179         case WM8958:
3180                 wm8994->hubs.dcs_readback_mode = 1;
3181                 break;
3182
3183         case WM1811:
3184                 wm8994->hubs.dcs_readback_mode = 2;
3185                 wm8994->hubs.no_series_update = 1;
3186
3187                 switch (wm8994->revision) {
3188                 case 0:
3189                 case 1:
3190                 case 2:
3191                 case 3:
3192                         wm8994->hubs.dcs_codes_l = -9;
3193                         wm8994->hubs.dcs_codes_r = -5;
3194                         break;
3195                 default:
3196                         break;
3197                 }
3198
3199                 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3200                                     WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3201                 break;
3202
3203         default:
3204                 break;
3205         }
3206
3207         wm8994_request_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR,
3208                            wm8994_fifo_error, "FIFO error", codec);
3209         wm8994_request_irq(codec->control_data, WM8994_IRQ_TEMP_WARN,
3210                            wm8994_temp_warn, "Thermal warning", codec);
3211         wm8994_request_irq(codec->control_data, WM8994_IRQ_TEMP_SHUT,
3212                            wm8994_temp_shut, "Thermal shutdown", codec);
3213
3214         ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3215                                  wm_hubs_dcs_done, "DC servo done",
3216                                  &wm8994->hubs);
3217         if (ret == 0)
3218                 wm8994->hubs.dcs_done_irq = true;
3219
3220         switch (control->type) {
3221         case WM8994:
3222                 if (wm8994->micdet_irq) {
3223                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3224                                                    wm8994_mic_irq,
3225                                                    IRQF_TRIGGER_RISING,
3226                                                    "Mic1 detect",
3227                                                    wm8994);
3228                         if (ret != 0)
3229                                 dev_warn(codec->dev,
3230                                          "Failed to request Mic1 detect IRQ: %d\n",
3231                                          ret);
3232                 }
3233
3234                 ret = wm8994_request_irq(codec->control_data,
3235                                          WM8994_IRQ_MIC1_SHRT,
3236                                          wm8994_mic_irq, "Mic 1 short",
3237                                          wm8994);
3238                 if (ret != 0)
3239                         dev_warn(codec->dev,
3240                                  "Failed to request Mic1 short IRQ: %d\n",
3241                                  ret);
3242
3243                 ret = wm8994_request_irq(codec->control_data,
3244                                          WM8994_IRQ_MIC2_DET,
3245                                          wm8994_mic_irq, "Mic 2 detect",
3246                                          wm8994);
3247                 if (ret != 0)
3248                         dev_warn(codec->dev,
3249                                  "Failed to request Mic2 detect IRQ: %d\n",
3250                                  ret);
3251
3252                 ret = wm8994_request_irq(codec->control_data,
3253                                          WM8994_IRQ_MIC2_SHRT,
3254                                          wm8994_mic_irq, "Mic 2 short",
3255                                          wm8994);
3256                 if (ret != 0)
3257                         dev_warn(codec->dev,
3258                                  "Failed to request Mic2 short IRQ: %d\n",
3259                                  ret);
3260                 break;
3261
3262         case WM8958:
3263         case WM1811:
3264                 if (wm8994->micdet_irq) {
3265                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3266                                                    wm8958_mic_irq,
3267                                                    IRQF_TRIGGER_RISING,
3268                                                    "Mic detect",
3269                                                    wm8994);
3270                         if (ret != 0)
3271                                 dev_warn(codec->dev,
3272                                          "Failed to request Mic detect IRQ: %d\n",
3273                                          ret);
3274                 }
3275         }
3276
3277         wm8994->fll_locked_irq = true;
3278         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
3279                 ret = wm8994_request_irq(codec->control_data,
3280                                          WM8994_IRQ_FLL1_LOCK + i,
3281                                          wm8994_fll_locked_irq, "FLL lock",
3282                                          &wm8994->fll_locked[i]);
3283                 if (ret != 0)
3284                         wm8994->fll_locked_irq = false;
3285         }
3286
3287         /* Remember if AIFnLRCLK is configured as a GPIO.  This should be
3288          * configured on init - if a system wants to do this dynamically
3289          * at runtime we can deal with that then.
3290          */
3291         ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
3292         if (ret < 0) {
3293                 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3294                 goto err_irq;
3295         }
3296         if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3297                 wm8994->lrclk_shared[0] = 1;
3298                 wm8994_dai[0].symmetric_rates = 1;
3299         } else {
3300                 wm8994->lrclk_shared[0] = 0;
3301         }
3302
3303         ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
3304         if (ret < 0) {
3305                 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3306                 goto err_irq;
3307         }
3308         if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3309                 wm8994->lrclk_shared[1] = 1;
3310                 wm8994_dai[1].symmetric_rates = 1;
3311         } else {
3312                 wm8994->lrclk_shared[1] = 0;
3313         }
3314
3315         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3316
3317         /* Latch volume updates (right only; we always do left then right). */
3318         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3319                             WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3320         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3321                             WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3322         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3323                             WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3324         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3325                             WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3326         snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3327                             WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3328         snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3329                             WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3330         snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3331                             WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3332         snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3333                             WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3334         snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3335                             WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3336         snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3337                             WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3338         snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3339                             WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3340         snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3341                             WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3342         snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3343                             WM8994_DAC1_VU, WM8994_DAC1_VU);
3344         snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3345                             WM8994_DAC1_VU, WM8994_DAC1_VU);
3346         snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3347                             WM8994_DAC2_VU, WM8994_DAC2_VU);
3348         snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3349                             WM8994_DAC2_VU, WM8994_DAC2_VU);
3350
3351         /* Set the low bit of the 3D stereo depth so TLV matches */
3352         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3353                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3354                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3355         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3356                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3357                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3358         snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3359                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3360                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3361
3362         /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3363          * use this; it only affects behaviour on idle TDM clock
3364          * cycles. */
3365         switch (control->type) {
3366         case WM8994:
3367         case WM8958:
3368                 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3369                                     WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3370                 break;
3371         default:
3372                 break;
3373         }
3374
3375         wm8994_update_class_w(codec);
3376
3377         wm8994_handle_pdata(wm8994);
3378
3379         wm_hubs_add_analogue_controls(codec);
3380         snd_soc_add_controls(codec, wm8994_snd_controls,
3381                              ARRAY_SIZE(wm8994_snd_controls));
3382         snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
3383                                   ARRAY_SIZE(wm8994_dapm_widgets));
3384
3385         switch (control->type) {
3386         case WM8994:
3387                 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3388                                           ARRAY_SIZE(wm8994_specific_dapm_widgets));
3389                 if (wm8994->revision < 4) {
3390                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3391                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3392                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3393                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
3394                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3395                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
3396                 } else {
3397                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3398                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
3399                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3400                                                   ARRAY_SIZE(wm8994_adc_widgets));
3401                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3402                                                   ARRAY_SIZE(wm8994_dac_widgets));
3403                 }
3404                 break;
3405         case WM8958:
3406                 snd_soc_add_controls(codec, wm8958_snd_controls,
3407                                      ARRAY_SIZE(wm8958_snd_controls));
3408                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3409                                           ARRAY_SIZE(wm8958_dapm_widgets));
3410                 if (wm8994->revision < 1) {
3411                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3412                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3413                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3414                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
3415                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3416                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
3417                 } else {
3418                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3419                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
3420                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3421                                                   ARRAY_SIZE(wm8994_adc_widgets));
3422                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3423                                                   ARRAY_SIZE(wm8994_dac_widgets));
3424                 }
3425                 break;
3426
3427         case WM1811:
3428                 snd_soc_add_controls(codec, wm8958_snd_controls,
3429                                      ARRAY_SIZE(wm8958_snd_controls));
3430                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3431                                           ARRAY_SIZE(wm8958_dapm_widgets));
3432                 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3433                                           ARRAY_SIZE(wm8994_lateclk_widgets));
3434                 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3435                                           ARRAY_SIZE(wm8994_adc_widgets));
3436                 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3437                                           ARRAY_SIZE(wm8994_dac_widgets));
3438                 break;
3439         }
3440
3441
3442         wm_hubs_add_analogue_routes(codec, 0, 0);
3443         snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
3444
3445         switch (control->type) {
3446         case WM8994:
3447                 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3448                                         ARRAY_SIZE(wm8994_intercon));
3449
3450                 if (wm8994->revision < 4) {
3451                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3452                                                 ARRAY_SIZE(wm8994_revd_intercon));
3453                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3454                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3455                 } else {
3456                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3457                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
3458                 }
3459                 break;
3460         case WM8958:
3461                 if (wm8994->revision < 1) {
3462                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3463                                                 ARRAY_SIZE(wm8994_revd_intercon));
3464                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3465                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3466                 } else {
3467                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3468                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
3469                         snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3470                                                 ARRAY_SIZE(wm8958_intercon));
3471                 }
3472
3473                 wm8958_dsp2_init(codec);
3474                 break;
3475         case WM1811:
3476                 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3477                                         ARRAY_SIZE(wm8994_lateclk_intercon));
3478                 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3479                                         ARRAY_SIZE(wm8958_intercon));
3480                 break;
3481         }
3482
3483         return 0;
3484
3485 err_irq:
3486         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
3487         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
3488         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
3489         if (wm8994->micdet_irq)
3490                 free_irq(wm8994->micdet_irq, wm8994);
3491         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3492                 wm8994_free_irq(codec->control_data, WM8994_IRQ_FLL1_LOCK + i,
3493                                 &wm8994->fll_locked[i]);
3494         wm8994_free_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3495                         &wm8994->hubs);
3496         wm8994_free_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR, codec);
3497         wm8994_free_irq(codec->control_data, WM8994_IRQ_TEMP_SHUT, codec);
3498         wm8994_free_irq(codec->control_data, WM8994_IRQ_TEMP_WARN, codec);
3499 err:
3500         kfree(wm8994);
3501         return ret;
3502 }
3503
3504 static int  wm8994_codec_remove(struct snd_soc_codec *codec)
3505 {
3506         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3507         struct wm8994 *control = codec->control_data;
3508         int i;
3509
3510         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3511
3512         pm_runtime_disable(codec->dev);
3513
3514         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3515                 wm8994_free_irq(codec->control_data, WM8994_IRQ_FLL1_LOCK + i,
3516                                 &wm8994->fll_locked[i]);
3517
3518         wm8994_free_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3519                         &wm8994->hubs);
3520         wm8994_free_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR, codec);
3521         wm8994_free_irq(codec->control_data, WM8994_IRQ_TEMP_SHUT, codec);
3522         wm8994_free_irq(codec->control_data, WM8994_IRQ_TEMP_WARN, codec);
3523
3524         switch (control->type) {
3525         case WM8994:
3526                 if (wm8994->micdet_irq)
3527                         free_irq(wm8994->micdet_irq, wm8994);
3528                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
3529                                 wm8994);
3530                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
3531                                 wm8994);
3532                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3533                                 wm8994);
3534                 break;
3535
3536         case WM1811:
3537         case WM8958:
3538                 if (wm8994->micdet_irq)
3539                         free_irq(wm8994->micdet_irq, wm8994);
3540                 break;
3541         }
3542         if (wm8994->mbc)
3543                 release_firmware(wm8994->mbc);
3544         if (wm8994->mbc_vss)
3545                 release_firmware(wm8994->mbc_vss);
3546         if (wm8994->enh_eq)
3547                 release_firmware(wm8994->enh_eq);
3548         kfree(wm8994->retune_mobile_texts);
3549         kfree(wm8994->drc_texts);
3550         kfree(wm8994);
3551
3552         return 0;
3553 }
3554
3555 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3556         .probe =        wm8994_codec_probe,
3557         .remove =       wm8994_codec_remove,
3558         .suspend =      wm8994_suspend,
3559         .resume =       wm8994_resume,
3560         .read =         wm8994_read,
3561         .write =        wm8994_write,
3562         .readable_register = wm8994_readable,
3563         .volatile_register = wm8994_volatile,
3564         .set_bias_level = wm8994_set_bias_level,
3565
3566         .reg_cache_size = WM8994_CACHE_SIZE,
3567         .reg_cache_default = wm8994_reg_defaults,
3568         .reg_word_size = 2,
3569         .compress_type = SND_SOC_RBTREE_COMPRESSION,
3570 };
3571
3572 static int __devinit wm8994_probe(struct platform_device *pdev)
3573 {
3574         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3575                         wm8994_dai, ARRAY_SIZE(wm8994_dai));
3576 }
3577
3578 static int __devexit wm8994_remove(struct platform_device *pdev)
3579 {
3580         snd_soc_unregister_codec(&pdev->dev);
3581         return 0;
3582 }
3583
3584 static struct platform_driver wm8994_codec_driver = {
3585         .driver = {
3586                    .name = "wm8994-codec",
3587                    .owner = THIS_MODULE,
3588                    },
3589         .probe = wm8994_probe,
3590         .remove = __devexit_p(wm8994_remove),
3591 };
3592
3593 static __init int wm8994_init(void)
3594 {
3595         return platform_driver_register(&wm8994_codec_driver);
3596 }
3597 module_init(wm8994_init);
3598
3599 static __exit void wm8994_exit(void)
3600 {
3601         platform_driver_unregister(&wm8994_codec_driver);
3602 }
3603 module_exit(wm8994_exit);
3604
3605
3606 MODULE_DESCRIPTION("ASoC WM8994 driver");
3607 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3608 MODULE_LICENSE("GPL");
3609 MODULE_ALIAS("platform:wm8994-codec");