sound/soc/codecs/wm8996.c

   1 /*
   2  * wm8996.c - WM8996 audio codec interface
   3  *
   4  * Copyright 2011 Wolfson Microelectronics PLC.
   5  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   6  *
   7  *  This program is free software; you can redistribute  it and/or modify it
   8  *  under  the terms of  the GNU General  Public License as published by the
   9  *  Free Software Foundation;  either version 2 of the  License, or (at your
  10  *  option) any later version.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/moduleparam.h>
  15 #include <linux/init.h>
  16 #include <linux/completion.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/gcd.h>
  20 #include <linux/gpio.h>
  21 #include <linux/i2c.h>
  22 #include <linux/regmap.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/slab.h>
  25 #include <linux/workqueue.h>
  26 #include <sound/core.h>
  27 #include <sound/jack.h>
  28 #include <sound/pcm.h>
  29 #include <sound/pcm_params.h>
  30 #include <sound/soc.h>
  31 #include <sound/initval.h>
  32 #include <sound/tlv.h>
  33 #include <trace/events/asoc.h>
  34
  35 #include <sound/wm8996.h>
  36 #include "wm8996.h"
  37
  38 #define WM8996_AIFS 2
  39
  40 #define HPOUT1L 1
  41 #define HPOUT1R 2
  42 #define HPOUT2L 4
  43 #define HPOUT2R 8
  44
  45 #define WM8996_NUM_SUPPLIES 3
  46 static const char *wm8996_supply_names[WM8996_NUM_SUPPLIES] = {
  47         "DBVDD",
  48         "AVDD1",
  49         "AVDD2",
  50 };
  51
  52 struct wm8996_priv {
  53         struct device *dev;
  54         struct regmap *regmap;
  55         struct snd_soc_codec *codec;
  56
  57         int ldo1ena;
  58
  59         int sysclk;
  60         int sysclk_src;
  61
  62         int fll_src;
  63         int fll_fref;
  64         int fll_fout;
  65
  66         struct completion fll_lock;
  67
  68         u16 dcs_pending;
  69         struct completion dcs_done;
  70
  71         u16 hpout_ena;
  72         u16 hpout_pending;
  73
  74         struct regulator_bulk_data supplies[WM8996_NUM_SUPPLIES];
  75         struct notifier_block disable_nb[WM8996_NUM_SUPPLIES];
  76         struct regulator *cpvdd;
  77         int bg_ena;
  78
  79         struct wm8996_pdata pdata;
  80
  81         int rx_rate[WM8996_AIFS];
  82         int bclk_rate[WM8996_AIFS];
  83
  84         /* Platform dependant ReTune mobile configuration */
  85         int num_retune_mobile_texts;
  86         const char **retune_mobile_texts;
  87         int retune_mobile_cfg[2];
  88         struct soc_enum retune_mobile_enum;
  89
  90         struct snd_soc_jack *jack;
  91         bool detecting;
  92         bool jack_mic;
  93         wm8996_polarity_fn polarity_cb;
  94
  95 #ifdef CONFIG_GPIOLIB
  96         struct gpio_chip gpio_chip;
  97 #endif
  98 };
  99
 100 /* We can't use the same notifier block for more than one supply and
 101  * there's no way I can see to get from a callback to the caller
 102  * except container_of().
 103  */
 104 #define WM8996_REGULATOR_EVENT(n) \
 105 static int wm8996_regulator_event_##n(struct notifier_block *nb, \
 106                                     unsigned long event, void *data)    \
 107 { \
 108         struct wm8996_priv *wm8996 = container_of(nb, struct wm8996_priv, \
 109                                                   disable_nb[n]); \
 110         if (event & REGULATOR_EVENT_DISABLE) { \
 111                 regcache_mark_dirty(wm8996->regmap);    \
 112         } \
 113         return 0; \
 114 }
 115
 116 WM8996_REGULATOR_EVENT(0)
 117 WM8996_REGULATOR_EVENT(1)
 118 WM8996_REGULATOR_EVENT(2)
 119
 120 static struct reg_default wm8996_reg[] = {
 121         { WM8996_SOFTWARE_RESET, 0x8996 },
 122         { WM8996_POWER_MANAGEMENT_1, 0x0 },
 123         { WM8996_POWER_MANAGEMENT_2, 0x0 },
 124         { WM8996_POWER_MANAGEMENT_3, 0x0 },
 125         { WM8996_POWER_MANAGEMENT_4, 0x0 },
 126         { WM8996_POWER_MANAGEMENT_5, 0x0 },
 127         { WM8996_POWER_MANAGEMENT_6, 0x0 },
 128         { WM8996_POWER_MANAGEMENT_7, 0x10 },
 129         { WM8996_POWER_MANAGEMENT_8, 0x0 },
 130         { WM8996_LEFT_LINE_INPUT_VOLUME, 0x0 },
 131         { WM8996_RIGHT_LINE_INPUT_VOLUME, 0x0 },
 132         { WM8996_LINE_INPUT_CONTROL, 0x0 },
 133         { WM8996_DAC1_HPOUT1_VOLUME, 0x88 },
 134         { WM8996_DAC2_HPOUT2_VOLUME, 0x88 },
 135         { WM8996_DAC1_LEFT_VOLUME, 0x2c0 },
 136         { WM8996_DAC1_RIGHT_VOLUME, 0x2c0 },
 137         { WM8996_DAC2_LEFT_VOLUME, 0x2c0 },
 138         { WM8996_DAC2_RIGHT_VOLUME, 0x2c0 },
 139         { WM8996_OUTPUT1_LEFT_VOLUME, 0x80 },
 140         { WM8996_OUTPUT1_RIGHT_VOLUME, 0x80 },
 141         { WM8996_OUTPUT2_LEFT_VOLUME, 0x80 },
 142         { WM8996_OUTPUT2_RIGHT_VOLUME, 0x80 },
 143         { WM8996_MICBIAS_1, 0x39 },
 144         { WM8996_MICBIAS_2, 0x39 },
 145         { WM8996_LDO_1, 0x3 },
 146         { WM8996_LDO_2, 0x13 },
 147         { WM8996_ACCESSORY_DETECT_MODE_1, 0x4 },
 148         { WM8996_ACCESSORY_DETECT_MODE_2, 0x0 },
 149         { WM8996_HEADPHONE_DETECT_1, 0x20 },
 150         { WM8996_HEADPHONE_DETECT_2, 0x0 },
 151         { WM8996_MIC_DETECT_1, 0x7600 },
 152         { WM8996_MIC_DETECT_2, 0xbf },
 153         { WM8996_CHARGE_PUMP_1, 0x1f25 },
 154         { WM8996_CHARGE_PUMP_2, 0xab19 },
 155         { WM8996_DC_SERVO_1, 0x0 },
 156         { WM8996_DC_SERVO_2, 0x0 },
 157         { WM8996_DC_SERVO_3, 0x0 },
 158         { WM8996_DC_SERVO_5, 0x2a2a },
 159         { WM8996_DC_SERVO_6, 0x0 },
 160         { WM8996_DC_SERVO_7, 0x0 },
 161         { WM8996_ANALOGUE_HP_1, 0x0 },
 162         { WM8996_ANALOGUE_HP_2, 0x0 },
 163         { WM8996_CONTROL_INTERFACE_1, 0x8004 },
 164         { WM8996_WRITE_SEQUENCER_CTRL_1, 0x0 },
 165         { WM8996_WRITE_SEQUENCER_CTRL_2, 0x0 },
 166         { WM8996_AIF_CLOCKING_1, 0x0 },
 167         { WM8996_AIF_CLOCKING_2, 0x0 },
 168         { WM8996_CLOCKING_1, 0x10 },
 169         { WM8996_CLOCKING_2, 0x0 },
 170         { WM8996_AIF_RATE, 0x83 },
 171         { WM8996_FLL_CONTROL_1, 0x0 },
 172         { WM8996_FLL_CONTROL_2, 0x0 },
 173         { WM8996_FLL_CONTROL_3, 0x0 },
 174         { WM8996_FLL_CONTROL_4, 0x5dc0 },
 175         { WM8996_FLL_CONTROL_5, 0xc84 },
 176         { WM8996_FLL_EFS_1, 0x0 },
 177         { WM8996_FLL_EFS_2, 0x2 },
 178         { WM8996_AIF1_CONTROL, 0x0 },
 179         { WM8996_AIF1_BCLK, 0x0 },
 180         { WM8996_AIF1_TX_LRCLK_1, 0x80 },
 181         { WM8996_AIF1_TX_LRCLK_2, 0x8 },
 182         { WM8996_AIF1_RX_LRCLK_1, 0x80 },
 183         { WM8996_AIF1_RX_LRCLK_2, 0x0 },
 184         { WM8996_AIF1TX_DATA_CONFIGURATION_1, 0x1818 },
 185         { WM8996_AIF1TX_DATA_CONFIGURATION_2, 0 },
 186         { WM8996_AIF1RX_DATA_CONFIGURATION, 0x1818 },
 187         { WM8996_AIF1TX_CHANNEL_0_CONFIGURATION, 0x0 },
 188         { WM8996_AIF1TX_CHANNEL_1_CONFIGURATION, 0x0 },
 189         { WM8996_AIF1TX_CHANNEL_2_CONFIGURATION, 0x0 },
 190         { WM8996_AIF1TX_CHANNEL_3_CONFIGURATION, 0x0 },
 191         { WM8996_AIF1TX_CHANNEL_4_CONFIGURATION, 0x0 },
 192         { WM8996_AIF1TX_CHANNEL_5_CONFIGURATION, 0x0 },
 193         { WM8996_AIF1RX_CHANNEL_0_CONFIGURATION, 0x0 },
 194         { WM8996_AIF1RX_CHANNEL_1_CONFIGURATION, 0x0 },
 195         { WM8996_AIF1RX_CHANNEL_2_CONFIGURATION, 0x0 },
 196         { WM8996_AIF1RX_CHANNEL_3_CONFIGURATION, 0x0 },
 197         { WM8996_AIF1RX_CHANNEL_4_CONFIGURATION, 0x0 },
 198         { WM8996_AIF1RX_CHANNEL_5_CONFIGURATION, 0x0 },
 199         { WM8996_AIF1RX_MONO_CONFIGURATION, 0x0 },
 200         { WM8996_AIF1TX_TEST, 0x7 },
 201         { WM8996_AIF2_CONTROL, 0x0 },
 202         { WM8996_AIF2_BCLK, 0x0 },
 203         { WM8996_AIF2_TX_LRCLK_1, 0x80 },
 204         { WM8996_AIF2_TX_LRCLK_2, 0x8 },
 205         { WM8996_AIF2_RX_LRCLK_1, 0x80 },
 206         { WM8996_AIF2_RX_LRCLK_2, 0x0 },
 207         { WM8996_AIF2TX_DATA_CONFIGURATION_1, 0x1818 },
 208         { WM8996_AIF2RX_DATA_CONFIGURATION, 0x1818 },
 209         { WM8996_AIF2RX_DATA_CONFIGURATION, 0x0 },
 210         { WM8996_AIF2TX_CHANNEL_0_CONFIGURATION, 0x0 },
 211         { WM8996_AIF2TX_CHANNEL_1_CONFIGURATION, 0x0 },
 212         { WM8996_AIF2RX_CHANNEL_0_CONFIGURATION, 0x0 },
 213         { WM8996_AIF2RX_CHANNEL_1_CONFIGURATION, 0x0 },
 214         { WM8996_AIF2RX_MONO_CONFIGURATION, 0x0 },
 215         { WM8996_AIF2TX_TEST, 0x1 },
 216         { WM8996_DSP1_TX_LEFT_VOLUME, 0xc0 },
 217         { WM8996_DSP1_TX_RIGHT_VOLUME, 0xc0 },
 218         { WM8996_DSP1_RX_LEFT_VOLUME, 0xc0 },
 219         { WM8996_DSP1_RX_RIGHT_VOLUME, 0xc0 },
 220         { WM8996_DSP1_TX_FILTERS, 0x2000 },
 221         { WM8996_DSP1_RX_FILTERS_1, 0x200 },
 222         { WM8996_DSP1_RX_FILTERS_2, 0x10 },
 223         { WM8996_DSP1_DRC_1, 0x98 },
 224         { WM8996_DSP1_DRC_2, 0x845 },
 225         { WM8996_DSP1_RX_EQ_GAINS_1, 0x6318 },
 226         { WM8996_DSP1_RX_EQ_GAINS_2, 0x6300 },
 227         { WM8996_DSP1_RX_EQ_BAND_1_A, 0xfca },
 228         { WM8996_DSP1_RX_EQ_BAND_1_B, 0x400 },
 229         { WM8996_DSP1_RX_EQ_BAND_1_PG, 0xd8 },
 230         { WM8996_DSP1_RX_EQ_BAND_2_A, 0x1eb5 },
 231         { WM8996_DSP1_RX_EQ_BAND_2_B, 0xf145 },
 232         { WM8996_DSP1_RX_EQ_BAND_2_C, 0xb75 },
 233         { WM8996_DSP1_RX_EQ_BAND_2_PG, 0x1c5 },
 234         { WM8996_DSP1_RX_EQ_BAND_3_A, 0x1c58 },
 235         { WM8996_DSP1_RX_EQ_BAND_3_B, 0xf373 },
 236         { WM8996_DSP1_RX_EQ_BAND_3_C, 0xa54 },
 237         { WM8996_DSP1_RX_EQ_BAND_3_PG, 0x558 },
 238         { WM8996_DSP1_RX_EQ_BAND_4_A, 0x168e },
 239         { WM8996_DSP1_RX_EQ_BAND_4_B, 0xf829 },
 240         { WM8996_DSP1_RX_EQ_BAND_4_C, 0x7ad },
 241         { WM8996_DSP1_RX_EQ_BAND_4_PG, 0x1103 },
 242         { WM8996_DSP1_RX_EQ_BAND_5_A, 0x564 },
 243         { WM8996_DSP1_RX_EQ_BAND_5_B, 0x559 },
 244         { WM8996_DSP1_RX_EQ_BAND_5_PG, 0x4000 },
 245         { WM8996_DSP2_TX_LEFT_VOLUME, 0xc0 },
 246         { WM8996_DSP2_TX_RIGHT_VOLUME, 0xc0 },
 247         { WM8996_DSP2_RX_LEFT_VOLUME, 0xc0 },
 248         { WM8996_DSP2_RX_RIGHT_VOLUME, 0xc0 },
 249         { WM8996_DSP2_TX_FILTERS, 0x2000 },
 250         { WM8996_DSP2_RX_FILTERS_1, 0x200 },
 251         { WM8996_DSP2_RX_FILTERS_2, 0x10 },
 252         { WM8996_DSP2_DRC_1, 0x98 },
 253         { WM8996_DSP2_DRC_2, 0x845 },
 254         { WM8996_DSP2_RX_EQ_GAINS_1, 0x6318 },
 255         { WM8996_DSP2_RX_EQ_GAINS_2, 0x6300 },
 256         { WM8996_DSP2_RX_EQ_BAND_1_A, 0xfca },
 257         { WM8996_DSP2_RX_EQ_BAND_1_B, 0x400 },
 258         { WM8996_DSP2_RX_EQ_BAND_1_PG, 0xd8 },
 259         { WM8996_DSP2_RX_EQ_BAND_2_A, 0x1eb5 },
 260         { WM8996_DSP2_RX_EQ_BAND_2_B, 0xf145 },
 261         { WM8996_DSP2_RX_EQ_BAND_2_C, 0xb75 },
 262         { WM8996_DSP2_RX_EQ_BAND_2_PG, 0x1c5 },
 263         { WM8996_DSP2_RX_EQ_BAND_3_A, 0x1c58 },
 264         { WM8996_DSP2_RX_EQ_BAND_3_B, 0xf373 },
 265         { WM8996_DSP2_RX_EQ_BAND_3_C, 0xa54 },
 266         { WM8996_DSP2_RX_EQ_BAND_3_PG, 0x558 },
 267         { WM8996_DSP2_RX_EQ_BAND_4_A, 0x168e },
 268         { WM8996_DSP2_RX_EQ_BAND_4_B, 0xf829 },
 269         { WM8996_DSP2_RX_EQ_BAND_4_C, 0x7ad },
 270         { WM8996_DSP2_RX_EQ_BAND_4_PG, 0x1103 },
 271         { WM8996_DSP2_RX_EQ_BAND_5_A, 0x564 },
 272         { WM8996_DSP2_RX_EQ_BAND_5_B, 0x559 },
 273         { WM8996_DSP2_RX_EQ_BAND_5_PG, 0x4000 },
 274         { WM8996_DAC1_MIXER_VOLUMES, 0x0 },
 275         { WM8996_DAC1_LEFT_MIXER_ROUTING, 0x0 },
 276         { WM8996_DAC1_RIGHT_MIXER_ROUTING, 0x0 },
 277         { WM8996_DAC2_MIXER_VOLUMES, 0x0 },
 278         { WM8996_DAC2_LEFT_MIXER_ROUTING, 0x0 },
 279         { WM8996_DAC2_RIGHT_MIXER_ROUTING, 0x0 },
 280         { WM8996_DSP1_TX_LEFT_MIXER_ROUTING, 0x0 },
 281         { WM8996_DSP1_TX_RIGHT_MIXER_ROUTING, 0x0 },
 282         { WM8996_DSP2_TX_LEFT_MIXER_ROUTING, 0x0 },
 283         { WM8996_DSP2_TX_RIGHT_MIXER_ROUTING, 0x0 },
 284         { WM8996_DSP_TX_MIXER_SELECT, 0x0 },
 285         { WM8996_DAC_SOFTMUTE, 0x0 },
 286         { WM8996_OVERSAMPLING, 0xd },
 287         { WM8996_SIDETONE, 0x1040 },
 288         { WM8996_GPIO_1, 0xa101 },
 289         { WM8996_GPIO_2, 0xa101 },
 290         { WM8996_GPIO_3, 0xa101 },
 291         { WM8996_GPIO_4, 0xa101 },
 292         { WM8996_GPIO_5, 0xa101 },
 293         { WM8996_PULL_CONTROL_1, 0x0 },
 294         { WM8996_PULL_CONTROL_2, 0x140 },
 295         { WM8996_INTERRUPT_STATUS_1_MASK, 0x1f },
 296         { WM8996_INTERRUPT_STATUS_2_MASK, 0x1ecf },
 297         { WM8996_LEFT_PDM_SPEAKER, 0x0 },
 298         { WM8996_RIGHT_PDM_SPEAKER, 0x1 },
 299         { WM8996_PDM_SPEAKER_MUTE_SEQUENCE, 0x69 },
 300         { WM8996_PDM_SPEAKER_VOLUME, 0x66 },
 301         { WM8996_WRITE_SEQUENCER_0, 0x1 },
 302         { WM8996_WRITE_SEQUENCER_1, 0x1 },
 303         { WM8996_WRITE_SEQUENCER_3, 0x6 },
 304         { WM8996_WRITE_SEQUENCER_4, 0x40 },
 305         { WM8996_WRITE_SEQUENCER_5, 0x1 },
 306         { WM8996_WRITE_SEQUENCER_6, 0xf },
 307         { WM8996_WRITE_SEQUENCER_7, 0x6 },
 308         { WM8996_WRITE_SEQUENCER_8, 0x1 },
 309         { WM8996_WRITE_SEQUENCER_9, 0x3 },
 310         { WM8996_WRITE_SEQUENCER_10, 0x104 },
 311         { WM8996_WRITE_SEQUENCER_12, 0x60 },
 312         { WM8996_WRITE_SEQUENCER_13, 0x11 },
 313         { WM8996_WRITE_SEQUENCER_14, 0x401 },
 314         { WM8996_WRITE_SEQUENCER_16, 0x50 },
 315         { WM8996_WRITE_SEQUENCER_17, 0x3 },
 316         { WM8996_WRITE_SEQUENCER_18, 0x100 },
 317         { WM8996_WRITE_SEQUENCER_20, 0x51 },
 318         { WM8996_WRITE_SEQUENCER_21, 0x3 },
 319         { WM8996_WRITE_SEQUENCER_22, 0x104 },
 320         { WM8996_WRITE_SEQUENCER_23, 0xa },
 321         { WM8996_WRITE_SEQUENCER_24, 0x60 },
 322         { WM8996_WRITE_SEQUENCER_25, 0x3b },
 323         { WM8996_WRITE_SEQUENCER_26, 0x502 },
 324         { WM8996_WRITE_SEQUENCER_27, 0x100 },
 325         { WM8996_WRITE_SEQUENCER_28, 0x2fff },
 326         { WM8996_WRITE_SEQUENCER_32, 0x2fff },
 327         { WM8996_WRITE_SEQUENCER_36, 0x2fff },
 328         { WM8996_WRITE_SEQUENCER_40, 0x2fff },
 329         { WM8996_WRITE_SEQUENCER_44, 0x2fff },
 330         { WM8996_WRITE_SEQUENCER_48, 0x2fff },
 331         { WM8996_WRITE_SEQUENCER_52, 0x2fff },
 332         { WM8996_WRITE_SEQUENCER_56, 0x2fff },
 333         { WM8996_WRITE_SEQUENCER_60, 0x2fff },
 334         { WM8996_WRITE_SEQUENCER_64, 0x1 },
 335         { WM8996_WRITE_SEQUENCER_65, 0x1 },
 336         { WM8996_WRITE_SEQUENCER_67, 0x6 },
 337         { WM8996_WRITE_SEQUENCER_68, 0x40 },
 338         { WM8996_WRITE_SEQUENCER_69, 0x1 },
 339         { WM8996_WRITE_SEQUENCER_70, 0xf },
 340         { WM8996_WRITE_SEQUENCER_71, 0x6 },
 341         { WM8996_WRITE_SEQUENCER_72, 0x1 },
 342         { WM8996_WRITE_SEQUENCER_73, 0x3 },
 343         { WM8996_WRITE_SEQUENCER_74, 0x104 },
 344         { WM8996_WRITE_SEQUENCER_76, 0x60 },
 345         { WM8996_WRITE_SEQUENCER_77, 0x11 },
 346         { WM8996_WRITE_SEQUENCER_78, 0x401 },
 347         { WM8996_WRITE_SEQUENCER_80, 0x50 },
 348         { WM8996_WRITE_SEQUENCER_81, 0x3 },
 349         { WM8996_WRITE_SEQUENCER_82, 0x100 },
 350         { WM8996_WRITE_SEQUENCER_84, 0x60 },
 351         { WM8996_WRITE_SEQUENCER_85, 0x3b },
 352         { WM8996_WRITE_SEQUENCER_86, 0x502 },
 353         { WM8996_WRITE_SEQUENCER_87, 0x100 },
 354         { WM8996_WRITE_SEQUENCER_88, 0x2fff },
 355         { WM8996_WRITE_SEQUENCER_92, 0x2fff },
 356         { WM8996_WRITE_SEQUENCER_96, 0x2fff },
 357         { WM8996_WRITE_SEQUENCER_100, 0x2fff },
 358         { WM8996_WRITE_SEQUENCER_104, 0x2fff },
 359         { WM8996_WRITE_SEQUENCER_108, 0x2fff },
 360         { WM8996_WRITE_SEQUENCER_112, 0x2fff },
 361         { WM8996_WRITE_SEQUENCER_116, 0x2fff },
 362         { WM8996_WRITE_SEQUENCER_120, 0x2fff },
 363         { WM8996_WRITE_SEQUENCER_124, 0x2fff },
 364         { WM8996_WRITE_SEQUENCER_128, 0x1 },
 365         { WM8996_WRITE_SEQUENCER_129, 0x1 },
 366         { WM8996_WRITE_SEQUENCER_131, 0x6 },
 367         { WM8996_WRITE_SEQUENCER_132, 0x40 },
 368         { WM8996_WRITE_SEQUENCER_133, 0x1 },
 369         { WM8996_WRITE_SEQUENCER_134, 0xf },
 370         { WM8996_WRITE_SEQUENCER_135, 0x6 },
 371         { WM8996_WRITE_SEQUENCER_136, 0x1 },
 372         { WM8996_WRITE_SEQUENCER_137, 0x3 },
 373         { WM8996_WRITE_SEQUENCER_138, 0x106 },
 374         { WM8996_WRITE_SEQUENCER_140, 0x61 },
 375         { WM8996_WRITE_SEQUENCER_141, 0x11 },
 376         { WM8996_WRITE_SEQUENCER_142, 0x401 },
 377         { WM8996_WRITE_SEQUENCER_144, 0x50 },
 378         { WM8996_WRITE_SEQUENCER_145, 0x3 },
 379         { WM8996_WRITE_SEQUENCER_146, 0x102 },
 380         { WM8996_WRITE_SEQUENCER_148, 0x51 },
 381         { WM8996_WRITE_SEQUENCER_149, 0x3 },
 382         { WM8996_WRITE_SEQUENCER_150, 0x106 },
 383         { WM8996_WRITE_SEQUENCER_151, 0xa },
 384         { WM8996_WRITE_SEQUENCER_152, 0x61 },
 385         { WM8996_WRITE_SEQUENCER_153, 0x3b },
 386         { WM8996_WRITE_SEQUENCER_154, 0x502 },
 387         { WM8996_WRITE_SEQUENCER_155, 0x100 },
 388         { WM8996_WRITE_SEQUENCER_156, 0x2fff },
 389         { WM8996_WRITE_SEQUENCER_160, 0x2fff },
 390         { WM8996_WRITE_SEQUENCER_164, 0x2fff },
 391         { WM8996_WRITE_SEQUENCER_168, 0x2fff },
 392         { WM8996_WRITE_SEQUENCER_172, 0x2fff },
 393         { WM8996_WRITE_SEQUENCER_176, 0x2fff },
 394         { WM8996_WRITE_SEQUENCER_180, 0x2fff },
 395         { WM8996_WRITE_SEQUENCER_184, 0x2fff },
 396         { WM8996_WRITE_SEQUENCER_188, 0x2fff },
 397         { WM8996_WRITE_SEQUENCER_192, 0x1 },
 398         { WM8996_WRITE_SEQUENCER_193, 0x1 },
 399         { WM8996_WRITE_SEQUENCER_195, 0x6 },
 400         { WM8996_WRITE_SEQUENCER_196, 0x40 },
 401         { WM8996_WRITE_SEQUENCER_197, 0x1 },
 402         { WM8996_WRITE_SEQUENCER_198, 0xf },
 403         { WM8996_WRITE_SEQUENCER_199, 0x6 },
 404         { WM8996_WRITE_SEQUENCER_200, 0x1 },
 405         { WM8996_WRITE_SEQUENCER_201, 0x3 },
 406         { WM8996_WRITE_SEQUENCER_202, 0x106 },
 407         { WM8996_WRITE_SEQUENCER_204, 0x61 },
 408         { WM8996_WRITE_SEQUENCER_205, 0x11 },
 409         { WM8996_WRITE_SEQUENCER_206, 0x401 },
 410         { WM8996_WRITE_SEQUENCER_208, 0x50 },
 411         { WM8996_WRITE_SEQUENCER_209, 0x3 },
 412         { WM8996_WRITE_SEQUENCER_210, 0x102 },
 413         { WM8996_WRITE_SEQUENCER_212, 0x61 },
 414         { WM8996_WRITE_SEQUENCER_213, 0x3b },
 415         { WM8996_WRITE_SEQUENCER_214, 0x502 },
 416         { WM8996_WRITE_SEQUENCER_215, 0x100 },
 417         { WM8996_WRITE_SEQUENCER_216, 0x2fff },
 418         { WM8996_WRITE_SEQUENCER_220, 0x2fff },
 419         { WM8996_WRITE_SEQUENCER_224, 0x2fff },
 420         { WM8996_WRITE_SEQUENCER_228, 0x2fff },
 421         { WM8996_WRITE_SEQUENCER_232, 0x2fff },
 422         { WM8996_WRITE_SEQUENCER_236, 0x2fff },
 423         { WM8996_WRITE_SEQUENCER_240, 0x2fff },
 424         { WM8996_WRITE_SEQUENCER_244, 0x2fff },
 425         { WM8996_WRITE_SEQUENCER_248, 0x2fff },
 426         { WM8996_WRITE_SEQUENCER_252, 0x2fff },
 427         { WM8996_WRITE_SEQUENCER_256, 0x60 },
 428         { WM8996_WRITE_SEQUENCER_258, 0x601 },
 429         { WM8996_WRITE_SEQUENCER_260, 0x50 },
 430         { WM8996_WRITE_SEQUENCER_262, 0x100 },
 431         { WM8996_WRITE_SEQUENCER_264, 0x1 },
 432         { WM8996_WRITE_SEQUENCER_266, 0x104 },
 433         { WM8996_WRITE_SEQUENCER_267, 0x100 },
 434         { WM8996_WRITE_SEQUENCER_268, 0x2fff },
 435         { WM8996_WRITE_SEQUENCER_272, 0x2fff },
 436         { WM8996_WRITE_SEQUENCER_276, 0x2fff },
 437         { WM8996_WRITE_SEQUENCER_280, 0x2fff },
 438         { WM8996_WRITE_SEQUENCER_284, 0x2fff },
 439         { WM8996_WRITE_SEQUENCER_288, 0x2fff },
 440         { WM8996_WRITE_SEQUENCER_292, 0x2fff },
 441         { WM8996_WRITE_SEQUENCER_296, 0x2fff },
 442         { WM8996_WRITE_SEQUENCER_300, 0x2fff },
 443         { WM8996_WRITE_SEQUENCER_304, 0x2fff },
 444         { WM8996_WRITE_SEQUENCER_308, 0x2fff },
 445         { WM8996_WRITE_SEQUENCER_312, 0x2fff },
 446         { WM8996_WRITE_SEQUENCER_316, 0x2fff },
 447         { WM8996_WRITE_SEQUENCER_320, 0x61 },
 448         { WM8996_WRITE_SEQUENCER_322, 0x601 },
 449         { WM8996_WRITE_SEQUENCER_324, 0x50 },
 450         { WM8996_WRITE_SEQUENCER_326, 0x102 },
 451         { WM8996_WRITE_SEQUENCER_328, 0x1 },
 452         { WM8996_WRITE_SEQUENCER_330, 0x106 },
 453         { WM8996_WRITE_SEQUENCER_331, 0x100 },
 454         { WM8996_WRITE_SEQUENCER_332, 0x2fff },
 455         { WM8996_WRITE_SEQUENCER_336, 0x2fff },
 456         { WM8996_WRITE_SEQUENCER_340, 0x2fff },
 457         { WM8996_WRITE_SEQUENCER_344, 0x2fff },
 458         { WM8996_WRITE_SEQUENCER_348, 0x2fff },
 459         { WM8996_WRITE_SEQUENCER_352, 0x2fff },
 460         { WM8996_WRITE_SEQUENCER_356, 0x2fff },
 461         { WM8996_WRITE_SEQUENCER_360, 0x2fff },
 462         { WM8996_WRITE_SEQUENCER_364, 0x2fff },
 463         { WM8996_WRITE_SEQUENCER_368, 0x2fff },
 464         { WM8996_WRITE_SEQUENCER_372, 0x2fff },
 465         { WM8996_WRITE_SEQUENCER_376, 0x2fff },
 466         { WM8996_WRITE_SEQUENCER_380, 0x2fff },
 467         { WM8996_WRITE_SEQUENCER_384, 0x60 },
 468         { WM8996_WRITE_SEQUENCER_386, 0x601 },
 469         { WM8996_WRITE_SEQUENCER_388, 0x61 },
 470         { WM8996_WRITE_SEQUENCER_390, 0x601 },
 471         { WM8996_WRITE_SEQUENCER_392, 0x50 },
 472         { WM8996_WRITE_SEQUENCER_394, 0x300 },
 473         { WM8996_WRITE_SEQUENCER_396, 0x1 },
 474         { WM8996_WRITE_SEQUENCER_398, 0x304 },
 475         { WM8996_WRITE_SEQUENCER_400, 0x40 },
 476         { WM8996_WRITE_SEQUENCER_402, 0xf },
 477         { WM8996_WRITE_SEQUENCER_404, 0x1 },
 478         { WM8996_WRITE_SEQUENCER_407, 0x100 },
 479 };
 480
 481 static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0, 100, 0);
 482 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
 483 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 484 static const DECLARE_TLV_DB_SCALE(out_digital_tlv, -1200, 150, 0);
 485 static const DECLARE_TLV_DB_SCALE(out_tlv, -900, 75, 0);
 486 static const DECLARE_TLV_DB_SCALE(spk_tlv, -900, 150, 0);
 487 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 488 static const DECLARE_TLV_DB_SCALE(threedstereo_tlv, -1600, 183, 1);
 489
 490 static const char *sidetone_hpf_text[] = {
 491         "2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz"
 492 };
 493
 494 static const struct soc_enum sidetone_hpf =
 495         SOC_ENUM_SINGLE(WM8996_SIDETONE, 7, 7, sidetone_hpf_text);
 496
 497 static const char *hpf_mode_text[] = {
 498         "HiFi", "Custom", "Voice"
 499 };
 500
 501 static const struct soc_enum dsp1tx_hpf_mode =
 502         SOC_ENUM_SINGLE(WM8996_DSP1_TX_FILTERS, 3, 3, hpf_mode_text);
 503
 504 static const struct soc_enum dsp2tx_hpf_mode =
 505         SOC_ENUM_SINGLE(WM8996_DSP2_TX_FILTERS, 3, 3, hpf_mode_text);
 506
 507 static const char *hpf_cutoff_text[] = {
 508         "50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
 509 };
 510
 511 static const struct soc_enum dsp1tx_hpf_cutoff =
 512         SOC_ENUM_SINGLE(WM8996_DSP1_TX_FILTERS, 0, 7, hpf_cutoff_text);
 513
 514 static const struct soc_enum dsp2tx_hpf_cutoff =
 515         SOC_ENUM_SINGLE(WM8996_DSP2_TX_FILTERS, 0, 7, hpf_cutoff_text);
 516
 517 static void wm8996_set_retune_mobile(struct snd_soc_codec *codec, int block)
 518 {
 519         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
 520         struct wm8996_pdata *pdata = &wm8996->pdata;
 521         int base, best, best_val, save, i, cfg, iface;
 522
 523         if (!wm8996->num_retune_mobile_texts)
 524                 return;
 525
 526         switch (block) {
 527         case 0:
 528                 base = WM8996_DSP1_RX_EQ_GAINS_1;
 529                 if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) &
 530                     WM8996_DSP1RX_SRC)
 531                         iface = 1;
 532                 else
 533                         iface = 0;
 534                 break;
 535         case 1:
 536                 base = WM8996_DSP1_RX_EQ_GAINS_2;
 537                 if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) &
 538                     WM8996_DSP2RX_SRC)
 539                         iface = 1;
 540                 else
 541                         iface = 0;
 542                 break;
 543         default:
 544                 return;
 545         }
 546
 547         /* Find the version of the currently selected configuration
 548          * with the nearest sample rate. */
 549         cfg = wm8996->retune_mobile_cfg[block];
 550         best = 0;
 551         best_val = INT_MAX;
 552         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
 553                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
 554                            wm8996->retune_mobile_texts[cfg]) == 0 &&
 555                     abs(pdata->retune_mobile_cfgs[i].rate
 556                         - wm8996->rx_rate[iface]) < best_val) {
 557                         best = i;
 558                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
 559                                        - wm8996->rx_rate[iface]);
 560                 }
 561         }
 562
 563         dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
 564                 block,
 565                 pdata->retune_mobile_cfgs[best].name,
 566                 pdata->retune_mobile_cfgs[best].rate,
 567                 wm8996->rx_rate[iface]);
 568
 569         /* The EQ will be disabled while reconfiguring it, remember the
 570          * current configuration.
 571          */
 572         save = snd_soc_read(codec, base);
 573         save &= WM8996_DSP1RX_EQ_ENA;
 574
 575         for (i = 0; i < ARRAY_SIZE(pdata->retune_mobile_cfgs[best].regs); i++)
 576                 snd_soc_update_bits(codec, base + i, 0xffff,
 577                                     pdata->retune_mobile_cfgs[best].regs[i]);
 578
 579         snd_soc_update_bits(codec, base, WM8996_DSP1RX_EQ_ENA, save);
 580 }
 581
 582 /* Icky as hell but saves code duplication */
 583 static int wm8996_get_retune_mobile_block(const char *name)
 584 {
 585         if (strcmp(name, "DSP1 EQ Mode") == 0)
 586                 return 0;
 587         if (strcmp(name, "DSP2 EQ Mode") == 0)
 588                 return 1;
 589         return -EINVAL;
 590 }
 591
 592 static int wm8996_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 593                                          struct snd_ctl_elem_value *ucontrol)
 594 {
 595         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 596         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
 597         struct wm8996_pdata *pdata = &wm8996->pdata;
 598         int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
 599         int value = ucontrol->value.integer.value[0];
 600
 601         if (block < 0)
 602                 return block;
 603
 604         if (value >= pdata->num_retune_mobile_cfgs)
 605                 return -EINVAL;
 606
 607         wm8996->retune_mobile_cfg[block] = value;
 608
 609         wm8996_set_retune_mobile(codec, block);
 610
 611         return 0;
 612 }
 613
 614 static int wm8996_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 615                                          struct snd_ctl_elem_value *ucontrol)
 616 {
 617         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 618         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
 619         int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
 620
 621         ucontrol->value.enumerated.item[0] = wm8996->retune_mobile_cfg[block];
 622
 623         return 0;
 624 }
 625
 626 static const struct snd_kcontrol_new wm8996_snd_controls[] = {
 627 SOC_DOUBLE_R_TLV("Capture Volume", WM8996_LEFT_LINE_INPUT_VOLUME,
 628                  WM8996_RIGHT_LINE_INPUT_VOLUME, 0, 31, 0, inpga_tlv),
 629 SOC_DOUBLE_R("Capture ZC Switch", WM8996_LEFT_LINE_INPUT_VOLUME,
 630              WM8996_RIGHT_LINE_INPUT_VOLUME, 5, 1, 0),
 631
 632 SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8996_DAC1_MIXER_VOLUMES,
 633                0, 5, 24, 0, sidetone_tlv),
 634 SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8996_DAC2_MIXER_VOLUMES,
 635                0, 5, 24, 0, sidetone_tlv),
 636 SOC_SINGLE("Sidetone LPF Switch", WM8996_SIDETONE, 12, 1, 0),
 637 SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf),
 638 SOC_SINGLE("Sidetone HPF Switch", WM8996_SIDETONE, 6, 1, 0),
 639
 640 SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8996_DSP1_TX_LEFT_VOLUME,
 641                  WM8996_DSP1_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 642 SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8996_DSP2_TX_LEFT_VOLUME,
 643                  WM8996_DSP2_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 644
 645 SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8996_DSP1_TX_FILTERS,
 646            13, 1, 0),
 647 SOC_DOUBLE("DSP1 Capture HPF Switch", WM8996_DSP1_TX_FILTERS, 12, 11, 1, 0),
 648 SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode),
 649 SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff),
 650
 651 SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8996_DSP2_TX_FILTERS,
 652            13, 1, 0),
 653 SOC_DOUBLE("DSP2 Capture HPF Switch", WM8996_DSP2_TX_FILTERS, 12, 11, 1, 0),
 654 SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode),
 655 SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff),
 656
 657 SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8996_DSP1_RX_LEFT_VOLUME,
 658                  WM8996_DSP1_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
 659 SOC_SINGLE("DSP1 Playback Switch", WM8996_DSP1_RX_FILTERS_1, 9, 1, 1),
 660
 661 SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8996_DSP2_RX_LEFT_VOLUME,
 662                  WM8996_DSP2_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
 663 SOC_SINGLE("DSP2 Playback Switch", WM8996_DSP2_RX_FILTERS_1, 9, 1, 1),
 664
 665 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8996_DAC1_LEFT_VOLUME,
 666                  WM8996_DAC1_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
 667 SOC_DOUBLE_R("DAC1 Switch", WM8996_DAC1_LEFT_VOLUME,
 668              WM8996_DAC1_RIGHT_VOLUME, 9, 1, 1),
 669
 670 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8996_DAC2_LEFT_VOLUME,
 671                  WM8996_DAC2_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
 672 SOC_DOUBLE_R("DAC2 Switch", WM8996_DAC2_LEFT_VOLUME,
 673              WM8996_DAC2_RIGHT_VOLUME, 9, 1, 1),
 674
 675 SOC_SINGLE("Speaker High Performance Switch", WM8996_OVERSAMPLING, 3, 1, 0),
 676 SOC_SINGLE("DMIC High Performance Switch", WM8996_OVERSAMPLING, 2, 1, 0),
 677 SOC_SINGLE("ADC High Performance Switch", WM8996_OVERSAMPLING, 1, 1, 0),
 678 SOC_SINGLE("DAC High Performance Switch", WM8996_OVERSAMPLING, 0, 1, 0),
 679
 680 SOC_SINGLE("DAC Soft Mute Switch", WM8996_DAC_SOFTMUTE, 1, 1, 0),
 681 SOC_SINGLE("DAC Slow Soft Mute Switch", WM8996_DAC_SOFTMUTE, 0, 1, 0),
 682
 683 SOC_SINGLE("DSP1 3D Stereo Switch", WM8996_DSP1_RX_FILTERS_2, 8, 1, 0),
 684 SOC_SINGLE("DSP2 3D Stereo Switch", WM8996_DSP2_RX_FILTERS_2, 8, 1, 0),
 685
 686 SOC_SINGLE_TLV("DSP1 3D Stereo Volume", WM8996_DSP1_RX_FILTERS_2, 10, 15,
 687                 0, threedstereo_tlv),
 688 SOC_SINGLE_TLV("DSP2 3D Stereo Volume", WM8996_DSP2_RX_FILTERS_2, 10, 15,
 689                 0, threedstereo_tlv),
 690
 691 SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8996_DAC1_HPOUT1_VOLUME, 0, 4,
 692                8, 0, out_digital_tlv),
 693 SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8996_DAC2_HPOUT2_VOLUME, 0, 4,
 694                8, 0, out_digital_tlv),
 695
 696 SOC_DOUBLE_R_TLV("Output 1 Volume", WM8996_OUTPUT1_LEFT_VOLUME,
 697                  WM8996_OUTPUT1_RIGHT_VOLUME, 0, 12, 0, out_tlv),
 698 SOC_DOUBLE_R("Output 1 ZC Switch",  WM8996_OUTPUT1_LEFT_VOLUME,
 699              WM8996_OUTPUT1_RIGHT_VOLUME, 7, 1, 0),
 700
 701 SOC_DOUBLE_R_TLV("Output 2 Volume", WM8996_OUTPUT2_LEFT_VOLUME,
 702                  WM8996_OUTPUT2_RIGHT_VOLUME, 0, 12, 0, out_tlv),
 703 SOC_DOUBLE_R("Output 2 ZC Switch",  WM8996_OUTPUT2_LEFT_VOLUME,
 704              WM8996_OUTPUT2_RIGHT_VOLUME, 7, 1, 0),
 705
 706 SOC_DOUBLE_TLV("Speaker Volume", WM8996_PDM_SPEAKER_VOLUME, 0, 4, 8, 0,
 707                spk_tlv),
 708 SOC_DOUBLE_R("Speaker Switch", WM8996_LEFT_PDM_SPEAKER,
 709              WM8996_RIGHT_PDM_SPEAKER, 3, 1, 1),
 710 SOC_DOUBLE_R("Speaker ZC Switch", WM8996_LEFT_PDM_SPEAKER,
 711              WM8996_RIGHT_PDM_SPEAKER, 2, 1, 0),
 712
 713 SOC_SINGLE("DSP1 EQ Switch", WM8996_DSP1_RX_EQ_GAINS_1, 0, 1, 0),
 714 SOC_SINGLE("DSP2 EQ Switch", WM8996_DSP2_RX_EQ_GAINS_1, 0, 1, 0),
 715
 716 SOC_SINGLE("DSP1 DRC TXL Switch", WM8996_DSP1_DRC_1, 0, 1, 0),
 717 SOC_SINGLE("DSP1 DRC TXR Switch", WM8996_DSP1_DRC_1, 1, 1, 0),
 718 SOC_SINGLE("DSP1 DRC RX Switch", WM8996_DSP1_DRC_1, 2, 1, 0),
 719
 720 SOC_SINGLE("DSP2 DRC TXL Switch", WM8996_DSP2_DRC_1, 0, 1, 0),
 721 SOC_SINGLE("DSP2 DRC TXR Switch", WM8996_DSP2_DRC_1, 1, 1, 0),
 722 SOC_SINGLE("DSP2 DRC RX Switch", WM8996_DSP2_DRC_1, 2, 1, 0),
 723 };
 724
 725 static const struct snd_kcontrol_new wm8996_eq_controls[] = {
 726 SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 11, 31, 0,
 727                eq_tlv),
 728 SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 6, 31, 0,
 729                eq_tlv),
 730 SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 1, 31, 0,
 731                eq_tlv),
 732 SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 11, 31, 0,
 733                eq_tlv),
 734 SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 6, 31, 0,
 735                eq_tlv),
 736
 737 SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 11, 31, 0,
 738                eq_tlv),
 739 SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 6, 31, 0,
 740                eq_tlv),
 741 SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 1, 31, 0,
 742                eq_tlv),
 743 SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 11, 31, 0,
 744                eq_tlv),
 745 SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 6, 31, 0,
 746                eq_tlv),
 747 };
 748
 749 static void wm8996_bg_enable(struct snd_soc_codec *codec)
 750 {
 751         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
 752
 753         wm8996->bg_ena++;
 754         if (wm8996->bg_ena == 1) {
 755                 snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1,
 756                                     WM8996_BG_ENA, WM8996_BG_ENA);
 757                 msleep(2);
 758         }
 759 }
 760
 761 static void wm8996_bg_disable(struct snd_soc_codec *codec)
 762 {
 763         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
 764
 765         wm8996->bg_ena--;
 766         if (!wm8996->bg_ena)
 767                 snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1,
 768                                     WM8996_BG_ENA, 0);
 769 }
 770
 771 static int bg_event(struct snd_soc_dapm_widget *w,
 772                     struct snd_kcontrol *kcontrol, int event)
 773 {
 774         struct snd_soc_codec *codec = w->codec;
 775         int ret = 0;
 776
 777         switch (event) {
 778         case SND_SOC_DAPM_PRE_PMU:
 779                 wm8996_bg_enable(codec);
 780                 break;
 781         case SND_SOC_DAPM_POST_PMD:
 782                 wm8996_bg_disable(codec);
 783                 break;
 784         default:
 785                 BUG();
 786                 ret = -EINVAL;
 787         }
 788
 789         return ret;
 790 }
 791
 792 static int cp_event(struct snd_soc_dapm_widget *w,
 793                     struct snd_kcontrol *kcontrol, int event)
 794 {
 795         struct snd_soc_codec *codec = w->codec;
 796         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
 797         int ret = 0;
 798
 799         switch (event) {
 800         case SND_SOC_DAPM_PRE_PMU:
 801                 ret = regulator_enable(wm8996->cpvdd);
 802                 if (ret != 0)
 803                         dev_err(codec->dev, "Failed to enable CPVDD: %d\n",
 804                                 ret);
 805                 break;
 806         case SND_SOC_DAPM_POST_PMU:
 807                 msleep(5);
 808                 break;
 809         case SND_SOC_DAPM_POST_PMD:
 810                 regulator_disable_deferred(wm8996->cpvdd, 20);
 811                 break;
 812         default:
 813                 BUG();
 814                 ret = -EINVAL;
 815         }
 816
 817         return ret;
 818 }
 819
 820 static int rmv_short_event(struct snd_soc_dapm_widget *w,
 821                            struct snd_kcontrol *kcontrol, int event)
 822 {
 823         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec);
 824
 825         /* Record which outputs we enabled */
 826         switch (event) {
 827         case SND_SOC_DAPM_PRE_PMD:
 828                 wm8996->hpout_pending &= ~w->shift;
 829                 break;
 830         case SND_SOC_DAPM_PRE_PMU:
 831                 wm8996->hpout_pending |= w->shift;
 832                 break;
 833         default:
 834                 BUG();
 835                 return -EINVAL;
 836         }
 837
 838         return 0;
 839 }
 840
 841 static void wait_for_dc_servo(struct snd_soc_codec *codec, u16 mask)
 842 {
 843         struct i2c_client *i2c = to_i2c_client(codec->dev);
 844         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
 845         int ret;
 846         unsigned long timeout = 200;
 847
 848         snd_soc_write(codec, WM8996_DC_SERVO_2, mask);
 849
 850         /* Use the interrupt if possible */
 851         do {
 852                 if (i2c->irq) {
 853                         timeout = wait_for_completion_timeout(&wm8996->dcs_done,
 854                                                               msecs_to_jiffies(200));
 855                         if (timeout == 0)
 856                                 dev_err(codec->dev, "DC servo timed out\n");
 857
 858                 } else {
 859                         msleep(1);
 860                         timeout--;
 861                 }
 862
 863                 ret = snd_soc_read(codec, WM8996_DC_SERVO_2);
 864                 dev_dbg(codec->dev, "DC servo state: %x\n", ret);
 865         } while (timeout && ret & mask);
 866
 867         if (timeout == 0)
 868                 dev_err(codec->dev, "DC servo timed out for %x\n", mask);
 869         else
 870                 dev_dbg(codec->dev, "DC servo complete for %x\n", mask);
 871 }
 872
 873 static void wm8996_seq_notifier(struct snd_soc_dapm_context *dapm,
 874                                 enum snd_soc_dapm_type event, int subseq)
 875 {
 876         struct snd_soc_codec *codec = container_of(dapm,
 877                                                    struct snd_soc_codec, dapm);
 878         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
 879         u16 val, mask;
 880
 881         /* Complete any pending DC servo starts */
 882         if (wm8996->dcs_pending) {
 883                 dev_dbg(codec->dev, "Starting DC servo for %x\n",
 884                         wm8996->dcs_pending);
 885
 886                 /* Trigger a startup sequence */
 887                 wait_for_dc_servo(codec, wm8996->dcs_pending
 888                                          << WM8996_DCS_TRIG_STARTUP_0_SHIFT);
 889
 890                 wm8996->dcs_pending = 0;
 891         }
 892
 893         if (wm8996->hpout_pending != wm8996->hpout_ena) {
 894                 dev_dbg(codec->dev, "Applying RMV_SHORTs %x->%x\n",
 895                         wm8996->hpout_ena, wm8996->hpout_pending);
 896
 897                 val = 0;
 898                 mask = 0;
 899                 if (wm8996->hpout_pending & HPOUT1L) {
 900                         val |= WM8996_HPOUT1L_RMV_SHORT;
 901                         mask |= WM8996_HPOUT1L_RMV_SHORT;
 902                 } else {
 903                         mask |= WM8996_HPOUT1L_RMV_SHORT |
 904                                 WM8996_HPOUT1L_OUTP |
 905                                 WM8996_HPOUT1L_DLY;
 906                 }
 907
 908                 if (wm8996->hpout_pending & HPOUT1R) {
 909                         val |= WM8996_HPOUT1R_RMV_SHORT;
 910                         mask |= WM8996_HPOUT1R_RMV_SHORT;
 911                 } else {
 912                         mask |= WM8996_HPOUT1R_RMV_SHORT |
 913                                 WM8996_HPOUT1R_OUTP |
 914                                 WM8996_HPOUT1R_DLY;
 915                 }
 916
 917                 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1, mask, val);
 918
 919                 val = 0;
 920                 mask = 0;
 921                 if (wm8996->hpout_pending & HPOUT2L) {
 922                         val |= WM8996_HPOUT2L_RMV_SHORT;
 923                         mask |= WM8996_HPOUT2L_RMV_SHORT;
 924                 } else {
 925                         mask |= WM8996_HPOUT2L_RMV_SHORT |
 926                                 WM8996_HPOUT2L_OUTP |
 927                                 WM8996_HPOUT2L_DLY;
 928                 }
 929
 930                 if (wm8996->hpout_pending & HPOUT2R) {
 931                         val |= WM8996_HPOUT2R_RMV_SHORT;
 932                         mask |= WM8996_HPOUT2R_RMV_SHORT;
 933                 } else {
 934                         mask |= WM8996_HPOUT2R_RMV_SHORT |
 935                                 WM8996_HPOUT2R_OUTP |
 936                                 WM8996_HPOUT2R_DLY;
 937                 }
 938
 939                 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_2, mask, val);
 940
 941                 wm8996->hpout_ena = wm8996->hpout_pending;
 942         }
 943 }
 944
 945 static int dcs_start(struct snd_soc_dapm_widget *w,
 946                      struct snd_kcontrol *kcontrol, int event)
 947 {
 948         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec);
 949
 950         switch (event) {
 951         case SND_SOC_DAPM_POST_PMU:
 952                 wm8996->dcs_pending |= 1 << w->shift;
 953                 break;
 954         default:
 955                 BUG();
 956                 return -EINVAL;
 957         }
 958
 959         return 0;
 960 }
 961
 962 static const char *sidetone_text[] = {
 963         "IN1", "IN2",
 964 };
 965
 966 static const struct soc_enum left_sidetone_enum =
 967         SOC_ENUM_SINGLE(WM8996_SIDETONE, 0, 2, sidetone_text);
 968
 969 static const struct snd_kcontrol_new left_sidetone =
 970         SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum);
 971
 972 static const struct soc_enum right_sidetone_enum =
 973         SOC_ENUM_SINGLE(WM8996_SIDETONE, 1, 2, sidetone_text);
 974
 975 static const struct snd_kcontrol_new right_sidetone =
 976         SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum);
 977
 978 static const char *spk_text[] = {
 979         "DAC1L", "DAC1R", "DAC2L", "DAC2R"
 980 };
 981
 982 static const struct soc_enum spkl_enum =
 983         SOC_ENUM_SINGLE(WM8996_LEFT_PDM_SPEAKER, 0, 4, spk_text);
 984
 985 static const struct snd_kcontrol_new spkl_mux =
 986         SOC_DAPM_ENUM("SPKL", spkl_enum);
 987
 988 static const struct soc_enum spkr_enum =
 989         SOC_ENUM_SINGLE(WM8996_RIGHT_PDM_SPEAKER, 0, 4, spk_text);
 990
 991 static const struct snd_kcontrol_new spkr_mux =
 992         SOC_DAPM_ENUM("SPKR", spkr_enum);
 993
 994 static const char *dsp1rx_text[] = {
 995         "AIF1", "AIF2"
 996 };
 997
 998 static const struct soc_enum dsp1rx_enum =
 999         SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 0, 2, dsp1rx_text);
1000
1001 static const struct snd_kcontrol_new dsp1rx =
1002         SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum);
1003
1004 static const char *dsp2rx_text[] = {
1005          "AIF2", "AIF1"
1006 };
1007
1008 static const struct soc_enum dsp2rx_enum =
1009         SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 4, 2, dsp2rx_text);
1010
1011 static const struct snd_kcontrol_new dsp2rx =
1012         SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum);
1013
1014 static const char *aif2tx_text[] = {
1015         "DSP2", "DSP1", "AIF1"
1016 };
1017
1018 static const struct soc_enum aif2tx_enum =
1019         SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 6, 3, aif2tx_text);
1020
1021 static const struct snd_kcontrol_new aif2tx =
1022         SOC_DAPM_ENUM("AIF2TX", aif2tx_enum);
1023
1024 static const char *inmux_text[] = {
1025         "ADC", "DMIC1", "DMIC2"
1026 };
1027
1028 static const struct soc_enum in1_enum =
1029         SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_7, 0, 3, inmux_text);
1030
1031 static const struct snd_kcontrol_new in1_mux =
1032         SOC_DAPM_ENUM("IN1 Mux", in1_enum);
1033
1034 static const struct soc_enum in2_enum =
1035         SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_7, 4, 3, inmux_text);
1036
1037 static const struct snd_kcontrol_new in2_mux =
1038         SOC_DAPM_ENUM("IN2 Mux", in2_enum);
1039
1040 static const struct snd_kcontrol_new dac2r_mix[] = {
1041 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
1042                 5, 1, 0),
1043 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
1044                 4, 1, 0),
1045 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 1, 1, 0),
1046 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 0, 1, 0),
1047 };
1048
1049 static const struct snd_kcontrol_new dac2l_mix[] = {
1050 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
1051                 5, 1, 0),
1052 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
1053                 4, 1, 0),
1054 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 1, 1, 0),
1055 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 0, 1, 0),
1056 };
1057
1058 static const struct snd_kcontrol_new dac1r_mix[] = {
1059 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
1060                 5, 1, 0),
1061 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
1062                 4, 1, 0),
1063 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 1, 1, 0),
1064 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 0, 1, 0),
1065 };
1066
1067 static const struct snd_kcontrol_new dac1l_mix[] = {
1068 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
1069                 5, 1, 0),
1070 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
1071                 4, 1, 0),
1072 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 1, 1, 0),
1073 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 0, 1, 0),
1074 };
1075
1076 static const struct snd_kcontrol_new dsp1txl[] = {
1077 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
1078                 1, 1, 0),
1079 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
1080                 0, 1, 0),
1081 };
1082
1083 static const struct snd_kcontrol_new dsp1txr[] = {
1084 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
1085                 1, 1, 0),
1086 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
1087                 0, 1, 0),
1088 };
1089
1090 static const struct snd_kcontrol_new dsp2txl[] = {
1091 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
1092                 1, 1, 0),
1093 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
1094                 0, 1, 0),
1095 };
1096
1097 static const struct snd_kcontrol_new dsp2txr[] = {
1098 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
1099                 1, 1, 0),
1100 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
1101                 0, 1, 0),
1102 };
1103
1104
1105 static const struct snd_soc_dapm_widget wm8996_dapm_widgets[] = {
1106 SND_SOC_DAPM_INPUT("IN1LN"),
1107 SND_SOC_DAPM_INPUT("IN1LP"),
1108 SND_SOC_DAPM_INPUT("IN1RN"),
1109 SND_SOC_DAPM_INPUT("IN1RP"),
1110
1111 SND_SOC_DAPM_INPUT("IN2LN"),
1112 SND_SOC_DAPM_INPUT("IN2LP"),
1113 SND_SOC_DAPM_INPUT("IN2RN"),
1114 SND_SOC_DAPM_INPUT("IN2RP"),
1115
1116 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1117 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1118
1119 SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8996_AIF_CLOCKING_1, 0, 0, NULL, 0),
1120 SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8996_CLOCKING_1, 1, 0, NULL, 0),
1121 SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8996_CLOCKING_1, 2, 0, NULL, 0),
1122 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8996_CHARGE_PUMP_1, 15, 0, cp_event,
1123                       SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1124                       SND_SOC_DAPM_POST_PMD),
1125 SND_SOC_DAPM_SUPPLY("Bandgap", SND_SOC_NOPM, 0, 0, bg_event,
1126                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1127 SND_SOC_DAPM_SUPPLY("LDO2", WM8996_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
1128 SND_SOC_DAPM_SUPPLY("MICB1 Audio", WM8996_MICBIAS_1, 4, 1, NULL, 0),
1129 SND_SOC_DAPM_SUPPLY("MICB2 Audio", WM8996_MICBIAS_2, 4, 1, NULL, 0),
1130 SND_SOC_DAPM_MICBIAS("MICB2", WM8996_POWER_MANAGEMENT_1, 9, 0),
1131 SND_SOC_DAPM_MICBIAS("MICB1", WM8996_POWER_MANAGEMENT_1, 8, 0),
1132
1133 SND_SOC_DAPM_PGA("IN1L PGA", WM8996_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
1134 SND_SOC_DAPM_PGA("IN1R PGA", WM8996_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
1135
1136 SND_SOC_DAPM_MUX("IN1L Mux", WM8996_POWER_MANAGEMENT_7, 2, 0, &in1_mux),
1137 SND_SOC_DAPM_MUX("IN1R Mux", WM8996_POWER_MANAGEMENT_7, 3, 0, &in1_mux),
1138 SND_SOC_DAPM_MUX("IN2L Mux", WM8996_POWER_MANAGEMENT_7, 6, 0, &in2_mux),
1139 SND_SOC_DAPM_MUX("IN2R Mux", WM8996_POWER_MANAGEMENT_7, 7, 0, &in2_mux),
1140
1141 SND_SOC_DAPM_SUPPLY("DMIC2", WM8996_POWER_MANAGEMENT_7, 9, 0, NULL, 0),
1142 SND_SOC_DAPM_SUPPLY("DMIC1", WM8996_POWER_MANAGEMENT_7, 8, 0, NULL, 0),
1143
1144 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8996_POWER_MANAGEMENT_3, 5, 0),
1145 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8996_POWER_MANAGEMENT_3, 4, 0),
1146 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8996_POWER_MANAGEMENT_3, 3, 0),
1147 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8996_POWER_MANAGEMENT_3, 2, 0),
1148
1149 SND_SOC_DAPM_ADC("ADCL", NULL, WM8996_POWER_MANAGEMENT_3, 1, 0),
1150 SND_SOC_DAPM_ADC("ADCR", NULL, WM8996_POWER_MANAGEMENT_3, 0, 0),
1151
1152 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &left_sidetone),
1153 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &right_sidetone),
1154
1155 SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 11, 0),
1156 SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 10, 0),
1157 SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 9, 0),
1158 SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 8, 0),
1159
1160 SND_SOC_DAPM_MIXER("DSP2TXL", WM8996_POWER_MANAGEMENT_5, 11, 0,
1161                    dsp2txl, ARRAY_SIZE(dsp2txl)),
1162 SND_SOC_DAPM_MIXER("DSP2TXR", WM8996_POWER_MANAGEMENT_5, 10, 0,
1163                    dsp2txr, ARRAY_SIZE(dsp2txr)),
1164 SND_SOC_DAPM_MIXER("DSP1TXL", WM8996_POWER_MANAGEMENT_5, 9, 0,
1165                    dsp1txl, ARRAY_SIZE(dsp1txl)),
1166 SND_SOC_DAPM_MIXER("DSP1TXR", WM8996_POWER_MANAGEMENT_5, 8, 0,
1167                    dsp1txr, ARRAY_SIZE(dsp1txr)),
1168
1169 SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1170                    dac2l_mix, ARRAY_SIZE(dac2l_mix)),
1171 SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1172                    dac2r_mix, ARRAY_SIZE(dac2r_mix)),
1173 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1174                    dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1175 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1176                    dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1177
1178 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8996_POWER_MANAGEMENT_5, 3, 0),
1179 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8996_POWER_MANAGEMENT_5, 2, 0),
1180 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8996_POWER_MANAGEMENT_5, 1, 0),
1181 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8996_POWER_MANAGEMENT_5, 0, 0),
1182
1183 SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 0,
1184                     WM8996_POWER_MANAGEMENT_4, 9, 0),
1185 SND_SOC_DAPM_AIF_IN("AIF2RX0", "AIF2 Playback", 1,
1186                     WM8996_POWER_MANAGEMENT_4, 8, 0),
1187
1188 SND_SOC_DAPM_AIF_OUT("AIF2TX1", "AIF2 Capture", 0,
1189                     WM8996_POWER_MANAGEMENT_6, 9, 0),
1190 SND_SOC_DAPM_AIF_OUT("AIF2TX0", "AIF2 Capture", 1,
1191                     WM8996_POWER_MANAGEMENT_6, 8, 0),
1192
1193 SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 5,
1194                     WM8996_POWER_MANAGEMENT_4, 5, 0),
1195 SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 4,
1196                     WM8996_POWER_MANAGEMENT_4, 4, 0),
1197 SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 3,
1198                     WM8996_POWER_MANAGEMENT_4, 3, 0),
1199 SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 2,
1200                     WM8996_POWER_MANAGEMENT_4, 2, 0),
1201 SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 1,
1202                     WM8996_POWER_MANAGEMENT_4, 1, 0),
1203 SND_SOC_DAPM_AIF_IN("AIF1RX0", "AIF1 Playback", 0,
1204                     WM8996_POWER_MANAGEMENT_4, 0, 0),
1205
1206 SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 5,
1207                      WM8996_POWER_MANAGEMENT_6, 5, 0),
1208 SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 4,
1209                      WM8996_POWER_MANAGEMENT_6, 4, 0),
1210 SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 3,
1211                      WM8996_POWER_MANAGEMENT_6, 3, 0),
1212 SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 2,
1213                      WM8996_POWER_MANAGEMENT_6, 2, 0),
1214 SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 1,
1215                      WM8996_POWER_MANAGEMENT_6, 1, 0),
1216 SND_SOC_DAPM_AIF_OUT("AIF1TX0", "AIF1 Capture", 0,
1217                      WM8996_POWER_MANAGEMENT_6, 0, 0),
1218
1219 /* We route as stereo pairs so define some dummy widgets to squash
1220  * things down for now.  RXA = 0,1, RXB = 2,3 and so on */
1221 SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 0, NULL, 0),
1222 SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 0, NULL, 0),
1223 SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 0, NULL, 0),
1224 SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0, NULL, 0),
1225 SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0, NULL, 0),
1226
1227 SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0, &dsp1rx),
1228 SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0, &dsp2rx),
1229 SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0, &aif2tx),
1230
1231 SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, &spkl_mux),
1232 SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, &spkr_mux),
1233 SND_SOC_DAPM_PGA("SPKL PGA", WM8996_LEFT_PDM_SPEAKER, 4, 0, NULL, 0),
1234 SND_SOC_DAPM_PGA("SPKR PGA", WM8996_RIGHT_PDM_SPEAKER, 4, 0, NULL, 0),
1235
1236 SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8996_POWER_MANAGEMENT_1, 7, 0, NULL, 0),
1237 SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8996_ANALOGUE_HP_2, 5, 0, NULL, 0),
1238 SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8996_DC_SERVO_1, 2, 0, dcs_start,
1239                    SND_SOC_DAPM_POST_PMU),
1240 SND_SOC_DAPM_PGA_S("HPOUT2L_OUTP", 3, WM8996_ANALOGUE_HP_2, 6, 0, NULL, 0),
1241 SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2L, 0,
1242                    rmv_short_event,
1243                    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1244
1245 SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8996_POWER_MANAGEMENT_1, 6, 0,NULL, 0),
1246 SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8996_ANALOGUE_HP_2, 1, 0, NULL, 0),
1247 SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8996_DC_SERVO_1, 3, 0, dcs_start,
1248                    SND_SOC_DAPM_POST_PMU),
1249 SND_SOC_DAPM_PGA_S("HPOUT2R_OUTP", 3, WM8996_ANALOGUE_HP_2, 2, 0, NULL, 0),
1250 SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2R, 0,
1251                    rmv_short_event,
1252                    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1253
1254 SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8996_POWER_MANAGEMENT_1, 5, 0, NULL, 0),
1255 SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8996_ANALOGUE_HP_1, 5, 0, NULL, 0),
1256 SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8996_DC_SERVO_1, 0, 0, dcs_start,
1257                    SND_SOC_DAPM_POST_PMU),
1258 SND_SOC_DAPM_PGA_S("HPOUT1L_OUTP", 3, WM8996_ANALOGUE_HP_1, 6, 0, NULL, 0),
1259 SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1L, 0,
1260                    rmv_short_event,
1261                    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1262
1263 SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8996_POWER_MANAGEMENT_1, 4, 0, NULL, 0),
1264 SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8996_ANALOGUE_HP_1, 1, 0, NULL, 0),
1265 SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8996_DC_SERVO_1, 1, 0, dcs_start,
1266                    SND_SOC_DAPM_POST_PMU),
1267 SND_SOC_DAPM_PGA_S("HPOUT1R_OUTP", 3, WM8996_ANALOGUE_HP_1, 2, 0, NULL, 0),
1268 SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1R, 0,
1269                    rmv_short_event,
1270                    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1271
1272 SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1273 SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1274 SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1275 SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1276 SND_SOC_DAPM_OUTPUT("SPKDAT"),
1277 };
1278
1279 static const struct snd_soc_dapm_route wm8996_dapm_routes[] = {
1280         { "AIFCLK", NULL, "SYSCLK" },
1281         { "SYSDSPCLK", NULL, "SYSCLK" },
1282         { "Charge Pump", NULL, "SYSCLK" },
1283
1284         { "MICB1", NULL, "LDO2" },
1285         { "MICB1", NULL, "MICB1 Audio" },
1286         { "MICB1", NULL, "Bandgap" },
1287         { "MICB2", NULL, "LDO2" },
1288         { "MICB2", NULL, "MICB2 Audio" },
1289         { "MICB2", NULL, "Bandgap" },
1290
1291         { "IN1L PGA", NULL, "IN2LN" },
1292         { "IN1L PGA", NULL, "IN2LP" },
1293         { "IN1L PGA", NULL, "IN1LN" },
1294         { "IN1L PGA", NULL, "IN1LP" },
1295         { "IN1L PGA", NULL, "Bandgap" },
1296
1297         { "IN1R PGA", NULL, "IN2RN" },
1298         { "IN1R PGA", NULL, "IN2RP" },
1299         { "IN1R PGA", NULL, "IN1RN" },
1300         { "IN1R PGA", NULL, "IN1RP" },
1301         { "IN1R PGA", NULL, "Bandgap" },
1302
1303         { "ADCL", NULL, "IN1L PGA" },
1304
1305         { "ADCR", NULL, "IN1R PGA" },
1306
1307         { "DMIC1L", NULL, "DMIC1DAT" },
1308         { "DMIC1R", NULL, "DMIC1DAT" },
1309         { "DMIC2L", NULL, "DMIC2DAT" },
1310         { "DMIC2R", NULL, "DMIC2DAT" },
1311
1312         { "DMIC2L", NULL, "DMIC2" },
1313         { "DMIC2R", NULL, "DMIC2" },
1314         { "DMIC1L", NULL, "DMIC1" },
1315         { "DMIC1R", NULL, "DMIC1" },
1316
1317         { "IN1L Mux", "ADC", "ADCL" },
1318         { "IN1L Mux", "DMIC1", "DMIC1L" },
1319         { "IN1L Mux", "DMIC2", "DMIC2L" },
1320
1321         { "IN1R Mux", "ADC", "ADCR" },
1322         { "IN1R Mux", "DMIC1", "DMIC1R" },
1323         { "IN1R Mux", "DMIC2", "DMIC2R" },
1324
1325         { "IN2L Mux", "ADC", "ADCL" },
1326         { "IN2L Mux", "DMIC1", "DMIC1L" },
1327         { "IN2L Mux", "DMIC2", "DMIC2L" },
1328
1329         { "IN2R Mux", "ADC", "ADCR" },
1330         { "IN2R Mux", "DMIC1", "DMIC1R" },
1331         { "IN2R Mux", "DMIC2", "DMIC2R" },
1332
1333         { "Left Sidetone", "IN1", "IN1L Mux" },
1334         { "Left Sidetone", "IN2", "IN2L Mux" },
1335
1336         { "Right Sidetone", "IN1", "IN1R Mux" },
1337         { "Right Sidetone", "IN2", "IN2R Mux" },
1338
1339         { "DSP1TXL", "IN1 Switch", "IN1L Mux" },
1340         { "DSP1TXR", "IN1 Switch", "IN1R Mux" },
1341
1342         { "DSP2TXL", "IN1 Switch", "IN2L Mux" },
1343         { "DSP2TXR", "IN1 Switch", "IN2R Mux" },
1344
1345         { "AIF1TX0", NULL, "DSP1TXL" },
1346         { "AIF1TX1", NULL, "DSP1TXR" },
1347         { "AIF1TX2", NULL, "DSP2TXL" },
1348         { "AIF1TX3", NULL, "DSP2TXR" },
1349         { "AIF1TX4", NULL, "AIF2RX0" },
1350         { "AIF1TX5", NULL, "AIF2RX1" },
1351
1352         { "AIF1RX0", NULL, "AIFCLK" },
1353         { "AIF1RX1", NULL, "AIFCLK" },
1354         { "AIF1RX2", NULL, "AIFCLK" },
1355         { "AIF1RX3", NULL, "AIFCLK" },
1356         { "AIF1RX4", NULL, "AIFCLK" },
1357         { "AIF1RX5", NULL, "AIFCLK" },
1358
1359         { "AIF2RX0", NULL, "AIFCLK" },
1360         { "AIF2RX1", NULL, "AIFCLK" },
1361
1362         { "AIF1TX0", NULL, "AIFCLK" },
1363         { "AIF1TX1", NULL, "AIFCLK" },
1364         { "AIF1TX2", NULL, "AIFCLK" },
1365         { "AIF1TX3", NULL, "AIFCLK" },
1366         { "AIF1TX4", NULL, "AIFCLK" },
1367         { "AIF1TX5", NULL, "AIFCLK" },
1368
1369         { "AIF2TX0", NULL, "AIFCLK" },
1370         { "AIF2TX1", NULL, "AIFCLK" },
1371
1372         { "DSP1RXL", NULL, "SYSDSPCLK" },
1373         { "DSP1RXR", NULL, "SYSDSPCLK" },
1374         { "DSP2RXL", NULL, "SYSDSPCLK" },
1375         { "DSP2RXR", NULL, "SYSDSPCLK" },
1376         { "DSP1TXL", NULL, "SYSDSPCLK" },
1377         { "DSP1TXR", NULL, "SYSDSPCLK" },
1378         { "DSP2TXL", NULL, "SYSDSPCLK" },
1379         { "DSP2TXR", NULL, "SYSDSPCLK" },
1380
1381         { "AIF1RXA", NULL, "AIF1RX0" },
1382         { "AIF1RXA", NULL, "AIF1RX1" },
1383         { "AIF1RXB", NULL, "AIF1RX2" },
1384         { "AIF1RXB", NULL, "AIF1RX3" },
1385         { "AIF1RXC", NULL, "AIF1RX4" },
1386         { "AIF1RXC", NULL, "AIF1RX5" },
1387
1388         { "AIF2RX", NULL, "AIF2RX0" },
1389         { "AIF2RX", NULL, "AIF2RX1" },
1390
1391         { "AIF2TX", "DSP2", "DSP2TX" },
1392         { "AIF2TX", "DSP1", "DSP1RX" },
1393         { "AIF2TX", "AIF1", "AIF1RXC" },
1394
1395         { "DSP1RXL", NULL, "DSP1RX" },
1396         { "DSP1RXR", NULL, "DSP1RX" },
1397         { "DSP2RXL", NULL, "DSP2RX" },
1398         { "DSP2RXR", NULL, "DSP2RX" },
1399
1400         { "DSP2TX", NULL, "DSP2TXL" },
1401         { "DSP2TX", NULL, "DSP2TXR" },
1402
1403         { "DSP1RX", "AIF1", "AIF1RXA" },
1404         { "DSP1RX", "AIF2", "AIF2RX" },
1405
1406         { "DSP2RX", "AIF1", "AIF1RXB" },
1407         { "DSP2RX", "AIF2", "AIF2RX" },
1408
1409         { "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" },
1410         { "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" },
1411         { "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1412         { "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1413
1414         { "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" },
1415         { "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" },
1416         { "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1417         { "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1418
1419         { "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" },
1420         { "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" },
1421         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1422         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1423
1424         { "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" },
1425         { "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" },
1426         { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1427         { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1428
1429         { "DAC1L", NULL, "DAC1L Mixer" },
1430         { "DAC1R", NULL, "DAC1R Mixer" },
1431         { "DAC2L", NULL, "DAC2L Mixer" },
1432         { "DAC2R", NULL, "DAC2R Mixer" },
1433
1434         { "HPOUT2L PGA", NULL, "Charge Pump" },
1435         { "HPOUT2L PGA", NULL, "Bandgap" },
1436         { "HPOUT2L PGA", NULL, "DAC2L" },
1437         { "HPOUT2L_DLY", NULL, "HPOUT2L PGA" },
1438         { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" },
1439         { "HPOUT2L_OUTP", NULL, "HPOUT2L_DCS" },
1440         { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L_OUTP" },
1441
1442         { "HPOUT2R PGA", NULL, "Charge Pump" },
1443         { "HPOUT2R PGA", NULL, "Bandgap" },
1444         { "HPOUT2R PGA", NULL, "DAC2R" },
1445         { "HPOUT2R_DLY", NULL, "HPOUT2R PGA" },
1446         { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" },
1447         { "HPOUT2R_OUTP", NULL, "HPOUT2R_DCS" },
1448         { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R_OUTP" },
1449
1450         { "HPOUT1L PGA", NULL, "Charge Pump" },
1451         { "HPOUT1L PGA", NULL, "Bandgap" },
1452         { "HPOUT1L PGA", NULL, "DAC1L" },
1453         { "HPOUT1L_DLY", NULL, "HPOUT1L PGA" },
1454         { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" },
1455         { "HPOUT1L_OUTP", NULL, "HPOUT1L_DCS" },
1456         { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L_OUTP" },
1457
1458         { "HPOUT1R PGA", NULL, "Charge Pump" },
1459         { "HPOUT1R PGA", NULL, "Bandgap" },
1460         { "HPOUT1R PGA", NULL, "DAC1R" },
1461         { "HPOUT1R_DLY", NULL, "HPOUT1R PGA" },
1462         { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" },
1463         { "HPOUT1R_OUTP", NULL, "HPOUT1R_DCS" },
1464         { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R_OUTP" },
1465
1466         { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT" },
1467         { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT" },
1468         { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT" },
1469         { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT" },
1470
1471         { "SPKL", "DAC1L", "DAC1L" },
1472         { "SPKL", "DAC1R", "DAC1R" },
1473         { "SPKL", "DAC2L", "DAC2L" },
1474         { "SPKL", "DAC2R", "DAC2R" },
1475
1476         { "SPKR", "DAC1L", "DAC1L" },
1477         { "SPKR", "DAC1R", "DAC1R" },
1478         { "SPKR", "DAC2L", "DAC2L" },
1479         { "SPKR", "DAC2R", "DAC2R" },
1480
1481         { "SPKL PGA", NULL, "SPKL" },
1482         { "SPKR PGA", NULL, "SPKR" },
1483
1484         { "SPKDAT", NULL, "SPKL PGA" },
1485         { "SPKDAT", NULL, "SPKR PGA" },
1486 };
1487
1488 static bool wm8996_readable_register(struct device *dev, unsigned int reg)
1489 {
1490         /* Due to the sparseness of the register map the compiler
1491          * output from an explicit switch statement ends up being much
1492          * more efficient than a table.
1493          */
1494         switch (reg) {
1495         case WM8996_SOFTWARE_RESET:
1496         case WM8996_POWER_MANAGEMENT_1:
1497         case WM8996_POWER_MANAGEMENT_2:
1498         case WM8996_POWER_MANAGEMENT_3:
1499         case WM8996_POWER_MANAGEMENT_4:
1500         case WM8996_POWER_MANAGEMENT_5:
1501         case WM8996_POWER_MANAGEMENT_6:
1502         case WM8996_POWER_MANAGEMENT_7:
1503         case WM8996_POWER_MANAGEMENT_8:
1504         case WM8996_LEFT_LINE_INPUT_VOLUME:
1505         case WM8996_RIGHT_LINE_INPUT_VOLUME:
1506         case WM8996_LINE_INPUT_CONTROL:
1507         case WM8996_DAC1_HPOUT1_VOLUME:
1508         case WM8996_DAC2_HPOUT2_VOLUME:
1509         case WM8996_DAC1_LEFT_VOLUME:
1510         case WM8996_DAC1_RIGHT_VOLUME:
1511         case WM8996_DAC2_LEFT_VOLUME:
1512         case WM8996_DAC2_RIGHT_VOLUME:
1513         case WM8996_OUTPUT1_LEFT_VOLUME:
1514         case WM8996_OUTPUT1_RIGHT_VOLUME:
1515         case WM8996_OUTPUT2_LEFT_VOLUME:
1516         case WM8996_OUTPUT2_RIGHT_VOLUME:
1517         case WM8996_MICBIAS_1:
1518         case WM8996_MICBIAS_2:
1519         case WM8996_LDO_1:
1520         case WM8996_LDO_2:
1521         case WM8996_ACCESSORY_DETECT_MODE_1:
1522         case WM8996_ACCESSORY_DETECT_MODE_2:
1523         case WM8996_HEADPHONE_DETECT_1:
1524         case WM8996_HEADPHONE_DETECT_2:
1525         case WM8996_MIC_DETECT_1:
1526         case WM8996_MIC_DETECT_2:
1527         case WM8996_MIC_DETECT_3:
1528         case WM8996_CHARGE_PUMP_1:
1529         case WM8996_CHARGE_PUMP_2:
1530         case WM8996_DC_SERVO_1:
1531         case WM8996_DC_SERVO_2:
1532         case WM8996_DC_SERVO_3:
1533         case WM8996_DC_SERVO_5:
1534         case WM8996_DC_SERVO_6:
1535         case WM8996_DC_SERVO_7:
1536         case WM8996_DC_SERVO_READBACK_0:
1537         case WM8996_ANALOGUE_HP_1:
1538         case WM8996_ANALOGUE_HP_2:
1539         case WM8996_CHIP_REVISION:
1540         case WM8996_CONTROL_INTERFACE_1:
1541         case WM8996_WRITE_SEQUENCER_CTRL_1:
1542         case WM8996_WRITE_SEQUENCER_CTRL_2:
1543         case WM8996_AIF_CLOCKING_1:
1544         case WM8996_AIF_CLOCKING_2:
1545         case WM8996_CLOCKING_1:
1546         case WM8996_CLOCKING_2:
1547         case WM8996_AIF_RATE:
1548         case WM8996_FLL_CONTROL_1:
1549         case WM8996_FLL_CONTROL_2:
1550         case WM8996_FLL_CONTROL_3:
1551         case WM8996_FLL_CONTROL_4:
1552         case WM8996_FLL_CONTROL_5:
1553         case WM8996_FLL_CONTROL_6:
1554         case WM8996_FLL_EFS_1:
1555         case WM8996_FLL_EFS_2:
1556         case WM8996_AIF1_CONTROL:
1557         case WM8996_AIF1_BCLK:
1558         case WM8996_AIF1_TX_LRCLK_1:
1559         case WM8996_AIF1_TX_LRCLK_2:
1560         case WM8996_AIF1_RX_LRCLK_1:
1561         case WM8996_AIF1_RX_LRCLK_2:
1562         case WM8996_AIF1TX_DATA_CONFIGURATION_1:
1563         case WM8996_AIF1TX_DATA_CONFIGURATION_2:
1564         case WM8996_AIF1RX_DATA_CONFIGURATION:
1565         case WM8996_AIF1TX_CHANNEL_0_CONFIGURATION:
1566         case WM8996_AIF1TX_CHANNEL_1_CONFIGURATION:
1567         case WM8996_AIF1TX_CHANNEL_2_CONFIGURATION:
1568         case WM8996_AIF1TX_CHANNEL_3_CONFIGURATION:
1569         case WM8996_AIF1TX_CHANNEL_4_CONFIGURATION:
1570         case WM8996_AIF1TX_CHANNEL_5_CONFIGURATION:
1571         case WM8996_AIF1RX_CHANNEL_0_CONFIGURATION:
1572         case WM8996_AIF1RX_CHANNEL_1_CONFIGURATION:
1573         case WM8996_AIF1RX_CHANNEL_2_CONFIGURATION:
1574         case WM8996_AIF1RX_CHANNEL_3_CONFIGURATION:
1575         case WM8996_AIF1RX_CHANNEL_4_CONFIGURATION:
1576         case WM8996_AIF1RX_CHANNEL_5_CONFIGURATION:
1577         case WM8996_AIF1RX_MONO_CONFIGURATION:
1578         case WM8996_AIF1TX_TEST:
1579         case WM8996_AIF2_CONTROL:
1580         case WM8996_AIF2_BCLK:
1581         case WM8996_AIF2_TX_LRCLK_1:
1582         case WM8996_AIF2_TX_LRCLK_2:
1583         case WM8996_AIF2_RX_LRCLK_1:
1584         case WM8996_AIF2_RX_LRCLK_2:
1585         case WM8996_AIF2TX_DATA_CONFIGURATION_1:
1586         case WM8996_AIF2TX_DATA_CONFIGURATION_2:
1587         case WM8996_AIF2RX_DATA_CONFIGURATION:
1588         case WM8996_AIF2TX_CHANNEL_0_CONFIGURATION:
1589         case WM8996_AIF2TX_CHANNEL_1_CONFIGURATION:
1590         case WM8996_AIF2RX_CHANNEL_0_CONFIGURATION:
1591         case WM8996_AIF2RX_CHANNEL_1_CONFIGURATION:
1592         case WM8996_AIF2RX_MONO_CONFIGURATION:
1593         case WM8996_AIF2TX_TEST:
1594         case WM8996_DSP1_TX_LEFT_VOLUME:
1595         case WM8996_DSP1_TX_RIGHT_VOLUME:
1596         case WM8996_DSP1_RX_LEFT_VOLUME:
1597         case WM8996_DSP1_RX_RIGHT_VOLUME:
1598         case WM8996_DSP1_TX_FILTERS:
1599         case WM8996_DSP1_RX_FILTERS_1:
1600         case WM8996_DSP1_RX_FILTERS_2:
1601         case WM8996_DSP1_DRC_1:
1602         case WM8996_DSP1_DRC_2:
1603         case WM8996_DSP1_DRC_3:
1604         case WM8996_DSP1_DRC_4:
1605         case WM8996_DSP1_DRC_5:
1606         case WM8996_DSP1_RX_EQ_GAINS_1:
1607         case WM8996_DSP1_RX_EQ_GAINS_2:
1608         case WM8996_DSP1_RX_EQ_BAND_1_A:
1609         case WM8996_DSP1_RX_EQ_BAND_1_B:
1610         case WM8996_DSP1_RX_EQ_BAND_1_PG:
1611         case WM8996_DSP1_RX_EQ_BAND_2_A:
1612         case WM8996_DSP1_RX_EQ_BAND_2_B:
1613         case WM8996_DSP1_RX_EQ_BAND_2_C:
1614         case WM8996_DSP1_RX_EQ_BAND_2_PG:
1615         case WM8996_DSP1_RX_EQ_BAND_3_A:
1616         case WM8996_DSP1_RX_EQ_BAND_3_B:
1617         case WM8996_DSP1_RX_EQ_BAND_3_C:
1618         case WM8996_DSP1_RX_EQ_BAND_3_PG:
1619         case WM8996_DSP1_RX_EQ_BAND_4_A:
1620         case WM8996_DSP1_RX_EQ_BAND_4_B:
1621         case WM8996_DSP1_RX_EQ_BAND_4_C:
1622         case WM8996_DSP1_RX_EQ_BAND_4_PG:
1623         case WM8996_DSP1_RX_EQ_BAND_5_A:
1624         case WM8996_DSP1_RX_EQ_BAND_5_B:
1625         case WM8996_DSP1_RX_EQ_BAND_5_PG:
1626         case WM8996_DSP2_TX_LEFT_VOLUME:
1627         case WM8996_DSP2_TX_RIGHT_VOLUME:
1628         case WM8996_DSP2_RX_LEFT_VOLUME:
1629         case WM8996_DSP2_RX_RIGHT_VOLUME:
1630         case WM8996_DSP2_TX_FILTERS:
1631         case WM8996_DSP2_RX_FILTERS_1:
1632         case WM8996_DSP2_RX_FILTERS_2:
1633         case WM8996_DSP2_DRC_1:
1634         case WM8996_DSP2_DRC_2:
1635         case WM8996_DSP2_DRC_3:
1636         case WM8996_DSP2_DRC_4:
1637         case WM8996_DSP2_DRC_5:
1638         case WM8996_DSP2_RX_EQ_GAINS_1:
1639         case WM8996_DSP2_RX_EQ_GAINS_2:
1640         case WM8996_DSP2_RX_EQ_BAND_1_A:
1641         case WM8996_DSP2_RX_EQ_BAND_1_B:
1642         case WM8996_DSP2_RX_EQ_BAND_1_PG:
1643         case WM8996_DSP2_RX_EQ_BAND_2_A:
1644         case WM8996_DSP2_RX_EQ_BAND_2_B:
1645         case WM8996_DSP2_RX_EQ_BAND_2_C:
1646         case WM8996_DSP2_RX_EQ_BAND_2_PG:
1647         case WM8996_DSP2_RX_EQ_BAND_3_A:
1648         case WM8996_DSP2_RX_EQ_BAND_3_B:
1649         case WM8996_DSP2_RX_EQ_BAND_3_C:
1650         case WM8996_DSP2_RX_EQ_BAND_3_PG:
1651         case WM8996_DSP2_RX_EQ_BAND_4_A:
1652         case WM8996_DSP2_RX_EQ_BAND_4_B:
1653         case WM8996_DSP2_RX_EQ_BAND_4_C:
1654         case WM8996_DSP2_RX_EQ_BAND_4_PG:
1655         case WM8996_DSP2_RX_EQ_BAND_5_A:
1656         case WM8996_DSP2_RX_EQ_BAND_5_B:
1657         case WM8996_DSP2_RX_EQ_BAND_5_PG:
1658         case WM8996_DAC1_MIXER_VOLUMES:
1659         case WM8996_DAC1_LEFT_MIXER_ROUTING:
1660         case WM8996_DAC1_RIGHT_MIXER_ROUTING:
1661         case WM8996_DAC2_MIXER_VOLUMES:
1662         case WM8996_DAC2_LEFT_MIXER_ROUTING:
1663         case WM8996_DAC2_RIGHT_MIXER_ROUTING:
1664         case WM8996_DSP1_TX_LEFT_MIXER_ROUTING:
1665         case WM8996_DSP1_TX_RIGHT_MIXER_ROUTING:
1666         case WM8996_DSP2_TX_LEFT_MIXER_ROUTING:
1667         case WM8996_DSP2_TX_RIGHT_MIXER_ROUTING:
1668         case WM8996_DSP_TX_MIXER_SELECT:
1669         case WM8996_DAC_SOFTMUTE:
1670         case WM8996_OVERSAMPLING:
1671         case WM8996_SIDETONE:
1672         case WM8996_GPIO_1:
1673         case WM8996_GPIO_2:
1674         case WM8996_GPIO_3:
1675         case WM8996_GPIO_4:
1676         case WM8996_GPIO_5:
1677         case WM8996_PULL_CONTROL_1:
1678         case WM8996_PULL_CONTROL_2:
1679         case WM8996_INTERRUPT_STATUS_1:
1680         case WM8996_INTERRUPT_STATUS_2:
1681         case WM8996_INTERRUPT_RAW_STATUS_2:
1682         case WM8996_INTERRUPT_STATUS_1_MASK:
1683         case WM8996_INTERRUPT_STATUS_2_MASK:
1684         case WM8996_INTERRUPT_CONTROL:
1685         case WM8996_LEFT_PDM_SPEAKER:
1686         case WM8996_RIGHT_PDM_SPEAKER:
1687         case WM8996_PDM_SPEAKER_MUTE_SEQUENCE:
1688         case WM8996_PDM_SPEAKER_VOLUME:
1689                 return 1;
1690         default:
1691                 return 0;
1692         }
1693 }
1694
1695 static bool wm8996_volatile_register(struct device *dev, unsigned int reg)
1696 {
1697         switch (reg) {
1698         case WM8996_SOFTWARE_RESET:
1699         case WM8996_CHIP_REVISION:
1700         case WM8996_LDO_1:
1701         case WM8996_LDO_2:
1702         case WM8996_INTERRUPT_STATUS_1:
1703         case WM8996_INTERRUPT_STATUS_2:
1704         case WM8996_INTERRUPT_RAW_STATUS_2:
1705         case WM8996_DC_SERVO_READBACK_0:
1706         case WM8996_DC_SERVO_2:
1707         case WM8996_DC_SERVO_6:
1708         case WM8996_DC_SERVO_7:
1709         case WM8996_FLL_CONTROL_6:
1710         case WM8996_MIC_DETECT_3:
1711         case WM8996_HEADPHONE_DETECT_1:
1712         case WM8996_HEADPHONE_DETECT_2:
1713                 return 1;
1714         default:
1715                 return 0;
1716         }
1717 }
1718
1719 static int wm8996_reset(struct wm8996_priv *wm8996)
1720 {
1721         if (wm8996->pdata.ldo_ena > 0) {
1722                 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
1723                 return 0;
1724         } else {
1725                 return regmap_write(wm8996->regmap, WM8996_SOFTWARE_RESET,
1726                                     0x8915);
1727         }
1728 }
1729
1730 static const int bclk_divs[] = {
1731         1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96
1732 };
1733
1734 static void wm8996_update_bclk(struct snd_soc_codec *codec)
1735 {
1736         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1737         int aif, best, cur_val, bclk_rate, bclk_reg, i;
1738
1739         /* Don't bother if we're in a low frequency idle mode that
1740          * can't support audio.
1741          */
1742         if (wm8996->sysclk < 64000)
1743                 return;
1744
1745         for (aif = 0; aif < WM8996_AIFS; aif++) {
1746                 switch (aif) {
1747                 case 0:
1748                         bclk_reg = WM8996_AIF1_BCLK;
1749                         break;
1750                 case 1:
1751                         bclk_reg = WM8996_AIF2_BCLK;
1752                         break;
1753                 }
1754
1755                 bclk_rate = wm8996->bclk_rate[aif];
1756
1757                 /* Pick a divisor for BCLK as close as we can get to ideal */
1758                 best = 0;
1759                 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1760                         cur_val = (wm8996->sysclk / bclk_divs[i]) - bclk_rate;
1761                         if (cur_val < 0) /* BCLK table is sorted */
1762                                 break;
1763                         best = i;
1764                 }
1765                 bclk_rate = wm8996->sysclk / bclk_divs[best];
1766                 dev_dbg(codec->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1767                         bclk_divs[best], bclk_rate);
1768
1769                 snd_soc_update_bits(codec, bclk_reg,
1770                                     WM8996_AIF1_BCLK_DIV_MASK, best);
1771         }
1772 }
1773
1774 static int wm8996_set_bias_level(struct snd_soc_codec *codec,
1775                                  enum snd_soc_bias_level level)
1776 {
1777         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1778         int ret;
1779
1780         switch (level) {
1781         case SND_SOC_BIAS_ON:
1782         case SND_SOC_BIAS_PREPARE:
1783                 break;
1784
1785         case SND_SOC_BIAS_STANDBY:
1786                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1787                         ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
1788                                                     wm8996->supplies);
1789                         if (ret != 0) {
1790                                 dev_err(codec->dev,
1791                                         "Failed to enable supplies: %d\n",
1792                                         ret);
1793                                 return ret;
1794                         }
1795
1796                         if (wm8996->pdata.ldo_ena >= 0) {
1797                                 gpio_set_value_cansleep(wm8996->pdata.ldo_ena,
1798                                                         1);
1799                                 msleep(5);
1800                         }
1801
1802                         regcache_cache_only(codec->control_data, false);
1803                         regcache_sync(codec->control_data);
1804                 }
1805                 break;
1806
1807         case SND_SOC_BIAS_OFF:
1808                 regcache_cache_only(codec->control_data, true);
1809                 if (wm8996->pdata.ldo_ena >= 0)
1810                         gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
1811                 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies),
1812                                        wm8996->supplies);
1813                 break;
1814         }
1815
1816         codec->dapm.bias_level = level;
1817
1818         return 0;
1819 }
1820
1821 static int wm8996_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1822 {
1823         struct snd_soc_codec *codec = dai->codec;
1824         int aifctrl = 0;
1825         int bclk = 0;
1826         int lrclk_tx = 0;
1827         int lrclk_rx = 0;
1828         int aifctrl_reg, bclk_reg, lrclk_tx_reg, lrclk_rx_reg;
1829
1830         switch (dai->id) {
1831         case 0:
1832                 aifctrl_reg = WM8996_AIF1_CONTROL;
1833                 bclk_reg = WM8996_AIF1_BCLK;
1834                 lrclk_tx_reg = WM8996_AIF1_TX_LRCLK_2;
1835                 lrclk_rx_reg = WM8996_AIF1_RX_LRCLK_2;
1836                 break;
1837         case 1:
1838                 aifctrl_reg = WM8996_AIF2_CONTROL;
1839                 bclk_reg = WM8996_AIF2_BCLK;
1840                 lrclk_tx_reg = WM8996_AIF2_TX_LRCLK_2;
1841                 lrclk_rx_reg = WM8996_AIF2_RX_LRCLK_2;
1842                 break;
1843         default:
1844                 BUG();
1845                 return -EINVAL;
1846         }
1847
1848         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1849         case SND_SOC_DAIFMT_NB_NF:
1850                 break;
1851         case SND_SOC_DAIFMT_IB_NF:
1852                 bclk |= WM8996_AIF1_BCLK_INV;
1853                 break;
1854         case SND_SOC_DAIFMT_NB_IF:
1855                 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
1856                 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
1857                 break;
1858         case SND_SOC_DAIFMT_IB_IF:
1859                 bclk |= WM8996_AIF1_BCLK_INV;
1860                 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
1861                 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
1862                 break;
1863         }
1864
1865         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1866         case SND_SOC_DAIFMT_CBS_CFS:
1867                 break;
1868         case SND_SOC_DAIFMT_CBS_CFM:
1869                 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
1870                 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
1871                 break;
1872         case SND_SOC_DAIFMT_CBM_CFS:
1873                 bclk |= WM8996_AIF1_BCLK_MSTR;
1874                 break;
1875         case SND_SOC_DAIFMT_CBM_CFM:
1876                 bclk |= WM8996_AIF1_BCLK_MSTR;
1877                 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
1878                 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
1879                 break;
1880         default:
1881                 return -EINVAL;
1882         }
1883
1884         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1885         case SND_SOC_DAIFMT_DSP_A:
1886                 break;
1887         case SND_SOC_DAIFMT_DSP_B:
1888                 aifctrl |= 1;
1889                 break;
1890         case SND_SOC_DAIFMT_I2S:
1891                 aifctrl |= 2;
1892                 break;
1893         case SND_SOC_DAIFMT_LEFT_J:
1894                 aifctrl |= 3;
1895                 break;
1896         default:
1897                 return -EINVAL;
1898         }
1899
1900         snd_soc_update_bits(codec, aifctrl_reg, WM8996_AIF1_FMT_MASK, aifctrl);
1901         snd_soc_update_bits(codec, bclk_reg,
1902                             WM8996_AIF1_BCLK_INV | WM8996_AIF1_BCLK_MSTR,
1903                             bclk);
1904         snd_soc_update_bits(codec, lrclk_tx_reg,
1905                             WM8996_AIF1TX_LRCLK_INV |
1906                             WM8996_AIF1TX_LRCLK_MSTR,
1907                             lrclk_tx);
1908         snd_soc_update_bits(codec, lrclk_rx_reg,
1909                             WM8996_AIF1RX_LRCLK_INV |
1910                             WM8996_AIF1RX_LRCLK_MSTR,
1911                             lrclk_rx);
1912
1913         return 0;
1914 }
1915
1916 static const int dsp_divs[] = {
1917         48000, 32000, 16000, 8000
1918 };
1919
1920 static int wm8996_hw_params(struct snd_pcm_substream *substream,
1921                             struct snd_pcm_hw_params *params,
1922                             struct snd_soc_dai *dai)
1923 {
1924         struct snd_soc_codec *codec = dai->codec;
1925         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1926         int bits, i, bclk_rate;
1927         int aifdata = 0;
1928         int lrclk = 0;
1929         int dsp = 0;
1930         int aifdata_reg, lrclk_reg, dsp_shift;
1931
1932         switch (dai->id) {
1933         case 0:
1934                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1935                     (snd_soc_read(codec, WM8996_GPIO_1)) & WM8996_GP1_FN_MASK) {
1936                         aifdata_reg = WM8996_AIF1RX_DATA_CONFIGURATION;
1937                         lrclk_reg = WM8996_AIF1_RX_LRCLK_1;
1938                 } else {
1939                         aifdata_reg = WM8996_AIF1TX_DATA_CONFIGURATION_1;
1940                         lrclk_reg = WM8996_AIF1_TX_LRCLK_1;
1941                 }
1942                 dsp_shift = 0;
1943                 break;
1944         case 1:
1945                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1946                     (snd_soc_read(codec, WM8996_GPIO_2)) & WM8996_GP2_FN_MASK) {
1947                         aifdata_reg = WM8996_AIF2RX_DATA_CONFIGURATION;
1948                         lrclk_reg = WM8996_AIF2_RX_LRCLK_1;
1949                 } else {
1950                         aifdata_reg = WM8996_AIF2TX_DATA_CONFIGURATION_1;
1951                         lrclk_reg = WM8996_AIF2_TX_LRCLK_1;
1952                 }
1953                 dsp_shift = WM8996_DSP2_DIV_SHIFT;
1954                 break;
1955         default:
1956                 BUG();
1957                 return -EINVAL;
1958         }
1959
1960         bclk_rate = snd_soc_params_to_bclk(params);
1961         if (bclk_rate < 0) {
1962                 dev_err(codec->dev, "Unsupported BCLK rate: %d\n", bclk_rate);
1963                 return bclk_rate;
1964         }
1965
1966         wm8996->bclk_rate[dai->id] = bclk_rate;
1967         wm8996->rx_rate[dai->id] = params_rate(params);
1968
1969         /* Needs looking at for TDM */
1970         bits = snd_pcm_format_width(params_format(params));
1971         if (bits < 0)
1972                 return bits;
1973         aifdata |= (bits << WM8996_AIF1TX_WL_SHIFT) | bits;
1974
1975         for (i = 0; i < ARRAY_SIZE(dsp_divs); i++) {
1976                 if (dsp_divs[i] == params_rate(params))
1977                         break;
1978         }
1979         if (i == ARRAY_SIZE(dsp_divs)) {
1980                 dev_err(codec->dev, "Unsupported sample rate %dHz\n",
1981                         params_rate(params));
1982                 return -EINVAL;
1983         }
1984         dsp |= i << dsp_shift;
1985
1986         wm8996_update_bclk(codec);
1987
1988         lrclk = bclk_rate / params_rate(params);
1989         dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1990                 lrclk, bclk_rate / lrclk);
1991
1992         snd_soc_update_bits(codec, aifdata_reg,
1993                             WM8996_AIF1TX_WL_MASK |
1994                             WM8996_AIF1TX_SLOT_LEN_MASK,
1995                             aifdata);
1996         snd_soc_update_bits(codec, lrclk_reg, WM8996_AIF1RX_RATE_MASK,
1997                             lrclk);
1998         snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_2,
1999                             WM8996_DSP1_DIV_MASK << dsp_shift, dsp);
2000
2001         return 0;
2002 }
2003
2004 static int wm8996_set_sysclk(struct snd_soc_dai *dai,
2005                 int clk_id, unsigned int freq, int dir)
2006 {
2007         struct snd_soc_codec *codec = dai->codec;
2008         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2009         int lfclk = 0;
2010         int ratediv = 0;
2011         int sync = WM8996_REG_SYNC;
2012         int src;
2013         int old;
2014
2015         if (freq == wm8996->sysclk && clk_id == wm8996->sysclk_src)
2016                 return 0;
2017
2018         /* Disable SYSCLK while we reconfigure */
2019         old = snd_soc_read(codec, WM8996_AIF_CLOCKING_1) & WM8996_SYSCLK_ENA;
2020         snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
2021                             WM8996_SYSCLK_ENA, 0);
2022
2023         switch (clk_id) {
2024         case WM8996_SYSCLK_MCLK1:
2025                 wm8996->sysclk = freq;
2026                 src = 0;
2027                 break;
2028         case WM8996_SYSCLK_MCLK2:
2029                 wm8996->sysclk = freq;
2030                 src = 1;
2031                 break;
2032         case WM8996_SYSCLK_FLL:
2033                 wm8996->sysclk = freq;
2034                 src = 2;
2035                 break;
2036         default:
2037                 dev_err(codec->dev, "Unsupported clock source %d\n", clk_id);
2038                 return -EINVAL;
2039         }
2040
2041         switch (wm8996->sysclk) {
2042         case 6144000:
2043                 snd_soc_update_bits(codec, WM8996_AIF_RATE,
2044                                     WM8996_SYSCLK_RATE, 0);
2045                 break;
2046         case 24576000:
2047                 ratediv = WM8996_SYSCLK_DIV;
2048                 wm8996->sysclk /= 2;
2049         case 12288000:
2050                 snd_soc_update_bits(codec, WM8996_AIF_RATE,
2051                                     WM8996_SYSCLK_RATE, WM8996_SYSCLK_RATE);
2052                 break;
2053         case 32000:
2054         case 32768:
2055                 lfclk = WM8996_LFCLK_ENA;
2056                 sync = 0;
2057                 break;
2058         default:
2059                 dev_warn(codec->dev, "Unsupported clock rate %dHz\n",
2060                          wm8996->sysclk);
2061                 return -EINVAL;
2062         }
2063
2064         wm8996_update_bclk(codec);
2065
2066         snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
2067                             WM8996_SYSCLK_SRC_MASK | WM8996_SYSCLK_DIV_MASK,
2068                             src << WM8996_SYSCLK_SRC_SHIFT | ratediv);
2069         snd_soc_update_bits(codec, WM8996_CLOCKING_1, WM8996_LFCLK_ENA, lfclk);
2070         snd_soc_update_bits(codec, WM8996_CONTROL_INTERFACE_1,
2071                             WM8996_REG_SYNC, sync);
2072         snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
2073                             WM8996_SYSCLK_ENA, old);
2074
2075         wm8996->sysclk_src = clk_id;
2076
2077         return 0;
2078 }
2079
2080 struct _fll_div {
2081         u16 fll_fratio;
2082         u16 fll_outdiv;
2083         u16 fll_refclk_div;
2084         u16 fll_loop_gain;
2085         u16 fll_ref_freq;
2086         u16 n;
2087         u16 theta;
2088         u16 lambda;
2089 };
2090
2091 static struct {
2092         unsigned int min;
2093         unsigned int max;
2094         u16 fll_fratio;
2095         int ratio;
2096 } fll_fratios[] = {
2097         {       0,    64000, 4, 16 },
2098         {   64000,   128000, 3,  8 },
2099         {  128000,   256000, 2,  4 },
2100         {  256000,  1000000, 1,  2 },
2101         { 1000000, 13500000, 0,  1 },
2102 };
2103
2104 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
2105                        unsigned int Fout)
2106 {
2107         unsigned int target;
2108         unsigned int div;
2109         unsigned int fratio, gcd_fll;
2110         int i;
2111
2112         /* Fref must be <=13.5MHz */
2113         div = 1;
2114         fll_div->fll_refclk_div = 0;
2115         while ((Fref / div) > 13500000) {
2116                 div *= 2;
2117                 fll_div->fll_refclk_div++;
2118
2119                 if (div > 8) {
2120                         pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
2121                                Fref);
2122                         return -EINVAL;
2123                 }
2124         }
2125
2126         pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
2127
2128         /* Apply the division for our remaining calculations */
2129         Fref /= div;
2130
2131         if (Fref >= 3000000)
2132                 fll_div->fll_loop_gain = 5;
2133         else
2134                 fll_div->fll_loop_gain = 0;
2135
2136         if (Fref >= 48000)
2137                 fll_div->fll_ref_freq = 0;
2138         else
2139                 fll_div->fll_ref_freq = 1;
2140
2141         /* Fvco should be 90-100MHz; don't check the upper bound */
2142         div = 2;
2143         while (Fout * div < 90000000) {
2144                 div++;
2145                 if (div > 64) {
2146                         pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
2147                                Fout);
2148                         return -EINVAL;
2149                 }
2150         }
2151         target = Fout * div;
2152         fll_div->fll_outdiv = div - 1;
2153
2154         pr_debug("FLL Fvco=%dHz\n", target);
2155
2156         /* Find an appropraite FLL_FRATIO and factor it out of the target */
2157         for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
2158                 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
2159                         fll_div->fll_fratio = fll_fratios[i].fll_fratio;
2160                         fratio = fll_fratios[i].ratio;
2161                         break;
2162                 }
2163         }
2164         if (i == ARRAY_SIZE(fll_fratios)) {
2165                 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
2166                 return -EINVAL;
2167         }
2168
2169         fll_div->n = target / (fratio * Fref);
2170
2171         if (target % Fref == 0) {
2172                 fll_div->theta = 0;
2173                 fll_div->lambda = 0;
2174         } else {
2175                 gcd_fll = gcd(target, fratio * Fref);
2176
2177                 fll_div->theta = (target - (fll_div->n * fratio * Fref))
2178                         / gcd_fll;
2179                 fll_div->lambda = (fratio * Fref) / gcd_fll;
2180         }
2181
2182         pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
2183                  fll_div->n, fll_div->theta, fll_div->lambda);
2184         pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
2185                  fll_div->fll_fratio, fll_div->fll_outdiv,
2186                  fll_div->fll_refclk_div);
2187
2188         return 0;
2189 }
2190
2191 static int wm8996_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
2192                           unsigned int Fref, unsigned int Fout)
2193 {
2194         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2195         struct i2c_client *i2c = to_i2c_client(codec->dev);
2196         struct _fll_div fll_div;
2197         unsigned long timeout;
2198         int ret, reg, retry;
2199
2200         /* Any change? */
2201         if (source == wm8996->fll_src && Fref == wm8996->fll_fref &&
2202             Fout == wm8996->fll_fout)
2203                 return 0;
2204
2205         if (Fout == 0) {
2206                 dev_dbg(codec->dev, "FLL disabled\n");
2207
2208                 wm8996->fll_fref = 0;
2209                 wm8996->fll_fout = 0;
2210
2211                 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1,
2212                                     WM8996_FLL_ENA, 0);
2213
2214                 wm8996_bg_disable(codec);
2215
2216                 return 0;
2217         }
2218
2219         ret = fll_factors(&fll_div, Fref, Fout);
2220         if (ret != 0)
2221                 return ret;
2222
2223         switch (source) {
2224         case WM8996_FLL_MCLK1:
2225                 reg = 0;
2226                 break;
2227         case WM8996_FLL_MCLK2:
2228                 reg = 1;
2229                 break;
2230         case WM8996_FLL_DACLRCLK1:
2231                 reg = 2;
2232                 break;
2233         case WM8996_FLL_BCLK1:
2234                 reg = 3;
2235                 break;
2236         default:
2237                 dev_err(codec->dev, "Unknown FLL source %d\n", ret);
2238                 return -EINVAL;
2239         }
2240
2241         reg |= fll_div.fll_refclk_div << WM8996_FLL_REFCLK_DIV_SHIFT;
2242         reg |= fll_div.fll_ref_freq << WM8996_FLL_REF_FREQ_SHIFT;
2243
2244         snd_soc_update_bits(codec, WM8996_FLL_CONTROL_5,
2245                             WM8996_FLL_REFCLK_DIV_MASK | WM8996_FLL_REF_FREQ |
2246                             WM8996_FLL_REFCLK_SRC_MASK, reg);
2247
2248         reg = 0;
2249         if (fll_div.theta || fll_div.lambda)
2250                 reg |= WM8996_FLL_EFS_ENA | (3 << WM8996_FLL_LFSR_SEL_SHIFT);
2251         else
2252                 reg |= 1 << WM8996_FLL_LFSR_SEL_SHIFT;
2253         snd_soc_write(codec, WM8996_FLL_EFS_2, reg);
2254
2255         snd_soc_update_bits(codec, WM8996_FLL_CONTROL_2,
2256                             WM8996_FLL_OUTDIV_MASK |
2257                             WM8996_FLL_FRATIO_MASK,
2258                             (fll_div.fll_outdiv << WM8996_FLL_OUTDIV_SHIFT) |
2259                             (fll_div.fll_fratio));
2260
2261         snd_soc_write(codec, WM8996_FLL_CONTROL_3, fll_div.theta);
2262
2263         snd_soc_update_bits(codec, WM8996_FLL_CONTROL_4,
2264                             WM8996_FLL_N_MASK | WM8996_FLL_LOOP_GAIN_MASK,
2265                             (fll_div.n << WM8996_FLL_N_SHIFT) |
2266                             fll_div.fll_loop_gain);
2267
2268         snd_soc_write(codec, WM8996_FLL_EFS_1, fll_div.lambda);
2269
2270         /* Enable the bandgap if it's not already enabled */
2271         ret = snd_soc_read(codec, WM8996_FLL_CONTROL_1);
2272         if (!(ret & WM8996_FLL_ENA))
2273                 wm8996_bg_enable(codec);
2274
2275         /* Clear any pending completions (eg, from failed startups) */
2276         try_wait_for_completion(&wm8996->fll_lock);
2277
2278         snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1,
2279                             WM8996_FLL_ENA, WM8996_FLL_ENA);
2280
2281         /* The FLL supports live reconfiguration - kick that in case we were
2282          * already enabled.
2283          */
2284         snd_soc_write(codec, WM8996_FLL_CONTROL_6, WM8996_FLL_SWITCH_CLK);
2285
2286         /* Wait for the FLL to lock, using the interrupt if possible */
2287         if (Fref > 1000000)
2288                 timeout = usecs_to_jiffies(300);
2289         else
2290                 timeout = msecs_to_jiffies(2);
2291
2292         /* Allow substantially longer if we've actually got the IRQ, poll
2293          * at a slightly higher rate if we don't.
2294          */
2295         if (i2c->irq)
2296                 timeout *= 10;
2297         else
2298                 timeout /= 2;
2299
2300         for (retry = 0; retry < 10; retry++) {
2301                 ret = wait_for_completion_timeout(&wm8996->fll_lock,
2302                                                   timeout);
2303                 if (ret != 0) {
2304                         WARN_ON(!i2c->irq);
2305                         break;
2306                 }
2307
2308                 ret = snd_soc_read(codec, WM8996_INTERRUPT_RAW_STATUS_2);
2309                 if (ret & WM8996_FLL_LOCK_STS)
2310                         break;
2311         }
2312         if (retry == 10) {
2313                 dev_err(codec->dev, "Timed out waiting for FLL\n");
2314                 ret = -ETIMEDOUT;
2315         }
2316
2317         dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2318
2319         wm8996->fll_fref = Fref;
2320         wm8996->fll_fout = Fout;
2321         wm8996->fll_src = source;
2322
2323         return ret;
2324 }
2325
2326 #ifdef CONFIG_GPIOLIB
2327 static inline struct wm8996_priv *gpio_to_wm8996(struct gpio_chip *chip)
2328 {
2329         return container_of(chip, struct wm8996_priv, gpio_chip);
2330 }
2331
2332 static void wm8996_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2333 {
2334         struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2335
2336         regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
2337                            WM8996_GP1_LVL, !!value << WM8996_GP1_LVL_SHIFT);
2338 }
2339
2340 static int wm8996_gpio_direction_out(struct gpio_chip *chip,
2341                                      unsigned offset, int value)
2342 {
2343         struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2344         int val;
2345
2346         val = (1 << WM8996_GP1_FN_SHIFT) | (!!value << WM8996_GP1_LVL_SHIFT);
2347
2348         return regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
2349                                   WM8996_GP1_FN_MASK | WM8996_GP1_DIR |
2350                                   WM8996_GP1_LVL, val);
2351 }
2352
2353 static int wm8996_gpio_get(struct gpio_chip *chip, unsigned offset)
2354 {
2355         struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2356         unsigned int reg;
2357         int ret;
2358
2359         ret = regmap_read(wm8996->regmap, WM8996_GPIO_1 + offset, &reg);
2360         if (ret < 0)
2361                 return ret;
2362
2363         return (reg & WM8996_GP1_LVL) != 0;
2364 }
2365
2366 static int wm8996_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2367 {
2368         struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2369
2370         return regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
2371                                   WM8996_GP1_FN_MASK | WM8996_GP1_DIR,
2372                                   (1 << WM8996_GP1_FN_SHIFT) |
2373                                   (1 << WM8996_GP1_DIR_SHIFT));
2374 }
2375
2376 static struct gpio_chip wm8996_template_chip = {
2377         .label                  = "wm8996",
2378         .owner                  = THIS_MODULE,
2379         .direction_output       = wm8996_gpio_direction_out,
2380         .set                    = wm8996_gpio_set,
2381         .direction_input        = wm8996_gpio_direction_in,
2382         .get                    = wm8996_gpio_get,
2383         .can_sleep              = 1,
2384 };
2385
2386 static void wm8996_init_gpio(struct wm8996_priv *wm8996)
2387 {
2388         int ret;
2389
2390         wm8996->gpio_chip = wm8996_template_chip;
2391         wm8996->gpio_chip.ngpio = 5;
2392         wm8996->gpio_chip.dev = wm8996->dev;
2393
2394         if (wm8996->pdata.gpio_base)
2395                 wm8996->gpio_chip.base = wm8996->pdata.gpio_base;
2396         else
2397                 wm8996->gpio_chip.base = -1;
2398
2399         ret = gpiochip_add(&wm8996->gpio_chip);
2400         if (ret != 0)
2401                 dev_err(wm8996->dev, "Failed to add GPIOs: %d\n", ret);
2402 }
2403
2404 static void wm8996_free_gpio(struct wm8996_priv *wm8996)
2405 {
2406         int ret;
2407
2408         ret = gpiochip_remove(&wm8996->gpio_chip);
2409         if (ret != 0)
2410                 dev_err(wm8996->dev, "Failed to remove GPIOs: %d\n", ret);
2411 }
2412 #else
2413 static void wm8996_init_gpio(struct wm8996_priv *wm8996)
2414 {
2415 }
2416
2417 static void wm8996_free_gpio(struct wm8996_priv *wm8996)
2418 {
2419 }
2420 #endif
2421
2422 /**
2423  * wm8996_detect - Enable default WM8996 jack detection
2424  *
2425  * The WM8996 has advanced accessory detection support for headsets.
2426  * This function provides a default implementation which integrates
2427  * the majority of this functionality with minimal user configuration.
2428  *
2429  * This will detect headset, headphone and short circuit button and
2430  * will also detect inverted microphone ground connections and update
2431  * the polarity of the connections.
2432  */
2433 int wm8996_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2434                   wm8996_polarity_fn polarity_cb)
2435 {
2436         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2437
2438         wm8996->jack = jack;
2439         wm8996->detecting = true;
2440         wm8996->polarity_cb = polarity_cb;
2441
2442         if (wm8996->polarity_cb)
2443                 wm8996->polarity_cb(codec, 0);
2444
2445         /* Clear discarge to avoid noise during detection */
2446         snd_soc_update_bits(codec, WM8996_MICBIAS_1,
2447                             WM8996_MICB1_DISCH, 0);
2448         snd_soc_update_bits(codec, WM8996_MICBIAS_2,
2449                             WM8996_MICB2_DISCH, 0);
2450
2451         /* LDO2 powers the microphones, SYSCLK clocks detection */
2452         snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
2453         snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK");
2454
2455         /* We start off just enabling microphone detection - even a
2456          * plain headphone will trigger detection.
2457          */
2458         snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2459                             WM8996_MICD_ENA, WM8996_MICD_ENA);
2460
2461         /* Slowest detection rate, gives debounce for initial detection */
2462         snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2463                             WM8996_MICD_RATE_MASK,
2464                             WM8996_MICD_RATE_MASK);
2465
2466         /* Enable interrupts and we're off */
2467         snd_soc_update_bits(codec, WM8996_INTERRUPT_STATUS_2_MASK,
2468                             WM8996_IM_MICD_EINT | WM8996_HP_DONE_EINT, 0);
2469
2470         return 0;
2471 }
2472 EXPORT_SYMBOL_GPL(wm8996_detect);
2473
2474 static void wm8996_hpdet_irq(struct snd_soc_codec *codec)
2475 {
2476         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2477         int val, reg, report;
2478
2479         /* Assume headphone in error conditions; we need to report
2480          * something or we stall our state machine.
2481          */
2482         report = SND_JACK_HEADPHONE;
2483
2484         reg = snd_soc_read(codec, WM8996_HEADPHONE_DETECT_2);
2485         if (reg < 0) {
2486                 dev_err(codec->dev, "Failed to read HPDET status\n");
2487                 goto out;
2488         }
2489
2490         if (!(reg & WM8996_HP_DONE)) {
2491                 dev_err(codec->dev, "Got HPDET IRQ but HPDET is busy\n");
2492                 goto out;
2493         }
2494
2495         val = reg & WM8996_HP_LVL_MASK;
2496
2497         dev_dbg(codec->dev, "HPDET measured %d ohms\n", val);
2498
2499         /* If we've got high enough impedence then report as line,
2500          * otherwise assume headphone.
2501          */
2502         if (val >= 126)
2503                 report = SND_JACK_LINEOUT;
2504         else
2505                 report = SND_JACK_HEADPHONE;
2506
2507 out:
2508         if (wm8996->jack_mic)
2509                 report |= SND_JACK_MICROPHONE;
2510
2511         snd_soc_jack_report(wm8996->jack, report,
2512                             SND_JACK_LINEOUT | SND_JACK_HEADSET);
2513
2514         wm8996->detecting = false;
2515
2516         /* If the output isn't running re-clamp it */
2517         if (!(snd_soc_read(codec, WM8996_POWER_MANAGEMENT_1) &
2518               (WM8996_HPOUT1L_ENA | WM8996_HPOUT1R_RMV_SHORT)))
2519                 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1,
2520                                     WM8996_HPOUT1L_RMV_SHORT |
2521                                     WM8996_HPOUT1R_RMV_SHORT, 0);
2522
2523         /* Go back to looking at the microphone */
2524         snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_1,
2525                             WM8996_JD_MODE_MASK, 0);
2526         snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, WM8996_MICD_ENA,
2527                             WM8996_MICD_ENA);
2528
2529         snd_soc_dapm_disable_pin(&codec->dapm, "Bandgap");
2530         snd_soc_dapm_sync(&codec->dapm);
2531 }
2532
2533 static void wm8996_hpdet_start(struct snd_soc_codec *codec)
2534 {
2535         /* Unclamp the output, we can't measure while we're shorting it */
2536         snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1,
2537                             WM8996_HPOUT1L_RMV_SHORT |
2538                             WM8996_HPOUT1R_RMV_SHORT,
2539                             WM8996_HPOUT1L_RMV_SHORT |
2540                             WM8996_HPOUT1R_RMV_SHORT);
2541
2542         /* We need bandgap for HPDET */
2543         snd_soc_dapm_force_enable_pin(&codec->dapm, "Bandgap");
2544         snd_soc_dapm_sync(&codec->dapm);
2545
2546         /* Go into headphone detect left mode */
2547         snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, WM8996_MICD_ENA, 0);
2548         snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_1,
2549                             WM8996_JD_MODE_MASK, 1);
2550
2551         /* Trigger a measurement */
2552         snd_soc_update_bits(codec, WM8996_HEADPHONE_DETECT_1,
2553                             WM8996_HP_POLL, WM8996_HP_POLL);
2554 }
2555
2556 static void wm8996_micd(struct snd_soc_codec *codec)
2557 {
2558         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2559         int val, reg;
2560
2561         val = snd_soc_read(codec, WM8996_MIC_DETECT_3);
2562
2563         dev_dbg(codec->dev, "Microphone event: %x\n", val);
2564
2565         if (!(val & WM8996_MICD_VALID)) {
2566                 dev_warn(codec->dev, "Microphone detection state invalid\n");
2567                 return;
2568         }
2569
2570         /* No accessory, reset everything and report removal */
2571         if (!(val & WM8996_MICD_STS)) {
2572                 dev_dbg(codec->dev, "Jack removal detected\n");
2573                 wm8996->jack_mic = false;
2574                 wm8996->detecting = true;
2575                 snd_soc_jack_report(wm8996->jack, 0,
2576                                     SND_JACK_LINEOUT | SND_JACK_HEADSET |
2577                                     SND_JACK_BTN_0);
2578
2579                 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2580                                     WM8996_MICD_RATE_MASK |
2581                                     WM8996_MICD_BIAS_STARTTIME_MASK,
2582                                     WM8996_MICD_RATE_MASK |
2583                                     9 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
2584                 return;
2585         }
2586
2587         /* If the measurement is very high we've got a microphone,
2588          * either we just detected one or if we already reported then
2589          * we've got a button release event.
2590          */
2591         if (val & 0x400) {
2592                 if (wm8996->detecting) {
2593                         dev_dbg(codec->dev, "Microphone detected\n");
2594                         wm8996->jack_mic = true;
2595                         wm8996_hpdet_start(codec);
2596
2597                         /* Increase poll rate to give better responsiveness
2598                          * for buttons */
2599                         snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2600                                             WM8996_MICD_RATE_MASK |
2601                                             WM8996_MICD_BIAS_STARTTIME_MASK,
2602                                             5 << WM8996_MICD_RATE_SHIFT |
2603                                             7 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
2604                 } else {
2605                         dev_dbg(codec->dev, "Mic button up\n");
2606                         snd_soc_jack_report(wm8996->jack, 0, SND_JACK_BTN_0);
2607                 }
2608
2609                 return;
2610         }
2611
2612         /* If we detected a lower impedence during initial startup
2613          * then we probably have the wrong polarity, flip it.  Don't
2614          * do this for the lowest impedences to speed up detection of
2615          * plain headphones.
2616          */
2617         if (wm8996->detecting && (val & 0x3f0)) {
2618                 reg = snd_soc_read(codec, WM8996_ACCESSORY_DETECT_MODE_2);
2619                 reg ^= WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
2620                         WM8996_MICD_BIAS_SRC;
2621                 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2,
2622                                     WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
2623                                     WM8996_MICD_BIAS_SRC, reg);
2624
2625                 if (wm8996->polarity_cb)
2626                         wm8996->polarity_cb(codec,
2627                                             (reg & WM8996_MICD_SRC) != 0);
2628
2629                 dev_dbg(codec->dev, "Set microphone polarity to %d\n",
2630                         (reg & WM8996_MICD_SRC) != 0);
2631
2632                 return;
2633         }
2634
2635         /* Don't distinguish between buttons, just report any low
2636          * impedence as BTN_0.
2637          */
2638         if (val & 0x3fc) {
2639                 if (wm8996->jack_mic) {
2640                         dev_dbg(codec->dev, "Mic button detected\n");
2641                         snd_soc_jack_report(wm8996->jack, SND_JACK_BTN_0,
2642                                             SND_JACK_BTN_0);
2643                 } else if (wm8996->detecting) {
2644                         dev_dbg(codec->dev, "Headphone detected\n");
2645                         wm8996_hpdet_start(codec);
2646
2647                         /* Increase the detection rate a bit for
2648                          * responsiveness.
2649                          */
2650                         snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2651                                             WM8996_MICD_RATE_MASK |
2652                                             WM8996_MICD_BIAS_STARTTIME_MASK,
2653                                             7 << WM8996_MICD_RATE_SHIFT |
2654                                             7 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
2655                 }
2656         }
2657 }
2658
2659 static irqreturn_t wm8996_irq(int irq, void *data)
2660 {
2661         struct snd_soc_codec *codec = data;
2662         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2663         int irq_val;
2664
2665         irq_val = snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2);
2666         if (irq_val < 0) {
2667                 dev_err(codec->dev, "Failed to read IRQ status: %d\n",
2668                         irq_val);
2669                 return IRQ_NONE;
2670         }
2671         irq_val &= ~snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2_MASK);
2672
2673         if (!irq_val)
2674                 return IRQ_NONE;
2675
2676         snd_soc_write(codec, WM8996_INTERRUPT_STATUS_2, irq_val);
2677
2678         if (irq_val & (WM8996_DCS_DONE_01_EINT | WM8996_DCS_DONE_23_EINT)) {
2679                 dev_dbg(codec->dev, "DC servo IRQ\n");
2680                 complete(&wm8996->dcs_done);
2681         }
2682
2683         if (irq_val & WM8996_FIFOS_ERR_EINT)
2684                 dev_err(codec->dev, "Digital core FIFO error\n");
2685
2686         if (irq_val & WM8996_FLL_LOCK_EINT) {
2687                 dev_dbg(codec->dev, "FLL locked\n");
2688                 complete(&wm8996->fll_lock);
2689         }
2690
2691         if (irq_val & WM8996_MICD_EINT)
2692                 wm8996_micd(codec);
2693
2694         if (irq_val & WM8996_HP_DONE_EINT)
2695                 wm8996_hpdet_irq(codec);
2696
2697         return IRQ_HANDLED;
2698 }
2699
2700 static irqreturn_t wm8996_edge_irq(int irq, void *data)
2701 {
2702         irqreturn_t ret = IRQ_NONE;
2703         irqreturn_t val;
2704
2705         do {
2706                 val = wm8996_irq(irq, data);
2707                 if (val != IRQ_NONE)
2708                         ret = val;
2709         } while (val != IRQ_NONE);
2710
2711         return ret;
2712 }
2713
2714 static void wm8996_retune_mobile_pdata(struct snd_soc_codec *codec)
2715 {
2716         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2717         struct wm8996_pdata *pdata = &wm8996->pdata;
2718
2719         struct snd_kcontrol_new controls[] = {
2720                 SOC_ENUM_EXT("DSP1 EQ Mode",
2721                              wm8996->retune_mobile_enum,
2722                              wm8996_get_retune_mobile_enum,
2723                              wm8996_put_retune_mobile_enum),
2724                 SOC_ENUM_EXT("DSP2 EQ Mode",
2725                              wm8996->retune_mobile_enum,
2726                              wm8996_get_retune_mobile_enum,
2727                              wm8996_put_retune_mobile_enum),
2728         };
2729         int ret, i, j;
2730         const char **t;
2731
2732         /* We need an array of texts for the enum API but the number
2733          * of texts is likely to be less than the number of
2734          * configurations due to the sample rate dependency of the
2735          * configurations. */
2736         wm8996->num_retune_mobile_texts = 0;
2737         wm8996->retune_mobile_texts = NULL;
2738         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2739                 for (j = 0; j < wm8996->num_retune_mobile_texts; j++) {
2740                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
2741                                    wm8996->retune_mobile_texts[j]) == 0)
2742                                 break;
2743                 }
2744
2745                 if (j != wm8996->num_retune_mobile_texts)
2746                         continue;
2747
2748                 /* Expand the array... */
2749                 t = krealloc(wm8996->retune_mobile_texts,
2750                              sizeof(char *) *
2751                              (wm8996->num_retune_mobile_texts + 1),
2752                              GFP_KERNEL);
2753                 if (t == NULL)
2754                         continue;
2755
2756                 /* ...store the new entry... */
2757                 t[wm8996->num_retune_mobile_texts] =
2758                         pdata->retune_mobile_cfgs[i].name;
2759
2760                 /* ...and remember the new version. */
2761                 wm8996->num_retune_mobile_texts++;
2762                 wm8996->retune_mobile_texts = t;
2763         }
2764
2765         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2766                 wm8996->num_retune_mobile_texts);
2767
2768         wm8996->retune_mobile_enum.max = wm8996->num_retune_mobile_texts;
2769         wm8996->retune_mobile_enum.texts = wm8996->retune_mobile_texts;
2770
2771         ret = snd_soc_add_controls(codec, controls, ARRAY_SIZE(controls));
2772         if (ret != 0)
2773                 dev_err(codec->dev,
2774                         "Failed to add ReTune Mobile controls: %d\n", ret);
2775 }
2776
2777 static const struct regmap_config wm8996_regmap = {
2778         .reg_bits = 16,
2779         .val_bits = 16,
2780
2781         .max_register = WM8996_MAX_REGISTER,
2782         .reg_defaults = wm8996_reg,
2783         .num_reg_defaults = ARRAY_SIZE(wm8996_reg),
2784         .volatile_reg = wm8996_volatile_register,
2785         .readable_reg = wm8996_readable_register,
2786         .cache_type = REGCACHE_RBTREE,
2787 };
2788
2789 static int wm8996_probe(struct snd_soc_codec *codec)
2790 {
2791         int ret;
2792         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2793         struct i2c_client *i2c = to_i2c_client(codec->dev);
2794         struct snd_soc_dapm_context *dapm = &codec->dapm;
2795         int i, irq_flags;
2796
2797         wm8996->codec = codec;
2798
2799         init_completion(&wm8996->dcs_done);
2800         init_completion(&wm8996->fll_lock);
2801
2802         dapm->idle_bias_off = true;
2803
2804         codec->control_data = wm8996->regmap;
2805
2806         ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
2807         if (ret != 0) {
2808                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2809                 goto err;
2810         }
2811
2812         wm8996->disable_nb[0].notifier_call = wm8996_regulator_event_0;
2813         wm8996->disable_nb[1].notifier_call = wm8996_regulator_event_1;
2814         wm8996->disable_nb[2].notifier_call = wm8996_regulator_event_2;
2815
2816         /* This should really be moved into the regulator core */
2817         for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) {
2818                 ret = regulator_register_notifier(wm8996->supplies[i].consumer,
2819                                                   &wm8996->disable_nb[i]);
2820                 if (ret != 0) {
2821                         dev_err(codec->dev,
2822                                 "Failed to register regulator notifier: %d\n",
2823                                 ret);
2824                 }
2825         }
2826
2827         regcache_cache_only(codec->control_data, true);
2828
2829         /* Apply platform data settings */
2830         snd_soc_update_bits(codec, WM8996_LINE_INPUT_CONTROL,
2831                             WM8996_INL_MODE_MASK | WM8996_INR_MODE_MASK,
2832                             wm8996->pdata.inl_mode << WM8996_INL_MODE_SHIFT |
2833                             wm8996->pdata.inr_mode);
2834
2835         for (i = 0; i < ARRAY_SIZE(wm8996->pdata.gpio_default); i++) {
2836                 if (!wm8996->pdata.gpio_default[i])
2837                         continue;
2838
2839                 snd_soc_write(codec, WM8996_GPIO_1 + i,
2840                               wm8996->pdata.gpio_default[i] & 0xffff);
2841         }
2842
2843         if (wm8996->pdata.spkmute_seq)
2844                 snd_soc_update_bits(codec, WM8996_PDM_SPEAKER_MUTE_SEQUENCE,
2845                                     WM8996_SPK_MUTE_ENDIAN |
2846                                     WM8996_SPK_MUTE_SEQ1_MASK,
2847                                     wm8996->pdata.spkmute_seq);
2848
2849         snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2,
2850                             WM8996_MICD_BIAS_SRC | WM8996_HPOUT1FB_SRC |
2851                             WM8996_MICD_SRC, wm8996->pdata.micdet_def);
2852
2853         /* Latch volume update bits */
2854         snd_soc_update_bits(codec, WM8996_LEFT_LINE_INPUT_VOLUME,
2855                             WM8996_IN1_VU, WM8996_IN1_VU);
2856         snd_soc_update_bits(codec, WM8996_RIGHT_LINE_INPUT_VOLUME,
2857                             WM8996_IN1_VU, WM8996_IN1_VU);
2858
2859         snd_soc_update_bits(codec, WM8996_DAC1_LEFT_VOLUME,
2860                             WM8996_DAC1_VU, WM8996_DAC1_VU);
2861         snd_soc_update_bits(codec, WM8996_DAC1_RIGHT_VOLUME,
2862                             WM8996_DAC1_VU, WM8996_DAC1_VU);
2863         snd_soc_update_bits(codec, WM8996_DAC2_LEFT_VOLUME,
2864                             WM8996_DAC2_VU, WM8996_DAC2_VU);
2865         snd_soc_update_bits(codec, WM8996_DAC2_RIGHT_VOLUME,
2866                             WM8996_DAC2_VU, WM8996_DAC2_VU);
2867
2868         snd_soc_update_bits(codec, WM8996_OUTPUT1_LEFT_VOLUME,
2869                             WM8996_DAC1_VU, WM8996_DAC1_VU);
2870         snd_soc_update_bits(codec, WM8996_OUTPUT1_RIGHT_VOLUME,
2871                             WM8996_DAC1_VU, WM8996_DAC1_VU);
2872         snd_soc_update_bits(codec, WM8996_OUTPUT2_LEFT_VOLUME,
2873                             WM8996_DAC2_VU, WM8996_DAC2_VU);
2874         snd_soc_update_bits(codec, WM8996_OUTPUT2_RIGHT_VOLUME,
2875                             WM8996_DAC2_VU, WM8996_DAC2_VU);
2876
2877         snd_soc_update_bits(codec, WM8996_DSP1_TX_LEFT_VOLUME,
2878                             WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2879         snd_soc_update_bits(codec, WM8996_DSP1_TX_RIGHT_VOLUME,
2880                             WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2881         snd_soc_update_bits(codec, WM8996_DSP2_TX_LEFT_VOLUME,
2882                             WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2883         snd_soc_update_bits(codec, WM8996_DSP2_TX_RIGHT_VOLUME,
2884                             WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2885
2886         snd_soc_update_bits(codec, WM8996_DSP1_RX_LEFT_VOLUME,
2887                             WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2888         snd_soc_update_bits(codec, WM8996_DSP1_RX_RIGHT_VOLUME,
2889                             WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2890         snd_soc_update_bits(codec, WM8996_DSP2_RX_LEFT_VOLUME,
2891                             WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2892         snd_soc_update_bits(codec, WM8996_DSP2_RX_RIGHT_VOLUME,
2893                             WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2894
2895         /* No support currently for the underclocked TDM modes and
2896          * pick a default TDM layout with each channel pair working with
2897          * slots 0 and 1. */
2898         snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_0_CONFIGURATION,
2899                             WM8996_AIF1RX_CHAN0_SLOTS_MASK |
2900                             WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2901                             1 << WM8996_AIF1RX_CHAN0_SLOTS_SHIFT | 0);
2902         snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_1_CONFIGURATION,
2903                             WM8996_AIF1RX_CHAN1_SLOTS_MASK |
2904                             WM8996_AIF1RX_CHAN1_START_SLOT_MASK,
2905                             1 << WM8996_AIF1RX_CHAN1_SLOTS_SHIFT | 1);
2906         snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_2_CONFIGURATION,
2907                             WM8996_AIF1RX_CHAN2_SLOTS_MASK |
2908                             WM8996_AIF1RX_CHAN2_START_SLOT_MASK,
2909                             1 << WM8996_AIF1RX_CHAN2_SLOTS_SHIFT | 0);
2910         snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_3_CONFIGURATION,
2911                             WM8996_AIF1RX_CHAN3_SLOTS_MASK |
2912                             WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2913                             1 << WM8996_AIF1RX_CHAN3_SLOTS_SHIFT | 1);
2914         snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_4_CONFIGURATION,
2915                             WM8996_AIF1RX_CHAN4_SLOTS_MASK |
2916                             WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2917                             1 << WM8996_AIF1RX_CHAN4_SLOTS_SHIFT | 0);
2918         snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_5_CONFIGURATION,
2919                             WM8996_AIF1RX_CHAN5_SLOTS_MASK |
2920                             WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2921                             1 << WM8996_AIF1RX_CHAN5_SLOTS_SHIFT | 1);
2922
2923         snd_soc_update_bits(codec, WM8996_AIF2RX_CHANNEL_0_CONFIGURATION,
2924                             WM8996_AIF2RX_CHAN0_SLOTS_MASK |
2925                             WM8996_AIF2RX_CHAN0_START_SLOT_MASK,
2926                             1 << WM8996_AIF2RX_CHAN0_SLOTS_SHIFT | 0);
2927         snd_soc_update_bits(codec, WM8996_AIF2RX_CHANNEL_1_CONFIGURATION,
2928                             WM8996_AIF2RX_CHAN1_SLOTS_MASK |
2929                             WM8996_AIF2RX_CHAN1_START_SLOT_MASK,
2930                             1 << WM8996_AIF2RX_CHAN1_SLOTS_SHIFT | 1);
2931
2932         snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_0_CONFIGURATION,
2933                             WM8996_AIF1TX_CHAN0_SLOTS_MASK |
2934                             WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2935                             1 << WM8996_AIF1TX_CHAN0_SLOTS_SHIFT | 0);
2936         snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
2937                             WM8996_AIF1TX_CHAN1_SLOTS_MASK |
2938                             WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2939                             1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2940         snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_2_CONFIGURATION,
2941                             WM8996_AIF1TX_CHAN2_SLOTS_MASK |
2942                             WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2943                             1 << WM8996_AIF1TX_CHAN2_SLOTS_SHIFT | 0);
2944         snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_3_CONFIGURATION,
2945                             WM8996_AIF1TX_CHAN3_SLOTS_MASK |
2946                             WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2947                             1 << WM8996_AIF1TX_CHAN3_SLOTS_SHIFT | 1);
2948         snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_4_CONFIGURATION,
2949                             WM8996_AIF1TX_CHAN4_SLOTS_MASK |
2950                             WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2951                             1 << WM8996_AIF1TX_CHAN4_SLOTS_SHIFT | 0);
2952         snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_5_CONFIGURATION,
2953                             WM8996_AIF1TX_CHAN5_SLOTS_MASK |
2954                             WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2955                             1 << WM8996_AIF1TX_CHAN5_SLOTS_SHIFT | 1);
2956
2957         snd_soc_update_bits(codec, WM8996_AIF2TX_CHANNEL_0_CONFIGURATION,
2958                             WM8996_AIF2TX_CHAN0_SLOTS_MASK |
2959                             WM8996_AIF2TX_CHAN0_START_SLOT_MASK,
2960                             1 << WM8996_AIF2TX_CHAN0_SLOTS_SHIFT | 0);
2961         snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
2962                             WM8996_AIF2TX_CHAN1_SLOTS_MASK |
2963                             WM8996_AIF2TX_CHAN1_START_SLOT_MASK,
2964                             1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2965
2966         if (wm8996->pdata.num_retune_mobile_cfgs)
2967                 wm8996_retune_mobile_pdata(codec);
2968         else
2969                 snd_soc_add_controls(codec, wm8996_eq_controls,
2970                                      ARRAY_SIZE(wm8996_eq_controls));
2971
2972         /* If the TX LRCLK pins are not in LRCLK mode configure the
2973          * AIFs to source their clocks from the RX LRCLKs.
2974          */
2975         if ((snd_soc_read(codec, WM8996_GPIO_1)))
2976                 snd_soc_update_bits(codec, WM8996_AIF1_TX_LRCLK_2,
2977                                     WM8996_AIF1TX_LRCLK_MODE,
2978                                     WM8996_AIF1TX_LRCLK_MODE);
2979
2980         if ((snd_soc_read(codec, WM8996_GPIO_2)))
2981                 snd_soc_update_bits(codec, WM8996_AIF2_TX_LRCLK_2,
2982                                     WM8996_AIF2TX_LRCLK_MODE,
2983                                     WM8996_AIF2TX_LRCLK_MODE);
2984
2985         if (i2c->irq) {
2986                 if (wm8996->pdata.irq_flags)
2987                         irq_flags = wm8996->pdata.irq_flags;
2988                 else
2989                         irq_flags = IRQF_TRIGGER_LOW;
2990
2991                 irq_flags |= IRQF_ONESHOT;
2992
2993                 if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
2994                         ret = request_threaded_irq(i2c->irq, NULL,
2995                                                    wm8996_edge_irq,
2996                                                    irq_flags, "wm8996", codec);
2997                 else
2998                         ret = request_threaded_irq(i2c->irq, NULL, wm8996_irq,
2999                                                    irq_flags, "wm8996", codec);
3000
3001                 if (ret == 0) {
3002                         /* Unmask the interrupt */
3003                         snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL,
3004                                             WM8996_IM_IRQ, 0);
3005
3006                         /* Enable error reporting and DC servo status */
3007                         snd_soc_update_bits(codec,
3008                                             WM8996_INTERRUPT_STATUS_2_MASK,
3009                                             WM8996_IM_DCS_DONE_23_EINT |
3010                                             WM8996_IM_DCS_DONE_01_EINT |
3011                                             WM8996_IM_FLL_LOCK_EINT |
3012                                             WM8996_IM_FIFOS_ERR_EINT,
3013                                             0);
3014                 } else {
3015                         dev_err(codec->dev, "Failed to request IRQ: %d\n",
3016                                 ret);
3017                 }
3018         }
3019
3020         return 0;
3021
3022 err:
3023         return ret;
3024 }
3025
3026 static int wm8996_remove(struct snd_soc_codec *codec)
3027 {
3028         struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
3029         struct i2c_client *i2c = to_i2c_client(codec->dev);
3030         int i;
3031
3032         snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL,
3033                             WM8996_IM_IRQ, WM8996_IM_IRQ);
3034
3035         if (i2c->irq)
3036                 free_irq(i2c->irq, codec);
3037
3038         for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++)
3039                 regulator_unregister_notifier(wm8996->supplies[i].consumer,
3040                                               &wm8996->disable_nb[i]);
3041         regulator_put(wm8996->cpvdd);
3042         regulator_bulk_free(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
3043
3044         return 0;
3045 }
3046
3047 static int wm8996_soc_volatile_register(struct snd_soc_codec *codec,
3048                                         unsigned int reg)
3049 {
3050         return true;
3051 }
3052
3053 static struct snd_soc_codec_driver soc_codec_dev_wm8996 = {
3054         .probe =        wm8996_probe,
3055         .remove =       wm8996_remove,
3056         .set_bias_level = wm8996_set_bias_level,
3057         .seq_notifier = wm8996_seq_notifier,
3058         .controls = wm8996_snd_controls,
3059         .num_controls = ARRAY_SIZE(wm8996_snd_controls),
3060         .dapm_widgets = wm8996_dapm_widgets,
3061         .num_dapm_widgets = ARRAY_SIZE(wm8996_dapm_widgets),
3062         .dapm_routes = wm8996_dapm_routes,
3063         .num_dapm_routes = ARRAY_SIZE(wm8996_dapm_routes),
3064         .set_pll = wm8996_set_fll,
3065         .reg_cache_size = WM8996_MAX_REGISTER,
3066         .volatile_register = wm8996_soc_volatile_register,
3067 };
3068
3069 #define WM8996_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
3070                       SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
3071 #define WM8996_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
3072                         SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
3073                         SNDRV_PCM_FMTBIT_S32_LE)
3074
3075 static const struct snd_soc_dai_ops wm8996_dai_ops = {
3076         .set_fmt = wm8996_set_fmt,
3077         .hw_params = wm8996_hw_params,
3078         .set_sysclk = wm8996_set_sysclk,
3079 };
3080
3081 static struct snd_soc_dai_driver wm8996_dai[] = {
3082         {
3083                 .name = "wm8996-aif1",
3084                 .playback = {
3085                         .stream_name = "AIF1 Playback",
3086                         .channels_min = 1,
3087                         .channels_max = 6,
3088                         .rates = WM8996_RATES,
3089                         .formats = WM8996_FORMATS,
3090                 },
3091                 .capture = {
3092                          .stream_name = "AIF1 Capture",
3093                          .channels_min = 1,
3094                          .channels_max = 6,
3095                          .rates = WM8996_RATES,
3096                          .formats = WM8996_FORMATS,
3097                  },
3098                 .ops = &wm8996_dai_ops,
3099         },
3100         {
3101                 .name = "wm8996-aif2",
3102                 .playback = {
3103                         .stream_name = "AIF2 Playback",
3104                         .channels_min = 1,
3105                         .channels_max = 2,
3106                         .rates = WM8996_RATES,
3107                         .formats = WM8996_FORMATS,
3108                 },
3109                 .capture = {
3110                          .stream_name = "AIF2 Capture",
3111                          .channels_min = 1,
3112                          .channels_max = 2,
3113                          .rates = WM8996_RATES,
3114                          .formats = WM8996_FORMATS,
3115                  },
3116                 .ops = &wm8996_dai_ops,
3117         },
3118 };
3119
3120 static __devinit int wm8996_i2c_probe(struct i2c_client *i2c,
3121                                       const struct i2c_device_id *id)
3122 {
3123         struct wm8996_priv *wm8996;
3124         int ret, i;
3125         unsigned int reg;
3126
3127         wm8996 = devm_kzalloc(&i2c->dev, sizeof(struct wm8996_priv),
3128                               GFP_KERNEL);
3129         if (wm8996 == NULL)
3130                 return -ENOMEM;
3131
3132         i2c_set_clientdata(i2c, wm8996);
3133         wm8996->dev = &i2c->dev;
3134
3135         if (dev_get_platdata(&i2c->dev))
3136                 memcpy(&wm8996->pdata, dev_get_platdata(&i2c->dev),
3137                        sizeof(wm8996->pdata));
3138
3139         if (wm8996->pdata.ldo_ena > 0) {
3140                 ret = gpio_request_one(wm8996->pdata.ldo_ena,
3141                                        GPIOF_OUT_INIT_LOW, "WM8996 ENA");
3142                 if (ret < 0) {
3143                         dev_err(&i2c->dev, "Failed to request GPIO %d: %d\n",
3144                                 wm8996->pdata.ldo_ena, ret);
3145                         goto err;
3146                 }
3147         }
3148
3149         for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++)
3150                 wm8996->supplies[i].supply = wm8996_supply_names[i];
3151
3152         ret = regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8996->supplies),
3153                                  wm8996->supplies);
3154         if (ret != 0) {
3155                 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3156                 goto err_gpio;
3157         }
3158
3159         wm8996->cpvdd = regulator_get(&i2c->dev, "CPVDD");
3160         if (IS_ERR(wm8996->cpvdd)) {
3161                 ret = PTR_ERR(wm8996->cpvdd);
3162                 dev_err(&i2c->dev, "Failed to get CPVDD: %d\n", ret);
3163                 goto err_get;
3164         }
3165
3166         ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
3167                                     wm8996->supplies);
3168         if (ret != 0) {
3169                 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
3170                 goto err_cpvdd;
3171         }
3172
3173         if (wm8996->pdata.ldo_ena > 0) {
3174                 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 1);
3175                 msleep(5);
3176         }
3177
3178         wm8996->regmap = regmap_init_i2c(i2c, &wm8996_regmap);
3179         if (IS_ERR(wm8996->regmap)) {
3180                 ret = PTR_ERR(wm8996->regmap);
3181                 dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
3182                 goto err_enable;
3183         }
3184
3185         ret = regmap_read(wm8996->regmap, WM8996_SOFTWARE_RESET, &reg);
3186         if (ret < 0) {
3187                 dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
3188                 goto err_regmap;
3189         }
3190         if (reg != 0x8915) {
3191                 dev_err(&i2c->dev, "Device is not a WM8996, ID %x\n", ret);
3192                 ret = -EINVAL;
3193                 goto err_regmap;
3194         }
3195
3196         ret = regmap_read(wm8996->regmap, WM8996_CHIP_REVISION, &reg);
3197         if (ret < 0) {
3198                 dev_err(&i2c->dev, "Failed to read device revision: %d\n",
3199                         ret);
3200                 goto err_regmap;
3201         }
3202
3203         dev_info(&i2c->dev, "revision %c\n",
3204                  (reg & WM8996_CHIP_REV_MASK) + 'A');
3205
3206         regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
3207
3208         ret = wm8996_reset(wm8996);
3209         if (ret < 0) {
3210                 dev_err(&i2c->dev, "Failed to issue reset\n");
3211                 goto err_regmap;
3212         }
3213
3214         wm8996_init_gpio(wm8996);
3215
3216         ret = snd_soc_register_codec(&i2c->dev,
3217                                      &soc_codec_dev_wm8996, wm8996_dai,
3218                                      ARRAY_SIZE(wm8996_dai));
3219         if (ret < 0)
3220                 goto err_gpiolib;
3221
3222         return ret;
3223
3224 err_gpiolib:
3225         wm8996_free_gpio(wm8996);
3226 err_regmap:
3227         regmap_exit(wm8996->regmap);
3228 err_enable:
3229         if (wm8996->pdata.ldo_ena > 0)
3230                 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
3231         regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
3232 err_cpvdd:
3233         regulator_put(wm8996->cpvdd);
3234 err_get:
3235         regulator_bulk_free(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
3236 err_gpio:
3237         if (wm8996->pdata.ldo_ena > 0)
3238                 gpio_free(wm8996->pdata.ldo_ena);
3239 err:
3240
3241         return ret;
3242 }
3243
3244 static __devexit int wm8996_i2c_remove(struct i2c_client *client)
3245 {
3246         struct wm8996_priv *wm8996 = i2c_get_clientdata(client);
3247
3248         snd_soc_unregister_codec(&client->dev);
3249         wm8996_free_gpio(wm8996);
3250         regulator_put(wm8996->cpvdd);
3251         regulator_bulk_free(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
3252         regmap_exit(wm8996->regmap);
3253         if (wm8996->pdata.ldo_ena > 0) {
3254                 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
3255                 gpio_free(wm8996->pdata.ldo_ena);
3256         }
3257         return 0;
3258 }
3259
3260 static const struct i2c_device_id wm8996_i2c_id[] = {
3261         { "wm8996", 0 },
3262         { }
3263 };
3264 MODULE_DEVICE_TABLE(i2c, wm8996_i2c_id);
3265
3266 static struct i2c_driver wm8996_i2c_driver = {
3267         .driver = {
3268                 .name = "wm8996",
3269                 .owner = THIS_MODULE,
3270         },
3271         .probe =    wm8996_i2c_probe,
3272         .remove =   __devexit_p(wm8996_i2c_remove),
3273         .id_table = wm8996_i2c_id,
3274 };
3275
3276 static int __init wm8996_modinit(void)
3277 {
3278         int ret;
3279
3280         ret = i2c_add_driver(&wm8996_i2c_driver);
3281         if (ret != 0) {
3282                 printk(KERN_ERR "Failed to register WM8996 I2C driver: %d\n",
3283                        ret);
3284         }
3285
3286         return ret;
3287 }
3288 module_init(wm8996_modinit);
3289
3290 static void __exit wm8996_exit(void)
3291 {
3292         i2c_del_driver(&wm8996_i2c_driver);
3293 }
3294 module_exit(wm8996_exit);
3295
3296 MODULE_DESCRIPTION("ASoC WM8996 driver");
3297 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3298 MODULE_LICENSE("GPL");