2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
4 * Author: Timur Tabi <timur@freescale.com>
6 * Copyright 2007-2010 Freescale Semiconductor, Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
17 * one FIFO which combines all valid receive slots. We cannot even select
18 * which slots we want to receive. The WM9712 with which this driver
19 * was developed with always sends GPIO status data in slot 12 which
20 * we receive in our (PCM-) data stream. The only chance we have is to
21 * manually skip this data in the FIQ handler. With sampling rates different
22 * from 48000Hz not every frame has valid receive data, so the ratio
23 * between pcm data and GPIO status data changes. Our FIQ handler is not
24 * able to handle this, hence this driver only works with 48000Hz sampling
26 * Reading and writing AC97 registers is another challenge. The core
27 * provides us status bits when the read register is updated with *another*
28 * value. When we read the same register two times (and the register still
29 * contains the same value) these status bits are not set. We work
30 * around this by not polling these bits but only wait a fixed delay.
33 #include <linux/init.h>
35 #include <linux/module.h>
36 #include <linux/interrupt.h>
37 #include <linux/clk.h>
38 #include <linux/device.h>
39 #include <linux/delay.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42 #include <linux/of_address.h>
43 #include <linux/of_irq.h>
44 #include <linux/of_platform.h>
46 #include <sound/core.h>
47 #include <sound/pcm.h>
48 #include <sound/pcm_params.h>
49 #include <sound/initval.h>
50 #include <sound/soc.h>
51 #include <sound/dmaengine_pcm.h>
57 #define read_ssi(addr) in_be32(addr)
58 #define write_ssi(val, addr) out_be32(addr, val)
59 #define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set)
61 #define read_ssi(addr) readl(addr)
62 #define write_ssi(val, addr) writel(val, addr)
64 * FIXME: Proper locking should be added at write_ssi_mask caller level
65 * to ensure this register read/modify/write sequence is race free.
67 static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set)
69 u32 val = readl(addr);
70 val = (val & ~clear) | set;
76 * FSLSSI_I2S_RATES: sample rates supported by the I2S
78 * This driver currently only supports the SSI running in I2S slave mode,
79 * which means the codec determines the sample rate. Therefore, we tell
80 * ALSA that we support all rates and let the codec driver decide what rates
81 * are really supported.
83 #define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS
86 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
88 * This driver currently only supports the SSI running in I2S slave mode.
90 * The SSI has a limitation in that the samples must be in the same byte
91 * order as the host CPU. This is because when multiple bytes are written
92 * to the STX register, the bytes and bits must be written in the same
93 * order. The STX is a shift register, so all the bits need to be aligned
94 * (bit-endianness must match byte-endianness). Processors typically write
95 * the bits within a byte in the same order that the bytes of a word are
96 * written in. So if the host CPU is big-endian, then only big-endian
97 * samples will be written to STX properly.
100 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
101 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
102 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
104 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
105 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
106 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
109 #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \
110 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \
111 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN)
112 #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \
113 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \
114 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN)
123 struct fsl_ssi_reg_val {
130 struct fsl_ssi_rxtx_reg_val {
131 struct fsl_ssi_reg_val rx;
132 struct fsl_ssi_reg_val tx;
135 struct fsl_ssi_soc_data {
142 * fsl_ssi_private: per-SSI private data
144 * @ssi: pointer to the SSI's registers
145 * @ssi_phys: physical address of the SSI registers
146 * @irq: IRQ of this SSI
147 * @playback: the number of playback streams opened
148 * @capture: the number of capture streams opened
149 * @cpu_dai: the CPU DAI for this device
150 * @dev_attr: the sysfs device attribute structure
151 * @stats: SSI statistics
153 struct fsl_ssi_private {
154 struct ccsr_ssi __iomem *ssi;
157 unsigned int fifo_depth;
158 struct snd_soc_dai_driver cpu_dai_drv;
159 struct platform_device *pdev;
160 unsigned int dai_fmt;
166 spinlock_t baudclk_lock;
169 struct snd_dmaengine_dai_dma_data dma_params_tx;
170 struct snd_dmaengine_dai_dma_data dma_params_rx;
171 struct imx_pcm_fiq_params fiq_params;
172 /* Register values for rx/tx configuration */
173 struct fsl_ssi_rxtx_reg_val rxtx_reg_val;
175 struct fsl_ssi_dbg dbg_stats;
177 const struct fsl_ssi_soc_data *soc;
181 * imx51 and later SoCs have a slightly different IP that allows the
182 * SSI configuration while the SSI unit is running.
184 * More important, it is necessary on those SoCs to configure the
185 * sperate TX/RX DMA bits just before starting the stream
186 * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi
187 * sends any DMA requests to the SDMA unit, otherwise it is not defined
188 * how the SDMA unit handles the DMA request.
190 * SDMA units are present on devices starting at imx35 but the imx35
191 * reference manual states that the DMA bits should not be changed
192 * while the SSI unit is running (SSIEN). So we support the necessary
193 * online configuration of fsl-ssi starting at imx51.
196 static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = {
198 .offline_config = true,
199 .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
200 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
201 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
204 static struct fsl_ssi_soc_data fsl_ssi_imx21 = {
206 .offline_config = true,
207 .sisr_write_mask = 0,
210 static struct fsl_ssi_soc_data fsl_ssi_imx35 = {
212 .offline_config = true,
213 .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
214 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
215 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
218 static struct fsl_ssi_soc_data fsl_ssi_imx51 = {
220 .offline_config = false,
221 .sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
222 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
225 static const struct of_device_id fsl_ssi_ids[] = {
226 { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 },
227 { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 },
228 { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 },
229 { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 },
232 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
234 static bool fsl_ssi_is_ac97(struct fsl_ssi_private *ssi_private)
236 return !!(ssi_private->dai_fmt & SND_SOC_DAIFMT_AC97);
240 * fsl_ssi_isr: SSI interrupt handler
242 * Although it's possible to use the interrupt handler to send and receive
243 * data to/from the SSI, we use the DMA instead. Programming is more
244 * complicated, but the performance is much better.
246 * This interrupt handler is used only to gather statistics.
248 * @irq: IRQ of the SSI device
249 * @dev_id: pointer to the ssi_private structure for this SSI device
251 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
253 struct fsl_ssi_private *ssi_private = dev_id;
254 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
258 /* We got an interrupt, so read the status register to see what we
259 were interrupted for. We mask it with the Interrupt Enable register
260 so that we only check for events that we're interested in.
262 sisr = read_ssi(&ssi->sisr);
264 sisr2 = sisr & ssi_private->soc->sisr_write_mask;
265 /* Clear the bits that we set */
267 write_ssi(sisr2, &ssi->sisr);
269 fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr);
275 * Enable/Disable all rx/tx config flags at once.
277 static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private,
280 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
281 struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val;
284 write_ssi_mask(&ssi->sier, 0, vals->rx.sier | vals->tx.sier);
285 write_ssi_mask(&ssi->srcr, 0, vals->rx.srcr | vals->tx.srcr);
286 write_ssi_mask(&ssi->stcr, 0, vals->rx.stcr | vals->tx.stcr);
288 write_ssi_mask(&ssi->srcr, vals->rx.srcr | vals->tx.srcr, 0);
289 write_ssi_mask(&ssi->stcr, vals->rx.stcr | vals->tx.stcr, 0);
290 write_ssi_mask(&ssi->sier, vals->rx.sier | vals->tx.sier, 0);
295 * Calculate the bits that have to be disabled for the current stream that is
296 * getting disabled. This keeps the bits enabled that are necessary for the
297 * second stream to work if 'stream_active' is true.
299 * Detailed calculation:
300 * These are the values that need to be active after disabling. For non-active
301 * second stream, this is 0:
302 * vals_stream * !!stream_active
304 * The following computes the overall differences between the setup for the
305 * to-disable stream and the active stream, a simple XOR:
306 * vals_disable ^ (vals_stream * !!(stream_active))
308 * The full expression adds a mask on all values we care about
310 #define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \
312 ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active))))
315 * Enable/Disable a ssi configuration. You have to pass either
316 * ssi_private->rxtx_reg_val.rx or tx as vals parameter.
318 static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
319 struct fsl_ssi_reg_val *vals)
321 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
322 struct fsl_ssi_reg_val *avals;
323 u32 scr_val = read_ssi(&ssi->scr);
324 int nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) +
325 !!(scr_val & CCSR_SSI_SCR_RE);
328 if (nr_active_streams - 1 > 0)
333 /* Find the other direction values rx or tx which we do not want to
335 if (&ssi_private->rxtx_reg_val.rx == vals)
336 avals = &ssi_private->rxtx_reg_val.tx;
338 avals = &ssi_private->rxtx_reg_val.rx;
340 /* If vals should be disabled, start with disabling the unit */
342 u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr,
344 write_ssi_mask(&ssi->scr, scr, 0);
348 * We are running on a SoC which does not support online SSI
349 * reconfiguration, so we have to enable all necessary flags at once
350 * even if we do not use them later (capture and playback configuration)
352 if (ssi_private->soc->offline_config) {
353 if ((enable && !nr_active_streams) ||
354 (!enable && !keep_active))
355 fsl_ssi_rxtx_config(ssi_private, enable);
361 * Configure single direction units while the SSI unit is running
362 * (online configuration)
365 write_ssi_mask(&ssi->sier, 0, vals->sier);
366 write_ssi_mask(&ssi->srcr, 0, vals->srcr);
367 write_ssi_mask(&ssi->stcr, 0, vals->stcr);
374 * Disabling the necessary flags for one of rx/tx while the
375 * other stream is active is a little bit more difficult. We
376 * have to disable only those flags that differ between both
377 * streams (rx XOR tx) and that are set in the stream that is
378 * disabled now. Otherwise we could alter flags of the other
382 /* These assignments are simply vals without bits set in avals*/
383 sier = fsl_ssi_disable_val(vals->sier, avals->sier,
385 srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr,
387 stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr,
390 write_ssi_mask(&ssi->srcr, srcr, 0);
391 write_ssi_mask(&ssi->stcr, stcr, 0);
392 write_ssi_mask(&ssi->sier, sier, 0);
396 /* Enabling of subunits is done after configuration */
398 write_ssi_mask(&ssi->scr, 0, vals->scr);
402 static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable)
404 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx);
407 static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable)
409 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx);
413 * Setup rx/tx register values used to enable/disable the streams. These will
414 * be used later in fsl_ssi_config to setup the streams without the need to
415 * check for all different SSI modes.
417 static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private)
419 struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val;
421 reg->rx.sier = CCSR_SSI_SIER_RFF0_EN;
422 reg->rx.srcr = CCSR_SSI_SRCR_RFEN0;
424 reg->tx.sier = CCSR_SSI_SIER_TFE0_EN;
425 reg->tx.stcr = CCSR_SSI_STCR_TFEN0;
428 if (!fsl_ssi_is_ac97(ssi_private)) {
429 reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE;
430 reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN;
431 reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE;
432 reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN;
435 if (ssi_private->use_dma) {
436 reg->rx.sier |= CCSR_SSI_SIER_RDMAE;
437 reg->tx.sier |= CCSR_SSI_SIER_TDMAE;
439 reg->rx.sier |= CCSR_SSI_SIER_RIE;
440 reg->tx.sier |= CCSR_SSI_SIER_TIE;
443 reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS;
444 reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS;
447 static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private)
449 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
452 * Setup the clock control register
454 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
456 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
460 * Enable AC97 mode and startup the SSI
462 write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV,
464 write_ssi(0xff, &ssi->saccdis);
465 write_ssi(0x300, &ssi->saccen);
468 * Enable SSI, Transmit and Receive. AC97 has to communicate with the
469 * codec before a stream is started.
471 write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN |
472 CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
474 write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor);
478 * fsl_ssi_startup: create a new substream
480 * This is the first function called when a stream is opened.
482 * If this is the first stream open, then grab the IRQ and program most of
485 static int fsl_ssi_startup(struct snd_pcm_substream *substream,
486 struct snd_soc_dai *dai)
488 struct snd_soc_pcm_runtime *rtd = substream->private_data;
489 struct fsl_ssi_private *ssi_private =
490 snd_soc_dai_get_drvdata(rtd->cpu_dai);
493 if (!dai->active && !fsl_ssi_is_ac97(ssi_private)) {
494 spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
495 ssi_private->baudclk_locked = false;
496 spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
499 /* When using dual fifo mode, it is safer to ensure an even period
500 * size. If appearing to an odd number while DMA always starts its
501 * task from fifo0, fifo1 would be neglected at the end of each
502 * period. But SSI would still access fifo1 with an invalid data.
504 if (ssi_private->use_dual_fifo)
505 snd_pcm_hw_constraint_step(substream->runtime, 0,
506 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
512 * fsl_ssi_set_dai_sysclk - configure Digital Audio Interface bit clock
514 * Note: This function can be only called when using SSI as DAI master
516 * Quick instruction for parameters:
517 * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
518 * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
520 static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
521 int clk_id, unsigned int freq, int dir)
523 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
524 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
525 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret;
526 u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
527 unsigned long flags, clkrate, baudrate, tmprate;
528 u64 sub, savesub = 100000;
530 /* Don't apply it to any non-baudclk circumstance */
531 if (IS_ERR(ssi_private->baudclk))
534 /* It should be already enough to divide clock by setting pm alone */
538 factor = (div2 + 1) * (7 * psr + 1) * 2;
540 for (i = 0; i < 255; i++) {
541 /* The bclk rate must be smaller than 1/5 sysclk rate */
542 if (factor * (i + 1) < 5)
545 tmprate = freq * factor * (i + 2);
546 clkrate = clk_round_rate(ssi_private->baudclk, tmprate);
548 do_div(clkrate, factor);
549 afreq = (u32)clkrate / (i + 1);
553 else if (freq / afreq == 1)
555 else if (afreq / freq == 1)
560 /* Calculate the fraction */
575 /* No proper pm found if it is still remaining the initial value */
577 dev_err(cpu_dai->dev, "failed to handle the required sysclk\n");
581 stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) |
582 (psr ? CCSR_SSI_SxCCR_PSR : 0);
583 mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 |
586 if (dir == SND_SOC_CLOCK_OUT || synchronous)
587 write_ssi_mask(&ssi->stccr, mask, stccr);
589 write_ssi_mask(&ssi->srccr, mask, stccr);
591 spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
592 if (!ssi_private->baudclk_locked) {
593 ret = clk_set_rate(ssi_private->baudclk, baudrate);
595 spin_unlock_irqrestore(&ssi_private->baudclk_lock,
597 dev_err(cpu_dai->dev, "failed to set baudclk rate\n");
600 ssi_private->baudclk_locked = true;
602 spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
608 * fsl_ssi_hw_params - program the sample size
610 * Most of the SSI registers have been programmed in the startup function,
611 * but the word length must be programmed here. Unfortunately, programming
612 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can
613 * cause a problem with supporting simultaneous playback and capture. If
614 * the SSI is already playing a stream, then that stream may be temporarily
615 * stopped when you start capture.
617 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
620 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
621 struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
623 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
624 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
625 unsigned int channels = params_channels(hw_params);
626 unsigned int sample_size =
627 snd_pcm_format_width(params_format(hw_params));
628 u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
629 int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
632 * If we're in synchronous mode, and the SSI is already enabled,
633 * then STCCR is already set properly.
635 if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
639 * FIXME: The documentation says that SxCCR[WL] should not be
640 * modified while the SSI is enabled. The only time this can
641 * happen is if we're trying to do simultaneous playback and
642 * capture in asynchronous mode. Unfortunately, I have been enable
643 * to get that to work at all on the P1022DS. Therefore, we don't
644 * bother to disable/enable the SSI when setting SxCCR[WL], because
645 * the SSI will stop anyway. Maybe one day, this will get fixed.
648 /* In synchronous mode, the SSI uses STCCR for capture */
649 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
650 ssi_private->cpu_dai_drv.symmetric_rates)
651 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl);
653 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl);
655 if (!fsl_ssi_is_ac97(ssi_private))
656 write_ssi_mask(&ssi->scr,
657 CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK,
658 channels == 1 ? 0 : ssi_private->i2s_mode);
664 * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
666 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
668 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
669 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
670 u32 strcr = 0, stcr, srcr, scr, mask;
673 ssi_private->dai_fmt = fmt;
675 fsl_ssi_setup_reg_vals(ssi_private);
677 scr = read_ssi(&ssi->scr) & ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK);
678 scr |= CCSR_SSI_SCR_SYNC_TX_FS;
680 mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR |
681 CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL |
683 stcr = read_ssi(&ssi->stcr) & ~mask;
684 srcr = read_ssi(&ssi->srcr) & ~mask;
686 ssi_private->i2s_mode = CCSR_SSI_SCR_NET;
687 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
688 case SND_SOC_DAIFMT_I2S:
689 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
690 case SND_SOC_DAIFMT_CBS_CFS:
691 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER;
693 case SND_SOC_DAIFMT_CBM_CFM:
694 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE;
700 /* Data on rising edge of bclk, frame low, 1clk before data */
701 strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP |
702 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
704 case SND_SOC_DAIFMT_LEFT_J:
705 /* Data on rising edge of bclk, frame high */
706 strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP;
708 case SND_SOC_DAIFMT_DSP_A:
709 /* Data on rising edge of bclk, frame high, 1clk before data */
710 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
711 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
713 case SND_SOC_DAIFMT_DSP_B:
714 /* Data on rising edge of bclk, frame high */
715 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
716 CCSR_SSI_STCR_TXBIT0;
718 case SND_SOC_DAIFMT_AC97:
719 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL;
724 scr |= ssi_private->i2s_mode;
726 /* DAI clock inversion */
727 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
728 case SND_SOC_DAIFMT_NB_NF:
729 /* Nothing to do for both normal cases */
731 case SND_SOC_DAIFMT_IB_NF:
732 /* Invert bit clock */
733 strcr ^= CCSR_SSI_STCR_TSCKP;
735 case SND_SOC_DAIFMT_NB_IF:
736 /* Invert frame clock */
737 strcr ^= CCSR_SSI_STCR_TFSI;
739 case SND_SOC_DAIFMT_IB_IF:
740 /* Invert both clocks */
741 strcr ^= CCSR_SSI_STCR_TSCKP;
742 strcr ^= CCSR_SSI_STCR_TFSI;
748 /* DAI clock master masks */
749 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
750 case SND_SOC_DAIFMT_CBS_CFS:
751 strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR;
752 scr |= CCSR_SSI_SCR_SYS_CLK_EN;
754 case SND_SOC_DAIFMT_CBM_CFM:
755 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
764 if (ssi_private->cpu_dai_drv.symmetric_rates) {
765 /* Need to clear RXDIR when using SYNC mode */
766 srcr &= ~CCSR_SSI_SRCR_RXDIR;
767 scr |= CCSR_SSI_SCR_SYN;
770 write_ssi(stcr, &ssi->stcr);
771 write_ssi(srcr, &ssi->srcr);
772 write_ssi(scr, &ssi->scr);
775 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
776 * use FIFO 1. We program the transmit water to signal a DMA transfer
777 * if there are only two (or fewer) elements left in the FIFO. Two
778 * elements equals one frame (left channel, right channel). This value,
779 * however, depends on the depth of the transmit buffer.
781 * We set the watermark on the same level as the DMA burstsize. For
782 * fiq it is probably better to use the biggest possible watermark
785 if (ssi_private->use_dma)
786 wm = ssi_private->fifo_depth - 2;
788 wm = ssi_private->fifo_depth;
790 write_ssi(CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
791 CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm),
794 if (ssi_private->use_dual_fifo) {
795 write_ssi_mask(&ssi->srcr, CCSR_SSI_SRCR_RFEN1,
796 CCSR_SSI_SRCR_RFEN1);
797 write_ssi_mask(&ssi->stcr, CCSR_SSI_STCR_TFEN1,
798 CCSR_SSI_STCR_TFEN1);
799 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TCH_EN,
800 CCSR_SSI_SCR_TCH_EN);
803 if (fmt & SND_SOC_DAIFMT_AC97)
804 fsl_ssi_setup_ac97(ssi_private);
810 * fsl_ssi_set_dai_tdm_slot - set TDM slot number
812 * Note: This function can be only called when using SSI as DAI master
814 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
815 u32 rx_mask, int slots, int slot_width)
817 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
818 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
821 /* The slot number should be >= 2 if using Network mode or I2S mode */
822 val = read_ssi(&ssi->scr) & (CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET);
823 if (val && slots < 2) {
824 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n");
828 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK,
829 CCSR_SSI_SxCCR_DC(slots));
830 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_DC_MASK,
831 CCSR_SSI_SxCCR_DC(slots));
833 /* The register SxMSKs needs SSI to provide essential clock due to
834 * hardware design. So we here temporarily enable SSI to set them.
836 val = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
837 write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN);
839 write_ssi(tx_mask, &ssi->stmsk);
840 write_ssi(rx_mask, &ssi->srmsk);
842 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, val);
848 * fsl_ssi_trigger: start and stop the DMA transfer.
850 * This function is called by ALSA to start, stop, pause, and resume the DMA
853 * The DMA channel is in external master start and pause mode, which
854 * means the SSI completely controls the flow of data.
856 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
857 struct snd_soc_dai *dai)
859 struct snd_soc_pcm_runtime *rtd = substream->private_data;
860 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
861 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
865 case SNDRV_PCM_TRIGGER_START:
866 case SNDRV_PCM_TRIGGER_RESUME:
867 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
868 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
869 fsl_ssi_tx_config(ssi_private, true);
871 fsl_ssi_rx_config(ssi_private, true);
874 case SNDRV_PCM_TRIGGER_STOP:
875 case SNDRV_PCM_TRIGGER_SUSPEND:
876 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
877 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
878 fsl_ssi_tx_config(ssi_private, false);
880 fsl_ssi_rx_config(ssi_private, false);
882 if (!fsl_ssi_is_ac97(ssi_private) && (read_ssi(&ssi->scr) &
883 (CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0) {
884 spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
885 ssi_private->baudclk_locked = false;
886 spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
894 if (fsl_ssi_is_ac97(ssi_private)) {
895 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
896 write_ssi(CCSR_SSI_SOR_TX_CLR, &ssi->sor);
898 write_ssi(CCSR_SSI_SOR_RX_CLR, &ssi->sor);
904 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
906 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
908 if (ssi_private->soc->imx && ssi_private->use_dma) {
909 dai->playback_dma_data = &ssi_private->dma_params_tx;
910 dai->capture_dma_data = &ssi_private->dma_params_rx;
916 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
917 .startup = fsl_ssi_startup,
918 .hw_params = fsl_ssi_hw_params,
919 .set_fmt = fsl_ssi_set_dai_fmt,
920 .set_sysclk = fsl_ssi_set_dai_sysclk,
921 .set_tdm_slot = fsl_ssi_set_dai_tdm_slot,
922 .trigger = fsl_ssi_trigger,
925 /* Template for the CPU dai driver structure */
926 static struct snd_soc_dai_driver fsl_ssi_dai_template = {
927 .probe = fsl_ssi_dai_probe,
931 .rates = FSLSSI_I2S_RATES,
932 .formats = FSLSSI_I2S_FORMATS,
937 .rates = FSLSSI_I2S_RATES,
938 .formats = FSLSSI_I2S_FORMATS,
940 .ops = &fsl_ssi_dai_ops,
943 static const struct snd_soc_component_driver fsl_ssi_component = {
947 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
950 .stream_name = "AC97 Playback",
953 .rates = SNDRV_PCM_RATE_8000_48000,
954 .formats = SNDRV_PCM_FMTBIT_S16_LE,
957 .stream_name = "AC97 Capture",
960 .rates = SNDRV_PCM_RATE_48000,
961 .formats = SNDRV_PCM_FMTBIT_S16_LE,
963 .ops = &fsl_ssi_dai_ops,
967 static struct fsl_ssi_private *fsl_ac97_data;
969 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
972 struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
981 write_ssi(lreg, &ssi->sacadd);
984 write_ssi(lval , &ssi->sacdat);
986 write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
991 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
994 struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
996 unsigned short val = -1;
999 lreg = (reg & 0x7f) << 12;
1000 write_ssi(lreg, &ssi->sacadd);
1001 write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
1006 val = (read_ssi(&ssi->sacdat) >> 4) & 0xffff;
1011 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
1012 .read = fsl_ssi_ac97_read,
1013 .write = fsl_ssi_ac97_write,
1017 * Make every character in a string lower-case
1019 static void make_lowercase(char *s)
1025 if ((c >= 'A') && (c <= 'Z'))
1026 *p = c + ('a' - 'A');
1031 static int fsl_ssi_imx_probe(struct platform_device *pdev,
1032 struct fsl_ssi_private *ssi_private, void __iomem *iomem)
1034 struct device_node *np = pdev->dev.of_node;
1038 ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
1039 if (IS_ERR(ssi_private->clk)) {
1040 ret = PTR_ERR(ssi_private->clk);
1041 dev_err(&pdev->dev, "could not get clock: %d\n", ret);
1045 ret = clk_prepare_enable(ssi_private->clk);
1047 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1051 /* For those SLAVE implementations, we ingore non-baudclk cases
1052 * and, instead, abandon MASTER mode that needs baud clock.
1054 ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud");
1055 if (IS_ERR(ssi_private->baudclk))
1056 dev_dbg(&pdev->dev, "could not get baud clock: %ld\n",
1057 PTR_ERR(ssi_private->baudclk));
1059 clk_prepare_enable(ssi_private->baudclk);
1062 * We have burstsize be "fifo_depth - 2" to match the SSI
1063 * watermark setting in fsl_ssi_startup().
1065 ssi_private->dma_params_tx.maxburst = ssi_private->fifo_depth - 2;
1066 ssi_private->dma_params_rx.maxburst = ssi_private->fifo_depth - 2;
1067 ssi_private->dma_params_tx.addr = ssi_private->ssi_phys +
1068 offsetof(struct ccsr_ssi, stx0);
1069 ssi_private->dma_params_rx.addr = ssi_private->ssi_phys +
1070 offsetof(struct ccsr_ssi, srx0);
1072 ret = !of_property_read_u32_array(np, "dmas", dmas, 4);
1073 if (ssi_private->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) {
1074 ssi_private->use_dual_fifo = true;
1075 /* When using dual fifo mode, we need to keep watermark
1076 * as even numbers due to dma script limitation.
1078 ssi_private->dma_params_tx.maxburst &= ~0x1;
1079 ssi_private->dma_params_rx.maxburst &= ~0x1;
1082 if (!ssi_private->use_dma) {
1085 * Some boards use an incompatible codec. To get it
1086 * working, we are using imx-fiq-pcm-audio, that
1087 * can handle those codecs. DMA is not possible in this
1091 ssi_private->fiq_params.irq = ssi_private->irq;
1092 ssi_private->fiq_params.base = iomem;
1093 ssi_private->fiq_params.dma_params_rx =
1094 &ssi_private->dma_params_rx;
1095 ssi_private->fiq_params.dma_params_tx =
1096 &ssi_private->dma_params_tx;
1098 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
1102 ret = imx_pcm_dma_init(pdev);
1110 if (!IS_ERR(ssi_private->baudclk))
1111 clk_disable_unprepare(ssi_private->baudclk);
1113 clk_disable_unprepare(ssi_private->clk);
1118 static void fsl_ssi_imx_clean(struct platform_device *pdev,
1119 struct fsl_ssi_private *ssi_private)
1121 if (!ssi_private->use_dma)
1122 imx_pcm_fiq_exit(pdev);
1123 if (!IS_ERR(ssi_private->baudclk))
1124 clk_disable_unprepare(ssi_private->baudclk);
1125 clk_disable_unprepare(ssi_private->clk);
1128 static int fsl_ssi_probe(struct platform_device *pdev)
1130 struct fsl_ssi_private *ssi_private;
1132 struct device_node *np = pdev->dev.of_node;
1133 const struct of_device_id *of_id;
1134 const char *p, *sprop;
1135 const uint32_t *iprop;
1136 struct resource res;
1140 /* SSIs that are not connected on the board should have a
1141 * status = "disabled"
1142 * property in their device tree nodes.
1144 if (!of_device_is_available(np))
1147 of_id = of_match_device(fsl_ssi_ids, &pdev->dev);
1148 if (!of_id || !of_id->data)
1151 sprop = of_get_property(np, "fsl,mode", NULL);
1153 dev_err(&pdev->dev, "fsl,mode property is necessary\n");
1156 if (!strcmp(sprop, "ac97-slave"))
1159 ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private),
1162 dev_err(&pdev->dev, "could not allocate DAI object\n");
1166 ssi_private->soc = of_id->data;
1168 ssi_private->use_dma = !of_property_read_bool(np,
1169 "fsl,fiq-stream-filter");
1172 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
1173 sizeof(fsl_ssi_ac97_dai));
1175 fsl_ac97_data = ssi_private;
1177 snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
1179 /* Initialize this copy of the CPU DAI driver structure */
1180 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
1181 sizeof(fsl_ssi_dai_template));
1183 ssi_private->cpu_dai_drv.name = dev_name(&pdev->dev);
1185 /* Get the addresses and IRQ */
1186 ret = of_address_to_resource(np, 0, &res);
1188 dev_err(&pdev->dev, "could not determine device resources\n");
1191 ssi_private->ssi = of_iomap(np, 0);
1192 if (!ssi_private->ssi) {
1193 dev_err(&pdev->dev, "could not map device resources\n");
1196 ssi_private->ssi_phys = res.start;
1198 ssi_private->irq = irq_of_parse_and_map(np, 0);
1199 if (!ssi_private->irq) {
1200 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
1204 /* Are the RX and the TX clocks locked? */
1205 if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) {
1206 ssi_private->cpu_dai_drv.symmetric_rates = 1;
1207 ssi_private->cpu_dai_drv.symmetric_channels = 1;
1208 ssi_private->cpu_dai_drv.symmetric_samplebits = 1;
1211 /* Determine the FIFO depth. */
1212 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
1214 ssi_private->fifo_depth = be32_to_cpup(iprop);
1216 /* Older 8610 DTs didn't have the fifo-depth property */
1217 ssi_private->fifo_depth = 8;
1219 ssi_private->baudclk_locked = false;
1220 spin_lock_init(&ssi_private->baudclk_lock);
1222 dev_set_drvdata(&pdev->dev, ssi_private);
1224 if (ssi_private->soc->imx) {
1225 ret = fsl_ssi_imx_probe(pdev, ssi_private, ssi_private->ssi);
1230 ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
1231 &ssi_private->cpu_dai_drv, 1);
1233 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1234 goto error_asoc_register;
1237 if (ssi_private->use_dma) {
1238 ret = devm_request_irq(&pdev->dev, ssi_private->irq,
1239 fsl_ssi_isr, 0, dev_name(&pdev->dev),
1242 dev_err(&pdev->dev, "could not claim irq %u\n",
1248 ret = fsl_ssi_debugfs_create(&ssi_private->dbg_stats, &pdev->dev);
1250 goto error_asoc_register;
1253 * If codec-handle property is missing from SSI node, we assume
1254 * that the machine driver uses new binding which does not require
1255 * SSI driver to trigger machine driver's probe.
1257 if (!of_get_property(np, "codec-handle", NULL))
1260 /* Trigger the machine driver's probe function. The platform driver
1261 * name of the machine driver is taken from /compatible property of the
1262 * device tree. We also pass the address of the CPU DAI driver
1265 sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
1266 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1267 p = strrchr(sprop, ',');
1270 snprintf(name, sizeof(name), "snd-soc-%s", sprop);
1271 make_lowercase(name);
1274 platform_device_register_data(&pdev->dev, name, 0, NULL, 0);
1275 if (IS_ERR(ssi_private->pdev)) {
1276 ret = PTR_ERR(ssi_private->pdev);
1277 dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
1278 goto error_sound_card;
1285 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1288 snd_soc_unregister_component(&pdev->dev);
1290 error_asoc_register:
1291 if (ssi_private->soc->imx)
1292 fsl_ssi_imx_clean(pdev, ssi_private);
1295 if (ssi_private->use_dma)
1296 irq_dispose_mapping(ssi_private->irq);
1301 static int fsl_ssi_remove(struct platform_device *pdev)
1303 struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
1305 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1307 if (ssi_private->pdev)
1308 platform_device_unregister(ssi_private->pdev);
1309 snd_soc_unregister_component(&pdev->dev);
1311 if (ssi_private->soc->imx)
1312 fsl_ssi_imx_clean(pdev, ssi_private);
1314 if (ssi_private->use_dma)
1315 irq_dispose_mapping(ssi_private->irq);
1320 static struct platform_driver fsl_ssi_driver = {
1322 .name = "fsl-ssi-dai",
1323 .owner = THIS_MODULE,
1324 .of_match_table = fsl_ssi_ids,
1326 .probe = fsl_ssi_probe,
1327 .remove = fsl_ssi_remove,
1330 module_platform_driver(fsl_ssi_driver);
1332 MODULE_ALIAS("platform:fsl-ssi-dai");
1333 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1334 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1335 MODULE_LICENSE("GPL v2");