sound/soc/sh/rcar/adg.c

   1 /*
   2  * Helper routines for R-Car sound ADG.
   3  *
   4  *  Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/clk-provider.h>
  11 #include "rsnd.h"
  12
  13 #define CLKA    0
  14 #define CLKB    1
  15 #define CLKC    2
  16 #define CLKI    3
  17 #define CLKMAX  4
  18
  19 #define CLKOUT  0
  20 #define CLKOUT1 1
  21 #define CLKOUT2 2
  22 #define CLKOUT3 3
  23 #define CLKOUTMAX 4
  24
  25 #define BRRx_MASK(x) (0x3FF & x)
  26
  27 static struct rsnd_mod_ops adg_ops = {
  28         .name = "adg",
  29 };
  30
  31 struct rsnd_adg {
  32         struct clk *clk[CLKMAX];
  33         struct clk *clkout[CLKOUTMAX];
  34         struct clk_onecell_data onecell;
  35         struct rsnd_mod mod;
  36
  37         int rbga_rate_for_441khz; /* RBGA */
  38         int rbgb_rate_for_48khz;  /* RBGB */
  39 };
  40
  41 #define for_each_rsnd_clk(pos, adg, i)          \
  42         for (i = 0;                             \
  43              (i < CLKMAX) &&                    \
  44              ((pos) = adg->clk[i]);             \
  45              i++)
  46 #define for_each_rsnd_clkout(pos, adg, i)       \
  47         for (i = 0;                             \
  48              (i < CLKOUTMAX) &&                 \
  49              ((pos) = adg->clkout[i]);  \
  50              i++)
  51 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
  52
  53 static u32 rsnd_adg_calculate_rbgx(unsigned long div)
  54 {
  55         int i, ratio;
  56
  57         if (!div)
  58                 return 0;
  59
  60         for (i = 3; i >= 0; i--) {
  61                 ratio = 2 << (i * 2);
  62                 if (0 == (div % ratio))
  63                         return (u32)((i << 8) | ((div / ratio) - 1));
  64         }
  65
  66         return ~0;
  67 }
  68
  69 static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
  70 {
  71         struct rsnd_mod *mod = rsnd_io_to_mod_ssi(io);
  72         struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
  73         int id = rsnd_mod_id(mod);
  74         int ws = id;
  75
  76         if (rsnd_ssi_is_pin_sharing(rsnd_ssi_mod_get(priv, id))) {
  77                 switch (id) {
  78                 case 1:
  79                 case 2:
  80                         ws = 0;
  81                         break;
  82                 case 4:
  83                         ws = 3;
  84                         break;
  85                 case 8:
  86                         ws = 7;
  87                         break;
  88                 }
  89         }
  90
  91         return (0x6 + ws) << 8;
  92 }
  93
  94 int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *mod,
  95                                  struct rsnd_dai_stream *io)
  96 {
  97         struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
  98         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
  99         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 100         int id = rsnd_mod_id(mod);
 101         int shift = (id % 2) ? 16 : 0;
 102         u32 mask, val;
 103
 104         val = rsnd_adg_ssi_ws_timing_gen2(io);
 105
 106         val  = val      << shift;
 107         mask = 0xffff   << shift;
 108
 109         rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val);
 110
 111         return 0;
 112 }
 113
 114 static int rsnd_adg_set_src_timsel_gen2(struct rsnd_mod *src_mod,
 115                                         struct rsnd_dai_stream *io,
 116                                         u32 timsel)
 117 {
 118         struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
 119         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 120         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 121         int is_play = rsnd_io_is_play(io);
 122         int id = rsnd_mod_id(src_mod);
 123         int shift = (id % 2) ? 16 : 0;
 124         u32 mask, ws;
 125         u32 in, out;
 126
 127         rsnd_mod_confirm_src(src_mod);
 128
 129         ws = rsnd_adg_ssi_ws_timing_gen2(io);
 130
 131         in  = (is_play) ? timsel : ws;
 132         out = (is_play) ? ws     : timsel;
 133
 134         in   = in       << shift;
 135         out  = out      << shift;
 136         mask = 0xffff   << shift;
 137
 138         switch (id / 2) {
 139         case 0:
 140                 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL0,  mask, in);
 141                 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL0, mask, out);
 142                 break;
 143         case 1:
 144                 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL1,  mask, in);
 145                 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL1, mask, out);
 146                 break;
 147         case 2:
 148                 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL2,  mask, in);
 149                 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL2, mask, out);
 150                 break;
 151         case 3:
 152                 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL3,  mask, in);
 153                 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL3, mask, out);
 154                 break;
 155         case 4:
 156                 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL4,  mask, in);
 157                 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL4, mask, out);
 158                 break;
 159         }
 160
 161         return 0;
 162 }
 163
 164 int rsnd_adg_set_convert_clk_gen2(struct rsnd_mod *src_mod,
 165                                   struct rsnd_dai_stream *io,
 166                                   unsigned int src_rate,
 167                                   unsigned int dst_rate)
 168 {
 169         struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
 170         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 171         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 172         struct device *dev = rsnd_priv_to_dev(priv);
 173         int idx, sel, div, step, ret;
 174         u32 val, en;
 175         unsigned int min, diff;
 176         unsigned int sel_rate [] = {
 177                 clk_get_rate(adg->clk[CLKA]),   /* 0000: CLKA */
 178                 clk_get_rate(adg->clk[CLKB]),   /* 0001: CLKB */
 179                 clk_get_rate(adg->clk[CLKC]),   /* 0010: CLKC */
 180                 adg->rbga_rate_for_441khz,      /* 0011: RBGA */
 181                 adg->rbgb_rate_for_48khz,       /* 0100: RBGB */
 182         };
 183
 184         rsnd_mod_confirm_src(src_mod);
 185
 186         min = ~0;
 187         val = 0;
 188         en = 0;
 189         for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
 190                 idx = 0;
 191                 step = 2;
 192
 193                 if (!sel_rate[sel])
 194                         continue;
 195
 196                 for (div = 2; div <= 98304; div += step) {
 197                         diff = abs(src_rate - sel_rate[sel] / div);
 198                         if (min > diff) {
 199                                 val = (sel << 8) | idx;
 200                                 min = diff;
 201                                 en = 1 << (sel + 1); /* fixme */
 202                         }
 203
 204                         /*
 205                          * step of 0_0000 / 0_0001 / 0_1101
 206                          * are out of order
 207                          */
 208                         if ((idx > 2) && (idx % 2))
 209                                 step *= 2;
 210                         if (idx == 0x1c) {
 211                                 div += step;
 212                                 step *= 2;
 213                         }
 214                         idx++;
 215                 }
 216         }
 217
 218         if (min == ~0) {
 219                 dev_err(dev, "no Input clock\n");
 220                 return -EIO;
 221         }
 222
 223         ret = rsnd_adg_set_src_timsel_gen2(src_mod, io, val);
 224         if (ret < 0) {
 225                 dev_err(dev, "timsel error\n");
 226                 return ret;
 227         }
 228
 229         rsnd_mod_bset(adg_mod, DIV_EN, en, en);
 230
 231         dev_dbg(dev, "convert rate %d <-> %d\n", src_rate, dst_rate);
 232
 233         return 0;
 234 }
 235
 236 int rsnd_adg_set_convert_timing_gen2(struct rsnd_mod *src_mod,
 237                                      struct rsnd_dai_stream *io)
 238 {
 239         u32 val = rsnd_adg_ssi_ws_timing_gen2(io);
 240
 241         rsnd_mod_confirm_src(src_mod);
 242
 243         return rsnd_adg_set_src_timsel_gen2(src_mod, io, val);
 244 }
 245
 246 int rsnd_adg_set_convert_clk_gen1(struct rsnd_priv *priv,
 247                                   struct rsnd_mod *mod,
 248                                   unsigned int src_rate,
 249                                   unsigned int dst_rate)
 250 {
 251         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 252         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 253         struct device *dev = rsnd_priv_to_dev(priv);
 254         int idx, sel, div, shift;
 255         u32 mask, val;
 256         int id = rsnd_mod_id(mod);
 257         unsigned int sel_rate [] = {
 258                 clk_get_rate(adg->clk[CLKA]),   /* 000: CLKA */
 259                 clk_get_rate(adg->clk[CLKB]),   /* 001: CLKB */
 260                 clk_get_rate(adg->clk[CLKC]),   /* 010: CLKC */
 261                 0,                              /* 011: MLBCLK (not used) */
 262                 adg->rbga_rate_for_441khz,      /* 100: RBGA */
 263                 adg->rbgb_rate_for_48khz,       /* 101: RBGB */
 264         };
 265
 266         /* find div (= 1/128, 1/256, 1/512, 1/1024, 1/2048 */
 267         for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
 268                 for (div  = 128,        idx = 0;
 269                      div <= 2048;
 270                      div *= 2,          idx++) {
 271                         if (src_rate == sel_rate[sel] / div) {
 272                                 val = (idx << 4) | sel;
 273                                 goto find_rate;
 274                         }
 275                 }
 276         }
 277         dev_err(dev, "can't find convert src clk\n");
 278         return -EINVAL;
 279
 280 find_rate:
 281         shift   = (id % 4) * 8;
 282         mask    = 0xFF << shift;
 283         val     = val << shift;
 284
 285         dev_dbg(dev, "adg convert src clk = %02x\n", val);
 286
 287         switch (id / 4) {
 288         case 0:
 289                 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL3, mask, val);
 290                 break;
 291         case 1:
 292                 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL4, mask, val);
 293                 break;
 294         case 2:
 295                 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL5, mask, val);
 296                 break;
 297         }
 298
 299         /*
 300          * Gen1 doesn't need dst_rate settings,
 301          * since it uses SSI WS pin.
 302          * see also rsnd_src_set_route_if_gen1()
 303          */
 304
 305         return 0;
 306 }
 307
 308 static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val)
 309 {
 310         struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
 311         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 312         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 313         int id = rsnd_mod_id(ssi_mod);
 314         int shift = (id % 4) * 8;
 315         u32 mask = 0xFF << shift;
 316
 317         rsnd_mod_confirm_ssi(ssi_mod);
 318
 319         val = val << shift;
 320
 321         /*
 322          * SSI 8 is not connected to ADG.
 323          * it works with SSI 7
 324          */
 325         if (id == 8)
 326                 return;
 327
 328         switch (id / 4) {
 329         case 0:
 330                 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL0, mask, val);
 331                 break;
 332         case 1:
 333                 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL1, mask, val);
 334                 break;
 335         case 2:
 336                 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL2, mask, val);
 337                 break;
 338         }
 339 }
 340
 341 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *mod)
 342 {
 343         /*
 344          * "mod" = "ssi" here.
 345          * we can get "ssi id" from mod
 346          */
 347         rsnd_adg_set_ssi_clk(mod, 0);
 348
 349         return 0;
 350 }
 351
 352 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *mod, unsigned int rate)
 353 {
 354         struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
 355         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 356         struct device *dev = rsnd_priv_to_dev(priv);
 357         struct clk *clk;
 358         int i;
 359         u32 data;
 360         int sel_table[] = {
 361                 [CLKA] = 0x1,
 362                 [CLKB] = 0x2,
 363                 [CLKC] = 0x3,
 364                 [CLKI] = 0x0,
 365         };
 366
 367         dev_dbg(dev, "request clock = %d\n", rate);
 368
 369         /*
 370          * find suitable clock from
 371          * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
 372          */
 373         data = 0;
 374         for_each_rsnd_clk(clk, adg, i) {
 375                 if (rate == clk_get_rate(clk)) {
 376                         data = sel_table[i];
 377                         goto found_clock;
 378                 }
 379         }
 380
 381         /*
 382          * find divided clock from BRGA/BRGB
 383          */
 384         if (rate  == adg->rbga_rate_for_441khz) {
 385                 data = 0x10;
 386                 goto found_clock;
 387         }
 388
 389         if (rate == adg->rbgb_rate_for_48khz) {
 390                 data = 0x20;
 391                 goto found_clock;
 392         }
 393
 394         return -EIO;
 395
 396 found_clock:
 397
 398         /*
 399          * This "mod" = "ssi" here.
 400          * we can get "ssi id" from mod
 401          */
 402         rsnd_adg_set_ssi_clk(mod, data);
 403
 404         dev_dbg(dev, "ADG: %s[%d] selects 0x%x for %d\n",
 405                 rsnd_mod_name(mod), rsnd_mod_id(mod),
 406                 data, rate);
 407
 408         return 0;
 409 }
 410
 411 static void rsnd_adg_get_clkin(struct rsnd_priv *priv,
 412                                struct rsnd_adg *adg)
 413 {
 414         struct device *dev = rsnd_priv_to_dev(priv);
 415         struct clk *clk;
 416         static const char * const clk_name[] = {
 417                 [CLKA]  = "clk_a",
 418                 [CLKB]  = "clk_b",
 419                 [CLKC]  = "clk_c",
 420                 [CLKI]  = "clk_i",
 421         };
 422         int i;
 423
 424         for (i = 0; i < CLKMAX; i++) {
 425                 clk = devm_clk_get(dev, clk_name[i]);
 426                 adg->clk[i] = IS_ERR(clk) ? NULL : clk;
 427         }
 428
 429         for_each_rsnd_clk(clk, adg, i)
 430                 dev_dbg(dev, "clk %d : %p : %ld\n", i, clk, clk_get_rate(clk));
 431 }
 432
 433 static void rsnd_adg_get_clkout(struct rsnd_priv *priv,
 434                                 struct rsnd_adg *adg)
 435 {
 436         struct clk *clk;
 437         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 438         struct device *dev = rsnd_priv_to_dev(priv);
 439         struct device_node *np = dev->of_node;
 440         u32 ckr, rbgx, rbga, rbgb;
 441         u32 rate, req_rate, div;
 442         uint32_t count = 0;
 443         unsigned long req_48kHz_rate, req_441kHz_rate;
 444         int i;
 445         const char *parent_clk_name = NULL;
 446         static const char * const clkout_name[] = {
 447                 [CLKOUT]  = "audio_clkout",
 448                 [CLKOUT1] = "audio_clkout1",
 449                 [CLKOUT2] = "audio_clkout2",
 450                 [CLKOUT3] = "audio_clkout3",
 451         };
 452         int brg_table[] = {
 453                 [CLKA] = 0x0,
 454                 [CLKB] = 0x1,
 455                 [CLKC] = 0x4,
 456                 [CLKI] = 0x2,
 457         };
 458
 459         of_property_read_u32(np, "#clock-cells", &count);
 460
 461         /*
 462          * ADG supports BRRA/BRRB output only
 463          * this means all clkout0/1/2/3 will be same rate
 464          */
 465         of_property_read_u32(np, "clock-frequency", &req_rate);
 466         req_48kHz_rate = 0;
 467         req_441kHz_rate = 0;
 468         if (0 == (req_rate % 44100))
 469                 req_441kHz_rate = req_rate;
 470         if (0 == (req_rate % 48000))
 471                 req_48kHz_rate = req_rate;
 472
 473         /*
 474          * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
 475          * have 44.1kHz or 48kHz base clocks for now.
 476          *
 477          * SSI itself can divide parent clock by 1/1 - 1/16
 478          * see
 479          *      rsnd_adg_ssi_clk_try_start()
 480          *      rsnd_ssi_master_clk_start()
 481          */
 482         ckr = 0;
 483         rbga = 2; /* default 1/6 */
 484         rbgb = 2; /* default 1/6 */
 485         adg->rbga_rate_for_441khz       = 0;
 486         adg->rbgb_rate_for_48khz        = 0;
 487         for_each_rsnd_clk(clk, adg, i) {
 488                 rate = clk_get_rate(clk);
 489
 490                 if (0 == rate) /* not used */
 491                         continue;
 492
 493                 /* RBGA */
 494                 if (!adg->rbga_rate_for_441khz && (0 == rate % 44100)) {
 495                         div = 6;
 496                         if (req_441kHz_rate)
 497                                 div = rate / req_441kHz_rate;
 498                         rbgx = rsnd_adg_calculate_rbgx(div);
 499                         if (BRRx_MASK(rbgx) == rbgx) {
 500                                 rbga = rbgx;
 501                                 adg->rbga_rate_for_441khz = rate / div;
 502                                 ckr |= brg_table[i] << 20;
 503                                 if (req_441kHz_rate)
 504                                         parent_clk_name = __clk_get_name(clk);
 505                         }
 506                 }
 507
 508                 /* RBGB */
 509                 if (!adg->rbgb_rate_for_48khz && (0 == rate % 48000)) {
 510                         div = 6;
 511                         if (req_48kHz_rate)
 512                                 div = rate / req_48kHz_rate;
 513                         rbgx = rsnd_adg_calculate_rbgx(div);
 514                         if (BRRx_MASK(rbgx) == rbgx) {
 515                                 rbgb = rbgx;
 516                                 adg->rbgb_rate_for_48khz = rate / div;
 517                                 ckr |= brg_table[i] << 16;
 518                                 if (req_48kHz_rate) {
 519                                         parent_clk_name = __clk_get_name(clk);
 520                                         ckr |= 0x80000000;
 521                                 }
 522                         }
 523                 }
 524         }
 525
 526         /*
 527          * ADG supports BRRA/BRRB output only.
 528          * this means all clkout0/1/2/3 will be * same rate
 529          */
 530
 531         /*
 532          * for clkout
 533          */
 534         if (!count) {
 535                 clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT],
 536                                               parent_clk_name,
 537                                               (parent_clk_name) ?
 538                                               0 : CLK_IS_ROOT, req_rate);
 539                 if (!IS_ERR(clk)) {
 540                         adg->clkout[CLKOUT] = clk;
 541                         of_clk_add_provider(np, of_clk_src_simple_get, clk);
 542                 }
 543         }
 544         /*
 545          * for clkout0/1/2/3
 546          */
 547         else {
 548                 for (i = 0; i < CLKOUTMAX; i++) {
 549                         clk = clk_register_fixed_rate(dev, clkout_name[i],
 550                                                       parent_clk_name,
 551                                                       (parent_clk_name) ?
 552                                                       0 : CLK_IS_ROOT,
 553                                                       req_rate);
 554                         if (!IS_ERR(clk)) {
 555                                 adg->onecell.clks       = adg->clkout;
 556                                 adg->onecell.clk_num    = CLKOUTMAX;
 557
 558                                 adg->clkout[i] = clk;
 559
 560                                 of_clk_add_provider(np, of_clk_src_onecell_get,
 561                                                     &adg->onecell);
 562                         }
 563                 }
 564         }
 565
 566         rsnd_mod_bset(adg_mod, SSICKR, 0x00FF0000, ckr);
 567         rsnd_mod_write(adg_mod, BRRA,  rbga);
 568         rsnd_mod_write(adg_mod, BRRB,  rbgb);
 569
 570         for_each_rsnd_clkout(clk, adg, i)
 571                 dev_dbg(dev, "clkout %d : %p : %ld\n", i, clk, clk_get_rate(clk));
 572         dev_dbg(dev, "SSICKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
 573                 ckr, rbga, rbgb);
 574 }
 575
 576 int rsnd_adg_probe(struct platform_device *pdev,
 577                    const struct rsnd_of_data *of_data,
 578                    struct rsnd_priv *priv)
 579 {
 580         struct rsnd_adg *adg;
 581         struct device *dev = rsnd_priv_to_dev(priv);
 582
 583         adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
 584         if (!adg) {
 585                 dev_err(dev, "ADG allocate failed\n");
 586                 return -ENOMEM;
 587         }
 588
 589         /*
 590          * ADG is special module.
 591          * Use ADG mod without rsnd_mod_init() to make debug easy
 592          * for rsnd_write/rsnd_read
 593          */
 594         adg->mod.ops = &adg_ops;
 595         adg->mod.priv = priv;
 596
 597         rsnd_adg_get_clkin(priv, adg);
 598         rsnd_adg_get_clkout(priv, adg);
 599
 600         priv->adg = adg;
 601
 602         return 0;
 603 }