tools/power/x86/turbostat/turbostat.c

   1 /*
   2  * turbostat -- show CPU frequency and C-state residency
   3  * on modern Intel turbo-capable processors.
   4  *
   5  * Copyright (c) 2013 Intel Corporation.
   6  * Len Brown <len.brown@intel.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2, as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  20  */
  21
  22 #define _GNU_SOURCE
  23 #include MSRHEADER
  24 #include INTEL_FAMILY_HEADER
  25 #include <stdarg.h>
  26 #include <stdio.h>
  27 #include <err.h>
  28 #include <unistd.h>
  29 #include <sys/types.h>
  30 #include <sys/wait.h>
  31 #include <sys/stat.h>
  32 #include <sys/resource.h>
  33 #include <fcntl.h>
  34 #include <signal.h>
  35 #include <sys/time.h>
  36 #include <stdlib.h>
  37 #include <getopt.h>
  38 #include <dirent.h>
  39 #include <string.h>
  40 #include <ctype.h>
  41 #include <sched.h>
  42 #include <time.h>
  43 #include <cpuid.h>
  44 #include <linux/capability.h>
  45 #include <errno.h>
  46
  47 char *proc_stat = "/proc/stat";
  48 FILE *outf;
  49 int *fd_percpu;
  50 struct timespec interval_ts = {5, 0};
  51 unsigned int debug;
  52 unsigned int rapl_joules;
  53 unsigned int summary_only;
  54 unsigned int dump_only;
  55 unsigned int do_snb_cstates;
  56 unsigned int do_knl_cstates;
  57 unsigned int do_pc2;
  58 unsigned int do_pc3;
  59 unsigned int do_pc6;
  60 unsigned int do_pc7;
  61 unsigned int do_c8_c9_c10;
  62 unsigned int do_skl_residency;
  63 unsigned int do_slm_cstates;
  64 unsigned int use_c1_residency_msr;
  65 unsigned int has_aperf;
  66 unsigned int has_epb;
  67 unsigned int do_irtl_snb;
  68 unsigned int do_irtl_hsw;
  69 unsigned int units = 1000000;   /* MHz etc */
  70 unsigned int genuine_intel;
  71 unsigned int has_invariant_tsc;
  72 unsigned int do_nhm_platform_info;
  73 unsigned int no_MSR_MISC_PWR_MGMT;
  74 unsigned int aperf_mperf_multiplier = 1;
  75 double bclk;
  76 double base_hz;
  77 unsigned int has_base_hz;
  78 double tsc_tweak = 1.0;
  79 unsigned int show_pkg_only;
  80 unsigned int show_core_only;
  81 char *output_buffer, *outp;
  82 unsigned int do_rapl;
  83 unsigned int do_dts;
  84 unsigned int do_ptm;
  85 unsigned long long  gfx_cur_rc6_ms;
  86 unsigned int gfx_cur_mhz;
  87 unsigned int tcc_activation_temp;
  88 unsigned int tcc_activation_temp_override;
  89 double rapl_power_units, rapl_time_units;
  90 double rapl_dram_energy_units, rapl_energy_units;
  91 double rapl_joule_counter_range;
  92 unsigned int do_core_perf_limit_reasons;
  93 unsigned int do_gfx_perf_limit_reasons;
  94 unsigned int do_ring_perf_limit_reasons;
  95 unsigned int crystal_hz;
  96 unsigned long long tsc_hz;
  97 int base_cpu;
  98 double discover_bclk(unsigned int family, unsigned int model);
  99 unsigned int has_hwp;   /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */
 100                         /* IA32_HWP_REQUEST, IA32_HWP_STATUS */
 101 unsigned int has_hwp_notify;            /* IA32_HWP_INTERRUPT */
 102 unsigned int has_hwp_activity_window;   /* IA32_HWP_REQUEST[bits 41:32] */
 103 unsigned int has_hwp_epp;               /* IA32_HWP_REQUEST[bits 31:24] */
 104 unsigned int has_hwp_pkg;               /* IA32_HWP_REQUEST_PKG */
 105
 106 #define RAPL_PKG                (1 << 0)
 107                                         /* 0x610 MSR_PKG_POWER_LIMIT */
 108                                         /* 0x611 MSR_PKG_ENERGY_STATUS */
 109 #define RAPL_PKG_PERF_STATUS    (1 << 1)
 110                                         /* 0x613 MSR_PKG_PERF_STATUS */
 111 #define RAPL_PKG_POWER_INFO     (1 << 2)
 112                                         /* 0x614 MSR_PKG_POWER_INFO */
 113
 114 #define RAPL_DRAM               (1 << 3)
 115                                         /* 0x618 MSR_DRAM_POWER_LIMIT */
 116                                         /* 0x619 MSR_DRAM_ENERGY_STATUS */
 117 #define RAPL_DRAM_PERF_STATUS   (1 << 4)
 118                                         /* 0x61b MSR_DRAM_PERF_STATUS */
 119 #define RAPL_DRAM_POWER_INFO    (1 << 5)
 120                                         /* 0x61c MSR_DRAM_POWER_INFO */
 121
 122 #define RAPL_CORES_POWER_LIMIT  (1 << 6)
 123                                         /* 0x638 MSR_PP0_POWER_LIMIT */
 124 #define RAPL_CORE_POLICY        (1 << 7)
 125                                         /* 0x63a MSR_PP0_POLICY */
 126
 127 #define RAPL_GFX                (1 << 8)
 128                                         /* 0x640 MSR_PP1_POWER_LIMIT */
 129                                         /* 0x641 MSR_PP1_ENERGY_STATUS */
 130                                         /* 0x642 MSR_PP1_POLICY */
 131
 132 #define RAPL_CORES_ENERGY_STATUS        (1 << 9)
 133                                         /* 0x639 MSR_PP0_ENERGY_STATUS */
 134 #define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT)
 135 #define TJMAX_DEFAULT   100
 136
 137 #define MAX(a, b) ((a) > (b) ? (a) : (b))
 138
 139 /*
 140  * buffer size used by sscanf() for added column names
 141  * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters
 142  */
 143 #define NAME_BYTES 20
 144
 145 int backwards_count;
 146 char *progname;
 147
 148 cpu_set_t *cpu_present_set, *cpu_affinity_set;
 149 size_t cpu_present_setsize, cpu_affinity_setsize;
 150 #define MAX_ADDED_COUNTERS 16
 151
 152 struct thread_data {
 153         unsigned long long tsc;
 154         unsigned long long aperf;
 155         unsigned long long mperf;
 156         unsigned long long c1;
 157         unsigned int irq_count;
 158         unsigned int smi_count;
 159         unsigned int cpu_id;
 160         unsigned int flags;
 161 #define CPU_IS_FIRST_THREAD_IN_CORE     0x2
 162 #define CPU_IS_FIRST_CORE_IN_PACKAGE    0x4
 163         unsigned long long counter[MAX_ADDED_COUNTERS];
 164 } *thread_even, *thread_odd;
 165
 166 struct core_data {
 167         unsigned long long c3;
 168         unsigned long long c6;
 169         unsigned long long c7;
 170         unsigned long long mc6_us;      /* duplicate as per-core for now, even though per module */
 171         unsigned int core_temp_c;
 172         unsigned int core_id;
 173         unsigned long long counter[MAX_ADDED_COUNTERS];
 174 } *core_even, *core_odd;
 175
 176 struct pkg_data {
 177         unsigned long long pc2;
 178         unsigned long long pc3;
 179         unsigned long long pc6;
 180         unsigned long long pc7;
 181         unsigned long long pc8;
 182         unsigned long long pc9;
 183         unsigned long long pc10;
 184         unsigned long long pkg_wtd_core_c0;
 185         unsigned long long pkg_any_core_c0;
 186         unsigned long long pkg_any_gfxe_c0;
 187         unsigned long long pkg_both_core_gfxe_c0;
 188         long long gfx_rc6_ms;
 189         unsigned int gfx_mhz;
 190         unsigned int package_id;
 191         unsigned int energy_pkg;        /* MSR_PKG_ENERGY_STATUS */
 192         unsigned int energy_dram;       /* MSR_DRAM_ENERGY_STATUS */
 193         unsigned int energy_cores;      /* MSR_PP0_ENERGY_STATUS */
 194         unsigned int energy_gfx;        /* MSR_PP1_ENERGY_STATUS */
 195         unsigned int rapl_pkg_perf_status;      /* MSR_PKG_PERF_STATUS */
 196         unsigned int rapl_dram_perf_status;     /* MSR_DRAM_PERF_STATUS */
 197         unsigned int pkg_temp_c;
 198         unsigned long long counter[MAX_ADDED_COUNTERS];
 199 } *package_even, *package_odd;
 200
 201 #define ODD_COUNTERS thread_odd, core_odd, package_odd
 202 #define EVEN_COUNTERS thread_even, core_even, package_even
 203
 204 #define GET_THREAD(thread_base, thread_no, core_no, pkg_no) \
 205         (thread_base + (pkg_no) * topo.num_cores_per_pkg * \
 206                 topo.num_threads_per_core + \
 207                 (core_no) * topo.num_threads_per_core + (thread_no))
 208 #define GET_CORE(core_base, core_no, pkg_no) \
 209         (core_base + (pkg_no) * topo.num_cores_per_pkg + (core_no))
 210 #define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no)
 211
 212 enum counter_scope {SCOPE_CPU, SCOPE_CORE, SCOPE_PACKAGE};
 213 enum counter_type {COUNTER_CYCLES, COUNTER_SECONDS};
 214 enum counter_format {FORMAT_RAW, FORMAT_DELTA, FORMAT_PERCENT};
 215
 216 struct msr_counter {
 217         unsigned int msr_num;
 218         char name[NAME_BYTES];
 219         unsigned int width;
 220         enum counter_type type;
 221         enum counter_format format;
 222         struct msr_counter *next;
 223         unsigned int flags;
 224 #define FLAGS_HIDE      (1 << 0)
 225 #define FLAGS_SHOW      (1 << 1)
 226 };
 227
 228 struct sys_counters {
 229         unsigned int added_thread_counters;
 230         unsigned int added_core_counters;
 231         unsigned int added_package_counters;
 232         struct msr_counter *tp;
 233         struct msr_counter *cp;
 234         struct msr_counter *pp;
 235 } sys;
 236
 237 struct system_summary {
 238         struct thread_data threads;
 239         struct core_data cores;
 240         struct pkg_data packages;
 241 } average;
 242
 243
 244 struct topo_params {
 245         int num_packages;
 246         int num_cpus;
 247         int num_cores;
 248         int max_cpu_num;
 249         int num_cores_per_pkg;
 250         int num_threads_per_core;
 251 } topo;
 252
 253 struct timeval tv_even, tv_odd, tv_delta;
 254
 255 int *irq_column_2_cpu;  /* /proc/interrupts column numbers */
 256 int *irqs_per_cpu;              /* indexed by cpu_num */
 257
 258 void setup_all_buffers(void);
 259
 260 int cpu_is_not_present(int cpu)
 261 {
 262         return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set);
 263 }
 264 /*
 265  * run func(thread, core, package) in topology order
 266  * skip non-present cpus
 267  */
 268
 269 int for_all_cpus(int (func)(struct thread_data *, struct core_data *, struct pkg_data *),
 270         struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base)
 271 {
 272         int retval, pkg_no, core_no, thread_no;
 273
 274         for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) {
 275                 for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) {
 276                         for (thread_no = 0; thread_no <
 277                                 topo.num_threads_per_core; ++thread_no) {
 278                                 struct thread_data *t;
 279                                 struct core_data *c;
 280                                 struct pkg_data *p;
 281
 282                                 t = GET_THREAD(thread_base, thread_no, core_no, pkg_no);
 283
 284                                 if (cpu_is_not_present(t->cpu_id))
 285                                         continue;
 286
 287                                 c = GET_CORE(core_base, core_no, pkg_no);
 288                                 p = GET_PKG(pkg_base, pkg_no);
 289
 290                                 retval = func(t, c, p);
 291                                 if (retval)
 292                                         return retval;
 293                         }
 294                 }
 295         }
 296         return 0;
 297 }
 298
 299 int cpu_migrate(int cpu)
 300 {
 301         CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set);
 302         CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set);
 303         if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1)
 304                 return -1;
 305         else
 306                 return 0;
 307 }
 308 int get_msr_fd(int cpu)
 309 {
 310         char pathname[32];
 311         int fd;
 312
 313         fd = fd_percpu[cpu];
 314
 315         if (fd)
 316                 return fd;
 317
 318         sprintf(pathname, "/dev/cpu/%d/msr", cpu);
 319         fd = open(pathname, O_RDONLY);
 320         if (fd < 0)
 321                 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname);
 322
 323         fd_percpu[cpu] = fd;
 324
 325         return fd;
 326 }
 327
 328 int get_msr(int cpu, off_t offset, unsigned long long *msr)
 329 {
 330         ssize_t retval;
 331
 332         retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset);
 333
 334         if (retval != sizeof *msr)
 335                 err(-1, "cpu%d: msr offset 0x%llx read failed", cpu, (unsigned long long)offset);
 336
 337         return 0;
 338 }
 339
 340 /*
 341  * Each string in this array is compared in --show and --hide cmdline.
 342  * Thus, strings that are proper sub-sets must follow their more specific peers.
 343  */
 344 struct msr_counter bic[] = {
 345         { 0x0, "Package" },
 346         { 0x0, "Avg_MHz" },
 347         { 0x0, "Bzy_MHz" },
 348         { 0x0, "TSC_MHz" },
 349         { 0x0, "IRQ" },
 350         { 0x0, "SMI", 32, 0, FORMAT_DELTA, NULL},
 351         { 0x0, "Busy%" },
 352         { 0x0, "CPU%c1" },
 353         { 0x0, "CPU%c3" },
 354         { 0x0, "CPU%c6" },
 355         { 0x0, "CPU%c7" },
 356         { 0x0, "ThreadC" },
 357         { 0x0, "CoreTmp" },
 358         { 0x0, "CoreCnt" },
 359         { 0x0, "PkgTmp" },
 360         { 0x0, "GFX%rc6" },
 361         { 0x0, "GFXMHz" },
 362         { 0x0, "Pkg%pc2" },
 363         { 0x0, "Pkg%pc3" },
 364         { 0x0, "Pkg%pc6" },
 365         { 0x0, "Pkg%pc7" },
 366         { 0x0, "PkgWatt" },
 367         { 0x0, "CorWatt" },
 368         { 0x0, "GFXWatt" },
 369         { 0x0, "PkgCnt" },
 370         { 0x0, "RAMWatt" },
 371         { 0x0, "PKG_%" },
 372         { 0x0, "RAM_%" },
 373         { 0x0, "Pkg_J" },
 374         { 0x0, "Cor_J" },
 375         { 0x0, "GFX_J" },
 376         { 0x0, "RAM_J" },
 377         { 0x0, "Core" },
 378         { 0x0, "CPU" },
 379         { 0x0, "Mod%c6" },
 380 };
 381
 382 #define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter))
 383 #define BIC_Package     (1ULL << 0)
 384 #define BIC_Avg_MHz     (1ULL << 1)
 385 #define BIC_Bzy_MHz     (1ULL << 2)
 386 #define BIC_TSC_MHz     (1ULL << 3)
 387 #define BIC_IRQ         (1ULL << 4)
 388 #define BIC_SMI         (1ULL << 5)
 389 #define BIC_Busy        (1ULL << 6)
 390 #define BIC_CPU_c1      (1ULL << 7)
 391 #define BIC_CPU_c3      (1ULL << 8)
 392 #define BIC_CPU_c6      (1ULL << 9)
 393 #define BIC_CPU_c7      (1ULL << 10)
 394 #define BIC_ThreadC     (1ULL << 11)
 395 #define BIC_CoreTmp     (1ULL << 12)
 396 #define BIC_CoreCnt     (1ULL << 13)
 397 #define BIC_PkgTmp      (1ULL << 14)
 398 #define BIC_GFX_rc6     (1ULL << 15)
 399 #define BIC_GFXMHz      (1ULL << 16)
 400 #define BIC_Pkgpc2      (1ULL << 17)
 401 #define BIC_Pkgpc3      (1ULL << 18)
 402 #define BIC_Pkgpc6      (1ULL << 19)
 403 #define BIC_Pkgpc7      (1ULL << 20)
 404 #define BIC_PkgWatt     (1ULL << 21)
 405 #define BIC_CorWatt     (1ULL << 22)
 406 #define BIC_GFXWatt     (1ULL << 23)
 407 #define BIC_PkgCnt      (1ULL << 24)
 408 #define BIC_RAMWatt     (1ULL << 27)
 409 #define BIC_PKG__       (1ULL << 28)
 410 #define BIC_RAM__       (1ULL << 29)
 411 #define BIC_Pkg_J       (1ULL << 30)
 412 #define BIC_Cor_J       (1ULL << 31)
 413 #define BIC_GFX_J       (1ULL << 30)
 414 #define BIC_RAM_J       (1ULL << 31)
 415 #define BIC_Core        (1ULL << 32)
 416 #define BIC_CPU         (1ULL << 33)
 417 #define BIC_Mod_c6      (1ULL << 34)
 418
 419 unsigned long long bic_enabled = 0xFFFFFFFFFFFFFFFFULL;
 420 unsigned long long bic_present;
 421
 422 #define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME)
 423 #define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT)
 424
 425 /*
 426  * bic_lookup
 427  * for all the strings in comma separate name_list,
 428  * set the approprate bit in return value.
 429  */
 430 unsigned long long bic_lookup(char *name_list)
 431 {
 432         int i;
 433         unsigned long long retval = 0;
 434
 435         while (name_list) {
 436                 char *comma;
 437
 438                 comma = strchr(name_list, ',');
 439
 440                 if (comma)
 441                         *comma = '\0';
 442
 443                 for (i = 0; i < MAX_BIC; ++i) {
 444                         if (!strcmp(name_list, bic[i].name)) {
 445                                 retval |= (1ULL << i);
 446                                 break;
 447                         }
 448                 }
 449                 if (i == MAX_BIC) {
 450                         fprintf(stderr, "Invalid counter name: %s\n", name_list);
 451                         exit(-1);
 452                 }
 453
 454                 name_list = comma;
 455                 if (name_list)
 456                         name_list++;
 457
 458         }
 459         return retval;
 460 }
 461
 462 void print_header(void)
 463 {
 464         struct msr_counter *mp;
 465
 466         if (DO_BIC(BIC_Package))
 467                 outp += sprintf(outp, "\tPackage");
 468         if (DO_BIC(BIC_Core))
 469                 outp += sprintf(outp, "\tCore");
 470         if (DO_BIC(BIC_CPU))
 471                 outp += sprintf(outp, "\tCPU");
 472         if (DO_BIC(BIC_Avg_MHz))
 473                 outp += sprintf(outp, "\tAvg_MHz");
 474         if (DO_BIC(BIC_Busy))
 475                 outp += sprintf(outp, "\tBusy%%");
 476         if (DO_BIC(BIC_Bzy_MHz))
 477                 outp += sprintf(outp, "\tBzy_MHz");
 478         if (DO_BIC(BIC_TSC_MHz))
 479                 outp += sprintf(outp, "\tTSC_MHz");
 480
 481         if (!debug)
 482                 goto done;
 483
 484         if (DO_BIC(BIC_IRQ))
 485                 outp += sprintf(outp, "\tIRQ");
 486         if (DO_BIC(BIC_SMI))
 487                 outp += sprintf(outp, "\tSMI");
 488
 489         if (DO_BIC(BIC_CPU_c1))
 490                 outp += sprintf(outp, "\tCPU%%c1");
 491
 492         for (mp = sys.tp; mp; mp = mp->next) {
 493                 if (mp->format == FORMAT_RAW) {
 494                         if (mp->width == 64)
 495                                 outp += sprintf(outp, "\t%18.18s", mp->name);
 496                         else
 497                                 outp += sprintf(outp, "\t%10.10s", mp->name);
 498                 } else {
 499                         outp += sprintf(outp, "\t%-7.7s", mp->name);
 500                 }
 501         }
 502
 503         if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates)
 504                 outp += sprintf(outp, "\tCPU%%c3");
 505         if (DO_BIC(BIC_CPU_c6))
 506                 outp += sprintf(outp, "\tCPU%%c6");
 507         if (DO_BIC(BIC_CPU_c7))
 508                 outp += sprintf(outp, "\tCPU%%c7");
 509
 510         if (DO_BIC(BIC_Mod_c6))
 511                 outp += sprintf(outp, "\tMod%%c6");
 512
 513         if (DO_BIC(BIC_CoreTmp))
 514                 outp += sprintf(outp, "\tCoreTmp");
 515
 516         for (mp = sys.cp; mp; mp = mp->next) {
 517                 if (mp->format == FORMAT_RAW) {
 518                         if (mp->width == 64)
 519                                 outp += sprintf(outp, "\t%18.18s", mp->name);
 520                         else
 521                                 outp += sprintf(outp, "\t%10.10s", mp->name);
 522                 } else {
 523                         outp += sprintf(outp, "\t%-7.7s", mp->name);
 524                 }
 525         }
 526
 527         if (DO_BIC(BIC_PkgTmp))
 528                 outp += sprintf(outp, "\tPkgTmp");
 529
 530         if (DO_BIC(BIC_GFX_rc6))
 531                 outp += sprintf(outp, "\tGFX%%rc6");
 532
 533         if (DO_BIC(BIC_GFXMHz))
 534                 outp += sprintf(outp, "\tGFXMHz");
 535
 536         if (do_skl_residency) {
 537                 outp += sprintf(outp, "\tTotl%%C0");
 538                 outp += sprintf(outp, "\tAny%%C0");
 539                 outp += sprintf(outp, "\tGFX%%C0");
 540                 outp += sprintf(outp, "\tCPUGFX%%");
 541         }
 542
 543         if (do_pc2)
 544                 outp += sprintf(outp, "\tPkg%%pc2");
 545         if (do_pc3)
 546                 outp += sprintf(outp, "\tPkg%%pc3");
 547         if (do_pc6)
 548                 outp += sprintf(outp, "\tPkg%%pc6");
 549         if (do_pc7)
 550                 outp += sprintf(outp, "\tPkg%%pc7");
 551         if (do_c8_c9_c10) {
 552                 outp += sprintf(outp, "\tPkg%%pc8");
 553                 outp += sprintf(outp, "\tPkg%%pc9");
 554                 outp += sprintf(outp, "\tPk%%pc10");
 555         }
 556
 557         if (do_rapl && !rapl_joules) {
 558                 if (DO_BIC(BIC_PkgWatt))
 559                         outp += sprintf(outp, "\tPkgWatt");
 560                 if (DO_BIC(BIC_CorWatt))
 561                         outp += sprintf(outp, "\tCorWatt");
 562                 if (DO_BIC(BIC_GFXWatt))
 563                         outp += sprintf(outp, "\tGFXWatt");
 564                 if (DO_BIC(BIC_RAMWatt))
 565                         outp += sprintf(outp, "\tRAMWatt");
 566                 if (DO_BIC(BIC_PKG__))
 567                         outp += sprintf(outp, "\tPKG_%%");
 568                 if (DO_BIC(BIC_RAM__))
 569                         outp += sprintf(outp, "\tRAM_%%");
 570         } else if (do_rapl && rapl_joules) {
 571                 if (DO_BIC(BIC_Pkg_J))
 572                         outp += sprintf(outp, "\tPkg_J");
 573                 if (DO_BIC(BIC_Cor_J))
 574                         outp += sprintf(outp, "\tCor_J");
 575                 if (DO_BIC(BIC_GFX_J))
 576                         outp += sprintf(outp, "\tGFX_J");
 577                 if (DO_BIC(BIC_RAM_J))
 578                         outp += sprintf(outp, "\tRAM_J");
 579                 if (DO_BIC(BIC_PKG__))
 580                         outp += sprintf(outp, "\tPKG_%%");
 581                 if (DO_BIC(BIC_RAM__))
 582                         outp += sprintf(outp, "\tRAM_%%");
 583         }
 584         for (mp = sys.pp; mp; mp = mp->next) {
 585                 if (mp->format == FORMAT_RAW) {
 586                         if (mp->width == 64)
 587                                 outp += sprintf(outp, "\t%18.18s", mp->name);
 588                         else
 589                                 outp += sprintf(outp, "\t%10.10s", mp->name);
 590                 } else {
 591                         outp += sprintf(outp, "\t%-7.7s", mp->name);
 592                 }
 593         }
 594
 595 done:
 596         outp += sprintf(outp, "\n");
 597 }
 598
 599 int dump_counters(struct thread_data *t, struct core_data *c,
 600         struct pkg_data *p)
 601 {
 602         int i;
 603         struct msr_counter *mp;
 604
 605         outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p);
 606
 607         if (t) {
 608                 outp += sprintf(outp, "CPU: %d flags 0x%x\n",
 609                         t->cpu_id, t->flags);
 610                 outp += sprintf(outp, "TSC: %016llX\n", t->tsc);
 611                 outp += sprintf(outp, "aperf: %016llX\n", t->aperf);
 612                 outp += sprintf(outp, "mperf: %016llX\n", t->mperf);
 613                 outp += sprintf(outp, "c1: %016llX\n", t->c1);
 614
 615                 if (DO_BIC(BIC_IRQ))
 616                         outp += sprintf(outp, "IRQ: %08X\n", t->irq_count);
 617                 if (DO_BIC(BIC_SMI))
 618                         outp += sprintf(outp, "SMI: %08X\n", t->smi_count);
 619
 620                 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
 621                         outp += sprintf(outp, "tADDED [%d] msr0x%x: %08llX\n",
 622                                 i, mp->msr_num, t->counter[i]);
 623                 }
 624         }
 625
 626         if (c) {
 627                 outp += sprintf(outp, "core: %d\n", c->core_id);
 628                 outp += sprintf(outp, "c3: %016llX\n", c->c3);
 629                 outp += sprintf(outp, "c6: %016llX\n", c->c6);
 630                 outp += sprintf(outp, "c7: %016llX\n", c->c7);
 631                 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c);
 632
 633                 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
 634                         outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n",
 635                                 i, mp->msr_num, c->counter[i]);
 636                 }
 637                 outp += sprintf(outp, "mc6_us: %016llX\n", c->mc6_us);
 638         }
 639
 640         if (p) {
 641                 outp += sprintf(outp, "package: %d\n", p->package_id);
 642
 643                 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0);
 644                 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0);
 645                 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0);
 646                 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0);
 647
 648                 outp += sprintf(outp, "pc2: %016llX\n", p->pc2);
 649                 if (do_pc3)
 650                         outp += sprintf(outp, "pc3: %016llX\n", p->pc3);
 651                 if (do_pc6)
 652                         outp += sprintf(outp, "pc6: %016llX\n", p->pc6);
 653                 if (do_pc7)
 654                         outp += sprintf(outp, "pc7: %016llX\n", p->pc7);
 655                 outp += sprintf(outp, "pc8: %016llX\n", p->pc8);
 656                 outp += sprintf(outp, "pc9: %016llX\n", p->pc9);
 657                 outp += sprintf(outp, "pc10: %016llX\n", p->pc10);
 658                 outp += sprintf(outp, "Joules PKG: %0X\n", p->energy_pkg);
 659                 outp += sprintf(outp, "Joules COR: %0X\n", p->energy_cores);
 660                 outp += sprintf(outp, "Joules GFX: %0X\n", p->energy_gfx);
 661                 outp += sprintf(outp, "Joules RAM: %0X\n", p->energy_dram);
 662                 outp += sprintf(outp, "Throttle PKG: %0X\n",
 663                         p->rapl_pkg_perf_status);
 664                 outp += sprintf(outp, "Throttle RAM: %0X\n",
 665                         p->rapl_dram_perf_status);
 666                 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c);
 667
 668                 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
 669                         outp += sprintf(outp, "pADDED [%d] msr0x%x: %08llX\n",
 670                                 i, mp->msr_num, p->counter[i]);
 671                 }
 672         }
 673
 674         outp += sprintf(outp, "\n");
 675
 676         return 0;
 677 }
 678
 679 /*
 680  * column formatting convention & formats
 681  */
 682 int format_counters(struct thread_data *t, struct core_data *c,
 683         struct pkg_data *p)
 684 {
 685         double interval_float;
 686         char *fmt8;
 687         int i;
 688         struct msr_counter *mp;
 689
 690          /* if showing only 1st thread in core and this isn't one, bail out */
 691         if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
 692                 return 0;
 693
 694          /* if showing only 1st thread in pkg and this isn't one, bail out */
 695         if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
 696                 return 0;
 697
 698         interval_float = tv_delta.tv_sec + tv_delta.tv_usec/1000000.0;
 699
 700         /* topo columns, print blanks on 1st (average) line */
 701         if (t == &average.threads) {
 702                 if (DO_BIC(BIC_Package))
 703                         outp += sprintf(outp, "\t-");
 704                 if (DO_BIC(BIC_Core))
 705                         outp += sprintf(outp, "\t-");
 706                 if (DO_BIC(BIC_CPU))
 707                         outp += sprintf(outp, "\t-");
 708         } else {
 709                 if (DO_BIC(BIC_Package)) {
 710                         if (p)
 711                                 outp += sprintf(outp, "\t%d", p->package_id);
 712                         else
 713                                 outp += sprintf(outp, "\t-");
 714                 }
 715                 if (DO_BIC(BIC_Core)) {
 716                         if (c)
 717                                 outp += sprintf(outp, "\t%d", c->core_id);
 718                         else
 719                                 outp += sprintf(outp, "\t-");
 720                 }
 721                 if (DO_BIC(BIC_CPU))
 722                         outp += sprintf(outp, "\t%d", t->cpu_id);
 723         }
 724
 725         if (DO_BIC(BIC_Avg_MHz))
 726                 outp += sprintf(outp, "\t%.0f",
 727                         1.0 / units * t->aperf / interval_float);
 728
 729         if (DO_BIC(BIC_Busy))
 730                 outp += sprintf(outp, "\t%.2f", 100.0 * t->mperf/t->tsc/tsc_tweak);
 731
 732         if (DO_BIC(BIC_Bzy_MHz)) {
 733                 if (has_base_hz)
 734                         outp += sprintf(outp, "\t%.0f", base_hz / units * t->aperf / t->mperf);
 735                 else
 736                         outp += sprintf(outp, "\t%.0f",
 737                                 1.0 * t->tsc / units * t->aperf / t->mperf / interval_float);
 738         }
 739
 740         if (DO_BIC(BIC_TSC_MHz))
 741                 outp += sprintf(outp, "\t%.0f", 1.0 * t->tsc/units/interval_float);
 742
 743         if (!debug)
 744                 goto done;
 745
 746         /* IRQ */
 747         if (DO_BIC(BIC_IRQ))
 748                 outp += sprintf(outp, "\t%d", t->irq_count);
 749
 750         /* SMI */
 751         if (DO_BIC(BIC_SMI))
 752                 outp += sprintf(outp, "\t%d", t->smi_count);
 753
 754         /* C1 */
 755         if (DO_BIC(BIC_CPU_c1))
 756                 outp += sprintf(outp, "\t%.2f", 100.0 * t->c1/t->tsc);
 757
 758         /* Added counters */
 759         for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
 760                 if (mp->format == FORMAT_RAW) {
 761                         if (mp->width == 32)
 762                                 outp += sprintf(outp, "\t0x%08lx", (unsigned long) t->counter[i]);
 763                         else
 764                                 outp += sprintf(outp, "\t0x%016llx", t->counter[i]);
 765                 } else if (mp->format == FORMAT_DELTA) {
 766                         outp += sprintf(outp, "\t%lld", t->counter[i]);
 767                 } else if (mp->format == FORMAT_PERCENT) {
 768                         outp += sprintf(outp, "\t%.2f", 100.0 * t->counter[i]/t->tsc);
 769                 }
 770         }
 771
 772         /* print per-core data only for 1st thread in core */
 773         if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
 774                 goto done;
 775
 776         if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates)
 777                 outp += sprintf(outp, "\t%.2f", 100.0 * c->c3/t->tsc);
 778         if (DO_BIC(BIC_CPU_c6))
 779                 outp += sprintf(outp, "\t%.2f", 100.0 * c->c6/t->tsc);
 780         if (DO_BIC(BIC_CPU_c7))
 781                 outp += sprintf(outp, "\t%.2f", 100.0 * c->c7/t->tsc);
 782
 783         /* Mod%c6 */
 784         if (DO_BIC(BIC_Mod_c6))
 785                 outp += sprintf(outp, "\t%.2f", 100.0 * c->mc6_us / t->tsc);
 786
 787         if (DO_BIC(BIC_CoreTmp))
 788                 outp += sprintf(outp, "\t%d", c->core_temp_c);
 789
 790         for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
 791                 if (mp->format == FORMAT_RAW) {
 792                         if (mp->width == 32)
 793                                 outp += sprintf(outp, "\t0x%08lx", (unsigned long) c->counter[i]);
 794                         else
 795                                 outp += sprintf(outp, "\t0x%016llx", c->counter[i]);
 796                 } else if (mp->format == FORMAT_DELTA) {
 797                         outp += sprintf(outp, "\t%lld", c->counter[i]);
 798                 } else if (mp->format == FORMAT_PERCENT) {
 799                         outp += sprintf(outp, "\t%.2f", 100.0 * c->counter[i]/t->tsc);
 800                 }
 801         }
 802
 803         /* print per-package data only for 1st core in package */
 804         if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
 805                 goto done;
 806
 807         /* PkgTmp */
 808         if (DO_BIC(BIC_PkgTmp))
 809                 outp += sprintf(outp, "\t%d", p->pkg_temp_c);
 810
 811         /* GFXrc6 */
 812         if (DO_BIC(BIC_GFX_rc6)) {
 813                 if (p->gfx_rc6_ms == -1) {      /* detect GFX counter reset */
 814                         outp += sprintf(outp, "\t**.**");
 815                 } else {
 816                         outp += sprintf(outp, "\t%.2f",
 817                                 p->gfx_rc6_ms / 10.0 / interval_float);
 818                 }
 819         }
 820
 821         /* GFXMHz */
 822         if (DO_BIC(BIC_GFXMHz))
 823                 outp += sprintf(outp, "\t%d", p->gfx_mhz);
 824
 825         /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */
 826         if (do_skl_residency) {
 827                 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_wtd_core_c0/t->tsc);
 828                 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_any_core_c0/t->tsc);
 829                 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_any_gfxe_c0/t->tsc);
 830                 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_both_core_gfxe_c0/t->tsc);
 831         }
 832
 833         if (do_pc2)
 834                 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc2/t->tsc);
 835         if (do_pc3)
 836                 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc3/t->tsc);
 837         if (do_pc6)
 838                 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc6/t->tsc);
 839         if (do_pc7)
 840                 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc7/t->tsc);
 841         if (do_c8_c9_c10) {
 842                 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc8/t->tsc);
 843                 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc9/t->tsc);
 844                 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc10/t->tsc);
 845         }
 846
 847         /*
 848          * If measurement interval exceeds minimum RAPL Joule Counter range,
 849          * indicate that results are suspect by printing "**" in fraction place.
 850          */
 851         if (interval_float < rapl_joule_counter_range)
 852                 fmt8 = "\t%.2f";
 853         else
 854                 fmt8 = "%6.0f**";
 855
 856         if (DO_BIC(BIC_PkgWatt))
 857                 outp += sprintf(outp, fmt8, p->energy_pkg * rapl_energy_units / interval_float);
 858         if (DO_BIC(BIC_CorWatt))
 859                 outp += sprintf(outp, fmt8, p->energy_cores * rapl_energy_units / interval_float);
 860         if (DO_BIC(BIC_GFXWatt))
 861                 outp += sprintf(outp, fmt8, p->energy_gfx * rapl_energy_units / interval_float);
 862         if (DO_BIC(BIC_RAMWatt))
 863                 outp += sprintf(outp, fmt8, p->energy_dram * rapl_dram_energy_units / interval_float);
 864         if (DO_BIC(BIC_Pkg_J))
 865                 outp += sprintf(outp, fmt8, p->energy_pkg * rapl_energy_units);
 866         if (DO_BIC(BIC_Cor_J))
 867                 outp += sprintf(outp, fmt8, p->energy_cores * rapl_energy_units);
 868         if (DO_BIC(BIC_GFX_J))
 869                 outp += sprintf(outp, fmt8, p->energy_gfx * rapl_energy_units);
 870         if (DO_BIC(BIC_RAM_J))
 871                 outp += sprintf(outp, fmt8, p->energy_dram * rapl_dram_energy_units);
 872         if (DO_BIC(BIC_PKG__))
 873                 outp += sprintf(outp, fmt8, 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float);
 874         if (DO_BIC(BIC_RAM__))
 875                 outp += sprintf(outp, fmt8, 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float);
 876
 877         for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
 878                 if (mp->format == FORMAT_RAW) {
 879                         if (mp->width == 32)
 880                                 outp += sprintf(outp, "\t0x%08lx", (unsigned long) p->counter[i]);
 881                         else
 882                                 outp += sprintf(outp, "\t0x%016llx", p->counter[i]);
 883                 } else if (mp->format == FORMAT_DELTA) {
 884                         outp += sprintf(outp, "\t%lld", p->counter[i]);
 885                 } else if (mp->format == FORMAT_PERCENT) {
 886                         outp += sprintf(outp, "\t%.2f", 100.0 * p->counter[i]/t->tsc);
 887                 }
 888         }
 889
 890 done:
 891         outp += sprintf(outp, "\n");
 892
 893         return 0;
 894 }
 895
 896 void flush_output_stdout(void)
 897 {
 898         FILE *filep;
 899
 900         if (outf == stderr)
 901                 filep = stdout;
 902         else
 903                 filep = outf;
 904
 905         fputs(output_buffer, filep);
 906         fflush(filep);
 907
 908         outp = output_buffer;
 909 }
 910 void flush_output_stderr(void)
 911 {
 912         fputs(output_buffer, outf);
 913         fflush(outf);
 914         outp = output_buffer;
 915 }
 916 void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
 917 {
 918         static int printed;
 919
 920         if (!printed || !summary_only)
 921                 print_header();
 922
 923         if (topo.num_cpus > 1)
 924                 format_counters(&average.threads, &average.cores,
 925                         &average.packages);
 926
 927         printed = 1;
 928
 929         if (summary_only)
 930                 return;
 931
 932         for_all_cpus(format_counters, t, c, p);
 933 }
 934
 935 #define DELTA_WRAP32(new, old)                  \
 936         if (new > old) {                        \
 937                 old = new - old;                \
 938         } else {                                \
 939                 old = 0x100000000 + new - old;  \
 940         }
 941
 942 int
 943 delta_package(struct pkg_data *new, struct pkg_data *old)
 944 {
 945         int i;
 946         struct msr_counter *mp;
 947
 948         if (do_skl_residency) {
 949                 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0;
 950                 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0;
 951                 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0;
 952                 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0;
 953         }
 954         old->pc2 = new->pc2 - old->pc2;
 955         if (do_pc3)
 956                 old->pc3 = new->pc3 - old->pc3;
 957         if (do_pc6)
 958                 old->pc6 = new->pc6 - old->pc6;
 959         if (do_pc7)
 960                 old->pc7 = new->pc7 - old->pc7;
 961         old->pc8 = new->pc8 - old->pc8;
 962         old->pc9 = new->pc9 - old->pc9;
 963         old->pc10 = new->pc10 - old->pc10;
 964         old->pkg_temp_c = new->pkg_temp_c;
 965
 966         /* flag an error when rc6 counter resets/wraps */
 967         if (old->gfx_rc6_ms >  new->gfx_rc6_ms)
 968                 old->gfx_rc6_ms = -1;
 969         else
 970                 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms;
 971
 972         old->gfx_mhz = new->gfx_mhz;
 973
 974         DELTA_WRAP32(new->energy_pkg, old->energy_pkg);
 975         DELTA_WRAP32(new->energy_cores, old->energy_cores);
 976         DELTA_WRAP32(new->energy_gfx, old->energy_gfx);
 977         DELTA_WRAP32(new->energy_dram, old->energy_dram);
 978         DELTA_WRAP32(new->rapl_pkg_perf_status, old->rapl_pkg_perf_status);
 979         DELTA_WRAP32(new->rapl_dram_perf_status, old->rapl_dram_perf_status);
 980
 981         for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
 982                 if (mp->format == FORMAT_RAW)
 983                         old->counter[i] = new->counter[i];
 984                 else
 985                         old->counter[i] = new->counter[i] - old->counter[i];
 986         }
 987
 988         return 0;
 989 }
 990
 991 void
 992 delta_core(struct core_data *new, struct core_data *old)
 993 {
 994         int i;
 995         struct msr_counter *mp;
 996
 997         old->c3 = new->c3 - old->c3;
 998         old->c6 = new->c6 - old->c6;
 999         old->c7 = new->c7 - old->c7;
1000         old->core_temp_c = new->core_temp_c;
1001         old->mc6_us = new->mc6_us - old->mc6_us;
1002
1003         for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1004                 if (mp->format == FORMAT_RAW)
1005                         old->counter[i] = new->counter[i];
1006                 else
1007                         old->counter[i] = new->counter[i] - old->counter[i];
1008         }
1009 }
1010
1011 /*
1012  * old = new - old
1013  */
1014 int
1015 delta_thread(struct thread_data *new, struct thread_data *old,
1016         struct core_data *core_delta)
1017 {
1018         int i;
1019         struct msr_counter *mp;
1020
1021         old->tsc = new->tsc - old->tsc;
1022
1023         /* check for TSC < 1 Mcycles over interval */
1024         if (old->tsc < (1000 * 1000))
1025                 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n"
1026                      "You can disable all c-states by booting with \"idle=poll\"\n"
1027                      "or just the deep ones with \"processor.max_cstate=1\"");
1028
1029         old->c1 = new->c1 - old->c1;
1030
1031         if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz)) {
1032                 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) {
1033                         old->aperf = new->aperf - old->aperf;
1034                         old->mperf = new->mperf - old->mperf;
1035                 } else {
1036                         return -1;
1037                 }
1038         }
1039
1040
1041         if (use_c1_residency_msr) {
1042                 /*
1043                  * Some models have a dedicated C1 residency MSR,
1044                  * which should be more accurate than the derivation below.
1045                  */
1046         } else {
1047                 /*
1048                  * As counter collection is not atomic,
1049                  * it is possible for mperf's non-halted cycles + idle states
1050                  * to exceed TSC's all cycles: show c1 = 0% in that case.
1051                  */
1052                 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > old->tsc)
1053                         old->c1 = 0;
1054                 else {
1055                         /* normal case, derive c1 */
1056                         old->c1 = old->tsc - old->mperf - core_delta->c3
1057                                 - core_delta->c6 - core_delta->c7;
1058                 }
1059         }
1060
1061         if (old->mperf == 0) {
1062                 if (debug > 1)
1063                         fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id);
1064                 old->mperf = 1; /* divide by 0 protection */
1065         }
1066
1067         if (DO_BIC(BIC_IRQ))
1068                 old->irq_count = new->irq_count - old->irq_count;
1069
1070         if (DO_BIC(BIC_SMI))
1071                 old->smi_count = new->smi_count - old->smi_count;
1072
1073         for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1074                 if (mp->format == FORMAT_RAW)
1075                         old->counter[i] = new->counter[i];
1076                 else
1077                         old->counter[i] = new->counter[i] - old->counter[i];
1078         }
1079         return 0;
1080 }
1081
1082 int delta_cpu(struct thread_data *t, struct core_data *c,
1083         struct pkg_data *p, struct thread_data *t2,
1084         struct core_data *c2, struct pkg_data *p2)
1085 {
1086         int retval = 0;
1087
1088         /* calculate core delta only for 1st thread in core */
1089         if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE)
1090                 delta_core(c, c2);
1091
1092         /* always calculate thread delta */
1093         retval = delta_thread(t, t2, c2);       /* c2 is core delta */
1094         if (retval)
1095                 return retval;
1096
1097         /* calculate package delta only for 1st core in package */
1098         if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)
1099                 retval = delta_package(p, p2);
1100
1101         return retval;
1102 }
1103
1104 void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1105 {
1106         int i;
1107         struct msr_counter  *mp;
1108
1109         t->tsc = 0;
1110         t->aperf = 0;
1111         t->mperf = 0;
1112         t->c1 = 0;
1113
1114         t->irq_count = 0;
1115         t->smi_count = 0;
1116
1117         /* tells format_counters to dump all fields from this set */
1118         t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE;
1119
1120         c->c3 = 0;
1121         c->c6 = 0;
1122         c->c7 = 0;
1123         c->mc6_us = 0;
1124         c->core_temp_c = 0;
1125
1126         p->pkg_wtd_core_c0 = 0;
1127         p->pkg_any_core_c0 = 0;
1128         p->pkg_any_gfxe_c0 = 0;
1129         p->pkg_both_core_gfxe_c0 = 0;
1130
1131         p->pc2 = 0;
1132         if (do_pc3)
1133                 p->pc3 = 0;
1134         if (do_pc6)
1135                 p->pc6 = 0;
1136         if (do_pc7)
1137                 p->pc7 = 0;
1138         p->pc8 = 0;
1139         p->pc9 = 0;
1140         p->pc10 = 0;
1141
1142         p->energy_pkg = 0;
1143         p->energy_dram = 0;
1144         p->energy_cores = 0;
1145         p->energy_gfx = 0;
1146         p->rapl_pkg_perf_status = 0;
1147         p->rapl_dram_perf_status = 0;
1148         p->pkg_temp_c = 0;
1149
1150         p->gfx_rc6_ms = 0;
1151         p->gfx_mhz = 0;
1152         for (i = 0, mp = sys.tp; mp; i++, mp = mp->next)
1153                 t->counter[i] = 0;
1154
1155         for (i = 0, mp = sys.cp; mp; i++, mp = mp->next)
1156                 c->counter[i] = 0;
1157
1158         for (i = 0, mp = sys.pp; mp; i++, mp = mp->next)
1159                 p->counter[i] = 0;
1160 }
1161 int sum_counters(struct thread_data *t, struct core_data *c,
1162         struct pkg_data *p)
1163 {
1164         int i;
1165         struct msr_counter *mp;
1166
1167         average.threads.tsc += t->tsc;
1168         average.threads.aperf += t->aperf;
1169         average.threads.mperf += t->mperf;
1170         average.threads.c1 += t->c1;
1171
1172         average.threads.irq_count += t->irq_count;
1173         average.threads.smi_count += t->smi_count;
1174
1175         for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1176                 if (mp->format == FORMAT_RAW)
1177                         continue;
1178                 average.threads.counter[i] += t->counter[i];
1179         }
1180
1181         /* sum per-core values only for 1st thread in core */
1182         if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
1183                 return 0;
1184
1185         average.cores.c3 += c->c3;
1186         average.cores.c6 += c->c6;
1187         average.cores.c7 += c->c7;
1188         average.cores.mc6_us += c->mc6_us;
1189
1190         average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c);
1191
1192         for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1193                 if (mp->format == FORMAT_RAW)
1194                         continue;
1195                 average.cores.counter[i] += c->counter[i];
1196         }
1197
1198         /* sum per-pkg values only for 1st core in pkg */
1199         if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
1200                 return 0;
1201
1202         if (do_skl_residency) {
1203                 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0;
1204                 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0;
1205                 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0;
1206                 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0;
1207         }
1208
1209         average.packages.pc2 += p->pc2;
1210         if (do_pc3)
1211                 average.packages.pc3 += p->pc3;
1212         if (do_pc6)
1213                 average.packages.pc6 += p->pc6;
1214         if (do_pc7)
1215                 average.packages.pc7 += p->pc7;
1216         average.packages.pc8 += p->pc8;
1217         average.packages.pc9 += p->pc9;
1218         average.packages.pc10 += p->pc10;
1219
1220         average.packages.energy_pkg += p->energy_pkg;
1221         average.packages.energy_dram += p->energy_dram;
1222         average.packages.energy_cores += p->energy_cores;
1223         average.packages.energy_gfx += p->energy_gfx;
1224
1225         average.packages.gfx_rc6_ms = p->gfx_rc6_ms;
1226         average.packages.gfx_mhz = p->gfx_mhz;
1227
1228         average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c);
1229
1230         average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status;
1231         average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status;
1232
1233         for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1234                 if (mp->format == FORMAT_RAW)
1235                         continue;
1236                 average.packages.counter[i] += p->counter[i];
1237         }
1238         return 0;
1239 }
1240 /*
1241  * sum the counters for all cpus in the system
1242  * compute the weighted average
1243  */
1244 void compute_average(struct thread_data *t, struct core_data *c,
1245         struct pkg_data *p)
1246 {
1247         int i;
1248         struct msr_counter *mp;
1249
1250         clear_counters(&average.threads, &average.cores, &average.packages);
1251
1252         for_all_cpus(sum_counters, t, c, p);
1253
1254         average.threads.tsc /= topo.num_cpus;
1255         average.threads.aperf /= topo.num_cpus;
1256         average.threads.mperf /= topo.num_cpus;
1257         average.threads.c1 /= topo.num_cpus;
1258
1259         average.cores.c3 /= topo.num_cores;
1260         average.cores.c6 /= topo.num_cores;
1261         average.cores.c7 /= topo.num_cores;
1262         average.cores.mc6_us /= topo.num_cores;
1263
1264         if (do_skl_residency) {
1265                 average.packages.pkg_wtd_core_c0 /= topo.num_packages;
1266                 average.packages.pkg_any_core_c0 /= topo.num_packages;
1267                 average.packages.pkg_any_gfxe_c0 /= topo.num_packages;
1268                 average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages;
1269         }
1270
1271         average.packages.pc2 /= topo.num_packages;
1272         if (do_pc3)
1273                 average.packages.pc3 /= topo.num_packages;
1274         if (do_pc6)
1275                 average.packages.pc6 /= topo.num_packages;
1276         if (do_pc7)
1277                 average.packages.pc7 /= topo.num_packages;
1278
1279         average.packages.pc8 /= topo.num_packages;
1280         average.packages.pc9 /= topo.num_packages;
1281         average.packages.pc10 /= topo.num_packages;
1282
1283         for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1284                 if (mp->format == FORMAT_RAW)
1285                         continue;
1286                 average.threads.counter[i] /= topo.num_cpus;
1287         }
1288         for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1289                 if (mp->format == FORMAT_RAW)
1290                         continue;
1291                 average.cores.counter[i] /= topo.num_cores;
1292         }
1293         for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1294                 if (mp->format == FORMAT_RAW)
1295                         continue;
1296                 average.packages.counter[i] /= topo.num_packages;
1297         }
1298 }
1299
1300 static unsigned long long rdtsc(void)
1301 {
1302         unsigned int low, high;
1303
1304         asm volatile("rdtsc" : "=a" (low), "=d" (high));
1305
1306         return low | ((unsigned long long)high) << 32;
1307 }
1308
1309 /*
1310  * get_counters(...)
1311  * migrate to cpu
1312  * acquire and record local counters for that cpu
1313  */
1314 int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1315 {
1316         int cpu = t->cpu_id;
1317         unsigned long long msr;
1318         int aperf_mperf_retry_count = 0;
1319         struct msr_counter *mp;
1320         int i;
1321
1322         if (cpu_migrate(cpu)) {
1323                 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
1324                 return -1;
1325         }
1326
1327 retry:
1328         t->tsc = rdtsc();       /* we are running on local CPU of interest */
1329
1330         if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz)) {
1331                 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time;
1332
1333                 /*
1334                  * The TSC, APERF and MPERF must be read together for
1335                  * APERF/MPERF and MPERF/TSC to give accurate results.
1336                  *
1337                  * Unfortunately, APERF and MPERF are read by
1338                  * individual system call, so delays may occur
1339                  * between them.  If the time to read them
1340                  * varies by a large amount, we re-read them.
1341                  */
1342
1343                 /*
1344                  * This initial dummy APERF read has been seen to
1345                  * reduce jitter in the subsequent reads.
1346                  */
1347
1348                 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
1349                         return -3;
1350
1351                 t->tsc = rdtsc();       /* re-read close to APERF */
1352
1353                 tsc_before = t->tsc;
1354
1355                 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
1356                         return -3;
1357
1358                 tsc_between = rdtsc();
1359
1360                 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf))
1361                         return -4;
1362
1363                 tsc_after = rdtsc();
1364
1365                 aperf_time = tsc_between - tsc_before;
1366                 mperf_time = tsc_after - tsc_between;
1367
1368                 /*
1369                  * If the system call latency to read APERF and MPERF
1370                  * differ by more than 2x, then try again.
1371                  */
1372                 if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) {
1373                         aperf_mperf_retry_count++;
1374                         if (aperf_mperf_retry_count < 5)
1375                                 goto retry;
1376                         else
1377                                 warnx("cpu%d jitter %lld %lld",
1378                                         cpu, aperf_time, mperf_time);
1379                 }
1380                 aperf_mperf_retry_count = 0;
1381
1382                 t->aperf = t->aperf * aperf_mperf_multiplier;
1383                 t->mperf = t->mperf * aperf_mperf_multiplier;
1384         }
1385
1386         if (DO_BIC(BIC_IRQ))
1387                 t->irq_count = irqs_per_cpu[cpu];
1388         if (DO_BIC(BIC_SMI)) {
1389                 if (get_msr(cpu, MSR_SMI_COUNT, &msr))
1390                         return -5;
1391                 t->smi_count = msr & 0xFFFFFFFF;
1392         }
1393         if (DO_BIC(BIC_CPU_c1) && use_c1_residency_msr) {
1394                 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1))
1395                         return -6;
1396         }
1397
1398         for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1399                 if (get_msr(cpu, mp->msr_num, &t->counter[i]))
1400                         return -10;
1401         }
1402
1403
1404         /* collect core counters only for 1st thread in core */
1405         if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
1406                 return 0;
1407
1408         if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates) {
1409                 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3))
1410                         return -6;
1411         }
1412
1413         if (DO_BIC(BIC_CPU_c6) && !do_knl_cstates) {
1414                 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6))
1415                         return -7;
1416         } else if (do_knl_cstates) {
1417                 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6))
1418                         return -7;
1419         }
1420
1421         if (DO_BIC(BIC_CPU_c7))
1422                 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7))
1423                         return -8;
1424
1425         if (DO_BIC(BIC_Mod_c6))
1426                 if (get_msr(cpu, MSR_MODULE_C6_RES_MS, &c->mc6_us))
1427                         return -8;
1428
1429         if (DO_BIC(BIC_CoreTmp)) {
1430                 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
1431                         return -9;
1432                 c->core_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F);
1433         }
1434
1435         for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1436                 if (get_msr(cpu, mp->msr_num, &c->counter[i]))
1437                         return -10;
1438         }
1439
1440         /* collect package counters only for 1st core in package */
1441         if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
1442                 return 0;
1443
1444         if (do_skl_residency) {
1445                 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0))
1446                         return -10;
1447                 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0))
1448                         return -11;
1449                 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0))
1450                         return -12;
1451                 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0))
1452                         return -13;
1453         }
1454         if (do_pc3)
1455                 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3))
1456                         return -9;
1457         if (do_pc6) {
1458                 if (do_slm_cstates) {
1459                         if (get_msr(cpu, MSR_ATOM_PKG_C6_RESIDENCY, &p->pc6))
1460                                 return -10;
1461                 } else {
1462                         if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6))
1463                                 return -10;
1464                 }
1465         }
1466
1467         if (do_pc2)
1468                 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2))
1469                         return -11;
1470         if (do_pc7)
1471                 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7))
1472                         return -12;
1473         if (do_c8_c9_c10) {
1474                 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8))
1475                         return -13;
1476                 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9))
1477                         return -13;
1478                 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10))
1479                         return -13;
1480         }
1481         if (do_rapl & RAPL_PKG) {
1482                 if (get_msr(cpu, MSR_PKG_ENERGY_STATUS, &msr))
1483                         return -13;
1484                 p->energy_pkg = msr & 0xFFFFFFFF;
1485         }
1486         if (do_rapl & RAPL_CORES_ENERGY_STATUS) {
1487                 if (get_msr(cpu, MSR_PP0_ENERGY_STATUS, &msr))
1488                         return -14;
1489                 p->energy_cores = msr & 0xFFFFFFFF;
1490         }
1491         if (do_rapl & RAPL_DRAM) {
1492                 if (get_msr(cpu, MSR_DRAM_ENERGY_STATUS, &msr))
1493                         return -15;
1494                 p->energy_dram = msr & 0xFFFFFFFF;
1495         }
1496         if (do_rapl & RAPL_GFX) {
1497                 if (get_msr(cpu, MSR_PP1_ENERGY_STATUS, &msr))
1498                         return -16;
1499                 p->energy_gfx = msr & 0xFFFFFFFF;
1500         }
1501         if (do_rapl & RAPL_PKG_PERF_STATUS) {
1502                 if (get_msr(cpu, MSR_PKG_PERF_STATUS, &msr))
1503                         return -16;
1504                 p->rapl_pkg_perf_status = msr & 0xFFFFFFFF;
1505         }
1506         if (do_rapl & RAPL_DRAM_PERF_STATUS) {
1507                 if (get_msr(cpu, MSR_DRAM_PERF_STATUS, &msr))
1508                         return -16;
1509                 p->rapl_dram_perf_status = msr & 0xFFFFFFFF;
1510         }
1511         if (DO_BIC(BIC_PkgTmp)) {
1512                 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
1513                         return -17;
1514                 p->pkg_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F);
1515         }
1516
1517         if (DO_BIC(BIC_GFX_rc6))
1518                 p->gfx_rc6_ms = gfx_cur_rc6_ms;
1519
1520         if (DO_BIC(BIC_GFXMHz))
1521                 p->gfx_mhz = gfx_cur_mhz;
1522
1523         for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1524                 if (get_msr(cpu, mp->msr_num, &p->counter[i]))
1525                         return -10;
1526         }
1527
1528         return 0;
1529 }
1530
1531 /*
1532  * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit:
1533  * If you change the values, note they are used both in comparisons
1534  * (>= PCL__7) and to index pkg_cstate_limit_strings[].
1535  */
1536
1537 #define PCLUKN 0 /* Unknown */
1538 #define PCLRSV 1 /* Reserved */
1539 #define PCL__0 2 /* PC0 */
1540 #define PCL__1 3 /* PC1 */
1541 #define PCL__2 4 /* PC2 */
1542 #define PCL__3 5 /* PC3 */
1543 #define PCL__4 6 /* PC4 */
1544 #define PCL__6 7 /* PC6 */
1545 #define PCL_6N 8 /* PC6 No Retention */
1546 #define PCL_6R 9 /* PC6 Retention */
1547 #define PCL__7 10 /* PC7 */
1548 #define PCL_7S 11 /* PC7 Shrink */
1549 #define PCL__8 12 /* PC8 */
1550 #define PCL__9 13 /* PC9 */
1551 #define PCLUNL 14 /* Unlimited */
1552
1553 int pkg_cstate_limit = PCLUKN;
1554 char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2",
1555         "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "unlimited"};
1556
1557 int nhm_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1558 int snb_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1559 int hsw_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1560 int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7};
1561 int amt_pkg_cstate_limits[16] = {PCLUNL, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1562 int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1563 int bxt_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1564 int skx_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1565
1566
1567 static void
1568 calculate_tsc_tweak()
1569 {
1570         tsc_tweak = base_hz / tsc_hz;
1571 }
1572
1573 static void
1574 dump_nhm_platform_info(void)
1575 {
1576         unsigned long long msr;
1577         unsigned int ratio;
1578
1579         get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
1580
1581         fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr);
1582
1583         ratio = (msr >> 40) & 0xFF;
1584         fprintf(outf, "%d * %.1f = %.1f MHz max efficiency frequency\n",
1585                 ratio, bclk, ratio * bclk);
1586
1587         ratio = (msr >> 8) & 0xFF;
1588         fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n",
1589                 ratio, bclk, ratio * bclk);
1590
1591         get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr);
1592         fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n",
1593                 base_cpu, msr, msr & 0x2 ? "EN" : "DIS");
1594
1595         return;
1596 }
1597
1598 static void
1599 dump_hsw_turbo_ratio_limits(void)
1600 {
1601         unsigned long long msr;
1602         unsigned int ratio;
1603
1604         get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr);
1605
1606         fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr);
1607
1608         ratio = (msr >> 8) & 0xFF;
1609         if (ratio)
1610                 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 18 active cores\n",
1611                         ratio, bclk, ratio * bclk);
1612
1613         ratio = (msr >> 0) & 0xFF;
1614         if (ratio)
1615                 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 17 active cores\n",
1616                         ratio, bclk, ratio * bclk);
1617         return;
1618 }
1619
1620 static void
1621 dump_ivt_turbo_ratio_limits(void)
1622 {
1623         unsigned long long msr;
1624         unsigned int ratio;
1625
1626         get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr);
1627
1628         fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr);
1629
1630         ratio = (msr >> 56) & 0xFF;
1631         if (ratio)
1632                 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 16 active cores\n",
1633                         ratio, bclk, ratio * bclk);
1634
1635         ratio = (msr >> 48) & 0xFF;
1636         if (ratio)
1637                 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 15 active cores\n",
1638                         ratio, bclk, ratio * bclk);
1639
1640         ratio = (msr >> 40) & 0xFF;
1641         if (ratio)
1642                 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 14 active cores\n",
1643                         ratio, bclk, ratio * bclk);
1644
1645         ratio = (msr >> 32) & 0xFF;
1646         if (ratio)
1647                 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 13 active cores\n",
1648                         ratio, bclk, ratio * bclk);
1649
1650         ratio = (msr >> 24) & 0xFF;
1651         if (ratio)
1652                 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 12 active cores\n",
1653                         ratio, bclk, ratio * bclk);
1654
1655         ratio = (msr >> 16) & 0xFF;
1656         if (ratio)
1657                 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 11 active cores\n",
1658                         ratio, bclk, ratio * bclk);
1659
1660         ratio = (msr >> 8) & 0xFF;
1661         if (ratio)
1662                 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 10 active cores\n",
1663                         ratio, bclk, ratio * bclk);
1664
1665         ratio = (msr >> 0) & 0xFF;
1666         if (ratio)
1667                 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 9 active cores\n",
1668                         ratio, bclk, ratio * bclk);
1669         return;
1670 }
1671
1672 static void
1673 dump_nhm_turbo_ratio_limits(void)
1674 {
1675         unsigned long long msr;
1676         unsigned int ratio;
1677
1678         get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr);
1679
1680         fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr);
1681
1682         ratio = (msr >> 56) & 0xFF;
1683         if (ratio)
1684                 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 8 active cores\n",
1685                         ratio, bclk, ratio * bclk);
1686
1687         ratio = (msr >> 48) & 0xFF;
1688         if (ratio)
1689                 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 7 active cores\n",
1690                         ratio, bclk, ratio * bclk);
1691
1692         ratio = (msr >> 40) & 0xFF;
1693         if (ratio)
1694                 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 6 active cores\n",
1695                         ratio, bclk, ratio * bclk);
1696
1697         ratio = (msr >> 32) & 0xFF;
1698         if (ratio)
1699                 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 5 active cores\n",
1700                         ratio, bclk, ratio * bclk);
1701
1702         ratio = (msr >> 24) & 0xFF;
1703         if (ratio)
1704                 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n",
1705                         ratio, bclk, ratio * bclk);
1706
1707         ratio = (msr >> 16) & 0xFF;
1708         if (ratio)
1709                 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n",
1710                         ratio, bclk, ratio * bclk);
1711
1712         ratio = (msr >> 8) & 0xFF;
1713         if (ratio)
1714                 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n",
1715                         ratio, bclk, ratio * bclk);
1716
1717         ratio = (msr >> 0) & 0xFF;
1718         if (ratio)
1719                 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active cores\n",
1720                         ratio, bclk, ratio * bclk);
1721         return;
1722 }
1723
1724 static void
1725 dump_atom_turbo_ratio_limits(void)
1726 {
1727         unsigned long long msr;
1728         unsigned int ratio;
1729
1730         get_msr(base_cpu, MSR_ATOM_CORE_RATIOS, &msr);
1731         fprintf(outf, "cpu%d: MSR_ATOM_CORE_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF);
1732
1733         ratio = (msr >> 0) & 0x3F;
1734         if (ratio)
1735                 fprintf(outf, "%d * %.1f = %.1f MHz minimum operating frequency\n",
1736                         ratio, bclk, ratio * bclk);
1737
1738         ratio = (msr >> 8) & 0x3F;
1739         if (ratio)
1740                 fprintf(outf, "%d * %.1f = %.1f MHz low frequency mode (LFM)\n",
1741                         ratio, bclk, ratio * bclk);
1742
1743         ratio = (msr >> 16) & 0x3F;
1744         if (ratio)
1745                 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n",
1746                         ratio, bclk, ratio * bclk);
1747
1748         get_msr(base_cpu, MSR_ATOM_CORE_TURBO_RATIOS, &msr);
1749         fprintf(outf, "cpu%d: MSR_ATOM_CORE_TURBO_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF);
1750
1751         ratio = (msr >> 24) & 0x3F;
1752         if (ratio)
1753                 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n",
1754                         ratio, bclk, ratio * bclk);
1755
1756         ratio = (msr >> 16) & 0x3F;
1757         if (ratio)
1758                 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n",
1759                         ratio, bclk, ratio * bclk);
1760
1761         ratio = (msr >> 8) & 0x3F;
1762         if (ratio)
1763                 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n",
1764                         ratio, bclk, ratio * bclk);
1765
1766         ratio = (msr >> 0) & 0x3F;
1767         if (ratio)
1768                 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active core\n",
1769                         ratio, bclk, ratio * bclk);
1770 }
1771
1772 static void
1773 dump_knl_turbo_ratio_limits(void)
1774 {
1775         const unsigned int buckets_no = 7;
1776
1777         unsigned long long msr;
1778         int delta_cores, delta_ratio;
1779         int i, b_nr;
1780         unsigned int cores[buckets_no];
1781         unsigned int ratio[buckets_no];
1782
1783         get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr);
1784
1785         fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n",
1786                 base_cpu, msr);
1787
1788         /**
1789          * Turbo encoding in KNL is as follows:
1790          * [0] -- Reserved
1791          * [7:1] -- Base value of number of active cores of bucket 1.
1792          * [15:8] -- Base value of freq ratio of bucket 1.
1793          * [20:16] -- +ve delta of number of active cores of bucket 2.
1794          * i.e. active cores of bucket 2 =
1795          * active cores of bucket 1 + delta
1796          * [23:21] -- Negative delta of freq ratio of bucket 2.
1797          * i.e. freq ratio of bucket 2 =
1798          * freq ratio of bucket 1 - delta
1799          * [28:24]-- +ve delta of number of active cores of bucket 3.
1800          * [31:29]-- -ve delta of freq ratio of bucket 3.
1801          * [36:32]-- +ve delta of number of active cores of bucket 4.
1802          * [39:37]-- -ve delta of freq ratio of bucket 4.
1803          * [44:40]-- +ve delta of number of active cores of bucket 5.
1804          * [47:45]-- -ve delta of freq ratio of bucket 5.
1805          * [52:48]-- +ve delta of number of active cores of bucket 6.
1806          * [55:53]-- -ve delta of freq ratio of bucket 6.
1807          * [60:56]-- +ve delta of number of active cores of bucket 7.
1808          * [63:61]-- -ve delta of freq ratio of bucket 7.
1809          */
1810
1811         b_nr = 0;
1812         cores[b_nr] = (msr & 0xFF) >> 1;
1813         ratio[b_nr] = (msr >> 8) & 0xFF;
1814
1815         for (i = 16; i < 64; i += 8) {
1816                 delta_cores = (msr >> i) & 0x1F;
1817                 delta_ratio = (msr >> (i + 5)) & 0x7;
1818
1819                 cores[b_nr + 1] = cores[b_nr] + delta_cores;
1820                 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio;
1821                 b_nr++;
1822         }
1823
1824         for (i = buckets_no - 1; i >= 0; i--)
1825                 if (i > 0 ? ratio[i] != ratio[i - 1] : 1)
1826                         fprintf(outf,
1827                                 "%d * %.1f = %.1f MHz max turbo %d active cores\n",
1828                                 ratio[i], bclk, ratio[i] * bclk, cores[i]);
1829 }
1830
1831 static void
1832 dump_nhm_cst_cfg(void)
1833 {
1834         unsigned long long msr;
1835
1836         get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr);
1837
1838 #define SNB_C1_AUTO_UNDEMOTE              (1UL << 27)
1839 #define SNB_C3_AUTO_UNDEMOTE              (1UL << 28)
1840
1841         fprintf(outf, "cpu%d: MSR_PKG_CST_CONFIG_CONTROL: 0x%08llx", base_cpu, msr);
1842
1843         fprintf(outf, " (%s%s%s%s%slocked: pkg-cstate-limit=%d: %s)\n",
1844                 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "",
1845                 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "",
1846                 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "",
1847                 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "",
1848                 (msr & (1 << 15)) ? "" : "UN",
1849                 (unsigned int)msr & 0xF,
1850                 pkg_cstate_limit_strings[pkg_cstate_limit]);
1851         return;
1852 }
1853
1854 static void
1855 dump_config_tdp(void)
1856 {
1857         unsigned long long msr;
1858
1859         get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr);
1860         fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr);
1861         fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF);
1862
1863         get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr);
1864         fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr);
1865         if (msr) {
1866                 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF);
1867                 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF);
1868                 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF);
1869                 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF);
1870         }
1871         fprintf(outf, ")\n");
1872
1873         get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr);
1874         fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr);
1875         if (msr) {
1876                 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF);
1877                 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF);
1878                 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF);
1879                 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF);
1880         }
1881         fprintf(outf, ")\n");
1882
1883         get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr);
1884         fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr);
1885         if ((msr) & 0x3)
1886                 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3);
1887         fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1);
1888         fprintf(outf, ")\n");
1889
1890         get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr);
1891         fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr);
1892         fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF);
1893         fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1);
1894         fprintf(outf, ")\n");
1895 }
1896
1897 unsigned int irtl_time_units[] = {1, 32, 1024, 32768, 1048576, 33554432, 0, 0 };
1898
1899 void print_irtl(void)
1900 {
1901         unsigned long long msr;
1902
1903         get_msr(base_cpu, MSR_PKGC3_IRTL, &msr);
1904         fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr);
1905         fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
1906                 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
1907
1908         get_msr(base_cpu, MSR_PKGC6_IRTL, &msr);
1909         fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr);
1910         fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
1911                 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
1912
1913         get_msr(base_cpu, MSR_PKGC7_IRTL, &msr);
1914         fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr);
1915         fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
1916                 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
1917
1918         if (!do_irtl_hsw)
1919                 return;
1920
1921         get_msr(base_cpu, MSR_PKGC8_IRTL, &msr);
1922         fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr);
1923         fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
1924                 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
1925
1926         get_msr(base_cpu, MSR_PKGC9_IRTL, &msr);
1927         fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr);
1928         fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
1929                 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
1930
1931         get_msr(base_cpu, MSR_PKGC10_IRTL, &msr);
1932         fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr);
1933         fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
1934                 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
1935
1936 }
1937 void free_fd_percpu(void)
1938 {
1939         int i;
1940
1941         for (i = 0; i < topo.max_cpu_num + 1; ++i) {
1942                 if (fd_percpu[i] != 0)
1943                         close(fd_percpu[i]);
1944         }
1945
1946         free(fd_percpu);
1947 }
1948
1949 void free_all_buffers(void)
1950 {
1951         CPU_FREE(cpu_present_set);
1952         cpu_present_set = NULL;
1953         cpu_present_setsize = 0;
1954
1955         CPU_FREE(cpu_affinity_set);
1956         cpu_affinity_set = NULL;
1957         cpu_affinity_setsize = 0;
1958
1959         free(thread_even);
1960         free(core_even);
1961         free(package_even);
1962
1963         thread_even = NULL;
1964         core_even = NULL;
1965         package_even = NULL;
1966
1967         free(thread_odd);
1968         free(core_odd);
1969         free(package_odd);
1970
1971         thread_odd = NULL;
1972         core_odd = NULL;
1973         package_odd = NULL;
1974
1975         free(output_buffer);
1976         output_buffer = NULL;
1977         outp = NULL;
1978
1979         free_fd_percpu();
1980
1981         free(irq_column_2_cpu);
1982         free(irqs_per_cpu);
1983 }
1984
1985 /*
1986  * Open a file, and exit on failure
1987  */
1988 FILE *fopen_or_die(const char *path, const char *mode)
1989 {
1990         FILE *filep = fopen(path, mode);
1991         if (!filep)
1992                 err(1, "%s: open failed", path);
1993         return filep;
1994 }
1995
1996 /*
1997  * Parse a file containing a single int.
1998  */
1999 int parse_int_file(const char *fmt, ...)
2000 {
2001         va_list args;
2002         char path[PATH_MAX];
2003         FILE *filep;
2004         int value;
2005
2006         va_start(args, fmt);
2007         vsnprintf(path, sizeof(path), fmt, args);
2008         va_end(args);
2009         filep = fopen_or_die(path, "r");
2010         if (fscanf(filep, "%d", &value) != 1)
2011                 err(1, "%s: failed to parse number from file", path);
2012         fclose(filep);
2013         return value;
2014 }
2015
2016 /*
2017  * get_cpu_position_in_core(cpu)
2018  * return the position of the CPU among its HT siblings in the core
2019  * return -1 if the sibling is not in list
2020  */
2021 int get_cpu_position_in_core(int cpu)
2022 {
2023         char path[64];
2024         FILE *filep;
2025         int this_cpu;
2026         char character;
2027         int i;
2028
2029         sprintf(path,
2030                 "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list",
2031                 cpu);
2032         filep = fopen(path, "r");
2033         if (filep == NULL) {
2034                 perror(path);
2035                 exit(1);
2036         }
2037
2038         for (i = 0; i < topo.num_threads_per_core; i++) {
2039                 fscanf(filep, "%d", &this_cpu);
2040                 if (this_cpu == cpu) {
2041                         fclose(filep);
2042                         return i;
2043                 }
2044
2045                 /* Account for no separator after last thread*/
2046                 if (i != (topo.num_threads_per_core - 1))
2047                         fscanf(filep, "%c", &character);
2048         }
2049
2050         fclose(filep);
2051         return -1;
2052 }
2053
2054 /*
2055  * cpu_is_first_core_in_package(cpu)
2056  * return 1 if given CPU is 1st core in package
2057  */
2058 int cpu_is_first_core_in_package(int cpu)
2059 {
2060         return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu);
2061 }
2062
2063 int get_physical_package_id(int cpu)
2064 {
2065         return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu);
2066 }
2067
2068 int get_core_id(int cpu)
2069 {
2070         return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu);
2071 }
2072
2073 int get_num_ht_siblings(int cpu)
2074 {
2075         char path[80];
2076         FILE *filep;
2077         int sib1;
2078         int matches = 0;
2079         char character;
2080         char str[100];
2081         char *ch;
2082
2083         sprintf(path, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list", cpu);
2084         filep = fopen_or_die(path, "r");
2085
2086         /*
2087          * file format:
2088          * A ',' separated or '-' separated set of numbers
2089          * (eg 1-2 or 1,3,4,5)
2090          */
2091         fscanf(filep, "%d%c\n", &sib1, &character);
2092         fseek(filep, 0, SEEK_SET);
2093         fgets(str, 100, filep);
2094         ch = strchr(str, character);
2095         while (ch != NULL) {
2096                 matches++;
2097                 ch = strchr(ch+1, character);
2098         }
2099
2100         fclose(filep);
2101         return matches+1;
2102 }
2103
2104 /*
2105  * run func(thread, core, package) in topology order
2106  * skip non-present cpus
2107  */
2108
2109 int for_all_cpus_2(int (func)(struct thread_data *, struct core_data *,
2110         struct pkg_data *, struct thread_data *, struct core_data *,
2111         struct pkg_data *), struct thread_data *thread_base,
2112         struct core_data *core_base, struct pkg_data *pkg_base,
2113         struct thread_data *thread_base2, struct core_data *core_base2,
2114         struct pkg_data *pkg_base2)
2115 {
2116         int retval, pkg_no, core_no, thread_no;
2117
2118         for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) {
2119                 for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) {
2120                         for (thread_no = 0; thread_no <
2121                                 topo.num_threads_per_core; ++thread_no) {
2122                                 struct thread_data *t, *t2;
2123                                 struct core_data *c, *c2;
2124                                 struct pkg_data *p, *p2;
2125
2126                                 t = GET_THREAD(thread_base, thread_no, core_no, pkg_no);
2127
2128                                 if (cpu_is_not_present(t->cpu_id))
2129                                         continue;
2130
2131                                 t2 = GET_THREAD(thread_base2, thread_no, core_no, pkg_no);
2132
2133                                 c = GET_CORE(core_base, core_no, pkg_no);
2134                                 c2 = GET_CORE(core_base2, core_no, pkg_no);
2135
2136                                 p = GET_PKG(pkg_base, pkg_no);
2137                                 p2 = GET_PKG(pkg_base2, pkg_no);
2138
2139                                 retval = func(t, c, p, t2, c2, p2);
2140                                 if (retval)
2141                                         return retval;
2142                         }
2143                 }
2144         }
2145         return 0;
2146 }
2147
2148 /*
2149  * run func(cpu) on every cpu in /proc/stat
2150  * return max_cpu number
2151  */
2152 int for_all_proc_cpus(int (func)(int))
2153 {
2154         FILE *fp;
2155         int cpu_num;
2156         int retval;
2157
2158         fp = fopen_or_die(proc_stat, "r");
2159
2160         retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n");
2161         if (retval != 0)
2162                 err(1, "%s: failed to parse format", proc_stat);
2163
2164         while (1) {
2165                 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num);
2166                 if (retval != 1)
2167                         break;
2168
2169                 retval = func(cpu_num);
2170                 if (retval) {
2171                         fclose(fp);
2172                         return(retval);
2173                 }
2174         }
2175         fclose(fp);
2176         return 0;
2177 }
2178
2179 void re_initialize(void)
2180 {
2181         free_all_buffers();
2182         setup_all_buffers();
2183         printf("turbostat: re-initialized with num_cpus %d\n", topo.num_cpus);
2184 }
2185
2186
2187 /*
2188  * count_cpus()
2189  * remember the last one seen, it will be the max
2190  */
2191 int count_cpus(int cpu)
2192 {
2193         if (topo.max_cpu_num < cpu)
2194                 topo.max_cpu_num = cpu;
2195
2196         topo.num_cpus += 1;
2197         return 0;
2198 }
2199 int mark_cpu_present(int cpu)
2200 {
2201         CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set);
2202         return 0;
2203 }
2204
2205 /*
2206  * snapshot_proc_interrupts()
2207  *
2208  * read and record summary of /proc/interrupts
2209  *
2210  * return 1 if config change requires a restart, else return 0
2211  */
2212 int snapshot_proc_interrupts(void)
2213 {
2214         static FILE *fp;
2215         int column, retval;
2216
2217         if (fp == NULL)
2218                 fp = fopen_or_die("/proc/interrupts", "r");
2219         else
2220                 rewind(fp);
2221
2222         /* read 1st line of /proc/interrupts to get cpu* name for each column */
2223         for (column = 0; column < topo.num_cpus; ++column) {
2224                 int cpu_number;
2225
2226                 retval = fscanf(fp, " CPU%d", &cpu_number);
2227                 if (retval != 1)
2228                         break;
2229
2230                 if (cpu_number > topo.max_cpu_num) {
2231                         warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num);
2232                         return 1;
2233                 }
2234
2235                 irq_column_2_cpu[column] = cpu_number;
2236                 irqs_per_cpu[cpu_number] = 0;
2237         }
2238
2239         /* read /proc/interrupt count lines and sum up irqs per cpu */
2240         while (1) {
2241                 int column;
2242                 char buf[64];
2243
2244                 retval = fscanf(fp, " %s:", buf);       /* flush irq# "N:" */
2245                 if (retval != 1)
2246                         break;
2247
2248                 /* read the count per cpu */
2249                 for (column = 0; column < topo.num_cpus; ++column) {
2250
2251                         int cpu_number, irq_count;
2252
2253                         retval = fscanf(fp, " %d", &irq_count);
2254                         if (retval != 1)
2255                                 break;
2256
2257                         cpu_number = irq_column_2_cpu[column];
2258                         irqs_per_cpu[cpu_number] += irq_count;
2259
2260                 }
2261
2262                 while (getc(fp) != '\n')
2263                         ;       /* flush interrupt description */
2264
2265         }
2266         return 0;
2267 }
2268 /*
2269  * snapshot_gfx_rc6_ms()
2270  *
2271  * record snapshot of
2272  * /sys/class/drm/card0/power/rc6_residency_ms
2273  *
2274  * return 1 if config change requires a restart, else return 0
2275  */
2276 int snapshot_gfx_rc6_ms(void)
2277 {
2278         FILE *fp;
2279         int retval;
2280
2281         fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r");
2282
2283         retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms);
2284         if (retval != 1)
2285                 err(1, "GFX rc6");
2286
2287         fclose(fp);
2288
2289         return 0;
2290 }
2291 /*
2292  * snapshot_gfx_mhz()
2293  *
2294  * record snapshot of
2295  * /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz
2296  *
2297  * return 1 if config change requires a restart, else return 0
2298  */
2299 int snapshot_gfx_mhz(void)
2300 {
2301         static FILE *fp;
2302         int retval;
2303
2304         if (fp == NULL)
2305                 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r");
2306         else
2307                 rewind(fp);
2308
2309         retval = fscanf(fp, "%d", &gfx_cur_mhz);
2310         if (retval != 1)
2311                 err(1, "GFX MHz");
2312
2313         return 0;
2314 }
2315
2316 /*
2317  * snapshot /proc and /sys files
2318  *
2319  * return 1 if configuration restart needed, else return 0
2320  */
2321 int snapshot_proc_sysfs_files(void)
2322 {
2323         if (snapshot_proc_interrupts())
2324                 return 1;
2325
2326         if (DO_BIC(BIC_GFX_rc6))
2327                 snapshot_gfx_rc6_ms();
2328
2329         if (DO_BIC(BIC_GFXMHz))
2330                 snapshot_gfx_mhz();
2331
2332         return 0;
2333 }
2334
2335 void turbostat_loop()
2336 {
2337         int retval;
2338         int restarted = 0;
2339
2340 restart:
2341         restarted++;
2342
2343         snapshot_proc_sysfs_files();
2344         retval = for_all_cpus(get_counters, EVEN_COUNTERS);
2345         if (retval < -1) {
2346                 exit(retval);
2347         } else if (retval == -1) {
2348                 if (restarted > 1) {
2349                         exit(retval);
2350                 }
2351                 re_initialize();
2352                 goto restart;
2353         }
2354         restarted = 0;
2355         gettimeofday(&tv_even, (struct timezone *)NULL);
2356
2357         while (1) {
2358                 if (for_all_proc_cpus(cpu_is_not_present)) {
2359                         re_initialize();
2360                         goto restart;
2361                 }
2362                 nanosleep(&interval_ts, NULL);
2363                 if (snapshot_proc_sysfs_files())
2364                         goto restart;
2365                 retval = for_all_cpus(get_counters, ODD_COUNTERS);
2366                 if (retval < -1) {
2367                         exit(retval);
2368                 } else if (retval == -1) {
2369                         re_initialize();
2370                         goto restart;
2371                 }
2372                 gettimeofday(&tv_odd, (struct timezone *)NULL);
2373                 timersub(&tv_odd, &tv_even, &tv_delta);
2374                 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) {
2375                         re_initialize();
2376                         goto restart;
2377                 }
2378                 compute_average(EVEN_COUNTERS);
2379                 format_all_counters(EVEN_COUNTERS);
2380                 flush_output_stdout();
2381                 nanosleep(&interval_ts, NULL);
2382                 if (snapshot_proc_sysfs_files())
2383                         goto restart;
2384                 retval = for_all_cpus(get_counters, EVEN_COUNTERS);
2385                 if (retval < -1) {
2386                         exit(retval);
2387                 } else if (retval == -1) {
2388                         re_initialize();
2389                         goto restart;
2390                 }
2391                 gettimeofday(&tv_even, (struct timezone *)NULL);
2392                 timersub(&tv_even, &tv_odd, &tv_delta);
2393                 if (for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS)) {
2394                         re_initialize();
2395                         goto restart;
2396                 }
2397                 compute_average(ODD_COUNTERS);
2398                 format_all_counters(ODD_COUNTERS);
2399                 flush_output_stdout();
2400         }
2401 }
2402
2403 void check_dev_msr()
2404 {
2405         struct stat sb;
2406         char pathname[32];
2407
2408         sprintf(pathname, "/dev/cpu/%d/msr", base_cpu);
2409         if (stat(pathname, &sb))
2410                 if (system("/sbin/modprobe msr > /dev/null 2>&1"))
2411                         err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" ");
2412 }
2413
2414 void check_permissions()
2415 {
2416         struct __user_cap_header_struct cap_header_data;
2417         cap_user_header_t cap_header = &cap_header_data;
2418         struct __user_cap_data_struct cap_data_data;
2419         cap_user_data_t cap_data = &cap_data_data;
2420         extern int capget(cap_user_header_t hdrp, cap_user_data_t datap);
2421         int do_exit = 0;
2422         char pathname[32];
2423
2424         /* check for CAP_SYS_RAWIO */
2425         cap_header->pid = getpid();
2426         cap_header->version = _LINUX_CAPABILITY_VERSION;
2427         if (capget(cap_header, cap_data) < 0)
2428                 err(-6, "capget(2) failed");
2429
2430         if ((cap_data->effective & (1 << CAP_SYS_RAWIO)) == 0) {
2431                 do_exit++;
2432                 warnx("capget(CAP_SYS_RAWIO) failed,"
2433                         " try \"# setcap cap_sys_rawio=ep %s\"", progname);
2434         }
2435
2436         /* test file permissions */
2437         sprintf(pathname, "/dev/cpu/%d/msr", base_cpu);
2438         if (euidaccess(pathname, R_OK)) {
2439                 do_exit++;
2440                 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr");
2441         }
2442
2443         /* if all else fails, thell them to be root */
2444         if (do_exit)
2445                 if (getuid() != 0)
2446                         warnx("... or simply run as root");
2447
2448         if (do_exit)
2449                 exit(-6);
2450 }
2451
2452 /*
2453  * NHM adds support for additional MSRs:
2454  *
2455  * MSR_SMI_COUNT                   0x00000034
2456  *
2457  * MSR_PLATFORM_INFO               0x000000ce
2458  * MSR_PKG_CST_CONFIG_CONTROL     0x000000e2
2459  *
2460  * MSR_MISC_PWR_MGMT               0x000001aa
2461  *
2462  * MSR_PKG_C3_RESIDENCY            0x000003f8
2463  * MSR_PKG_C6_RESIDENCY            0x000003f9
2464  * MSR_CORE_C3_RESIDENCY           0x000003fc
2465  * MSR_CORE_C6_RESIDENCY           0x000003fd
2466  *
2467  * Side effect:
2468  * sets global pkg_cstate_limit to decode MSR_PKG_CST_CONFIG_CONTROL
2469  */
2470 int probe_nhm_msrs(unsigned int family, unsigned int model)
2471 {
2472         unsigned long long msr;
2473         unsigned int base_ratio;
2474         int *pkg_cstate_limits;
2475
2476         if (!genuine_intel)
2477                 return 0;
2478
2479         if (family != 6)
2480                 return 0;
2481
2482         bclk = discover_bclk(family, model);
2483
2484         switch (model) {
2485         case INTEL_FAM6_NEHALEM_EP:     /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */
2486         case INTEL_FAM6_NEHALEM:        /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */
2487         case 0x1F:      /* Core i7 and i5 Processor - Nehalem */
2488         case INTEL_FAM6_WESTMERE:       /* Westmere Client - Clarkdale, Arrandale */
2489         case INTEL_FAM6_WESTMERE_EP:    /* Westmere EP - Gulftown */
2490         case INTEL_FAM6_NEHALEM_EX:     /* Nehalem-EX Xeon - Beckton */
2491         case INTEL_FAM6_WESTMERE_EX:    /* Westmere-EX Xeon - Eagleton */
2492                 pkg_cstate_limits = nhm_pkg_cstate_limits;
2493                 break;
2494         case INTEL_FAM6_SANDYBRIDGE:    /* SNB */
2495         case INTEL_FAM6_SANDYBRIDGE_X:  /* SNB Xeon */
2496         case INTEL_FAM6_IVYBRIDGE:      /* IVB */
2497         case INTEL_FAM6_IVYBRIDGE_X:    /* IVB Xeon */
2498                 pkg_cstate_limits = snb_pkg_cstate_limits;
2499                 break;
2500         case INTEL_FAM6_HASWELL_CORE:   /* HSW */
2501         case INTEL_FAM6_HASWELL_X:      /* HSX */
2502         case INTEL_FAM6_HASWELL_ULT:    /* HSW */
2503         case INTEL_FAM6_HASWELL_GT3E:   /* HSW */
2504         case INTEL_FAM6_BROADWELL_CORE: /* BDW */
2505         case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
2506         case INTEL_FAM6_BROADWELL_X:    /* BDX */
2507         case INTEL_FAM6_BROADWELL_XEON_D:       /* BDX-DE */
2508         case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
2509         case INTEL_FAM6_SKYLAKE_DESKTOP:        /* SKL */
2510         case INTEL_FAM6_KABYLAKE_MOBILE:        /* KBL */
2511         case INTEL_FAM6_KABYLAKE_DESKTOP:       /* KBL */
2512                 pkg_cstate_limits = hsw_pkg_cstate_limits;
2513                 break;
2514         case INTEL_FAM6_SKYLAKE_X:      /* SKX */
2515                 pkg_cstate_limits = skx_pkg_cstate_limits;
2516                 break;
2517         case INTEL_FAM6_ATOM_SILVERMONT1:       /* BYT */
2518                 no_MSR_MISC_PWR_MGMT = 1;
2519         case INTEL_FAM6_ATOM_SILVERMONT2:       /* AVN */
2520                 pkg_cstate_limits = slv_pkg_cstate_limits;
2521                 break;
2522         case INTEL_FAM6_ATOM_AIRMONT:   /* AMT */
2523                 pkg_cstate_limits = amt_pkg_cstate_limits;
2524                 no_MSR_MISC_PWR_MGMT = 1;
2525                 break;
2526         case INTEL_FAM6_XEON_PHI_KNL:   /* PHI */
2527         case INTEL_FAM6_XEON_PHI_KNM:
2528                 pkg_cstate_limits = phi_pkg_cstate_limits;
2529                 break;
2530         case INTEL_FAM6_ATOM_GOLDMONT:  /* BXT */
2531         case INTEL_FAM6_ATOM_DENVERTON: /* DNV */
2532                 pkg_cstate_limits = bxt_pkg_cstate_limits;
2533                 break;
2534         default:
2535                 return 0;
2536         }
2537         get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr);
2538         pkg_cstate_limit = pkg_cstate_limits[msr & 0xF];
2539
2540         get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
2541         base_ratio = (msr >> 8) & 0xFF;
2542
2543         base_hz = base_ratio * bclk * 1000000;
2544         has_base_hz = 1;
2545         return 1;
2546 }
2547 /*
2548  * SLV client has supporet for unique MSRs:
2549  *
2550  * MSR_CC6_DEMOTION_POLICY_CONFIG
2551  * MSR_MC6_DEMOTION_POLICY_CONFIG
2552  */
2553
2554 int has_slv_msrs(unsigned int family, unsigned int model)
2555 {
2556         if (!genuine_intel)
2557                 return 0;
2558
2559         switch (model) {
2560         case INTEL_FAM6_ATOM_SILVERMONT1:
2561         case INTEL_FAM6_ATOM_MERRIFIELD:
2562         case INTEL_FAM6_ATOM_MOOREFIELD:
2563                 return 1;
2564         }
2565         return 0;
2566 }
2567
2568 int has_nhm_turbo_ratio_limit(unsigned int family, unsigned int model)
2569 {
2570         if (has_slv_msrs(family, model))
2571                 return 0;
2572
2573         switch (model) {
2574         /* Nehalem compatible, but do not include turbo-ratio limit support */
2575         case INTEL_FAM6_NEHALEM_EX:     /* Nehalem-EX Xeon - Beckton */
2576         case INTEL_FAM6_WESTMERE_EX:    /* Westmere-EX Xeon - Eagleton */
2577         case INTEL_FAM6_XEON_PHI_KNL:   /* PHI - Knights Landing (different MSR definition) */
2578         case INTEL_FAM6_XEON_PHI_KNM:
2579                 return 0;
2580         default:
2581                 return 1;
2582         }
2583 }
2584 int has_atom_turbo_ratio_limit(unsigned int family, unsigned int model)
2585 {
2586         if (has_slv_msrs(family, model))
2587                 return 1;
2588
2589         return 0;
2590 }
2591 int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model)
2592 {
2593         if (!genuine_intel)
2594                 return 0;
2595
2596         if (family != 6)
2597                 return 0;
2598
2599         switch (model) {
2600         case INTEL_FAM6_IVYBRIDGE_X:    /* IVB Xeon */
2601         case INTEL_FAM6_HASWELL_X:      /* HSW Xeon */
2602                 return 1;
2603         default:
2604                 return 0;
2605         }
2606 }
2607 int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model)
2608 {
2609         if (!genuine_intel)
2610                 return 0;
2611
2612         if (family != 6)
2613                 return 0;
2614
2615         switch (model) {
2616         case INTEL_FAM6_HASWELL_X:      /* HSW Xeon */
2617                 return 1;
2618         default:
2619                 return 0;
2620         }
2621 }
2622
2623 int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model)
2624 {
2625         if (!genuine_intel)
2626                 return 0;
2627
2628         if (family != 6)
2629                 return 0;
2630
2631         switch (model) {
2632         case INTEL_FAM6_XEON_PHI_KNL:   /* Knights Landing */
2633         case INTEL_FAM6_XEON_PHI_KNM:
2634                 return 1;
2635         default:
2636                 return 0;
2637         }
2638 }
2639 int has_config_tdp(unsigned int family, unsigned int model)
2640 {
2641         if (!genuine_intel)
2642                 return 0;
2643
2644         if (family != 6)
2645                 return 0;
2646
2647         switch (model) {
2648         case INTEL_FAM6_IVYBRIDGE:      /* IVB */
2649         case INTEL_FAM6_HASWELL_CORE:   /* HSW */
2650         case INTEL_FAM6_HASWELL_X:      /* HSX */
2651         case INTEL_FAM6_HASWELL_ULT:    /* HSW */
2652         case INTEL_FAM6_HASWELL_GT3E:   /* HSW */
2653         case INTEL_FAM6_BROADWELL_CORE: /* BDW */
2654         case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
2655         case INTEL_FAM6_BROADWELL_X:    /* BDX */
2656         case INTEL_FAM6_BROADWELL_XEON_D:       /* BDX-DE */
2657         case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
2658         case INTEL_FAM6_SKYLAKE_DESKTOP:        /* SKL */
2659         case INTEL_FAM6_KABYLAKE_MOBILE:        /* KBL */
2660         case INTEL_FAM6_KABYLAKE_DESKTOP:       /* KBL */
2661         case INTEL_FAM6_SKYLAKE_X:      /* SKX */
2662
2663         case INTEL_FAM6_XEON_PHI_KNL:   /* Knights Landing */
2664         case INTEL_FAM6_XEON_PHI_KNM:
2665                 return 1;
2666         default:
2667                 return 0;
2668         }
2669 }
2670
2671 static void
2672 dump_cstate_pstate_config_info(unsigned int family, unsigned int model)
2673 {
2674         if (!do_nhm_platform_info)
2675                 return;
2676
2677         dump_nhm_platform_info();
2678
2679         if (has_hsw_turbo_ratio_limit(family, model))
2680                 dump_hsw_turbo_ratio_limits();
2681
2682         if (has_ivt_turbo_ratio_limit(family, model))
2683                 dump_ivt_turbo_ratio_limits();
2684
2685         if (has_nhm_turbo_ratio_limit(family, model))
2686                 dump_nhm_turbo_ratio_limits();
2687
2688         if (has_atom_turbo_ratio_limit(family, model))
2689                 dump_atom_turbo_ratio_limits();
2690
2691         if (has_knl_turbo_ratio_limit(family, model))
2692                 dump_knl_turbo_ratio_limits();
2693
2694         if (has_config_tdp(family, model))
2695                 dump_config_tdp();
2696
2697         dump_nhm_cst_cfg();
2698 }
2699
2700
2701 /*
2702  * print_epb()
2703  * Decode the ENERGY_PERF_BIAS MSR
2704  */
2705 int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2706 {
2707         unsigned long long msr;
2708         char *epb_string;
2709         int cpu;
2710
2711         if (!has_epb)
2712                 return 0;
2713
2714         cpu = t->cpu_id;
2715
2716         /* EPB is per-package */
2717         if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
2718                 return 0;
2719
2720         if (cpu_migrate(cpu)) {
2721                 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
2722                 return -1;
2723         }
2724
2725         if (get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr))
2726                 return 0;
2727
2728         switch (msr & 0xF) {
2729         case ENERGY_PERF_BIAS_PERFORMANCE:
2730                 epb_string = "performance";
2731                 break;
2732         case ENERGY_PERF_BIAS_NORMAL:
2733                 epb_string = "balanced";
2734                 break;
2735         case ENERGY_PERF_BIAS_POWERSAVE:
2736                 epb_string = "powersave";
2737                 break;
2738         default:
2739                 epb_string = "custom";
2740                 break;
2741         }
2742         fprintf(outf, "cpu%d: MSR_IA32_ENERGY_PERF_BIAS: 0x%08llx (%s)\n", cpu, msr, epb_string);
2743
2744         return 0;
2745 }
2746 /*
2747  * print_hwp()
2748  * Decode the MSR_HWP_CAPABILITIES
2749  */
2750 int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2751 {
2752         unsigned long long msr;
2753         int cpu;
2754
2755         if (!has_hwp)
2756                 return 0;
2757
2758         cpu = t->cpu_id;
2759
2760         /* MSR_HWP_CAPABILITIES is per-package */
2761         if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
2762                 return 0;
2763
2764         if (cpu_migrate(cpu)) {
2765                 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
2766                 return -1;
2767         }
2768
2769         if (get_msr(cpu, MSR_PM_ENABLE, &msr))
2770                 return 0;
2771
2772         fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n",
2773                 cpu, msr, (msr & (1 << 0)) ? "" : "No-");
2774
2775         /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */
2776         if ((msr & (1 << 0)) == 0)
2777                 return 0;
2778
2779         if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr))
2780                 return 0;
2781
2782         fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx "
2783                         "(high 0x%x guar 0x%x eff 0x%x low 0x%x)\n",
2784                         cpu, msr,
2785                         (unsigned int)HWP_HIGHEST_PERF(msr),
2786                         (unsigned int)HWP_GUARANTEED_PERF(msr),
2787                         (unsigned int)HWP_MOSTEFFICIENT_PERF(msr),
2788                         (unsigned int)HWP_LOWEST_PERF(msr));
2789
2790         if (get_msr(cpu, MSR_HWP_REQUEST, &msr))
2791                 return 0;
2792
2793         fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx "
2794                         "(min 0x%x max 0x%x des 0x%x epp 0x%x window 0x%x pkg 0x%x)\n",
2795                         cpu, msr,
2796                         (unsigned int)(((msr) >> 0) & 0xff),
2797                         (unsigned int)(((msr) >> 8) & 0xff),
2798                         (unsigned int)(((msr) >> 16) & 0xff),
2799                         (unsigned int)(((msr) >> 24) & 0xff),
2800                         (unsigned int)(((msr) >> 32) & 0xff3),
2801                         (unsigned int)(((msr) >> 42) & 0x1));
2802
2803         if (has_hwp_pkg) {
2804                 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr))
2805                         return 0;
2806
2807                 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx "
2808                         "(min 0x%x max 0x%x des 0x%x epp 0x%x window 0x%x)\n",
2809                         cpu, msr,
2810                         (unsigned int)(((msr) >> 0) & 0xff),
2811                         (unsigned int)(((msr) >> 8) & 0xff),
2812                         (unsigned int)(((msr) >> 16) & 0xff),
2813                         (unsigned int)(((msr) >> 24) & 0xff),
2814                         (unsigned int)(((msr) >> 32) & 0xff3));
2815         }
2816         if (has_hwp_notify) {
2817                 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr))
2818                         return 0;
2819
2820                 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx "
2821                         "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n",
2822                         cpu, msr,
2823                         ((msr) & 0x1) ? "EN" : "Dis",
2824                         ((msr) & 0x2) ? "EN" : "Dis");
2825         }
2826         if (get_msr(cpu, MSR_HWP_STATUS, &msr))
2827                 return 0;
2828
2829         fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx "
2830                         "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n",
2831                         cpu, msr,
2832                         ((msr) & 0x1) ? "" : "No-",
2833                         ((msr) & 0x2) ? "" : "No-");
2834
2835         return 0;
2836 }
2837
2838 /*
2839  * print_perf_limit()
2840  */
2841 int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2842 {
2843         unsigned long long msr;
2844         int cpu;
2845
2846         cpu = t->cpu_id;
2847
2848         /* per-package */
2849         if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
2850                 return 0;
2851
2852         if (cpu_migrate(cpu)) {
2853                 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
2854                 return -1;
2855         }
2856
2857         if (do_core_perf_limit_reasons) {
2858                 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr);
2859                 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
2860                 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)",
2861                         (msr & 1 << 15) ? "bit15, " : "",
2862                         (msr & 1 << 14) ? "bit14, " : "",
2863                         (msr & 1 << 13) ? "Transitions, " : "",
2864                         (msr & 1 << 12) ? "MultiCoreTurbo, " : "",
2865                         (msr & 1 << 11) ? "PkgPwrL2, " : "",
2866                         (msr & 1 << 10) ? "PkgPwrL1, " : "",
2867                         (msr & 1 << 9) ? "CorePwr, " : "",
2868                         (msr & 1 << 8) ? "Amps, " : "",
2869                         (msr & 1 << 6) ? "VR-Therm, " : "",
2870                         (msr & 1 << 5) ? "Auto-HWP, " : "",
2871                         (msr & 1 << 4) ? "Graphics, " : "",
2872                         (msr & 1 << 2) ? "bit2, " : "",
2873                         (msr & 1 << 1) ? "ThermStatus, " : "",
2874                         (msr & 1 << 0) ? "PROCHOT, " : "");
2875                 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n",
2876                         (msr & 1 << 31) ? "bit31, " : "",
2877                         (msr & 1 << 30) ? "bit30, " : "",
2878                         (msr & 1 << 29) ? "Transitions, " : "",
2879                         (msr & 1 << 28) ? "MultiCoreTurbo, " : "",
2880                         (msr & 1 << 27) ? "PkgPwrL2, " : "",
2881                         (msr & 1 << 26) ? "PkgPwrL1, " : "",
2882                         (msr & 1 << 25) ? "CorePwr, " : "",
2883                         (msr & 1 << 24) ? "Amps, " : "",
2884                         (msr & 1 << 22) ? "VR-Therm, " : "",
2885                         (msr & 1 << 21) ? "Auto-HWP, " : "",
2886                         (msr & 1 << 20) ? "Graphics, " : "",
2887                         (msr & 1 << 18) ? "bit18, " : "",
2888                         (msr & 1 << 17) ? "ThermStatus, " : "",
2889                         (msr & 1 << 16) ? "PROCHOT, " : "");
2890
2891         }
2892         if (do_gfx_perf_limit_reasons) {
2893                 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr);
2894                 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
2895                 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)",
2896                         (msr & 1 << 0) ? "PROCHOT, " : "",
2897                         (msr & 1 << 1) ? "ThermStatus, " : "",
2898                         (msr & 1 << 4) ? "Graphics, " : "",
2899                         (msr & 1 << 6) ? "VR-Therm, " : "",
2900                         (msr & 1 << 8) ? "Amps, " : "",
2901                         (msr & 1 << 9) ? "GFXPwr, " : "",
2902                         (msr & 1 << 10) ? "PkgPwrL1, " : "",
2903                         (msr & 1 << 11) ? "PkgPwrL2, " : "");
2904                 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n",
2905                         (msr & 1 << 16) ? "PROCHOT, " : "",
2906                         (msr & 1 << 17) ? "ThermStatus, " : "",
2907                         (msr & 1 << 20) ? "Graphics, " : "",
2908                         (msr & 1 << 22) ? "VR-Therm, " : "",
2909                         (msr & 1 << 24) ? "Amps, " : "",
2910                         (msr & 1 << 25) ? "GFXPwr, " : "",
2911                         (msr & 1 << 26) ? "PkgPwrL1, " : "",
2912                         (msr & 1 << 27) ? "PkgPwrL2, " : "");
2913         }
2914         if (do_ring_perf_limit_reasons) {
2915                 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr);
2916                 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
2917                 fprintf(outf, " (Active: %s%s%s%s%s%s)",
2918                         (msr & 1 << 0) ? "PROCHOT, " : "",
2919                         (msr & 1 << 1) ? "ThermStatus, " : "",
2920                         (msr & 1 << 6) ? "VR-Therm, " : "",
2921                         (msr & 1 << 8) ? "Amps, " : "",
2922                         (msr & 1 << 10) ? "PkgPwrL1, " : "",
2923                         (msr & 1 << 11) ? "PkgPwrL2, " : "");
2924                 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n",
2925                         (msr & 1 << 16) ? "PROCHOT, " : "",
2926                         (msr & 1 << 17) ? "ThermStatus, " : "",
2927                         (msr & 1 << 22) ? "VR-Therm, " : "",
2928                         (msr & 1 << 24) ? "Amps, " : "",
2929                         (msr & 1 << 26) ? "PkgPwrL1, " : "",
2930                         (msr & 1 << 27) ? "PkgPwrL2, " : "");
2931         }
2932         return 0;
2933 }
2934
2935 #define RAPL_POWER_GRANULARITY  0x7FFF  /* 15 bit power granularity */
2936 #define RAPL_TIME_GRANULARITY   0x3F /* 6 bit time granularity */
2937
2938 double get_tdp(unsigned int model)
2939 {
2940         unsigned long long msr;
2941
2942         if (do_rapl & RAPL_PKG_POWER_INFO)
2943                 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr))
2944                         return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units;
2945
2946         switch (model) {
2947         case INTEL_FAM6_ATOM_SILVERMONT1:
2948         case INTEL_FAM6_ATOM_SILVERMONT2:
2949                 return 30.0;
2950         default:
2951                 return 135.0;
2952         }
2953 }
2954
2955 /*
2956  * rapl_dram_energy_units_probe()
2957  * Energy units are either hard-coded, or come from RAPL Energy Unit MSR.
2958  */
2959 static double
2960 rapl_dram_energy_units_probe(int  model, double rapl_energy_units)
2961 {
2962         /* only called for genuine_intel, family 6 */
2963
2964         switch (model) {
2965         case INTEL_FAM6_HASWELL_X:      /* HSX */
2966         case INTEL_FAM6_BROADWELL_X:    /* BDX */
2967         case INTEL_FAM6_BROADWELL_XEON_D:       /* BDX-DE */
2968         case INTEL_FAM6_XEON_PHI_KNL:   /* KNL */
2969         case INTEL_FAM6_XEON_PHI_KNM:
2970                 return (rapl_dram_energy_units = 15.3 / 1000000);
2971         default:
2972                 return (rapl_energy_units);
2973         }
2974 }
2975
2976
2977 /*
2978  * rapl_probe()
2979  *
2980  * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units
2981  */
2982 void rapl_probe(unsigned int family, unsigned int model)
2983 {
2984         unsigned long long msr;
2985         unsigned int time_unit;
2986         double tdp;
2987
2988         if (!genuine_intel)
2989                 return;
2990
2991         if (family != 6)
2992                 return;
2993
2994         switch (model) {
2995         case INTEL_FAM6_SANDYBRIDGE:
2996         case INTEL_FAM6_IVYBRIDGE:
2997         case INTEL_FAM6_HASWELL_CORE:   /* HSW */
2998         case INTEL_FAM6_HASWELL_ULT:    /* HSW */
2999         case INTEL_FAM6_HASWELL_GT3E:   /* HSW */
3000         case INTEL_FAM6_BROADWELL_CORE: /* BDW */
3001         case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
3002                 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO;
3003                 if (rapl_joules) {
3004                         BIC_PRESENT(BIC_Pkg_J);
3005                         BIC_PRESENT(BIC_Cor_J);
3006                         BIC_PRESENT(BIC_GFX_J);
3007                 } else {
3008                         BIC_PRESENT(BIC_PkgWatt);
3009                         BIC_PRESENT(BIC_CorWatt);
3010                         BIC_PRESENT(BIC_GFXWatt);
3011                 }
3012                 break;
3013         case INTEL_FAM6_ATOM_GOLDMONT:  /* BXT */
3014                 do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO;
3015                 if (rapl_joules)
3016                         BIC_PRESENT(BIC_Pkg_J);
3017                 else
3018                         BIC_PRESENT(BIC_PkgWatt);
3019                 break;
3020         case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
3021         case INTEL_FAM6_SKYLAKE_DESKTOP:        /* SKL */
3022         case INTEL_FAM6_KABYLAKE_MOBILE:        /* KBL */
3023         case INTEL_FAM6_KABYLAKE_DESKTOP:       /* KBL */
3024                 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO;
3025                 BIC_PRESENT(BIC_PKG__);
3026                 BIC_PRESENT(BIC_RAM__);
3027                 if (rapl_joules) {
3028                         BIC_PRESENT(BIC_Pkg_J);
3029                         BIC_PRESENT(BIC_Cor_J);
3030                         BIC_PRESENT(BIC_RAM_J);
3031                 } else {
3032                         BIC_PRESENT(BIC_PkgWatt);
3033                         BIC_PRESENT(BIC_CorWatt);
3034                         BIC_PRESENT(BIC_RAMWatt);
3035                 }
3036                 break;
3037         case INTEL_FAM6_HASWELL_X:      /* HSX */
3038         case INTEL_FAM6_BROADWELL_X:    /* BDX */
3039         case INTEL_FAM6_BROADWELL_XEON_D:       /* BDX-DE */
3040         case INTEL_FAM6_SKYLAKE_X:      /* SKX */
3041         case INTEL_FAM6_XEON_PHI_KNL:   /* KNL */
3042         case INTEL_FAM6_XEON_PHI_KNM:
3043                 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO;
3044                 BIC_PRESENT(BIC_PKG__);
3045                 BIC_PRESENT(BIC_RAM__);
3046                 if (rapl_joules) {
3047                         BIC_PRESENT(BIC_Pkg_J);
3048                         BIC_PRESENT(BIC_RAM_J);
3049                 } else {
3050                         BIC_PRESENT(BIC_PkgWatt);
3051                         BIC_PRESENT(BIC_RAMWatt);
3052                 }
3053                 break;
3054         case INTEL_FAM6_SANDYBRIDGE_X:
3055         case INTEL_FAM6_IVYBRIDGE_X:
3056                 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO;
3057                 BIC_PRESENT(BIC_PKG__);
3058                 BIC_PRESENT(BIC_RAM__);
3059                 if (rapl_joules) {
3060                         BIC_PRESENT(BIC_Pkg_J);
3061                         BIC_PRESENT(BIC_Cor_J);
3062                         BIC_PRESENT(BIC_RAM_J);
3063                 } else {
3064                         BIC_PRESENT(BIC_PkgWatt);
3065                         BIC_PRESENT(BIC_CorWatt);
3066                         BIC_PRESENT(BIC_RAMWatt);
3067                 }
3068                 break;
3069         case INTEL_FAM6_ATOM_SILVERMONT1:       /* BYT */
3070         case INTEL_FAM6_ATOM_SILVERMONT2:       /* AVN */
3071                 do_rapl = RAPL_PKG | RAPL_CORES;
3072                 if (rapl_joules) {
3073                         BIC_PRESENT(BIC_Pkg_J);
3074                         BIC_PRESENT(BIC_Cor_J);
3075                 } else {
3076                         BIC_PRESENT(BIC_PkgWatt);
3077                         BIC_PRESENT(BIC_CorWatt);
3078                 }
3079                 break;
3080         case INTEL_FAM6_ATOM_DENVERTON: /* DNV */
3081                 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS;
3082                 BIC_PRESENT(BIC_PKG__);
3083                 BIC_PRESENT(BIC_RAM__);
3084                 if (rapl_joules) {
3085                         BIC_PRESENT(BIC_Pkg_J);
3086                         BIC_PRESENT(BIC_Cor_J);
3087                         BIC_PRESENT(BIC_RAM_J);
3088                 } else {
3089                         BIC_PRESENT(BIC_PkgWatt);
3090                         BIC_PRESENT(BIC_CorWatt);
3091                         BIC_PRESENT(BIC_RAMWatt);
3092                 }
3093                 break;
3094         default:
3095                 return;
3096         }
3097
3098         /* units on package 0, verify later other packages match */
3099         if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr))
3100                 return;
3101
3102         rapl_power_units = 1.0 / (1 << (msr & 0xF));
3103         if (model == INTEL_FAM6_ATOM_SILVERMONT1)
3104                 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000;
3105         else
3106                 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F));
3107
3108         rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units);
3109
3110         time_unit = msr >> 16 & 0xF;
3111         if (time_unit == 0)
3112                 time_unit = 0xA;
3113
3114         rapl_time_units = 1.0 / (1 << (time_unit));
3115
3116         tdp = get_tdp(model);
3117
3118         rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp;
3119         if (debug)
3120                 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp);
3121
3122         return;
3123 }
3124
3125 void perf_limit_reasons_probe(unsigned int family, unsigned int model)
3126 {
3127         if (!genuine_intel)
3128                 return;
3129
3130         if (family != 6)
3131                 return;
3132
3133         switch (model) {
3134         case INTEL_FAM6_HASWELL_CORE:   /* HSW */
3135         case INTEL_FAM6_HASWELL_ULT:    /* HSW */
3136         case INTEL_FAM6_HASWELL_GT3E:   /* HSW */
3137                 do_gfx_perf_limit_reasons = 1;
3138         case INTEL_FAM6_HASWELL_X:      /* HSX */
3139                 do_core_perf_limit_reasons = 1;
3140                 do_ring_perf_limit_reasons = 1;
3141         default:
3142                 return;
3143         }
3144 }
3145
3146 int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p)
3147 {
3148         unsigned long long msr;
3149         unsigned int dts;
3150         int cpu;
3151
3152         if (!(do_dts || do_ptm))
3153                 return 0;
3154
3155         cpu = t->cpu_id;
3156
3157         /* DTS is per-core, no need to print for each thread */
3158         if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
3159                 return 0;
3160
3161         if (cpu_migrate(cpu)) {
3162                 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
3163                 return -1;
3164         }
3165
3166         if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) {
3167                 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
3168                         return 0;
3169
3170                 dts = (msr >> 16) & 0x7F;
3171                 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n",
3172                         cpu, msr, tcc_activation_temp - dts);
3173
3174 #ifdef  THERM_DEBUG
3175                 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr))
3176                         return 0;
3177
3178                 dts = (msr >> 16) & 0x7F;
3179                 dts2 = (msr >> 8) & 0x7F;
3180                 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
3181                         cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2);
3182 #endif
3183         }
3184
3185
3186         if (do_dts) {
3187                 unsigned int resolution;
3188
3189                 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
3190                         return 0;
3191
3192                 dts = (msr >> 16) & 0x7F;
3193                 resolution = (msr >> 27) & 0xF;
3194                 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n",
3195                         cpu, msr, tcc_activation_temp - dts, resolution);
3196
3197 #ifdef THERM_DEBUG
3198                 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr))
3199                         return 0;
3200
3201                 dts = (msr >> 16) & 0x7F;
3202                 dts2 = (msr >> 8) & 0x7F;
3203                 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
3204                         cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2);
3205 #endif
3206         }
3207
3208         return 0;
3209 }
3210
3211 void print_power_limit_msr(int cpu, unsigned long long msr, char *label)
3212 {
3213         fprintf(outf, "cpu%d: %s: %sabled (%f Watts, %f sec, clamp %sabled)\n",
3214                 cpu, label,
3215                 ((msr >> 15) & 1) ? "EN" : "DIS",
3216                 ((msr >> 0) & 0x7FFF) * rapl_power_units,
3217                 (1.0 + (((msr >> 22) & 0x3)/4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units,
3218                 (((msr >> 16) & 1) ? "EN" : "DIS"));
3219
3220         return;
3221 }
3222
3223 int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p)
3224 {
3225         unsigned long long msr;
3226         int cpu;
3227
3228         if (!do_rapl)
3229                 return 0;
3230
3231         /* RAPL counters are per package, so print only for 1st thread/package */
3232         if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
3233                 return 0;
3234
3235         cpu = t->cpu_id;
3236         if (cpu_migrate(cpu)) {
3237                 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
3238                 return -1;
3239         }
3240
3241         if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr))
3242                 return -1;
3243
3244         if (debug) {
3245                 fprintf(outf, "cpu%d: MSR_RAPL_POWER_UNIT: 0x%08llx "
3246                         "(%f Watts, %f Joules, %f sec.)\n", cpu, msr,
3247                         rapl_power_units, rapl_energy_units, rapl_time_units);
3248         }
3249         if (do_rapl & RAPL_PKG_POWER_INFO) {
3250
3251                 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr))
3252                         return -5;
3253
3254
3255                 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
3256                         cpu, msr,
3257                         ((msr >>  0) & RAPL_POWER_GRANULARITY) * rapl_power_units,
3258                         ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units,
3259                         ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units,
3260                         ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units);
3261
3262         }
3263         if (do_rapl & RAPL_PKG) {
3264
3265                 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr))
3266                         return -9;
3267
3268                 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n",
3269                         cpu, msr, (msr >> 63) & 1 ? "": "UN");
3270
3271                 print_power_limit_msr(cpu, msr, "PKG Limit #1");
3272                 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%f Watts, %f* sec, clamp %sabled)\n",
3273                         cpu,
3274                         ((msr >> 47) & 1) ? "EN" : "DIS",
3275                         ((msr >> 32) & 0x7FFF) * rapl_power_units,
3276                         (1.0 + (((msr >> 54) & 0x3)/4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units,
3277                         ((msr >> 48) & 1) ? "EN" : "DIS");
3278         }
3279
3280         if (do_rapl & RAPL_DRAM_POWER_INFO) {
3281                 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr))
3282                         return -6;
3283
3284                 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
3285                         cpu, msr,
3286                         ((msr >>  0) & RAPL_POWER_GRANULARITY) * rapl_power_units,
3287                         ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units,
3288                         ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units,
3289                         ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units);
3290         }
3291         if (do_rapl & RAPL_DRAM) {
3292                 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr))
3293                         return -9;
3294                 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n",
3295                                 cpu, msr, (msr >> 31) & 1 ? "": "UN");
3296
3297                 print_power_limit_msr(cpu, msr, "DRAM Limit");
3298         }
3299         if (do_rapl & RAPL_CORE_POLICY) {
3300                 if (debug) {
3301                         if (get_msr(cpu, MSR_PP0_POLICY, &msr))
3302                                 return -7;
3303
3304                         fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF);
3305                 }
3306         }
3307         if (do_rapl & RAPL_CORES_POWER_LIMIT) {
3308                 if (debug) {
3309                         if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr))
3310                                 return -9;
3311                         fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n",
3312                                         cpu, msr, (msr >> 31) & 1 ? "": "UN");
3313                         print_power_limit_msr(cpu, msr, "Cores Limit");
3314                 }
3315         }
3316         if (do_rapl & RAPL_GFX) {
3317                 if (debug) {
3318                         if (get_msr(cpu, MSR_PP1_POLICY, &msr))
3319                                 return -8;
3320
3321                         fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF);
3322
3323                         if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr))
3324                                 return -9;
3325                         fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n",
3326                                         cpu, msr, (msr >> 31) & 1 ? "": "UN");
3327                         print_power_limit_msr(cpu, msr, "GFX Limit");
3328                 }
3329         }
3330         return 0;
3331 }
3332
3333 /*
3334  * SNB adds support for additional MSRs:
3335  *
3336  * MSR_PKG_C7_RESIDENCY            0x000003fa
3337  * MSR_CORE_C7_RESIDENCY           0x000003fe
3338  * MSR_PKG_C2_RESIDENCY            0x0000060d
3339  */
3340
3341 int has_snb_msrs(unsigned int family, unsigned int model)
3342 {
3343         if (!genuine_intel)
3344                 return 0;
3345
3346         switch (model) {
3347         case INTEL_FAM6_SANDYBRIDGE:
3348         case INTEL_FAM6_SANDYBRIDGE_X:
3349         case INTEL_FAM6_IVYBRIDGE:      /* IVB */
3350         case INTEL_FAM6_IVYBRIDGE_X:    /* IVB Xeon */
3351         case INTEL_FAM6_HASWELL_CORE:   /* HSW */
3352         case INTEL_FAM6_HASWELL_X:      /* HSW */
3353         case INTEL_FAM6_HASWELL_ULT:    /* HSW */
3354         case INTEL_FAM6_HASWELL_GT3E:   /* HSW */
3355         case INTEL_FAM6_BROADWELL_CORE: /* BDW */
3356         case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
3357         case INTEL_FAM6_BROADWELL_X:    /* BDX */
3358         case INTEL_FAM6_BROADWELL_XEON_D:       /* BDX-DE */
3359         case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
3360         case INTEL_FAM6_SKYLAKE_DESKTOP:        /* SKL */
3361         case INTEL_FAM6_KABYLAKE_MOBILE:        /* KBL */
3362         case INTEL_FAM6_KABYLAKE_DESKTOP:       /* KBL */
3363         case INTEL_FAM6_SKYLAKE_X:      /* SKX */
3364         case INTEL_FAM6_ATOM_GOLDMONT:  /* BXT */
3365         case INTEL_FAM6_ATOM_DENVERTON: /* DNV */
3366                 return 1;
3367         }
3368         return 0;
3369 }
3370
3371 /*
3372  * HSW adds support for additional MSRs:
3373  *
3374  * MSR_PKG_C8_RESIDENCY         0x00000630
3375  * MSR_PKG_C9_RESIDENCY         0x00000631
3376  * MSR_PKG_C10_RESIDENCY        0x00000632
3377  *
3378  * MSR_PKGC8_IRTL               0x00000633
3379  * MSR_PKGC9_IRTL               0x00000634
3380  * MSR_PKGC10_IRTL              0x00000635
3381  *
3382  */
3383 int has_hsw_msrs(unsigned int family, unsigned int model)
3384 {
3385         if (!genuine_intel)
3386                 return 0;
3387
3388         switch (model) {
3389         case INTEL_FAM6_HASWELL_ULT:    /* HSW */
3390         case INTEL_FAM6_BROADWELL_CORE: /* BDW */
3391         case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
3392         case INTEL_FAM6_SKYLAKE_DESKTOP:        /* SKL */
3393         case INTEL_FAM6_KABYLAKE_MOBILE:        /* KBL */
3394         case INTEL_FAM6_KABYLAKE_DESKTOP:       /* KBL */
3395         case INTEL_FAM6_ATOM_GOLDMONT:  /* BXT */
3396                 return 1;
3397         }
3398         return 0;
3399 }
3400
3401 /*
3402  * SKL adds support for additional MSRS:
3403  *
3404  * MSR_PKG_WEIGHTED_CORE_C0_RES    0x00000658
3405  * MSR_PKG_ANY_CORE_C0_RES         0x00000659
3406  * MSR_PKG_ANY_GFXE_C0_RES         0x0000065A
3407  * MSR_PKG_BOTH_CORE_GFXE_C0_RES   0x0000065B
3408  */
3409 int has_skl_msrs(unsigned int family, unsigned int model)
3410 {
3411         if (!genuine_intel)
3412                 return 0;
3413
3414         switch (model) {
3415         case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
3416         case INTEL_FAM6_SKYLAKE_DESKTOP:        /* SKL */
3417         case INTEL_FAM6_KABYLAKE_MOBILE:        /* KBL */
3418         case INTEL_FAM6_KABYLAKE_DESKTOP:       /* KBL */
3419                 return 1;
3420         }
3421         return 0;
3422 }
3423
3424 int is_slm(unsigned int family, unsigned int model)
3425 {
3426         if (!genuine_intel)
3427                 return 0;
3428         switch (model) {
3429         case INTEL_FAM6_ATOM_SILVERMONT1:       /* BYT */
3430         case INTEL_FAM6_ATOM_SILVERMONT2:       /* AVN */
3431                 return 1;
3432         }
3433         return 0;
3434 }
3435
3436 int is_knl(unsigned int family, unsigned int model)
3437 {
3438         if (!genuine_intel)
3439                 return 0;
3440         switch (model) {
3441         case INTEL_FAM6_XEON_PHI_KNL:   /* KNL */
3442         case INTEL_FAM6_XEON_PHI_KNM:
3443                 return 1;
3444         }
3445         return 0;
3446 }
3447
3448 unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model)
3449 {
3450         if (is_knl(family, model))
3451                 return 1024;
3452         return 1;
3453 }
3454
3455 #define SLM_BCLK_FREQS 5
3456 double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0};
3457
3458 double slm_bclk(void)
3459 {
3460         unsigned long long msr = 3;
3461         unsigned int i;
3462         double freq;
3463
3464         if (get_msr(base_cpu, MSR_FSB_FREQ, &msr))
3465                 fprintf(outf, "SLM BCLK: unknown\n");
3466
3467         i = msr & 0xf;
3468         if (i >= SLM_BCLK_FREQS) {
3469                 fprintf(outf, "SLM BCLK[%d] invalid\n", i);
3470                 i = 3;
3471         }
3472         freq = slm_freq_table[i];
3473
3474         if (debug)
3475                 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq);
3476
3477         return freq;
3478 }
3479
3480 double discover_bclk(unsigned int family, unsigned int model)
3481 {
3482         if (has_snb_msrs(family, model) || is_knl(family, model))
3483                 return 100.00;
3484         else if (is_slm(family, model))
3485                 return slm_bclk();
3486         else
3487                 return 133.33;
3488 }
3489
3490 /*
3491  * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where
3492  * the Thermal Control Circuit (TCC) activates.
3493  * This is usually equal to tjMax.
3494  *
3495  * Older processors do not have this MSR, so there we guess,
3496  * but also allow cmdline over-ride with -T.
3497  *
3498  * Several MSR temperature values are in units of degrees-C
3499  * below this value, including the Digital Thermal Sensor (DTS),
3500  * Package Thermal Management Sensor (PTM), and thermal event thresholds.
3501  */
3502 int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p)
3503 {
3504         unsigned long long msr;
3505         unsigned int target_c_local;
3506         int cpu;
3507
3508         /* tcc_activation_temp is used only for dts or ptm */
3509         if (!(do_dts || do_ptm))
3510                 return 0;
3511
3512         /* this is a per-package concept */
3513         if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
3514                 return 0;
3515
3516         cpu = t->cpu_id;
3517         if (cpu_migrate(cpu)) {
3518                 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
3519                 return -1;
3520         }
3521
3522         if (tcc_activation_temp_override != 0) {
3523                 tcc_activation_temp = tcc_activation_temp_override;
3524                 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n",
3525                         cpu, tcc_activation_temp);
3526                 return 0;
3527         }
3528
3529         /* Temperature Target MSR is Nehalem and newer only */
3530         if (!do_nhm_platform_info)
3531                 goto guess;
3532
3533         if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr))
3534                 goto guess;
3535
3536         target_c_local = (msr >> 16) & 0xFF;
3537
3538         if (debug)
3539                 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n",
3540                         cpu, msr, target_c_local);
3541
3542         if (!target_c_local)
3543                 goto guess;
3544
3545         tcc_activation_temp = target_c_local;
3546
3547         return 0;
3548
3549 guess:
3550         tcc_activation_temp = TJMAX_DEFAULT;
3551         fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n",
3552                 cpu, tcc_activation_temp);
3553
3554         return 0;
3555 }
3556
3557 void decode_feature_control_msr(void)
3558 {
3559         unsigned long long msr;
3560
3561         if (!get_msr(base_cpu, MSR_IA32_FEATURE_CONTROL, &msr))
3562                 fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n",
3563                         base_cpu, msr,
3564                         msr & FEATURE_CONTROL_LOCKED ? "" : "UN-",
3565                         msr & (1 << 18) ? "SGX" : "");
3566 }
3567
3568 void decode_misc_enable_msr(void)
3569 {
3570         unsigned long long msr;
3571
3572         if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr))
3573                 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n",
3574                         base_cpu, msr,
3575                         msr & MSR_IA32_MISC_ENABLE_TM1 ? "" : "No-",
3576                         msr & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP ? "" : "No-",
3577                         msr & MSR_IA32_MISC_ENABLE_MWAIT ? "No-" : "",
3578                         msr & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE ? "No-" : "",
3579                         msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ? "No-" : "");
3580 }
3581
3582 /*
3583  * Decode MSR_MISC_PWR_MGMT
3584  *
3585  * Decode the bits according to the Nehalem documentation
3586  * bit[0] seems to continue to have same meaning going forward
3587  * bit[1] less so...
3588  */
3589 void decode_misc_pwr_mgmt_msr(void)
3590 {
3591         unsigned long long msr;
3592
3593         if (!do_nhm_platform_info)
3594                 return;
3595
3596         if (no_MSR_MISC_PWR_MGMT)
3597                 return;
3598
3599         if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr))
3600                 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n",
3601                         base_cpu, msr,
3602                         msr & (1 << 0) ? "DIS" : "EN",
3603                         msr & (1 << 1) ? "EN" : "DIS",
3604                         msr & (1 << 8) ? "EN" : "DIS");
3605 }
3606 /*
3607  * Decode MSR_CC6_DEMOTION_POLICY_CONFIG, MSR_MC6_DEMOTION_POLICY_CONFIG
3608  *
3609  * This MSRs are present on Silvermont processors,
3610  * Intel Atom processor E3000 series (Baytrail), and friends.
3611  */
3612 void decode_c6_demotion_policy_msr(void)
3613 {
3614         unsigned long long msr;
3615
3616         if (!get_msr(base_cpu, MSR_CC6_DEMOTION_POLICY_CONFIG, &msr))
3617                 fprintf(outf, "cpu%d: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-CC6-Demotion)\n",
3618                         base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS");
3619
3620         if (!get_msr(base_cpu, MSR_MC6_DEMOTION_POLICY_CONFIG, &msr))
3621                 fprintf(outf, "cpu%d: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-MC6-Demotion)\n",
3622                         base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS");
3623 }
3624
3625 void process_cpuid()
3626 {
3627         unsigned int eax, ebx, ecx, edx, max_level, max_extended_level;
3628         unsigned int fms, family, model, stepping;
3629
3630         eax = ebx = ecx = edx = 0;
3631
3632         __cpuid(0, max_level, ebx, ecx, edx);
3633
3634         if (ebx == 0x756e6547 && edx == 0x49656e69 && ecx == 0x6c65746e)
3635                 genuine_intel = 1;
3636
3637         if (debug)
3638                 fprintf(outf, "CPUID(0): %.4s%.4s%.4s ",
3639                         (char *)&ebx, (char *)&edx, (char *)&ecx);
3640
3641         __cpuid(1, fms, ebx, ecx, edx);
3642         family = (fms >> 8) & 0xf;
3643         model = (fms >> 4) & 0xf;
3644         stepping = fms & 0xf;
3645         if (family == 6 || family == 0xf)
3646                 model += ((fms >> 16) & 0xf) << 4;
3647
3648         if (debug) {
3649                 fprintf(outf, "%d CPUID levels; family:model:stepping 0x%x:%x:%x (%d:%d:%d)\n",
3650                         max_level, family, model, stepping, family, model, stepping);
3651                 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s\n",
3652                         ecx & (1 << 0) ? "SSE3" : "-",
3653                         ecx & (1 << 3) ? "MONITOR" : "-",
3654                         ecx & (1 << 6) ? "SMX" : "-",
3655                         ecx & (1 << 7) ? "EIST" : "-",
3656                         ecx & (1 << 8) ? "TM2" : "-",
3657                         edx & (1 << 4) ? "TSC" : "-",
3658                         edx & (1 << 5) ? "MSR" : "-",
3659                         edx & (1 << 22) ? "ACPI-TM" : "-",
3660                         edx & (1 << 29) ? "TM" : "-");
3661         }
3662
3663         if (!(edx & (1 << 5)))
3664                 errx(1, "CPUID: no MSR");
3665
3666         /*
3667          * check max extended function levels of CPUID.
3668          * This is needed to check for invariant TSC.
3669          * This check is valid for both Intel and AMD.
3670          */
3671         ebx = ecx = edx = 0;
3672         __cpuid(0x80000000, max_extended_level, ebx, ecx, edx);
3673
3674         if (max_extended_level >= 0x80000007) {
3675
3676                 /*
3677                  * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8
3678                  * this check is valid for both Intel and AMD
3679                  */
3680                 __cpuid(0x80000007, eax, ebx, ecx, edx);
3681                 has_invariant_tsc = edx & (1 << 8);
3682         }
3683
3684         /*
3685          * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0
3686          * this check is valid for both Intel and AMD
3687          */
3688
3689         __cpuid(0x6, eax, ebx, ecx, edx);
3690         has_aperf = ecx & (1 << 0);
3691         if (has_aperf) {
3692                 BIC_PRESENT(BIC_Avg_MHz);
3693                 BIC_PRESENT(BIC_Busy);
3694                 BIC_PRESENT(BIC_Bzy_MHz);
3695         }
3696         do_dts = eax & (1 << 0);
3697         if (do_dts)
3698                 BIC_PRESENT(BIC_CoreTmp);
3699         do_ptm = eax & (1 << 6);
3700         if (do_ptm)
3701                 BIC_PRESENT(BIC_PkgTmp);
3702         has_hwp = eax & (1 << 7);
3703         has_hwp_notify = eax & (1 << 8);
3704         has_hwp_activity_window = eax & (1 << 9);
3705         has_hwp_epp = eax & (1 << 10);
3706         has_hwp_pkg = eax & (1 << 11);
3707         has_epb = ecx & (1 << 3);
3708
3709         if (debug)
3710                 fprintf(outf, "CPUID(6): %sAPERF, %sDTS, %sPTM, %sHWP, "
3711                         "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n",
3712                         has_aperf ? "" : "No-",
3713                         do_dts ? "" : "No-",
3714                         do_ptm ? "" : "No-",
3715                         has_hwp ? "" : "No-",
3716                         has_hwp_notify ? "" : "No-",
3717                         has_hwp_activity_window ? "" : "No-",
3718                         has_hwp_epp ? "" : "No-",
3719                         has_hwp_pkg ? "" : "No-",
3720                         has_epb ? "" : "No-");
3721
3722         if (debug)
3723                 decode_misc_enable_msr();
3724
3725         if (max_level >= 0x7 && debug) {
3726                 int has_sgx;
3727
3728                 ecx = 0;
3729
3730                 __cpuid_count(0x7, 0, eax, ebx, ecx, edx);
3731
3732                 has_sgx = ebx & (1 << 2);
3733                 fprintf(outf, "CPUID(7): %sSGX\n", has_sgx ? "" : "No-");
3734
3735                 if (has_sgx)
3736                         decode_feature_control_msr();
3737         }
3738
3739         if (max_level >= 0x15) {
3740                 unsigned int eax_crystal;
3741                 unsigned int ebx_tsc;
3742
3743                 /*
3744                  * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz
3745                  */
3746                 eax_crystal = ebx_tsc = crystal_hz = edx = 0;
3747                 __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx);
3748
3749                 if (ebx_tsc != 0) {
3750
3751                         if (debug && (ebx != 0))
3752                                 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n",
3753                                         eax_crystal, ebx_tsc, crystal_hz);
3754
3755                         if (crystal_hz == 0)
3756                                 switch(model) {
3757                                 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
3758                                 case INTEL_FAM6_SKYLAKE_DESKTOP:        /* SKL */
3759                                 case INTEL_FAM6_KABYLAKE_MOBILE:        /* KBL */
3760                                 case INTEL_FAM6_KABYLAKE_DESKTOP:       /* KBL */
3761                                         crystal_hz = 24000000;  /* 24.0 MHz */
3762                                         break;
3763                                 case INTEL_FAM6_SKYLAKE_X:      /* SKX */
3764                                 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */
3765                                         crystal_hz = 25000000;  /* 25.0 MHz */
3766                                         break;
3767                                 case INTEL_FAM6_ATOM_GOLDMONT:  /* BXT */
3768                                         crystal_hz = 19200000;  /* 19.2 MHz */
3769                                         break;
3770                                 default:
3771                                         crystal_hz = 0;
3772                         }
3773
3774                         if (crystal_hz) {
3775                                 tsc_hz =  (unsigned long long) crystal_hz * ebx_tsc / eax_crystal;
3776                                 if (debug)
3777                                         fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n",
3778                                                 tsc_hz / 1000000, crystal_hz, ebx_tsc,  eax_crystal);
3779                         }
3780                 }
3781         }
3782         if (max_level >= 0x16) {
3783                 unsigned int base_mhz, max_mhz, bus_mhz, edx;
3784
3785                 /*
3786                  * CPUID 16H Base MHz, Max MHz, Bus MHz
3787                  */
3788                 base_mhz = max_mhz = bus_mhz = edx = 0;
3789
3790                 __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx);
3791                 if (debug)
3792                         fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n",
3793                                 base_mhz, max_mhz, bus_mhz);
3794         }
3795
3796         if (has_aperf)
3797                 aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model);
3798
3799         BIC_PRESENT(BIC_IRQ);
3800         BIC_PRESENT(BIC_TSC_MHz);
3801
3802         if (probe_nhm_msrs(family, model)) {
3803                 do_nhm_platform_info = 1;
3804                 BIC_PRESENT(BIC_CPU_c1);
3805                 BIC_PRESENT(BIC_CPU_c3);
3806                 BIC_PRESENT(BIC_CPU_c6);
3807                 BIC_PRESENT(BIC_SMI);
3808         }
3809         do_snb_cstates = has_snb_msrs(family, model);
3810
3811         if (do_snb_cstates)
3812                 BIC_PRESENT(BIC_CPU_c7);
3813
3814         do_irtl_snb = has_snb_msrs(family, model);
3815         do_pc2 = do_snb_cstates && (pkg_cstate_limit >= PCL__2);
3816         do_pc3 = (pkg_cstate_limit >= PCL__3);
3817         do_pc6 = (pkg_cstate_limit >= PCL__6);
3818         do_pc7 = do_snb_cstates && (pkg_cstate_limit >= PCL__7);
3819         if (has_slv_msrs(family, model)) {
3820                 do_pc2 = do_pc3 = do_pc7 = 0;
3821                 do_pc6 = 1;
3822                 BIC_PRESENT(BIC_Mod_c6);
3823                 use_c1_residency_msr = 1;
3824         }
3825         do_c8_c9_c10 = has_hsw_msrs(family, model);
3826         do_irtl_hsw = has_hsw_msrs(family, model);
3827         do_skl_residency = has_skl_msrs(family, model);
3828         do_slm_cstates = is_slm(family, model);
3829         do_knl_cstates  = is_knl(family, model);
3830
3831         if (debug)
3832                 decode_misc_pwr_mgmt_msr();
3833
3834         if (debug && has_slv_msrs(family, model))
3835                 decode_c6_demotion_policy_msr();
3836
3837         rapl_probe(family, model);
3838         perf_limit_reasons_probe(family, model);
3839
3840         if (debug)
3841                 dump_cstate_pstate_config_info(family, model);
3842
3843         if (has_skl_msrs(family, model))
3844                 calculate_tsc_tweak();
3845
3846         if (!access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK))
3847                 BIC_PRESENT(BIC_GFX_rc6);
3848
3849         if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK))
3850                 BIC_PRESENT(BIC_GFXMHz);
3851
3852         return;
3853 }
3854
3855 void help()
3856 {
3857         fprintf(outf,
3858         "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n"
3859         "\n"
3860         "Turbostat forks the specified COMMAND and prints statistics\n"
3861         "when COMMAND completes.\n"
3862         "If no COMMAND is specified, turbostat wakes every 5-seconds\n"
3863         "to print statistics, until interrupted.\n"
3864         "--add          add a counter\n"
3865         "               eg. --add msr0x10,u64,cpu,delta,MY_TSC\n"
3866         "--debug        run in \"debug\" mode\n"
3867         "--interval sec Override default 5-second measurement interval\n"
3868         "--help         print this help message\n"
3869         "--out file     create or truncate \"file\" for all output\n"
3870         "--version      print version information\n"
3871         "\n"
3872         "For more help, run \"man turbostat\"\n");
3873 }
3874
3875
3876 /*
3877  * in /dev/cpu/ return success for names that are numbers
3878  * ie. filter out ".", "..", "microcode".
3879  */
3880 int dir_filter(const struct dirent *dirp)
3881 {
3882         if (isdigit(dirp->d_name[0]))
3883                 return 1;
3884         else
3885                 return 0;
3886 }
3887
3888 int open_dev_cpu_msr(int dummy1)
3889 {
3890         return 0;
3891 }
3892
3893 void topology_probe()
3894 {
3895         int i;
3896         int max_core_id = 0;
3897         int max_package_id = 0;
3898         int max_siblings = 0;
3899         struct cpu_topology {
3900                 int core_id;
3901                 int physical_package_id;
3902         } *cpus;
3903
3904         /* Initialize num_cpus, max_cpu_num */
3905         topo.num_cpus = 0;
3906         topo.max_cpu_num = 0;
3907         for_all_proc_cpus(count_cpus);
3908         if (!summary_only && topo.num_cpus > 1)
3909                 BIC_PRESENT(BIC_CPU);
3910
3911         if (debug > 1)
3912                 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num);
3913
3914         cpus = calloc(1, (topo.max_cpu_num  + 1) * sizeof(struct cpu_topology));
3915         if (cpus == NULL)
3916                 err(1, "calloc cpus");
3917
3918         /*
3919          * Allocate and initialize cpu_present_set
3920          */
3921         cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1));
3922         if (cpu_present_set == NULL)
3923                 err(3, "CPU_ALLOC");
3924         cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
3925         CPU_ZERO_S(cpu_present_setsize, cpu_present_set);
3926         for_all_proc_cpus(mark_cpu_present);
3927
3928         /*
3929          * Allocate and initialize cpu_affinity_set
3930          */
3931         cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1));
3932         if (cpu_affinity_set == NULL)
3933                 err(3, "CPU_ALLOC");
3934         cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
3935         CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set);
3936
3937
3938         /*
3939          * For online cpus
3940          * find max_core_id, max_package_id
3941          */
3942         for (i = 0; i <= topo.max_cpu_num; ++i) {
3943                 int siblings;
3944
3945                 if (cpu_is_not_present(i)) {
3946                         if (debug > 1)
3947                                 fprintf(outf, "cpu%d NOT PRESENT\n", i);
3948                         continue;
3949                 }
3950                 cpus[i].core_id = get_core_id(i);
3951                 if (cpus[i].core_id > max_core_id)
3952                         max_core_id = cpus[i].core_id;
3953
3954                 cpus[i].physical_package_id = get_physical_package_id(i);
3955                 if (cpus[i].physical_package_id > max_package_id)
3956                         max_package_id = cpus[i].physical_package_id;
3957
3958                 siblings = get_num_ht_siblings(i);
3959                 if (siblings > max_siblings)
3960                         max_siblings = siblings;
3961                 if (debug > 1)
3962                         fprintf(outf, "cpu %d pkg %d core %d\n",
3963                                 i, cpus[i].physical_package_id, cpus[i].core_id);
3964         }
3965         topo.num_cores_per_pkg = max_core_id + 1;
3966         if (debug > 1)
3967                 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n",
3968                         max_core_id, topo.num_cores_per_pkg);
3969         if (debug && !summary_only && topo.num_cores_per_pkg > 1)
3970                 BIC_PRESENT(BIC_Core);
3971
3972         topo.num_packages = max_package_id + 1;
3973         if (debug > 1)
3974                 fprintf(outf, "max_package_id %d, sizing for %d packages\n",
3975                         max_package_id, topo.num_packages);
3976         if (debug && !summary_only && topo.num_packages > 1)
3977                 BIC_PRESENT(BIC_Package);
3978
3979         topo.num_threads_per_core = max_siblings;
3980         if (debug > 1)
3981                 fprintf(outf, "max_siblings %d\n", max_siblings);
3982
3983         free(cpus);
3984 }
3985
3986 void
3987 allocate_counters(struct thread_data **t, struct core_data **c, struct pkg_data **p)
3988 {
3989         int i;
3990
3991         *t = calloc(topo.num_threads_per_core * topo.num_cores_per_pkg *
3992                 topo.num_packages, sizeof(struct thread_data));
3993         if (*t == NULL)
3994                 goto error;
3995
3996         for (i = 0; i < topo.num_threads_per_core *
3997                 topo.num_cores_per_pkg * topo.num_packages; i++)
3998                 (*t)[i].cpu_id = -1;
3999
4000         *c = calloc(topo.num_cores_per_pkg * topo.num_packages,
4001                 sizeof(struct core_data));
4002         if (*c == NULL)
4003                 goto error;
4004
4005         for (i = 0; i < topo.num_cores_per_pkg * topo.num_packages; i++)
4006                 (*c)[i].core_id = -1;
4007
4008         *p = calloc(topo.num_packages, sizeof(struct pkg_data));
4009         if (*p == NULL)
4010                 goto error;
4011
4012         for (i = 0; i < topo.num_packages; i++)
4013                 (*p)[i].package_id = i;
4014
4015         return;
4016 error:
4017         err(1, "calloc counters");
4018 }
4019 /*
4020  * init_counter()
4021  *
4022  * set cpu_id, core_num, pkg_num
4023  * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE
4024  *
4025  * increment topo.num_cores when 1st core in pkg seen
4026  */
4027 void init_counter(struct thread_data *thread_base, struct core_data *core_base,
4028         struct pkg_data *pkg_base, int thread_num, int core_num,
4029         int pkg_num, int cpu_id)
4030 {
4031         struct thread_data *t;
4032         struct core_data *c;
4033         struct pkg_data *p;
4034
4035         t = GET_THREAD(thread_base, thread_num, core_num, pkg_num);
4036         c = GET_CORE(core_base, core_num, pkg_num);
4037         p = GET_PKG(pkg_base, pkg_num);
4038
4039         t->cpu_id = cpu_id;
4040         if (thread_num == 0) {
4041                 t->flags |= CPU_IS_FIRST_THREAD_IN_CORE;
4042                 if (cpu_is_first_core_in_package(cpu_id))
4043                         t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE;
4044         }
4045
4046         c->core_id = core_num;
4047         p->package_id = pkg_num;
4048 }
4049
4050
4051 int initialize_counters(int cpu_id)
4052 {
4053         int my_thread_id, my_core_id, my_package_id;
4054
4055         my_package_id = get_physical_package_id(cpu_id);
4056         my_core_id = get_core_id(cpu_id);
4057         my_thread_id = get_cpu_position_in_core(cpu_id);
4058         if (!my_thread_id)
4059                 topo.num_cores++;
4060
4061         init_counter(EVEN_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id);
4062         init_counter(ODD_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id);
4063         return 0;
4064 }
4065
4066 void allocate_output_buffer()
4067 {
4068         output_buffer = calloc(1, (1 + topo.num_cpus) * 1024);
4069         outp = output_buffer;
4070         if (outp == NULL)
4071                 err(-1, "calloc output buffer");
4072 }
4073 void allocate_fd_percpu(void)
4074 {
4075         fd_percpu = calloc(topo.max_cpu_num + 1, sizeof(int));
4076         if (fd_percpu == NULL)
4077                 err(-1, "calloc fd_percpu");
4078 }
4079 void allocate_irq_buffers(void)
4080 {
4081         irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int));
4082         if (irq_column_2_cpu == NULL)
4083                 err(-1, "calloc %d", topo.num_cpus);
4084
4085         irqs_per_cpu = calloc(topo.max_cpu_num + 1, sizeof(int));
4086         if (irqs_per_cpu == NULL)
4087                 err(-1, "calloc %d", topo.max_cpu_num + 1);
4088 }
4089 void setup_all_buffers(void)
4090 {
4091         topology_probe();
4092         allocate_irq_buffers();
4093         allocate_fd_percpu();
4094         allocate_counters(&thread_even, &core_even, &package_even);
4095         allocate_counters(&thread_odd, &core_odd, &package_odd);
4096         allocate_output_buffer();
4097         for_all_proc_cpus(initialize_counters);
4098 }
4099
4100 void set_base_cpu(void)
4101 {
4102         base_cpu = sched_getcpu();
4103         if (base_cpu < 0)
4104                 err(-ENODEV, "No valid cpus found");
4105
4106         if (debug > 1)
4107                 fprintf(outf, "base_cpu = %d\n", base_cpu);
4108 }
4109
4110 void turbostat_init()
4111 {
4112         setup_all_buffers();
4113         set_base_cpu();
4114         check_dev_msr();
4115         check_permissions();
4116         process_cpuid();
4117
4118
4119         if (debug)
4120                 for_all_cpus(print_hwp, ODD_COUNTERS);
4121
4122         if (debug)
4123                 for_all_cpus(print_epb, ODD_COUNTERS);
4124
4125         if (debug)
4126                 for_all_cpus(print_perf_limit, ODD_COUNTERS);
4127
4128         if (debug)
4129                 for_all_cpus(print_rapl, ODD_COUNTERS);
4130
4131         for_all_cpus(set_temperature_target, ODD_COUNTERS);
4132
4133         if (debug)
4134                 for_all_cpus(print_thermal, ODD_COUNTERS);
4135
4136         if (debug && do_irtl_snb)
4137                 print_irtl();
4138 }
4139
4140 int fork_it(char **argv)
4141 {
4142         pid_t child_pid;
4143         int status;
4144
4145         status = for_all_cpus(get_counters, EVEN_COUNTERS);
4146         if (status)
4147                 exit(status);
4148         /* clear affinity side-effect of get_counters() */
4149         sched_setaffinity(0, cpu_present_setsize, cpu_present_set);
4150         gettimeofday(&tv_even, (struct timezone *)NULL);
4151
4152         child_pid = fork();
4153         if (!child_pid) {
4154                 /* child */
4155                 execvp(argv[0], argv);
4156         } else {
4157
4158                 /* parent */
4159                 if (child_pid == -1)
4160                         err(1, "fork");
4161
4162                 signal(SIGINT, SIG_IGN);
4163                 signal(SIGQUIT, SIG_IGN);
4164                 if (waitpid(child_pid, &status, 0) == -1)
4165                         err(status, "waitpid");
4166         }
4167         /*
4168          * n.b. fork_it() does not check for errors from for_all_cpus()
4169          * because re-starting is problematic when forking
4170          */
4171         for_all_cpus(get_counters, ODD_COUNTERS);
4172         gettimeofday(&tv_odd, (struct timezone *)NULL);
4173         timersub(&tv_odd, &tv_even, &tv_delta);
4174         if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS))
4175                 fprintf(outf, "%s: Counter reset detected\n", progname);
4176         else {
4177                 compute_average(EVEN_COUNTERS);
4178                 format_all_counters(EVEN_COUNTERS);
4179         }
4180
4181         fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec/1000000.0);
4182
4183         flush_output_stderr();
4184
4185         return status;
4186 }
4187
4188 int get_and_dump_counters(void)
4189 {
4190         int status;
4191
4192         status = for_all_cpus(get_counters, ODD_COUNTERS);
4193         if (status)
4194                 return status;
4195
4196         status = for_all_cpus(dump_counters, ODD_COUNTERS);
4197         if (status)
4198                 return status;
4199
4200         flush_output_stdout();
4201
4202         return status;
4203 }
4204
4205 void print_version() {
4206         fprintf(outf, "turbostat version 4.17 10 Jan 2017"
4207                 " - Len Brown <lenb@kernel.org>\n");
4208 }
4209
4210 int add_counter(unsigned int msr_num, char *name, unsigned int width,
4211         enum counter_scope scope, enum counter_type type,
4212         enum counter_format format)
4213 {
4214         struct msr_counter *msrp;
4215
4216         msrp = calloc(1, sizeof(struct msr_counter));
4217         if (msrp == NULL) {
4218                 perror("calloc");
4219                 exit(1);
4220         }
4221
4222         msrp->msr_num = msr_num;
4223         strncpy(msrp->name, name, NAME_BYTES);
4224         msrp->width = width;
4225         msrp->type = type;
4226         msrp->format = format;
4227
4228         switch (scope) {
4229
4230         case SCOPE_CPU:
4231                 msrp->next = sys.tp;
4232                 sys.tp = msrp;
4233                 sys.added_thread_counters++;
4234                 if (sys.added_thread_counters > MAX_ADDED_COUNTERS) {
4235                         fprintf(stderr, "exceeded max %d added thread counters\n",
4236                                 MAX_ADDED_COUNTERS);
4237                         exit(-1);
4238                 }
4239                 break;
4240
4241         case SCOPE_CORE:
4242                 msrp->next = sys.cp;
4243                 sys.cp = msrp;
4244                 sys.added_core_counters++;
4245                 if (sys.added_core_counters > MAX_ADDED_COUNTERS) {
4246                         fprintf(stderr, "exceeded max %d added core counters\n",
4247                                 MAX_ADDED_COUNTERS);
4248                         exit(-1);
4249                 }
4250                 break;
4251
4252         case SCOPE_PACKAGE:
4253                 msrp->next = sys.pp;
4254                 sys.pp = msrp;
4255                 sys.added_package_counters++;
4256                 if (sys.added_package_counters > MAX_ADDED_COUNTERS) {
4257                         fprintf(stderr, "exceeded max %d added package counters\n",
4258                                 MAX_ADDED_COUNTERS);
4259                         exit(-1);
4260                 }
4261                 break;
4262         }
4263
4264         return 0;
4265 }
4266
4267 void parse_add_command(char *add_command)
4268 {
4269         int msr_num = 0;
4270         char name_buffer[NAME_BYTES];
4271         int width = 64;
4272         int fail = 0;
4273         enum counter_scope scope = SCOPE_CPU;
4274         enum counter_type type = COUNTER_CYCLES;
4275         enum counter_format format = FORMAT_DELTA;
4276
4277         while (add_command) {
4278
4279                 if (sscanf(add_command, "msr0x%x", &msr_num) == 1)
4280                         goto next;
4281
4282                 if (sscanf(add_command, "msr%d", &msr_num) == 1)
4283                         goto next;
4284
4285                 if (sscanf(add_command, "u%d", &width) == 1) {
4286                         if ((width == 32) || (width == 64))
4287                                 goto next;
4288                         width = 64;
4289                 }
4290                 if (!strncmp(add_command, "cpu", strlen("cpu"))) {
4291                         scope = SCOPE_CPU;
4292                         goto next;
4293                 }
4294                 if (!strncmp(add_command, "core", strlen("core"))) {
4295                         scope = SCOPE_CORE;
4296                         goto next;
4297                 }
4298                 if (!strncmp(add_command, "package", strlen("package"))) {
4299                         scope = SCOPE_PACKAGE;
4300                         goto next;
4301                 }
4302                 if (!strncmp(add_command, "cycles", strlen("cycles"))) {
4303                         type = COUNTER_CYCLES;
4304                         goto next;
4305                 }
4306                 if (!strncmp(add_command, "seconds", strlen("seconds"))) {
4307                         type = COUNTER_SECONDS;
4308                         goto next;
4309                 }
4310                 if (!strncmp(add_command, "raw", strlen("raw"))) {
4311                         format = FORMAT_RAW;
4312                         goto next;
4313                 }
4314                 if (!strncmp(add_command, "delta", strlen("delta"))) {
4315                         format = FORMAT_DELTA;
4316                         goto next;
4317                 }
4318                 if (!strncmp(add_command, "percent", strlen("percent"))) {
4319                         format = FORMAT_PERCENT;
4320                         goto next;
4321                 }
4322
4323                 if (sscanf(add_command, "%18s,%*s", name_buffer) == 1) {        /* 18 < NAME_BYTES */
4324                         char *eos;
4325
4326                         eos = strchr(name_buffer, ',');
4327                         if (eos)
4328                                 *eos = '\0';
4329                         goto next;
4330                 }
4331
4332 next:
4333                 add_command = strchr(add_command, ',');
4334                 if (add_command)
4335                         add_command++;
4336
4337         }
4338         if (msr_num == 0) {
4339                 fprintf(stderr, "--add: (msrDDD | msr0xXXX) required\n");
4340                 fail++;
4341         }
4342
4343         /* generate default column header */
4344         if (*name_buffer == '\0') {
4345                 if (format == FORMAT_RAW) {
4346                         if (width == 32)
4347                                 sprintf(name_buffer, "msr%d", msr_num);
4348                         else
4349                                 sprintf(name_buffer, "MSR%d", msr_num);
4350                 } else if (format == FORMAT_DELTA) {
4351                         if (width == 32)
4352                                 sprintf(name_buffer, "cnt%d", msr_num);
4353                         else
4354                                 sprintf(name_buffer, "CNT%d", msr_num);
4355                 } else if (format == FORMAT_PERCENT) {
4356                         if (width == 32)
4357                                 sprintf(name_buffer, "msr%d%%", msr_num);
4358                         else
4359                                 sprintf(name_buffer, "MSR%d%%", msr_num);
4360                 }
4361         }
4362
4363         if (add_counter(msr_num, name_buffer, width, scope, type, format))
4364                 fail++;
4365
4366         if (fail) {
4367                 help();
4368                 exit(1);
4369         }
4370 }
4371 /*
4372  * HIDE_LIST - hide this list of counters, show the rest [default]
4373  * SHOW_LIST - show this list of counters, hide the rest
4374  */
4375 enum show_hide_mode { SHOW_LIST, HIDE_LIST } global_show_hide_mode = HIDE_LIST;
4376
4377 int shown;
4378 /*
4379  * parse_show_hide() - process cmdline to set default counter action
4380  */
4381 void parse_show_hide(char *optarg, enum show_hide_mode new_mode)
4382 {
4383         /*
4384          * --show: show only those specified
4385          *  The 1st invocation will clear and replace the enabled mask
4386          *  subsequent invocations can add to it.
4387          */
4388         if (new_mode == SHOW_LIST) {
4389                 if (shown == 0)
4390                         bic_enabled = bic_lookup(optarg);
4391                 else
4392                         bic_enabled |= bic_lookup(optarg);
4393                 shown = 1;
4394
4395                 return;
4396         }
4397
4398         /*
4399          * --hide: do not show those specified
4400          *  multiple invocations simply clear more bits in enabled mask
4401          */
4402         bic_enabled &= ~bic_lookup(optarg);
4403 }
4404
4405 void cmdline(int argc, char **argv)
4406 {
4407         int opt;
4408         int option_index = 0;
4409         static struct option long_options[] = {
4410                 {"add",         required_argument,      0, 'a'},
4411                 {"Dump",        no_argument,            0, 'D'},
4412                 {"debug",       no_argument,            0, 'd'},
4413                 {"interval",    required_argument,      0, 'i'},
4414                 {"help",        no_argument,            0, 'h'},
4415                 {"hide",        required_argument,      0, 'H'},        // meh, -h taken by --help
4416                 {"Joules",      no_argument,            0, 'J'},
4417                 {"out",         required_argument,      0, 'o'},
4418                 {"Package",     no_argument,            0, 'p'},
4419                 {"processor",   no_argument,            0, 'p'},
4420                 {"show",        required_argument,      0, 's'},
4421                 {"Summary",     no_argument,            0, 'S'},
4422                 {"TCC",         required_argument,      0, 'T'},
4423                 {"version",     no_argument,            0, 'v' },
4424                 {0,             0,                      0,  0 }
4425         };
4426
4427         progname = argv[0];
4428
4429         while ((opt = getopt_long_only(argc, argv, "+C:c:Ddhi:JM:m:o:PpST:v",
4430                                 long_options, &option_index)) != -1) {
4431                 switch (opt) {
4432                 case 'a':
4433                         parse_add_command(optarg);
4434                         break;
4435                 case 'D':
4436                         dump_only++;
4437                         break;
4438                 case 'd':
4439                         debug++;
4440                         break;
4441                 case 'H':
4442                         parse_show_hide(optarg, HIDE_LIST);
4443                         break;
4444                 case 'h':
4445                 default:
4446                         help();
4447                         exit(1);
4448                 case 'i':
4449                         {
4450                                 double interval = strtod(optarg, NULL);
4451
4452                                 if (interval < 0.001) {
4453                                         fprintf(outf, "interval %f seconds is too small\n",
4454                                                 interval);
4455                                         exit(2);
4456                                 }
4457
4458                                 interval_ts.tv_sec = interval;
4459                                 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000;
4460                         }
4461                         break;
4462                 case 'J':
4463                         rapl_joules++;
4464                         break;
4465                 case 'o':
4466                         outf = fopen_or_die(optarg, "w");
4467                         break;
4468                 case 'P':
4469                         show_pkg_only++;
4470                         break;
4471                 case 'p':
4472                         show_core_only++;
4473                         break;
4474                 case 's':
4475                         parse_show_hide(optarg, SHOW_LIST);
4476                         break;
4477                 case 'S':
4478                         summary_only++;
4479                         break;
4480                 case 'T':
4481                         tcc_activation_temp_override = atoi(optarg);
4482                         break;
4483                 case 'v':
4484                         print_version();
4485                         exit(0);
4486                         break;
4487                 }
4488         }
4489 }
4490
4491 int main(int argc, char **argv)
4492 {
4493         outf = stderr;
4494
4495         cmdline(argc, argv);
4496
4497         if (debug)
4498                 print_version();
4499
4500         turbostat_init();
4501
4502         /* dump counters and exit */
4503         if (dump_only)
4504                 return get_and_dump_counters();
4505
4506         /*
4507          * if any params left, it must be a command to fork
4508          */
4509         if (argc - optind)
4510                 return fork_it(argv + optind);
4511         else
4512                 turbostat_loop();
4513
4514         return 0;
4515 }