virt/kvm/arm/pmu.c

   1 /*
   2  * Copyright (C) 2015 Linaro Ltd.
   3  * Author: Shannon Zhao <shannon.zhao@linaro.org>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/cpu.h>
  19 #include <linux/kvm.h>
  20 #include <linux/kvm_host.h>
  21 #include <linux/perf_event.h>
  22 #include <linux/uaccess.h>
  23 #include <asm/kvm_emulate.h>
  24 #include <kvm/arm_pmu.h>
  25 #include <kvm/arm_vgic.h>
  26
  27 /**
  28  * kvm_pmu_get_counter_value - get PMU counter value
  29  * @vcpu: The vcpu pointer
  30  * @select_idx: The counter index
  31  */
  32 u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx)
  33 {
  34         u64 counter, reg, enabled, running;
  35         struct kvm_pmu *pmu = &vcpu->arch.pmu;
  36         struct kvm_pmc *pmc = &pmu->pmc[select_idx];
  37
  38         reg = (select_idx == ARMV8_PMU_CYCLE_IDX)
  39               ? PMCCNTR_EL0 : PMEVCNTR0_EL0 + select_idx;
  40         counter = vcpu_sys_reg(vcpu, reg);
  41
  42         /* The real counter value is equal to the value of counter register plus
  43          * the value perf event counts.
  44          */
  45         if (pmc->perf_event)
  46                 counter += perf_event_read_value(pmc->perf_event, &enabled,
  47                                                  &running);
  48
  49         return counter & pmc->bitmask;
  50 }
  51
  52 /**
  53  * kvm_pmu_set_counter_value - set PMU counter value
  54  * @vcpu: The vcpu pointer
  55  * @select_idx: The counter index
  56  * @val: The counter value
  57  */
  58 void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val)
  59 {
  60         u64 reg;
  61
  62         reg = (select_idx == ARMV8_PMU_CYCLE_IDX)
  63               ? PMCCNTR_EL0 : PMEVCNTR0_EL0 + select_idx;
  64         vcpu_sys_reg(vcpu, reg) += (s64)val - kvm_pmu_get_counter_value(vcpu, select_idx);
  65 }
  66
  67 /**
  68  * kvm_pmu_stop_counter - stop PMU counter
  69  * @pmc: The PMU counter pointer
  70  *
  71  * If this counter has been configured to monitor some event, release it here.
  72  */
  73 static void kvm_pmu_stop_counter(struct kvm_vcpu *vcpu, struct kvm_pmc *pmc)
  74 {
  75         u64 counter, reg;
  76
  77         if (pmc->perf_event) {
  78                 counter = kvm_pmu_get_counter_value(vcpu, pmc->idx);
  79                 reg = (pmc->idx == ARMV8_PMU_CYCLE_IDX)
  80                        ? PMCCNTR_EL0 : PMEVCNTR0_EL0 + pmc->idx;
  81                 vcpu_sys_reg(vcpu, reg) = counter;
  82                 perf_event_disable(pmc->perf_event);
  83                 perf_event_release_kernel(pmc->perf_event);
  84                 pmc->perf_event = NULL;
  85         }
  86 }
  87
  88 /**
  89  * kvm_pmu_vcpu_reset - reset pmu state for cpu
  90  * @vcpu: The vcpu pointer
  91  *
  92  */
  93 void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu)
  94 {
  95         int i;
  96         struct kvm_pmu *pmu = &vcpu->arch.pmu;
  97
  98         for (i = 0; i < ARMV8_PMU_MAX_COUNTERS; i++) {
  99                 kvm_pmu_stop_counter(vcpu, &pmu->pmc[i]);
 100                 pmu->pmc[i].idx = i;
 101                 pmu->pmc[i].bitmask = 0xffffffffUL;
 102         }
 103 }
 104
 105 /**
 106  * kvm_pmu_vcpu_destroy - free perf event of PMU for cpu
 107  * @vcpu: The vcpu pointer
 108  *
 109  */
 110 void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu)
 111 {
 112         int i;
 113         struct kvm_pmu *pmu = &vcpu->arch.pmu;
 114
 115         for (i = 0; i < ARMV8_PMU_MAX_COUNTERS; i++) {
 116                 struct kvm_pmc *pmc = &pmu->pmc[i];
 117
 118                 if (pmc->perf_event) {
 119                         perf_event_disable(pmc->perf_event);
 120                         perf_event_release_kernel(pmc->perf_event);
 121                         pmc->perf_event = NULL;
 122                 }
 123         }
 124 }
 125
 126 u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu)
 127 {
 128         u64 val = vcpu_sys_reg(vcpu, PMCR_EL0) >> ARMV8_PMU_PMCR_N_SHIFT;
 129
 130         val &= ARMV8_PMU_PMCR_N_MASK;
 131         if (val == 0)
 132                 return BIT(ARMV8_PMU_CYCLE_IDX);
 133         else
 134                 return GENMASK(val - 1, 0) | BIT(ARMV8_PMU_CYCLE_IDX);
 135 }
 136
 137 /**
 138  * kvm_pmu_enable_counter - enable selected PMU counter
 139  * @vcpu: The vcpu pointer
 140  * @val: the value guest writes to PMCNTENSET register
 141  *
 142  * Call perf_event_enable to start counting the perf event
 143  */
 144 void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val)
 145 {
 146         int i;
 147         struct kvm_pmu *pmu = &vcpu->arch.pmu;
 148         struct kvm_pmc *pmc;
 149
 150         if (!(vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E) || !val)
 151                 return;
 152
 153         for (i = 0; i < ARMV8_PMU_MAX_COUNTERS; i++) {
 154                 if (!(val & BIT(i)))
 155                         continue;
 156
 157                 pmc = &pmu->pmc[i];
 158                 if (pmc->perf_event) {
 159                         perf_event_enable(pmc->perf_event);
 160                         if (pmc->perf_event->state != PERF_EVENT_STATE_ACTIVE)
 161                                 kvm_debug("fail to enable perf event\n");
 162                 }
 163         }
 164 }
 165
 166 /**
 167  * kvm_pmu_disable_counter - disable selected PMU counter
 168  * @vcpu: The vcpu pointer
 169  * @val: the value guest writes to PMCNTENCLR register
 170  *
 171  * Call perf_event_disable to stop counting the perf event
 172  */
 173 void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val)
 174 {
 175         int i;
 176         struct kvm_pmu *pmu = &vcpu->arch.pmu;
 177         struct kvm_pmc *pmc;
 178
 179         if (!val)
 180                 return;
 181
 182         for (i = 0; i < ARMV8_PMU_MAX_COUNTERS; i++) {
 183                 if (!(val & BIT(i)))
 184                         continue;
 185
 186                 pmc = &pmu->pmc[i];
 187                 if (pmc->perf_event)
 188                         perf_event_disable(pmc->perf_event);
 189         }
 190 }
 191
 192 static u64 kvm_pmu_overflow_status(struct kvm_vcpu *vcpu)
 193 {
 194         u64 reg = 0;
 195
 196         if ((vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E)) {
 197                 reg = vcpu_sys_reg(vcpu, PMOVSSET_EL0);
 198                 reg &= vcpu_sys_reg(vcpu, PMCNTENSET_EL0);
 199                 reg &= vcpu_sys_reg(vcpu, PMINTENSET_EL1);
 200                 reg &= kvm_pmu_valid_counter_mask(vcpu);
 201         }
 202
 203         return reg;
 204 }
 205
 206 static void kvm_pmu_check_overflow(struct kvm_vcpu *vcpu)
 207 {
 208         struct kvm_pmu *pmu = &vcpu->arch.pmu;
 209         bool overflow = !!kvm_pmu_overflow_status(vcpu);
 210
 211         if (pmu->irq_level == overflow)
 212                 return;
 213
 214         pmu->irq_level = overflow;
 215
 216         if (likely(irqchip_in_kernel(vcpu->kvm))) {
 217                 int ret = kvm_vgic_inject_irq(vcpu->kvm, vcpu->vcpu_id,
 218                                               pmu->irq_num, overflow);
 219                 WARN_ON(ret);
 220         }
 221 }
 222
 223 /**
 224  * kvm_pmu_overflow_set - set PMU overflow interrupt
 225  * @vcpu: The vcpu pointer
 226  * @val: the value guest writes to PMOVSSET register
 227  */
 228 void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val)
 229 {
 230         if (val == 0)
 231                 return;
 232
 233         vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= val;
 234         kvm_pmu_check_overflow(vcpu);
 235 }
 236
 237 static void kvm_pmu_update_state(struct kvm_vcpu *vcpu)
 238 {
 239         if (!kvm_arm_pmu_v3_ready(vcpu))
 240                 return;
 241         kvm_pmu_check_overflow(vcpu);
 242 }
 243
 244 bool kvm_pmu_should_notify_user(struct kvm_vcpu *vcpu)
 245 {
 246         struct kvm_pmu *pmu = &vcpu->arch.pmu;
 247         struct kvm_sync_regs *sregs = &vcpu->run->s.regs;
 248         bool run_level = sregs->device_irq_level & KVM_ARM_DEV_PMU;
 249
 250         if (likely(irqchip_in_kernel(vcpu->kvm)))
 251                 return false;
 252
 253         return pmu->irq_level != run_level;
 254 }
 255
 256 /*
 257  * Reflect the PMU overflow interrupt output level into the kvm_run structure
 258  */
 259 void kvm_pmu_update_run(struct kvm_vcpu *vcpu)
 260 {
 261         struct kvm_sync_regs *regs = &vcpu->run->s.regs;
 262
 263         /* Populate the timer bitmap for user space */
 264         regs->device_irq_level &= ~KVM_ARM_DEV_PMU;
 265         if (vcpu->arch.pmu.irq_level)
 266                 regs->device_irq_level |= KVM_ARM_DEV_PMU;
 267 }
 268
 269 /**
 270  * kvm_pmu_flush_hwstate - flush pmu state to cpu
 271  * @vcpu: The vcpu pointer
 272  *
 273  * Check if the PMU has overflowed while we were running in the host, and inject
 274  * an interrupt if that was the case.
 275  */
 276 void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu)
 277 {
 278         kvm_pmu_update_state(vcpu);
 279 }
 280
 281 /**
 282  * kvm_pmu_sync_hwstate - sync pmu state from cpu
 283  * @vcpu: The vcpu pointer
 284  *
 285  * Check if the PMU has overflowed while we were running in the guest, and
 286  * inject an interrupt if that was the case.
 287  */
 288 void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu)
 289 {
 290         kvm_pmu_update_state(vcpu);
 291 }
 292
 293 static inline struct kvm_vcpu *kvm_pmc_to_vcpu(struct kvm_pmc *pmc)
 294 {
 295         struct kvm_pmu *pmu;
 296         struct kvm_vcpu_arch *vcpu_arch;
 297
 298         pmc -= pmc->idx;
 299         pmu = container_of(pmc, struct kvm_pmu, pmc[0]);
 300         vcpu_arch = container_of(pmu, struct kvm_vcpu_arch, pmu);
 301         return container_of(vcpu_arch, struct kvm_vcpu, arch);
 302 }
 303
 304 /**
 305  * When perf event overflows, call kvm_pmu_overflow_set to set overflow status.
 306  */
 307 static void kvm_pmu_perf_overflow(struct perf_event *perf_event,
 308                                   struct perf_sample_data *data,
 309                                   struct pt_regs *regs)
 310 {
 311         struct kvm_pmc *pmc = perf_event->overflow_handler_context;
 312         struct kvm_vcpu *vcpu = kvm_pmc_to_vcpu(pmc);
 313         int idx = pmc->idx;
 314
 315         kvm_pmu_overflow_set(vcpu, BIT(idx));
 316 }
 317
 318 /**
 319  * kvm_pmu_software_increment - do software increment
 320  * @vcpu: The vcpu pointer
 321  * @val: the value guest writes to PMSWINC register
 322  */
 323 void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val)
 324 {
 325         int i;
 326         u64 type, enable, reg;
 327
 328         if (val == 0)
 329                 return;
 330
 331         enable = vcpu_sys_reg(vcpu, PMCNTENSET_EL0);
 332         for (i = 0; i < ARMV8_PMU_CYCLE_IDX; i++) {
 333                 if (!(val & BIT(i)))
 334                         continue;
 335                 type = vcpu_sys_reg(vcpu, PMEVTYPER0_EL0 + i)
 336                        & ARMV8_PMU_EVTYPE_EVENT;
 337                 if ((type == ARMV8_PMUV3_PERFCTR_SW_INCR)
 338                     && (enable & BIT(i))) {
 339                         reg = vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i) + 1;
 340                         reg = lower_32_bits(reg);
 341                         vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i) = reg;
 342                         if (!reg)
 343                                 kvm_pmu_overflow_set(vcpu, BIT(i));
 344                 }
 345         }
 346 }
 347
 348 /**
 349  * kvm_pmu_handle_pmcr - handle PMCR register
 350  * @vcpu: The vcpu pointer
 351  * @val: the value guest writes to PMCR register
 352  */
 353 void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val)
 354 {
 355         struct kvm_pmu *pmu = &vcpu->arch.pmu;
 356         struct kvm_pmc *pmc;
 357         u64 mask;
 358         int i;
 359
 360         mask = kvm_pmu_valid_counter_mask(vcpu);
 361         if (val & ARMV8_PMU_PMCR_E) {
 362                 kvm_pmu_enable_counter(vcpu,
 363                                 vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask);
 364         } else {
 365                 kvm_pmu_disable_counter(vcpu, mask);
 366         }
 367
 368         if (val & ARMV8_PMU_PMCR_C)
 369                 kvm_pmu_set_counter_value(vcpu, ARMV8_PMU_CYCLE_IDX, 0);
 370
 371         if (val & ARMV8_PMU_PMCR_P) {
 372                 for (i = 0; i < ARMV8_PMU_CYCLE_IDX; i++)
 373                         kvm_pmu_set_counter_value(vcpu, i, 0);
 374         }
 375
 376         if (val & ARMV8_PMU_PMCR_LC) {
 377                 pmc = &pmu->pmc[ARMV8_PMU_CYCLE_IDX];
 378                 pmc->bitmask = 0xffffffffffffffffUL;
 379         }
 380 }
 381
 382 static bool kvm_pmu_counter_is_enabled(struct kvm_vcpu *vcpu, u64 select_idx)
 383 {
 384         return (vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E) &&
 385                (vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & BIT(select_idx));
 386 }
 387
 388 /**
 389  * kvm_pmu_set_counter_event_type - set selected counter to monitor some event
 390  * @vcpu: The vcpu pointer
 391  * @data: The data guest writes to PMXEVTYPER_EL0
 392  * @select_idx: The number of selected counter
 393  *
 394  * When OS accesses PMXEVTYPER_EL0, that means it wants to set a PMC to count an
 395  * event with given hardware event number. Here we call perf_event API to
 396  * emulate this action and create a kernel perf event for it.
 397  */
 398 void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
 399                                     u64 select_idx)
 400 {
 401         struct kvm_pmu *pmu = &vcpu->arch.pmu;
 402         struct kvm_pmc *pmc = &pmu->pmc[select_idx];
 403         struct perf_event *event;
 404         struct perf_event_attr attr;
 405         u64 eventsel, counter;
 406
 407         kvm_pmu_stop_counter(vcpu, pmc);
 408         eventsel = data & ARMV8_PMU_EVTYPE_EVENT;
 409
 410         /* Software increment event does't need to be backed by a perf event */
 411         if (eventsel == ARMV8_PMUV3_PERFCTR_SW_INCR &&
 412             select_idx != ARMV8_PMU_CYCLE_IDX)
 413                 return;
 414
 415         memset(&attr, 0, sizeof(struct perf_event_attr));
 416         attr.type = PERF_TYPE_RAW;
 417         attr.size = sizeof(attr);
 418         attr.pinned = 1;
 419         attr.disabled = !kvm_pmu_counter_is_enabled(vcpu, select_idx);
 420         attr.exclude_user = data & ARMV8_PMU_EXCLUDE_EL0 ? 1 : 0;
 421         attr.exclude_kernel = data & ARMV8_PMU_EXCLUDE_EL1 ? 1 : 0;
 422         attr.exclude_hv = 1; /* Don't count EL2 events */
 423         attr.exclude_host = 1; /* Don't count host events */
 424         attr.config = (select_idx == ARMV8_PMU_CYCLE_IDX) ?
 425                 ARMV8_PMUV3_PERFCTR_CPU_CYCLES : eventsel;
 426
 427         counter = kvm_pmu_get_counter_value(vcpu, select_idx);
 428         /* The initial sample period (overflow count) of an event. */
 429         attr.sample_period = (-counter) & pmc->bitmask;
 430
 431         event = perf_event_create_kernel_counter(&attr, -1, current,
 432                                                  kvm_pmu_perf_overflow, pmc);
 433         if (IS_ERR(event)) {
 434                 pr_err_once("kvm: pmu event creation failed %ld\n",
 435                             PTR_ERR(event));
 436                 return;
 437         }
 438
 439         pmc->perf_event = event;
 440 }
 441
 442 bool kvm_arm_support_pmu_v3(void)
 443 {
 444         /*
 445          * Check if HW_PERF_EVENTS are supported by checking the number of
 446          * hardware performance counters. This could ensure the presence of
 447          * a physical PMU and CONFIG_PERF_EVENT is selected.
 448          */
 449         return (perf_num_counters() > 0);
 450 }
 451
 452 int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu)
 453 {
 454         if (!vcpu->arch.pmu.created)
 455                 return 0;
 456
 457         /*
 458          * A valid interrupt configuration for the PMU is either to have a
 459          * properly configured interrupt number and using an in-kernel
 460          * irqchip, or to neither set an IRQ nor create an in-kernel irqchip.
 461          */
 462         if (kvm_arm_pmu_irq_initialized(vcpu) != irqchip_in_kernel(vcpu->kvm))
 463                 return -EINVAL;
 464
 465         kvm_pmu_vcpu_reset(vcpu);
 466         vcpu->arch.pmu.ready = true;
 467
 468         return 0;
 469 }
 470
 471 static int kvm_arm_pmu_v3_init(struct kvm_vcpu *vcpu)
 472 {
 473         if (!kvm_arm_support_pmu_v3())
 474                 return -ENODEV;
 475
 476         if (!test_bit(KVM_ARM_VCPU_PMU_V3, vcpu->arch.features))
 477                 return -ENXIO;
 478
 479         if (vcpu->arch.pmu.created)
 480                 return -EBUSY;
 481
 482         if (irqchip_in_kernel(vcpu->kvm)) {
 483                 /*
 484                  * If using the PMU with an in-kernel virtual GIC
 485                  * implementation, we require the GIC to be already
 486                  * initialized when initializing the PMU.
 487                  */
 488                 if (!vgic_initialized(vcpu->kvm))
 489                         return -ENODEV;
 490
 491                 if (!kvm_arm_pmu_irq_initialized(vcpu))
 492                         return -ENXIO;
 493         }
 494
 495         vcpu->arch.pmu.created = true;
 496         return 0;
 497 }
 498
 499 #define irq_is_ppi(irq) ((irq) >= VGIC_NR_SGIS && (irq) < VGIC_NR_PRIVATE_IRQS)
 500
 501 /*
 502  * For one VM the interrupt type must be same for each vcpu.
 503  * As a PPI, the interrupt number is the same for all vcpus,
 504  * while as an SPI it must be a separate number per vcpu.
 505  */
 506 static bool pmu_irq_is_valid(struct kvm *kvm, int irq)
 507 {
 508         int i;
 509         struct kvm_vcpu *vcpu;
 510
 511         kvm_for_each_vcpu(i, vcpu, kvm) {
 512                 if (!kvm_arm_pmu_irq_initialized(vcpu))
 513                         continue;
 514
 515                 if (irq_is_ppi(irq)) {
 516                         if (vcpu->arch.pmu.irq_num != irq)
 517                                 return false;
 518                 } else {
 519                         if (vcpu->arch.pmu.irq_num == irq)
 520                                 return false;
 521                 }
 522         }
 523
 524         return true;
 525 }
 526
 527 int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr)
 528 {
 529         switch (attr->attr) {
 530         case KVM_ARM_VCPU_PMU_V3_IRQ: {
 531                 int __user *uaddr = (int __user *)(long)attr->addr;
 532                 int irq;
 533
 534                 if (!irqchip_in_kernel(vcpu->kvm))
 535                         return -EINVAL;
 536
 537                 if (!test_bit(KVM_ARM_VCPU_PMU_V3, vcpu->arch.features))
 538                         return -ENODEV;
 539
 540                 if (get_user(irq, uaddr))
 541                         return -EFAULT;
 542
 543                 /* The PMU overflow interrupt can be a PPI or a valid SPI. */
 544                 if (!(irq_is_ppi(irq) || vgic_valid_spi(vcpu->kvm, irq)))
 545                         return -EINVAL;
 546
 547                 if (!pmu_irq_is_valid(vcpu->kvm, irq))
 548                         return -EINVAL;
 549
 550                 if (kvm_arm_pmu_irq_initialized(vcpu))
 551                         return -EBUSY;
 552
 553                 kvm_debug("Set kvm ARM PMU irq: %d\n", irq);
 554                 vcpu->arch.pmu.irq_num = irq;
 555                 return 0;
 556         }
 557         case KVM_ARM_VCPU_PMU_V3_INIT:
 558                 return kvm_arm_pmu_v3_init(vcpu);
 559         }
 560
 561         return -ENXIO;
 562 }
 563
 564 int kvm_arm_pmu_v3_get_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr)
 565 {
 566         switch (attr->attr) {
 567         case KVM_ARM_VCPU_PMU_V3_IRQ: {
 568                 int __user *uaddr = (int __user *)(long)attr->addr;
 569                 int irq;
 570
 571                 if (!irqchip_in_kernel(vcpu->kvm))
 572                         return -EINVAL;
 573
 574                 if (!test_bit(KVM_ARM_VCPU_PMU_V3, vcpu->arch.features))
 575                         return -ENODEV;
 576
 577                 if (!kvm_arm_pmu_irq_initialized(vcpu))
 578                         return -ENXIO;
 579
 580                 irq = vcpu->arch.pmu.irq_num;
 581                 return put_user(irq, uaddr);
 582         }
 583         }
 584
 585         return -ENXIO;
 586 }
 587
 588 int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr)
 589 {
 590         switch (attr->attr) {
 591         case KVM_ARM_VCPU_PMU_V3_IRQ:
 592         case KVM_ARM_VCPU_PMU_V3_INIT:
 593                 if (kvm_arm_support_pmu_v3() &&
 594                     test_bit(KVM_ARM_VCPU_PMU_V3, vcpu->arch.features))
 595                         return 0;
 596         }
 597
 598         return -ENXIO;
 599 }