2 * VGIC MMIO handling functions
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/bitops.h>
15 #include <linux/bsearch.h>
16 #include <linux/kvm.h>
17 #include <linux/kvm_host.h>
18 #include <kvm/iodev.h>
19 #include <kvm/arm_vgic.h>
22 #include "vgic-mmio.h"
24 unsigned long vgic_mmio_read_raz(struct kvm_vcpu *vcpu,
25 gpa_t addr, unsigned int len)
30 unsigned long vgic_mmio_read_rao(struct kvm_vcpu *vcpu,
31 gpa_t addr, unsigned int len)
36 void vgic_mmio_write_wi(struct kvm_vcpu *vcpu, gpa_t addr,
37 unsigned int len, unsigned long val)
43 * Read accesses to both GICD_ICENABLER and GICD_ISENABLER return the value
44 * of the enabled bit, so there is only one function for both here.
46 unsigned long vgic_mmio_read_enable(struct kvm_vcpu *vcpu,
47 gpa_t addr, unsigned int len)
49 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
53 /* Loop over all IRQs affected by this read */
54 for (i = 0; i < len * 8; i++) {
55 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
60 vgic_put_irq(vcpu->kvm, irq);
66 void vgic_mmio_write_senable(struct kvm_vcpu *vcpu,
67 gpa_t addr, unsigned int len,
70 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
73 for_each_set_bit(i, &val, len * 8) {
74 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
76 spin_lock(&irq->irq_lock);
78 vgic_queue_irq_unlock(vcpu->kvm, irq);
80 vgic_put_irq(vcpu->kvm, irq);
84 void vgic_mmio_write_cenable(struct kvm_vcpu *vcpu,
85 gpa_t addr, unsigned int len,
88 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
91 for_each_set_bit(i, &val, len * 8) {
92 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
94 spin_lock(&irq->irq_lock);
98 spin_unlock(&irq->irq_lock);
99 vgic_put_irq(vcpu->kvm, irq);
103 unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu,
104 gpa_t addr, unsigned int len)
106 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
110 /* Loop over all IRQs affected by this read */
111 for (i = 0; i < len * 8; i++) {
112 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
114 if (irq_is_pending(irq))
117 vgic_put_irq(vcpu->kvm, irq);
123 void vgic_mmio_write_spending(struct kvm_vcpu *vcpu,
124 gpa_t addr, unsigned int len,
127 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
130 for_each_set_bit(i, &val, len * 8) {
131 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
133 spin_lock(&irq->irq_lock);
134 irq->pending_latch = true;
136 vgic_queue_irq_unlock(vcpu->kvm, irq);
137 vgic_put_irq(vcpu->kvm, irq);
141 void vgic_mmio_write_cpending(struct kvm_vcpu *vcpu,
142 gpa_t addr, unsigned int len,
145 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
148 for_each_set_bit(i, &val, len * 8) {
149 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
151 spin_lock(&irq->irq_lock);
153 irq->pending_latch = false;
155 spin_unlock(&irq->irq_lock);
156 vgic_put_irq(vcpu->kvm, irq);
160 unsigned long vgic_mmio_read_active(struct kvm_vcpu *vcpu,
161 gpa_t addr, unsigned int len)
163 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
167 /* Loop over all IRQs affected by this read */
168 for (i = 0; i < len * 8; i++) {
169 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
174 vgic_put_irq(vcpu->kvm, irq);
180 static void vgic_mmio_change_active(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
181 bool new_active_state)
183 spin_lock(&irq->irq_lock);
185 * If this virtual IRQ was written into a list register, we
186 * have to make sure the CPU that runs the VCPU thread has
187 * synced back LR state to the struct vgic_irq. We can only
188 * know this for sure, when either this irq is not assigned to
189 * anyone's AP list anymore, or the VCPU thread is not
190 * running on any CPUs.
192 * In the opposite case, we know the VCPU thread may be on its
193 * way back from the guest and still has to sync back this
194 * IRQ, so we release and re-acquire the spin_lock to let the
195 * other thread sync back the IRQ.
197 while (irq->vcpu && /* IRQ may have state in an LR somewhere */
198 irq->vcpu->cpu != -1) /* VCPU thread is running */
199 cond_resched_lock(&irq->irq_lock);
201 irq->active = new_active_state;
202 if (new_active_state)
203 vgic_queue_irq_unlock(vcpu->kvm, irq);
205 spin_unlock(&irq->irq_lock);
209 * If we are fiddling with an IRQ's active state, we have to make sure the IRQ
210 * is not queued on some running VCPU's LRs, because then the change to the
211 * active state can be overwritten when the VCPU's state is synced coming back
214 * For shared interrupts, we have to stop all the VCPUs because interrupts can
215 * be migrated while we don't hold the IRQ locks and we don't want to be
216 * chasing moving targets.
218 * For private interrupts, we only have to make sure the single and only VCPU
219 * that can potentially queue the IRQ is stopped.
221 static void vgic_change_active_prepare(struct kvm_vcpu *vcpu, u32 intid)
223 if (intid < VGIC_NR_PRIVATE_IRQS)
224 kvm_arm_halt_vcpu(vcpu);
226 kvm_arm_halt_guest(vcpu->kvm);
229 /* See vgic_change_active_prepare */
230 static void vgic_change_active_finish(struct kvm_vcpu *vcpu, u32 intid)
232 if (intid < VGIC_NR_PRIVATE_IRQS)
233 kvm_arm_resume_vcpu(vcpu);
235 kvm_arm_resume_guest(vcpu->kvm);
238 void vgic_mmio_write_cactive(struct kvm_vcpu *vcpu,
239 gpa_t addr, unsigned int len,
242 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
245 vgic_change_active_prepare(vcpu, intid);
246 for_each_set_bit(i, &val, len * 8) {
247 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
248 vgic_mmio_change_active(vcpu, irq, false);
249 vgic_put_irq(vcpu->kvm, irq);
251 vgic_change_active_finish(vcpu, intid);
254 void vgic_mmio_write_sactive(struct kvm_vcpu *vcpu,
255 gpa_t addr, unsigned int len,
258 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
261 vgic_change_active_prepare(vcpu, intid);
262 for_each_set_bit(i, &val, len * 8) {
263 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
264 vgic_mmio_change_active(vcpu, irq, true);
265 vgic_put_irq(vcpu->kvm, irq);
267 vgic_change_active_finish(vcpu, intid);
270 unsigned long vgic_mmio_read_priority(struct kvm_vcpu *vcpu,
271 gpa_t addr, unsigned int len)
273 u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
277 for (i = 0; i < len; i++) {
278 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
280 val |= (u64)irq->priority << (i * 8);
282 vgic_put_irq(vcpu->kvm, irq);
289 * We currently don't handle changing the priority of an interrupt that
290 * is already pending on a VCPU. If there is a need for this, we would
291 * need to make this VCPU exit and re-evaluate the priorities, potentially
292 * leading to this interrupt getting presented now to the guest (if it has
293 * been masked by the priority mask before).
295 void vgic_mmio_write_priority(struct kvm_vcpu *vcpu,
296 gpa_t addr, unsigned int len,
299 u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
302 for (i = 0; i < len; i++) {
303 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
305 spin_lock(&irq->irq_lock);
306 /* Narrow the priority range to what we actually support */
307 irq->priority = (val >> (i * 8)) & GENMASK(7, 8 - VGIC_PRI_BITS);
308 spin_unlock(&irq->irq_lock);
310 vgic_put_irq(vcpu->kvm, irq);
314 unsigned long vgic_mmio_read_config(struct kvm_vcpu *vcpu,
315 gpa_t addr, unsigned int len)
317 u32 intid = VGIC_ADDR_TO_INTID(addr, 2);
321 for (i = 0; i < len * 4; i++) {
322 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
324 if (irq->config == VGIC_CONFIG_EDGE)
325 value |= (2U << (i * 2));
327 vgic_put_irq(vcpu->kvm, irq);
333 void vgic_mmio_write_config(struct kvm_vcpu *vcpu,
334 gpa_t addr, unsigned int len,
337 u32 intid = VGIC_ADDR_TO_INTID(addr, 2);
340 for (i = 0; i < len * 4; i++) {
341 struct vgic_irq *irq;
344 * The configuration cannot be changed for SGIs in general,
345 * for PPIs this is IMPLEMENTATION DEFINED. The arch timer
346 * code relies on PPIs being level triggered, so we also
347 * make them read-only here.
349 if (intid + i < VGIC_NR_PRIVATE_IRQS)
352 irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
353 spin_lock(&irq->irq_lock);
355 if (test_bit(i * 2 + 1, &val))
356 irq->config = VGIC_CONFIG_EDGE;
358 irq->config = VGIC_CONFIG_LEVEL;
360 spin_unlock(&irq->irq_lock);
361 vgic_put_irq(vcpu->kvm, irq);
365 static int match_region(const void *key, const void *elt)
367 const unsigned int offset = (unsigned long)key;
368 const struct vgic_register_region *region = elt;
370 if (offset < region->reg_offset)
373 if (offset >= region->reg_offset + region->len)
379 /* Find the proper register handler entry given a certain address offset. */
380 static const struct vgic_register_region *
381 vgic_find_mmio_region(const struct vgic_register_region *region, int nr_regions,
384 return bsearch((void *)(uintptr_t)offset, region, nr_regions,
385 sizeof(region[0]), match_region);
389 * kvm_mmio_read_buf() returns a value in a format where it can be converted
390 * to a byte array and be directly observed as the guest wanted it to appear
391 * in memory if it had done the store itself, which is LE for the GIC, as the
392 * guest knows the GIC is always LE.
394 * We convert this value to the CPUs native format to deal with it as a data
397 unsigned long vgic_data_mmio_bus_to_host(const void *val, unsigned int len)
399 unsigned long data = kvm_mmio_read_buf(val, len);
405 return le16_to_cpu(data);
407 return le32_to_cpu(data);
409 return le64_to_cpu(data);
414 * kvm_mmio_write_buf() expects a value in a format such that if converted to
415 * a byte array it is observed as the guest would see it if it could perform
416 * the load directly. Since the GIC is LE, and the guest knows this, the
417 * guest expects a value in little endian format.
419 * We convert the data value from the CPUs native format to LE so that the
420 * value is returned in the proper format.
422 void vgic_data_host_to_mmio_bus(void *buf, unsigned int len,
429 data = cpu_to_le16(data);
432 data = cpu_to_le32(data);
435 data = cpu_to_le64(data);
438 kvm_mmio_write_buf(buf, len, data);
442 struct vgic_io_device *kvm_to_vgic_iodev(const struct kvm_io_device *dev)
444 return container_of(dev, struct vgic_io_device, dev);
447 static bool check_region(const struct kvm *kvm,
448 const struct vgic_register_region *region,
451 int flags, nr_irqs = kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
455 flags = VGIC_ACCESS_8bit;
458 flags = VGIC_ACCESS_32bit;
461 flags = VGIC_ACCESS_64bit;
467 if ((region->access_flags & flags) && IS_ALIGNED(addr, len)) {
468 if (!region->bits_per_irq)
471 /* Do we access a non-allocated IRQ? */
472 return VGIC_ADDR_TO_INTID(addr, region->bits_per_irq) < nr_irqs;
478 static int dispatch_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
479 gpa_t addr, int len, void *val)
481 struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
482 const struct vgic_register_region *region;
483 unsigned long data = 0;
485 region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
486 addr - iodev->base_addr);
487 if (!region || !check_region(vcpu->kvm, region, addr, len)) {
492 switch (iodev->iodev_type) {
494 data = region->read(vcpu, addr, len);
497 data = region->read(vcpu, addr, len);
500 data = region->read(iodev->redist_vcpu, addr, len);
503 data = region->its_read(vcpu->kvm, iodev->its, addr, len);
507 vgic_data_host_to_mmio_bus(val, len, data);
511 static int dispatch_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
512 gpa_t addr, int len, const void *val)
514 struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
515 const struct vgic_register_region *region;
516 unsigned long data = vgic_data_mmio_bus_to_host(val, len);
518 region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
519 addr - iodev->base_addr);
520 if (!region || !check_region(vcpu->kvm, region, addr, len))
523 switch (iodev->iodev_type) {
525 region->write(vcpu, addr, len, data);
528 region->write(vcpu, addr, len, data);
531 region->write(iodev->redist_vcpu, addr, len, data);
534 region->its_write(vcpu->kvm, iodev->its, addr, len, data);
541 struct kvm_io_device_ops kvm_io_gic_ops = {
542 .read = dispatch_mmio_read,
543 .write = dispatch_mmio_write,
546 int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
549 struct vgic_io_device *io_device = &kvm->arch.vgic.dist_iodev;
555 len = vgic_v2_init_dist_iodev(io_device);
558 len = vgic_v3_init_dist_iodev(io_device);
564 io_device->base_addr = dist_base_address;
565 io_device->iodev_type = IODEV_DIST;
566 io_device->redist_vcpu = NULL;
568 mutex_lock(&kvm->slots_lock);
569 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, dist_base_address,
570 len, &io_device->dev);
571 mutex_unlock(&kvm->slots_lock);