+ usart3 {
+ pinctrl_usart3: usart3-0 {
+ atmel,pins =
+ <1 8 0x1 0x1 /* PB9 periph A with pullup */
+ 1 9 0x1 0x0>; /* PB8 periph A */
+ };
+
+ pinctrl_usart3_rts: usart3_rts-0 {
+ atmel,pins =
+ <0 23 0x2 0x0>; /* PA23 periph B */
+ };
+
+ pinctrl_usart3_cts: usart3_cts-0 {
+ atmel,pins =
+ <0 24 0x2 0x0>; /* PA24 periph B */
+ };
+ };
+
+ nand {
+ pinctrl_nand: nand-0 {
+ atmel,pins =
+ <2 8 0x0 0x1 /* PC8 gpio RDY pin pull_up*/
+ 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
+ };
+ };
+
+ macb {
+ pinctrl_macb_rmii: macb_rmii-0 {
+ atmel,pins =
+ <0 10 0x1 0x0 /* PA10 periph A */
+ 0 11 0x1 0x0 /* PA11 periph A */
+ 0 12 0x1 0x0 /* PA12 periph A */
+ 0 13 0x1 0x0 /* PA13 periph A */
+ 0 14 0x1 0x0 /* PA14 periph A */
+ 0 15 0x1 0x0 /* PA15 periph A */
+ 0 16 0x1 0x0 /* PA16 periph A */
+ 0 17 0x1 0x0 /* PA17 periph A */
+ 0 18 0x1 0x0 /* PA18 periph A */
+ 0 19 0x1 0x0>; /* PA19 periph A */
+ };
+
+ pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
+ atmel,pins =
+ <0 6 0x2 0x0 /* PA6 periph B */
+ 0 7 0x2 0x0 /* PA7 periph B */
+ 0 8 0x2 0x0 /* PA8 periph B */
+ 0 9 0x2 0x0 /* PA9 periph B */
+ 0 27 0x2 0x0 /* PA27 periph B */
+ 0 28 0x2 0x0 /* PA28 periph B */
+ 0 29 0x2 0x0 /* PA29 periph B */
+ 0 30 0x2 0x0>; /* PA30 periph B */
+ };
+ };
+
+ mmc0 {
+ pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
+ atmel,pins =
+ <0 0 0x1 0x0 /* PA0 periph A */
+ 0 1 0x1 0x1 /* PA1 periph A with pullup */
+ 0 2 0x1 0x1>; /* PA2 periph A with pullup */
+ };
+
+ pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
+ atmel,pins =
+ <0 3 0x1 0x1 /* PA3 periph A with pullup */
+ 0 4 0x1 0x1 /* PA4 periph A with pullup */
+ 0 5 0x1 0x1>; /* PA5 periph A with pullup */
+ };
+
+ pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
+ atmel,pins =
+ <0 6 0x1 0x1 /* PA6 periph A with pullup */
+ 0 7 0x1 0x1 /* PA7 periph A with pullup */
+ 0 8 0x1 0x1 /* PA8 periph A with pullup */
+ 0 9 0x1 0x1>; /* PA9 periph A with pullup */
+ };
+ };
+
+ mmc1 {
+ pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
+ atmel,pins =
+ <0 31 0x1 0x0 /* PA31 periph A */
+ 0 22 0x1 0x1 /* PA22 periph A with pullup */
+ 0 23 0x1 0x1>; /* PA23 periph A with pullup */
+ };
+
+ pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
+ atmel,pins =
+ <0 24 0x1 0x1 /* PA24 periph A with pullup */
+ 0 25 0x1 0x1 /* PA25 periph A with pullup */
+ 0 26 0x1 0x1>; /* PA26 periph A with pullup */
+ };
+
+ pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
+ atmel,pins =
+ <0 27 0x1 0x1 /* PA27 periph A with pullup */
+ 0 28 0x1 0x1 /* PA28 periph A with pullup */
+ 0 29 0x1 0x1 /* PA29 periph A with pullup */
+ 0 20 0x1 0x1>; /* PA30 periph A with pullup */
+ };
+ };
+
+ ssc0 {
+ pinctrl_ssc0_tx: ssc0_tx-0 {
+ atmel,pins =
+ <3 0 0x1 0x0 /* PD0 periph A */
+ 3 1 0x1 0x0 /* PD1 periph A */
+ 3 2 0x1 0x0>; /* PD2 periph A */
+ };
+
+ pinctrl_ssc0_rx: ssc0_rx-0 {
+ atmel,pins =
+ <3 3 0x1 0x0 /* PD3 periph A */
+ 3 4 0x1 0x0 /* PD4 periph A */
+ 3 5 0x1 0x0>; /* PD5 periph A */
+ };
+ };
+
+ ssc1 {
+ pinctrl_ssc1_tx: ssc1_tx-0 {
+ atmel,pins =
+ <3 10 0x1 0x0 /* PD10 periph A */
+ 3 11 0x1 0x0 /* PD11 periph A */
+ 3 12 0x1 0x0>; /* PD12 periph A */
+ };
+
+ pinctrl_ssc1_rx: ssc1_rx-0 {
+ atmel,pins =
+ <3 13 0x1 0x0 /* PD13 periph A */
+ 3 14 0x1 0x0 /* PD14 periph A */
+ 3 15 0x1 0x0>; /* PD15 periph A */
+ };
+ };
+
+ pioA: gpio@fffff200 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff200 0x200>;
+ interrupts = <2 4 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pioB: gpio@fffff400 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff400 0x200>;
+ interrupts = <3 4 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pioC: gpio@fffff600 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff600 0x200>;
+ interrupts = <4 4 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pioD: gpio@fffff800 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff800 0x200>;
+ interrupts = <5 4 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pioE: gpio@fffffa00 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffffa00 0x200>;
+ interrupts = <5 4 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };