- /*
- * Enable MMU to use DCache as DRAM
- */
- /* Domain access -- enable for all CPs */
- ldr r0, =0x0000ffff
- mcr p15, 0, r0, c3, c0, 0
-
- /* Point TTBR to MMU table */
- ldr r0, =mmu_table
- adr r2, _start
- orr r0, r2
- mcr p15, 0, r0, c2, c0, 0
-
-/* !!! Hereby, check if the code is running from SRAM !!! */
-/* If the code is running from SRAM, alias SRAM to 0x0 to simulate NOR. The code
- * is linked to 0x0 too, so this makes things easier. */
- cmp r2, #0x5c000000
-
- ldreq r1, [r0]
- orreq r1, r2
- streq r1, [r0]
-
- /* Kick in MMU, ICache, DCache, BTB */
- mrc p15, 0, r0, c1, c0, 0
- bic r0, #0x1b00
- bic r0, #0x0087
- orr r0, #0x1800
- orr r0, #0x0005
- mcr p15, 0, r0, c1, c0, 0
- CPWAIT r0
-
- /* Unlock Icache, Dcache */
- mcr p15, 0, r0, c9, c1, 1
- mcr p15, 0, r0, c9, c2, 1
-
- /* Flush Icache, Dcache, BTB */
- mcr p15, 0, r0, c7, c7, 0
-
- /* Unlock I-TLB, D-TLB */
- mcr p15, 0, r0, c10, c4, 1
- mcr p15, 0, r0, c10, c8, 1
-
- /* Flush TLB */
- mcr p15, 0, r0, c8, c7, 0
- /* Allocate 4096 bytes of Dcache as RAM */
-
- /* Drain pending loads and stores */
- mcr p15, 0, r0, c7, c10, 4