+CONFIG_SYS_ENET_BD_BASE
+ -- defines the base address of the FEC buffer descriptors
+
+CONFIG_SYS_MFD
+ -- defines the PLL Multiplication Factor Devider
+ (see table 9-4 of MCF user manual)
+CONFIG_SYS_RFD -- defines the PLL Reduce Frecuency Devider
+ (see table 9-4 of MCF user manual)
+
+CONFIG_SYS_CSx_BASE -- defines the base address of chip select x
+CONFIG_SYS_CSx_SIZE -- defines the memory size (address range) of chip select x
+CONFIG_SYS_CSx_WIDTH -- defines the bus with of chip select x
+CONFIG_SYS_CSx_RO -- if set to 0 chip select x is read/wirte
+ else chipselct is read only
+CONFIG_SYS_CSx_WS -- defines the number of wait states of chip select x
+
+CONFIG_SYS_PxDDR -- defines the contents of the Data Direction Registers
+CONFIG_SYS_PxDAT -- defines the contents of the Data Registers
+CONFIG_SYS_PXCNT -- defines the contents of the Port Configuration Registers
+
+CONFIG_SYS_PxPAR -- defines the function of ports