+ ATMEL_BASE_SPI0 + AT91_SPI_CSR(1));
+#endif
+#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS2
+ /* Configure CS2 */
+ writel(AT91_SPI_NCPHA |
+ (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
+ (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
+ ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
+ ATMEL_BASE_SPI0 + AT91_SPI_CSR(2));