+
+static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
+ char *data, int length, int write, unsigned long flags)
+{
+ struct mxs_dma_desc *desc = slave->desc;
+ struct mxs_ssp_regs *ssp_regs = slave->regs;
+ uint32_t ctrl0 = SSP_CTRL0_DATA_XFER;
+ uint32_t cache_data_count;
+ int dmach;
+
+ memset(desc, 0, sizeof(struct mxs_dma_desc));
+ desc->address = (dma_addr_t)desc;
+
+ if (flags & SPI_XFER_BEGIN)
+ ctrl0 |= SSP_CTRL0_LOCK_CS;
+ if (flags & SPI_XFER_END)
+ ctrl0 |= SSP_CTRL0_IGNORE_CRC;
+ if (!write)
+ ctrl0 |= SSP_CTRL0_READ;
+
+ writel(length, &ssp_regs->hw_ssp_xfer_size);
+
+ if (length % ARCH_DMA_MINALIGN)
+ cache_data_count = roundup(length, ARCH_DMA_MINALIGN);
+ else
+ cache_data_count = length;
+
+ if (!write) {
+ slave->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
+ slave->desc->cmd.address = (dma_addr_t)data;
+ } else {
+ slave->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
+ slave->desc->cmd.address = (dma_addr_t)data;
+
+ /* Flush data to DRAM so DMA can pick them up */
+ flush_dcache_range((uint32_t)data,
+ (uint32_t)(data + cache_data_count));
+ }
+
+ slave->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
+ (length << MXS_DMA_DESC_BYTES_OFFSET) |
+ (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
+ MXS_DMA_DESC_WAIT4END;
+
+ slave->desc->cmd.pio_words[0] = ctrl0;
+
+ dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus;
+ mxs_dma_desc_append(dmach, slave->desc);
+ if (mxs_dma_go(dmach))
+ return -EINVAL;
+
+ /* The data arrived into DRAM, invalidate cache over them */
+ if (!write) {
+ invalidate_dcache_range((uint32_t)data,
+ (uint32_t)(data + cache_data_count));
+ }
+
+ return 0;
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
+ struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
+ int len = bitlen / 8;
+ char dummy;
+ int write = 0;
+ char *data = NULL;
+
+#ifdef CONFIG_MXS_SPI_DMA_ENABLE
+ int dma = 1;
+#else
+ int dma = 0;
+#endif
+
+ if (bitlen == 0) {
+ if (flags & SPI_XFER_END) {
+ din = (void *)&dummy;
+ len = 1;
+ } else
+ return 0;
+ }
+
+ /* Half-duplex only */
+ if (din && dout)
+ return -EINVAL;
+ /* No data */
+ if (!din && !dout)
+ return 0;
+
+ if (dout) {
+ data = (char *)dout;
+ write = 1;
+ } else if (din) {
+ data = (char *)din;
+ write = 0;
+ }
+
+ /*
+ * Check for alignment, if the buffer is aligned, do DMA transfer,
+ * PIO otherwise. This is a temporary workaround until proper bounce
+ * buffer is in place.
+ */
+ if (dma) {
+ if (((uint32_t)data) & (ARCH_DMA_MINALIGN - 1))
+ dma = 0;
+ if (((uint32_t)len) & (ARCH_DMA_MINALIGN - 1))
+ dma = 0;
+ }
+
+ if (!dma || (len < MXSSSP_SMALL_TRANSFER)) {
+ writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
+ return mxs_spi_xfer_pio(mxs_slave, data, len, write, flags);
+ } else {
+ writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
+ return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags);
+ }
+}