-#define CONFIG_SYS_SMC0_SETUP0_VAL 0x0A0A0A0A /* SMC_SETUP */
-#define CONFIG_SYS_SMC0_PULSE0_VAL 0x0B0B0B0B /* SMC_PULSE */
-#define CONFIG_SYS_SMC0_CYCLE0_VAL 0x00160016 /* SMC_CYCLE */
-#define CONFIG_SYS_SMC0_CTRL0_VAL 0x00161003 /* SMC_MODE */
-
-/* setup SMC1, CS0 (PSRAM) - 16-bit */
-#define CONFIG_SYS_SMC1_SETUP0_VAL 0x00000000 /* SMC_SETUP */
-#define CONFIG_SYS_SMC1_PULSE0_VAL 0x07020707 /* SMC_PULSE */
-#define CONFIG_SYS_SMC1_CYCLE0_VAL 0x00080008 /* SMC_CYCLE */
-#define CONFIG_SYS_SMC1_CTRL0_VAL 0x31001000 /* SMC_MODE */
-
-#define CONFIG_SYS_RSTC_RMR_VAL 0xA5000301 /* user reset enable */
-
-/* Watchdog */
-#define CONFIG_SYS_WDTC_WDMR_VAL 0x3fff8fff /* disable watchdog */
-
-/* */
+#define CONFIG_SYS_SMC0_SETUP0_VAL \
+ (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
+ AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
+#define CONFIG_SYS_SMC0_PULSE0_VAL \
+ (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
+ AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
+#define CONFIG_SYS_SMC0_CYCLE0_VAL \
+ (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
+#define CONFIG_SYS_SMC0_MODE0_VAL \
+ (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
+ AT91_SMC_MODE_DBW_16 | \
+ AT91_SMC_MODE_TDF | \
+ AT91_SMC_MODE_TDF_CYCLE(6))
+
+/* user reset enable */
+#define CONFIG_SYS_RSTC_RMR_VAL \
+ (AT91_RSTC_KEY | \
+ AT91_RSTC_CR_PROCRST | \
+ AT91_RSTC_MR_ERSTL(1) | \
+ AT91_RSTC_MR_ERSTL(2))
+
+/* Disable Watchdog */
+#define CONFIG_SYS_WDTC_WDMR_VAL \
+ (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
+ AT91_WDT_MR_WDV(0xfff) | \
+ AT91_WDT_MR_WDDIS | \
+ AT91_WDT_MR_WDD(0xfff))